case O_vector:
*seg = reg_section;
break;
+ case O_predicate:
+ *seg = absolute_section;
+ break;
default:
- abort ();
+ abort();
}
return true;
{
if (op == O_add && left->X_op == O_constant)
left->X_md = right->X_md;
+ else if ((ppc_cpu & PPC_OPCODE_SVP64)
+ && (op == O_left_shift)
+ && (left->X_op == O_constant)
+ && (left->X_add_number == 1)
+ && (right->X_add_number == 3)) /* 1<<r3 */
+ {
+ left->X_op = O_predicate;
+ left->X_add_number = SVP64_PREDICATE_1BIT_R3;
+ return 1;
+ }
else
as_warn (_("invalid register expression"));
}