-@c Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
+@c Copyright (C) 2009-2018 Free Software Foundation, Inc.
@c Contributed by ARM Ltd.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@end ifclear
@cindex AArch64 support
-@cindex Thumb support
@menu
* AArch64 Options:: Options
+* AArch64 Extensions:: Extensions
* AArch64 Syntax:: Syntax
* AArch64 Floating Point:: Floating Point
* AArch64 Directives:: AArch64 Machine Directives
@c man begin OPTIONS
@table @gcctabopt
-@cindex @code{-EB} command line option, AArch64
+@cindex @option{-EB} command-line option, AArch64
@item -EB
This option specifies that the output generated by the assembler should
be marked as being encoded for a big-endian processor.
-@cindex @code{-EL} command line option, AArch64
+@cindex @option{-EL} command-line option, AArch64
@item -EL
This option specifies that the output generated by the assembler should
be marked as being encoded for a little-endian processor.
-@cindex @code{-mabi=} command line option, AArch64
+@cindex @option{-mabi=} command-line option, AArch64
@item -mabi=@var{abi}
Specify which ABI the source code uses. The recognized arguments
are: @code{ilp32} and @code{lp64}, which decides the generated object
file in ELF32 and ELF64 format respectively. The default is @code{lp64}.
+@cindex @option{-mcpu=} command-line option, AArch64
+@item -mcpu=@var{processor}[+@var{extension}@dots{}]
+This option specifies the target processor. The assembler will issue an error
+message if an attempt is made to assemble an instruction which will not execute
+on the target processor. The following processor names are recognized:
+@code{cortex-a35},
+@code{cortex-a53},
+@code{cortex-a55},
+@code{cortex-a57},
+@code{cortex-a72},
+@code{cortex-a73},
+@code{cortex-a75},
+@code{cortex-a76},
+@code{exynos-m1},
+@code{falkor},
+@code{qdf24xx},
+@code{saphira},
+@code{thunderx},
+@code{vulcan},
+@code{xgene1}
+and
+@code{xgene2}.
+The special name @code{all} may be used to allow the assembler to accept
+instructions valid for any supported processor, including all optional
+extensions.
+
+In addition to the basic instruction set, the assembler can be told to
+accept, or restrict, various extension mnemonics that extend the
+processor. @xref{AArch64 Extensions}.
+
+If some implementations of a particular processor can have an
+extension, then then those extensions are automatically enabled.
+Consequently, you will not normally have to specify any additional
+extensions.
+
+@cindex @option{-march=} command-line option, AArch64
+@item -march=@var{architecture}[+@var{extension}@dots{}]
+This option specifies the target architecture. The assembler will
+issue an error message if an attempt is made to assemble an
+instruction which will not execute on the target architecture. The
+following architecture names are recognized: @code{armv8-a},
+@code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a}
+and @code{armv8.5-a}.
+
+If both @option{-mcpu} and @option{-march} are specified, the
+assembler will use the setting for @option{-mcpu}. If neither are
+specified, the assembler will default to @option{-mcpu=all}.
+
+The architecture option can be extended with the same instruction set
+extension options as the @option{-mcpu} option. Unlike
+@option{-mcpu}, extensions are not always enabled by default,
+@xref{AArch64 Extensions}.
+
+@cindex @code{-mverbose-error} command-line option, AArch64
+@item -mverbose-error
+This option enables verbose error messages for AArch64 gas. This option
+is enabled by default.
+
+@cindex @code{-mno-verbose-error} command-line option, AArch64
+@item -mno-verbose-error
+This option disables verbose error messages in AArch64 gas.
+
@end table
@c man end
+@node AArch64 Extensions
+@section Architecture Extensions
+
+The table below lists the permitted architecture extensions that are
+supported by the assembler and the conditions under which they are
+automatically enabled.
+
+Multiple extensions may be specified, separated by a @code{+}.
+Extension mnemonics may also be removed from those the assembler
+accepts. This is done by prepending @code{no} to the option that adds
+the extension. Extensions that are removed must be listed after all
+extensions that have been added.
+
+Enabling an extension that requires other extensions will
+automatically cause those extensions to be enabled. Similarly,
+disabling an extension that is required by other extensions will
+automatically cause those extensions to be disabled.
+
+@multitable @columnfractions .12 .17 .17 .54
+@headitem Extension @tab Minimum Architecture @tab Enabled by default
+ @tab Description
+@item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later
+ @tab Enable the complex number SIMD extensions. This implies
+ @code{fp16} and @code{simd}.
+@item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later
+ @tab Enable CRC instructions.
+@item @code{crypto} @tab ARMv8-A @tab No
+ @tab Enable cryptographic extensions. This implies @code{fp}, @code{simd}, @code{aes} and @code{sha2}.
+@item @code{aes} @tab ARMv8-A @tab No
+ @tab Enable the AES cryptographic extensions. This implies @code{fp} and @code{simd}.
+@item @code{sha2} @tab ARMv8-A @tab No
+ @tab Enable the SHA2 cryptographic extensions. This implies @code{fp} and @code{simd}.
+@item @code{sha3} @tab ARMv8.2-A @tab No
+ @tab Enable the ARMv8.2-A SHA2 and SHA3 cryptographic extensions. This implies @code{fp}, @code{simd} and @code{sha2}.
+@item @code{sm4} @tab ARMv8.2-A @tab No
+ @tab Enable the ARMv8.2-A SM3 and SM4 cryptographic extensions. This implies @code{fp} and @code{simd}.
+@item @code{fp} @tab ARMv8-A @tab ARMv8-A or later
+ @tab Enable floating-point extensions.
+@item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later
+ @tab Enable ARMv8.2 16-bit floating-point support. This implies
+ @code{fp}.
+@item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
+ @tab Enable Limited Ordering Regions extensions.
+@item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later
+ @tab Enable Large System extensions.
+@item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later
+ @tab Enable Privileged Access Never support.
+@item @code{profile} @tab ARMv8.2-A @tab No
+ @tab Enable statistical profiling extensions.
+@item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later
+ @tab Enable the Reliability, Availability and Serviceability
+ extension.
+@item @code{rcpc} @tab ARMv8.2-A @tab ARMv8.3-A or later
+ @tab Enable the weak release consistency extension.
+@item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later
+ @tab Enable ARMv8.1 Advanced SIMD extensions. This implies @code{simd}.
+@item @code{simd} @tab ARMv8-A @tab ARMv8-A or later
+ @tab Enable Advanced SIMD extensions. This implies @code{fp}.
+@item @code{sve} @tab ARMv8.2-A @tab No
+ @tab Enable the Scalable Vector Extensions. This implies @code{fp16},
+ @code{simd} and @code{compnum}.
+@item @code{dotprod} @tab ARMv8.2-A @tab ARMv8.4-A or later
+ @tab Enable the Dot Product extension. This implies @code{simd}.
+@item @code{fp16fml} @tab ARMv8.2-A @tab ARMv8.4-A or later
+ @tab Enable ARMv8.2 16-bit floating-point multiplication variant support.
+ This implies @code{fp16}.
+@item @code{sb} @tab ARMv8-A @tab ARMv8.5-A or later
+ @tab Enable the speculation barrier instruction sb.
+@item @code{predres} @tab ARMv8-A @tab ARMv8.5-A or later
+ @tab Enable the Execution and Data and Prediction instructions.
+@item @code{rng} @tab ARMv8.5-A @tab No
+ @tab Enable ARMv8.5-A random number instructions.
+@item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later
+ @tab Enable Speculative Store Bypassing Safe state read and write.
+@item @code{memtag} @tab ARMv8.5-A @tab No
+ @tab Enable ARMv8.5-A Memory Tagging Extensions.
+@end multitable
+
@node AArch64 Syntax
@section Syntax
@menu
@cindex ADRP, ADD, LDR/STR group relocations, AArch64
Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
instructions can be generated by prefixing the label with
-@samp{#:pg_hi21:} and @samp{#:lo12:} respectively.
+@samp{:pg_hi21:} and @samp{#:lo12:} respectively.
For example to use 33-bit (+/-4GB) pc-relative addressing to
load the address of @var{foo} into x0:
@smallexample
- adrp x0, #:pg_hi21:foo
+ adrp x0, :pg_hi21:foo
add x0, x0, #:lo12:foo
@end smallexample
Or to load the value of @var{foo} into x0:
@smallexample
- adrp x0, #:pg_hi21:foo
+ adrp x0, :pg_hi21:foo
ldr x0, [x0, #:lo12:foo]
@end smallexample
-Note that @samp{#:pg_hi21:} is optional.
+Note that @samp{:pg_hi21:} is optional.
@smallexample
adrp x0, foo
is equivalent to
@smallexample
- adrp x0, #:pg_hi21:foo
+ adrp x0, :pg_hi21:foo
@end smallexample
@node AArch64 Floating Point
@table @code
@c AAAAAAAAAAAAAAAAAAAAAAAAA
+
+@cindex @code{.arch} directive, AArch64
+@item .arch @var{name}
+Select the target architecture. Valid values for @var{name} are the same as
+for the @option{-march} command-line option.
+
+Specifying @code{.arch} clears any previously selected architecture
+extensions.
+
+@cindex @code{.arch_extension} directive, AArch64
+@item .arch_extension @var{name}
+Add or remove an architecture extension to the target architecture. Valid
+values for @var{name} are the same as those accepted as architectural
+extensions by the @option{-mcpu} command-line option.
+
+@code{.arch_extension} may be used multiple times to add or remove extensions
+incrementally to the architecture being compiled for.
+
@c BBBBBBBBBBBBBBBBBBBBBBBBBB
@cindex @code{.bss} directive, AArch64
This directive switches to the @code{.bss} section.
@c CCCCCCCCCCCCCCCCCCCCCCCCCC
+
+@cindex @code{.cpu} directive, AArch64
+@item .cpu @var{name}
+Set the target processor. Valid values for @var{name} are the same as
+those accepted by the @option{-mcpu=} command-line option.
+
@c DDDDDDDDDDDDDDDDDDDDDDDDDD
+
+@cindex @code{.dword} directive, AArch64
+@item .dword @var{expressions}
+The @code{.dword} directive produces 64 bit values.
+
@c EEEEEEEEEEEEEEEEEEEEEEEEEE
+
+@cindex @code{.even} directive, AArch64
+@item .even
+The @code{.even} directive aligns the output on the next even byte
+boundary.
+
@c FFFFFFFFFFFFFFFFFFFFFFFFFF
@c GGGGGGGGGGGGGGGGGGGGGGGGGG
@c HHHHHHHHHHHHHHHHHHHHHHHHHH
@c IIIIIIIIIIIIIIIIIIIIIIIIII
+
+@cindex @code{.inst} directive, AArch64
+@item .inst @var{expressions}
+Inserts the expressions into the output as if they were instructions,
+rather than data.
+
@c JJJJJJJJJJJJJJJJJJJJJJJJJJ
@c KKKKKKKKKKKKKKKKKKKKKKKKKK
@c LLLLLLLLLLLLLLLLLLLLLLLLLL
This directive causes the current contents of the literal pool to be
dumped into the current section (which is assumed to be the .text
section) at the current location (aligned to a word boundary).
-@code{GAS} maintains a separate literal pool for each section and each
+GAS maintains a separate literal pool for each section and each
sub-section. The @code{.ltorg} directive will only affect the literal
pool of the current section and sub-section. At the end of assembly
all remaining, un-empty literal pools will automatically be dumped.
-Note - older versions of @code{GAS} would dump the current literal
+Note - older versions of GAS would dump the current literal
pool any time a section change occurred. This is no longer done, since
it prevents accurate control of the placement of literal pools.
foo .req w0
@end smallexample
+ip0, ip1, lr and fp are automatically defined to
+alias to X16, X17, X30 and X29 respectively.
+
@c SSSSSSSSSSSSSSSSSSSSSSSSSS
@c TTTTTTTTTTTTTTTTTTTTTTTTTT
+@cindex @code{.tlsdescadd} directive, AArch64
+@item @code{.tlsdescadd}
+Emits a TLSDESC_ADD reloc on the next instruction.
+
+@cindex @code{.tlsdesccall} directive, AArch64
+@item @code{.tlsdesccall}
+Emits a TLSDESC_CALL reloc on the next instruction.
+
+@cindex @code{.tlsdescldr} directive, AArch64
+@item @code{.tlsdescldr}
+Emits a TLSDESC_LDR reloc on the next instruction.
+
@c UUUUUUUUUUUUUUUUUUUUUUUUUU
@cindex @code{.unreq} directive, AArch64
@c WWWWWWWWWWWWWWWWWWWWWWWWWW
@c XXXXXXXXXXXXXXXXXXXXXXXXXX
+
+@cindex @code{.xword} directive, AArch64
+@item .xword @var{expressions}
+The @code{.xword} directive produces 64 bit values. This is the same
+as the @code{.dword} directive.
+
@c YYYYYYYYYYYYYYYYYYYYYYYYYY
@c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
+@cindex @code{.cfi_b_key_frame} directive, AArch64
+@item @code{.cfi_b_key_frame}
+The @code{.cfi_b_key_frame} directive inserts a 'B' character into the CIE
+corresponding to the current frame's FDE, meaning that its return address has
+been signed with the B-key. If two frames are signed with differing keys then
+they will not share the same CIE. This information is intended to be used by
+the stack unwinder in order to properly authenticate return addresses.
+
@end table
@node AArch64 Opcodes
@cindex AArch64 opcodes
@cindex opcodes for AArch64
-@code{@value{AS}} implements all the standard AArch64 opcodes. It also
+GAS implements all the standard AArch64 opcodes. It also
implements several pseudo opcodes, including several synthetic load
instructions.
projects / binutils-gdb.git / blobdiff