-@c Copyright (C) 1996, 1998, 1999 Free Software Foundation, Inc.
+@c Copyright 1996, 1997, 1998, 1999, 2000, 2001
+@c Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@section Options
@cindex ARM options (none)
@cindex options for ARM (none)
+
@table @code
-@cindex @code{-marm} command line option, ARM
-@item -marm [@var{2}|@var{250}|@var{3}|@var{6}|@var{60}|@var{600}|@var{610}|@var{620}|@var{7}|@var{7m}|@var{7d}|@var{7dm}|@var{7di}|@var{7dmi}|@var{70}|@var{700}|@var{700i}|@var{710}|@var{710c}|@var{7100}|@var{7500}|@var{7500fe}|@var{7tdmi}|@var{8}|@var{810}|@var{9}|@var{9tdmi}|@var{920}|@var{strongarm}|@var{strongarm110}|@var{strongarm1100}]
+
+@cindex @code{-mcpu=} command line option, ARM
+@item -mcpu=@var{processor}[+@var{extension}@dots{}]
This option specifies the target processor. The assembler will issue an
error message if an attempt is made to assemble an instruction which
-will not execute on the target processor.
-@cindex @code{-marmv} command line option, ARM
-@item -marmv [@var{2}|@var{2a}|@var{3}|@var{3m}|@var{4}|@var{4t}|@var{5}|@var{5t}]
+will not execute on the target processor. The following processor names are
+recognized:
+@code{arm1},
+@code{arm2},
+@code{arm250},
+@code{arm3},
+@code{arm6},
+@code{arm60},
+@code{arm600},
+@code{arm610},
+@code{arm620},
+@code{arm7},
+@code{arm7m},
+@code{arm7d},
+@code{arm7dm},
+@code{arm7di},
+@code{arm7dmi},
+@code{arm70},
+@code{arm700},
+@code{arm700i},
+@code{arm710},
+@code{arm710t},
+@code{arm720},
+@code{arm720t},
+@code{arm740t},
+@code{arm710c},
+@code{arm7100},
+@code{arm7500},
+@code{arm7500fe},
+@code{arm7t},
+@code{arm7tdmi},
+@code{arm8},
+@code{arm810},
+@code{strongarm},
+@code{strongarm1},
+@code{strongarm110},
+@code{strongarm1100},
+@code{strongarm1110},
+@code{arm9},
+@code{arm920},
+@code{arm920t},
+@code{arm922t},
+@code{arm940t},
+@code{arm9tdmi},
+@code{arm9e},
+@code{arm946e-r0},
+@code{arm946e},
+@code{arm966e-r0},
+@code{arm966e},
+@code{arm10t},
+@code{arm10e},
+@code{arm1020},
+@code{arm1020t},
+@code{arm1020e},
+@code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
+@code{i80200} (Intel XScale processor)
+and
+@code{xscale}.
+The special name @code{all} may be used to allow the
+assembler to accept instructions valid for any ARM processor.
+
+In addition to the basic instruction set, the assembler can be told to
+accept various extension mnemonics that extend the processor using the
+co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
+is equivalent to specifying @code{-mcpu=ep9312}. The following extensions
+are currently supported:
+@code{+maverick}
+and
+@code{+xscale}.
+
+@cindex @code{-march=} command line option, ARM
+@item -march=@var{architecture}[+@var{extension}@dots{}]
This option specifies the target architecture. The assembler will issue
an error message if an attempt is made to assemble an instruction which
-will not execute on the target architecture.
+will not execute on the target architecture. The following architecture
+names are recognized:
+@code{armv1},
+@code{armv2},
+@code{armv2a},
+@code{armv2s},
+@code{armv3},
+@code{armv3m},
+@code{armv4},
+@code{armv4xm},
+@code{armv4t},
+@code{armv4txm},
+@code{armv5},
+@code{armv5t},
+@code{armv5txm},
+@code{armv5te},
+@code{armv5texp}
+and
+@code{xscale}.
+If both @code{-mcpu} and
+@code{-march} are specified, the assembler will use
+the setting for @code{-mcpu}.
+
+The architecture option can be extended with the same instruction set
+extension options as the @code{-mcpu} option.
+
+@cindex @code{-mfpu=} command line option, ARM
+@item -mfpu=@var{floating-point-format}
+
+This option specifies the floating point format to assemble for. The
+assembler will issue an error message if an attempt is made to assemble
+an instruction which will not execute on the target floating point unit.
+The following format options are recognized:
+@code{softfpa},
+@code{fpe},
+@code{fpe2},
+@code{fpe3},
+@code{fpa},
+@code{fpa10},
+@code{fpa11},
+@code{arm7500fe},
+@code{softvfp},
+@code{softvfp+vfp},
+@code{vfp},
+@code{vfp10},
+@code{vfp10-r0},
+@code{vfp9},
+@code{vfpxd},
+@code{arm1020t}
+and
+@code{arm1020e}.
+
+In addition to determining which instructions are assembled, this option
+also affects the way in which the @code{.double} assembler directive behaves
+when assembling little-endian code.
+
+The default is dependent on the processor selected. For Architecture 5 or
+later, the default is to assembler for VFP instructions; for earlier
+architectures the default is to assemble for FPA instructions.
+
@cindex @code{-mthumb} command line option, ARM
@item -mthumb
-This option specifies that only Thumb instructions should be assembled.
-@cindex @code{-mall} command line option, ARM
-@item -mall
-This option specifies that any Arm or Thumb instruction should be assembled.
-@cindex @code{-mfpa} command line option, ARM
-@item -mfpa [@var{10}|@var{11}]
-This option specifies the floating point architecture in use on the
-target processor.
-@cindex @code{-mfpe-old} command line option, ARM
-@item -mfpe-old
-Do not allow the assemble of floating point multiple instructions.
-@cindex @code{-mno-fpu} command line option, ARM
-@item -mno-fpu
-Do not allow the assembly of any floating point instructions.
+This option specifies that the assembler should start assembling Thumb
+instructions; that is, it should behave as though the file starts with a
+@code{.code 16} directive.
+
@cindex @code{-mthumb-interwork} command line option, ARM
@item -mthumb-interwork
This option specifies that the output generated by the assembler should
be marked as supporting interworking.
+
@cindex @code{-mapcs} command line option, ARM
-@item -mapcs [@var{26}|@var{32}]
+@item -mapcs @code{[26|32]}
This option specifies that the output generated by the assembler should
be marked as supporting the indicated version of the Arm Procedure.
Calling Standard.
+
+@cindex @code{-matpcs} command line option, ARM
+@item -matpcs
+This option specifies that the output generated by the assembler should
+be marked as supporting the Arm/Thumb Procedure Calling Standard. If
+enabled this option will cause the assembler to create an empty
+debugging section in the object file called .arm.atpcs. Debuggers can
+use this to determine the ABI being used by.
+
+@cindex @code{-mapcs-float} command line option, ARM
@item -mapcs-float
This indicates the the floating point variant of the APCS should be
used. In this variant floating point arguments are passed in FP
registers rather than integer registers.
+
+@cindex @code{-mapcs-reentrant} command line option, ARM
@item -mapcs-reentrant
This indicates that the reentrant variant of the APCS should be used.
This variant supports position independent code.
+
@cindex @code{-EB} command line option, ARM
@item -EB
This option specifies that the output generated by the assembler should
be marked as being encoded for a big-endian processor.
+
@cindex @code{-EL} command line option, ARM
@item -EL
This option specifies that the output generated by the assembler should
be marked as being encoded for a little-endian processor.
+
@cindex @code{-k} command line option, ARM
@cindex PIC code generation for ARM
@item -k
-This option enables the generation of PIC (position independent code).
+This option specifies that the output of the assembler should be marked
+as position-independent code (PIC).
+
+@cindex @code{-moabi} command line option, ARM
@item -moabi
This indicates that the code should be assembled using the old ARM ELF
conventions, based on a beta release release of the ARM-ELF
specifications, rather than the default conventions which are based on
the final release of the ARM-ELF specifications.
+
@end table
@cindex line separator, ARM
@cindex statement separator, ARM
@cindex ARM line separator
-On ARM systems running the GNU/Linux operating system, @samp{;} can be
-used instead of a newline to separate statements.
+The @samp{;} character can be used instead of a newline to separate
+statements.
@cindex immediate character, ARM
@cindex ARM immediate character
@cindex ARM machine directives
@table @code
+@cindex @code{align} directive, ARM
+@item .align @var{expression} [, @var{expression}]
+This is the generic @var{.align} directive. For the ARM however if the
+first argument is zero (ie no alignment is needed) the assembler will
+behave as if the argument had been 2 (ie pad to the next four byte
+boundary). This is for compatability with ARM's own assembler.
+
@cindex @code{req} directive, ARM
@item @var{name} .req @var{register name}
This creates an alias for @var{register name} called @var{name}. For
@end smallexample
@cindex @code{code} directive, ARM
-@item .code [@var{16}|@var{32}]
+@item .code @code{[16|32]}
This directive selects the instruction set being generated. The value 16
selects Thumb, with the value 32 selecting ARM.
Thumb encoded function. This information is necessary in order to allow
the assembler and linker to generate correct code for interworking
between Arm and Thumb instructions and should be used even if
-interworking is not going to be performed.
+interworking is not going to be performed. The presence of this
+directive also implies @code{.thumb}
@cindex @code{thumb_set} directive, ARM
@item .thumb_set
This directive causes the current contents of the literal pool to be
dumped into the current section (which is assumed to be the .text
section) at the current location (aligned to a word boundary).
+@code{GAS} maintains a separate literal pool for each section and each
+sub-section. The @code{.ltorg} directive will only affect the literal
+pool of the current section and sub-section. At the end of assembly
+all remaining, un-empty literal pools will automatically be dumped.
+
+Note - older versions of @code{GAS} would dump the current literal
+pool any time a section change occurred. This is no longer done, since
+it prevents accurate control of the placement of literal pools.
@cindex @code{.pool} directive, ARM
@item .pool
@end smallexample
This instruction will load the address of @var{label} into the indicated
-register. The instruction will evaluate to one or two a PC relative ADD
+register. The instruction will evaluate to one or two PC relative ADD
or SUB instructions depending upon where the label is located. If a
second instruction is not needed a NOP instruction will be generated in
its place, so that this instruction is always 8 bytes long.
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