RISC-V: Add 'Sstc' extension and its CSRs

[binutils-gdb.git] / gas / doc / c-m68hc11.texi

diff --git a/gas/doc/c-m68hc11.texi b/gas/doc/c-m68hc11.texi
index bebc53ed5562b40c9337ec912632a75583bdf909..5e71152b56f54e7ac8adb58065b89d8cc6b38e69 100644 (file)
--- a/gas/doc/c-m68hc11.texi
+++ b/gas/doc/c-m68hc11.texi
@@ -1,6 +1,4 @@
-@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2003,
-@c 2006, 2011
-@c Free Software Foundation, Inc.
+@c Copyright (C) 1991-2022 Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 @ifset GENERIC
@@ -35,24 +33,40 @@ dependent options.
 
 @cindex @samp{-m68hc11}
 @item -m68hc11
-This option switches the assembler in the M68HC11 mode. In this mode,
+This option switches the assembler into the M68HC11 mode. In this mode,
 the assembler only accepts 68HC11 operands and mnemonics. It produces
 code for the 68HC11.
 
 @cindex @samp{-m68hc12}
 @item -m68hc12
-This option switches the assembler in the M68HC12 mode. In this mode,
+This option switches the assembler into the M68HC12 mode. In this mode,
 the assembler also accepts 68HC12 operands and mnemonics. It produces
 code for the 68HC12. A few 68HC11 instructions are replaced by
 some 68HC12 instructions as recommended by Motorola specifications.
 
 @cindex @samp{-m68hcs12}
 @item -m68hcs12
-This option switches the assembler in the M68HCS12 mode.  This mode is
+This option switches the assembler into the M68HCS12 mode.  This mode is
 similar to @samp{-m68hc12} but specifies to assemble for the 68HCS12
 series.  The only difference is on the assembling of the @samp{movb}
 and @samp{movw} instruction when a PC-relative operand is used.
 
+@cindex @samp{-mm9s12x}
+@item -mm9s12x
+This option switches the assembler into the M9S12X mode.  This mode is
+similar to @samp{-m68hc12} but specifies to assemble for the S12X
+series which is a superset of the HCS12.
+
+@cindex @samp{-mm9s12xg}
+@item -mm9s12xg
+This option switches the assembler into the XGATE mode for the RISC
+co-processor featured on some S12X-family chips.
+
+@cindex @samp{--xgate-ramoffset}
+@item --xgate-ramoffset
+This option instructs the linker to offset RAM addresses from S12X address
+space into XGATE address space.
+
 @cindex @samp{-mshort}
 @item -mshort
 This option controls the ABI and indicates to use a 16-bit integer ABI.
@@ -105,7 +119,7 @@ associated to the @samp{jbra}, @samp{jbsr} and @samp{jbXX} pseudo opcodes.
 The @samp{--force-long-branches} option forces the translation of
 relative branches into absolute branches. This option does not affect
 the optimization associated to the @samp{jbra}, @samp{jbsr} and
-@samp{jbXX} pseudo opcodes. 
+@samp{jbXX} pseudo opcodes.
 
 @cindex @samp{--print-insn-syntax}
 @item --print-insn-syntax
@@ -418,7 +432,7 @@ The following table summarizes the pseudo-operations.
  bra | bra <pc-rel>    <error>  |               jmp <abs>          |
 jbsr | bsr <pc-rel>   jsr <abs> | bsr <pc-rel>  jsr <abs>          |
 jbra | bra <pc-rel>   jmp <abs> | bra <pc-rel>  jmp <abs>          |
- bXX | bXX <pc-rel>    <error>  |               bNX +3; jmp <abs>  | 
+ bXX | bXX <pc-rel>    <error>  |               bNX +3; jmp <abs>  |
 jbXX | bXX <pc-rel>   bNX +3;   | bXX <pc-rel>  bNX +3; jmp <abs>  |
      |                jmp <abs> |                                  |
      +--------------------------+----------------------------------+