RISC-V: Add 'Sstc' extension and its CSRs

[binutils-gdb.git] / gas / doc / c-rx.texi

diff --git a/gas/doc/c-rx.texi b/gas/doc/c-rx.texi
index d671d0922951da46f738fc0da9e60a05b91067d6..0ea27ef4dbccfe120dcf2d9d514411027c00dbcb 100644 (file)
--- a/gas/doc/c-rx.texi
+++ b/gas/doc/c-rx.texi
@@ -1,4 +1,4 @@
-@c Copyright (C) 2008-2019 Free Software Foundation, Inc.
+@c Copyright (C) 2008-2022 Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 @ifset GENERIC
@@ -65,8 +65,8 @@ initialised data (.data) and uninitialised data sections (.bss).
 
 @cindex @samp{-muse-renesas-section-names}
 @item -muse-renesas-section-names
-This option controls the default names given to the code (.P),
-initialised data (.D_1) and uninitialised data sections (.B_1).
+This option controls the default names given to the code (P),
+initialised data (D_1) and uninitialised data sections (B_1).
 This is the default.
 
 @cindex @samp{-msmall-data-limit}
@@ -108,10 +108,10 @@ alignments.  This option is the default.
 @cindex @samp{-mcpu=}
 @item -mcpu=@var{name}
 This option tells the assembler the target CPU type.  Currently the
-@code{rx100}, @code{rx200}, @code{rx600}, @code{rx610} and @code{rxv2}
-are recognised as valid cpu names.  Attempting to assemble an instruction
-not supported by the indicated cpu type will result in an error message
-being generated.
+@code{rx100}, @code{rx200}, @code{rx600}, @code{rx610}, @code{rxv2},
+@code{rxv3} and @code{rxv3-dfpu} are recognised as valid cpu names.
+Attempting to assemble an instructionnot supported by the indicated
+cpu type will result in an error message being generated.
 
 @cindex @samp{-mno-allow-string-insns}
 @item -mno-allow-string-insns