+2014-05-11 Richard Sandiford <rdsandiford@googlemail.com>
+
+ PR tree-optimization/61136
+ * wide-int.h (multiple_of_p): Define a version that doesn't return
+ the quotient.
+ * fold-const.c (extract_muldiv_1): Use wi::multiple_of_p instead of an
+ integer_zerop/const_binop pair.
+ (multiple_of_p): Likewise, converting both operands to widest_int
+ precision.
+
+2014-05-09 Teresa Johnson <tejohnson@google.com>
+
+ * cgraphunit.c (analyze_functions): Use correct dump file.
+
+2014-05-09 Florian Weimer <fweimer@redhat.com>
+
+ * cfgexpand.c (stack_protect_decl_p): New function, extracted from
+ expand_used_vars.
+ (stack_protect_return_slot_p): New function.
+ (expand_used_vars): Call stack_protect_decl_p and
+ stack_protect_return_slot_p for -fstack-protector-strong.
+
+2014-05-09 Kenneth Zadeck <zadeck@naturalbridge.com>
+
+ PR middle-end/61111
+ * fold-const.c (fold_binary_loc): Changed width of mask.
+
+2014-05-09 Georg-Johann Lay <avr@gjlay.de>
+
+ * config/avr/avr-fixed.md (round<mode>3): Use -1U instead of -1 in
+ unsigned int initializers for regno_in, regno_out.
+
+2014-05-09 Georg-Johann Lay <avr@gjlay.de>
+
+ PR target/61055
+ * config/avr/avr.md (cc): Add new attribute set_vzn.
+ (addqi3, addqq3, adduqq3, subqi3, subqq3, subuqq3, negqi2) [cc]:
+ Set cc insn attribute to set_vzn instead of set_zn for alternatives
+ with INC, DEC or NEG.
+ * config/avr/avr.c (avr_notice_update_cc): Handle SET_VZN.
+ (avr_out_plus_1): ADIW sets cc0 to CC_SET_CZN.
+ INC, DEC and ADD+ADC set cc0 to CC_CLOBBER.
+
+2014-05-09 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+
+ Revert:
+ 2014-05-08 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+
+ * wide-int.cc (UTItype): Define.
+ (UDWtype): Define for appropriate W_TYPE_SIZE.
+
+2014-05-09 Richard Biener <rguenther@suse.de>
+
+ * Makefile.in (GTFILES): Remove tree-ssa-propagate.c.
+ * tree-ssa-propagate.c: Do not include gt-tree-ssa-propagate.h.
+ (interesting_ssa_edges, varying_ssa_edges): Move out of GC space.
+ (add_ssa_edge, process_ssa_edge_worklist, ssa_prop_init,
+ ssa_propagate): Adjust.
+
+2014-05-08 Jeff Law <law@redhat.com>
+
+ PR tree-optimization/61009
+ * tree-ssa-threadedge.c (thread_through_normal_block): Return a
+ tri-state rather than a boolean. When a block is too big to
+ thread through, inform caller via negative return value.
+ (thread_across_edge): If a block was too big for normal threading,
+ then it's too big for a joiner too, so remove temporary equivalences
+ and return immediately.
+
+2014-05-08 Manuel López-Ibáñez <manu@gcc.gnu.org>
+ Matthias Klose <doko@ubuntu.com>
+
+ PR driver/61106
+ * optc-gen.awk: Fix option handling for -Wunused-parameter.
+
+2014-05-08 Uros Bizjak <ubizjak@gmail.com>
+
+ PR target/59952
+ * config/i386/i386.c (PTA_HASWELL): Remove PTA_RTM.
+
+2014-05-08 Uros Bizjak <ubizjak@gmail.com>
+
+ PR target/61092
+ * config/alpha/alpha.c: Include gimple-iterator.h.
+ (alpha_gimple_fold_builtin): New function. Move
+ ALPHA_BUILTIN_UMULH folding from ...
+ (alpha_fold_builtin): ... here.
+ (TARGET_GIMPLE_FOLD_BUILTIN): New define.
+
+2014-05-08 Wei Mi <wmi@google.com>
+
+ PR target/58066
+ * config/i386/i386.c (ix86_compute_frame_layout): Update
+ preferred_stack_boundary for call, expanded from tls descriptor.
+ * config/i386/i386.md (*tls_global_dynamic_32_gnu): Update RTX
+ to depend on SP register.
+ (*tls_local_dynamic_base_32_gnu): Ditto.
+ (*tls_local_dynamic_32_once): Ditto.
+ (tls_global_dynamic_64_<mode>): Set
+ ix86_tls_descriptor_calls_expanded_in_cfun.
+ (tls_local_dynamic_base_64_<mode>): Ditto.
+ (tls_global_dynamic_32): Set
+ ix86_tls_descriptor_calls_expanded_in_cfun. Update RTX
+ to depend on SP register.
+ (tls_local_dynamic_base_32): Ditto.
+
+2014-05-08 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+
+ * config/arm/arm_neon.h: Update comment.
+ * config/arm/neon-docgen.ml: Delete.
+ * config/arm/neon-gen.ml: Delete.
+ * doc/arm-neon-intrinsics.texi: Update comment.
+
+2014-05-08 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+
+ * config/arm/arm_neon_builtins.def (vadd, vsub): Only define the v2sf
+ and v4sf versions.
+ (vand, vorr, veor, vorn, vbic): Remove.
+ * config/arm/neon.md (neon_vadd, neon_vsub, neon_vadd_unspec): Adjust
+ iterator.
+ (neon_vsub_unspec): Likewise.
+ (neon_vorr, neon_vand, neon_vbic, neon_veor, neon_vorn): Remove.
+
+2014-05-08 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+
+ * config/arm/arm_neon.h (vadd_s8): GNU C implementation
+ (vadd_s16): Likewise.
+ (vadd_s32): Likewise.
+ (vadd_f32): Likewise.
+ (vadd_u8): Likewise.
+ (vadd_u16): Likewise.
+ (vadd_u32): Likewise.
+ (vadd_s64): Likewise.
+ (vadd_u64): Likewise.
+ (vaddq_s8): Likewise.
+ (vaddq_s16): Likewise.
+ (vaddq_s32): Likewise.
+ (vaddq_s64): Likewise.
+ (vaddq_f32): Likewise.
+ (vaddq_u8): Likewise.
+ (vaddq_u16): Likewise.
+ (vaddq_u32): Likewise.
+ (vaddq_u64): Likewise.
+ (vmul_s8): Likewise.
+ (vmul_s16): Likewise.
+ (vmul_s32): Likewise.
+ (vmul_f32): Likewise.
+ (vmul_u8): Likewise.
+ (vmul_u16): Likewise.
+ (vmul_u32): Likewise.
+ (vmul_p8): Likewise.
+ (vmulq_s8): Likewise.
+ (vmulq_s16): Likewise.
+ (vmulq_s32): Likewise.
+ (vmulq_f32): Likewise.
+ (vmulq_u8): Likewise.
+ (vmulq_u16): Likewise.
+ (vmulq_u32): Likewise.
+ (vsub_s8): Likewise.
+ (vsub_s16): Likewise.
+ (vsub_s32): Likewise.
+ (vsub_f32): Likewise.
+ (vsub_u8): Likewise.
+ (vsub_u16): Likewise.
+ (vsub_u32): Likewise.
+ (vsub_s64): Likewise.
+ (vsub_u64): Likewise.
+ (vsubq_s8): Likewise.
+ (vsubq_s16): Likewise.
+ (vsubq_s32): Likewise.
+ (vsubq_s64): Likewise.
+ (vsubq_f32): Likewise.
+ (vsubq_u8): Likewise.
+ (vsubq_u16): Likewise.
+ (vsubq_u32): Likewise.
+ (vsubq_u64): Likewise.
+ (vand_s8): Likewise.
+ (vand_s16): Likewise.
+ (vand_s32): Likewise.
+ (vand_u8): Likewise.
+ (vand_u16): Likewise.
+ (vand_u32): Likewise.
+ (vand_s64): Likewise.
+ (vand_u64): Likewise.
+ (vandq_s8): Likewise.
+ (vandq_s16): Likewise.
+ (vandq_s32): Likewise.
+ (vandq_s64): Likewise.
+ (vandq_u8): Likewise.
+ (vandq_u16): Likewise.
+ (vandq_u32): Likewise.
+ (vandq_u64): Likewise.
+ (vorr_s8): Likewise.
+ (vorr_s16): Likewise.
+ (vorr_s32): Likewise.
+ (vorr_u8): Likewise.
+ (vorr_u16): Likewise.
+ (vorr_u32): Likewise.
+ (vorr_s64): Likewise.
+ (vorr_u64): Likewise.
+ (vorrq_s8): Likewise.
+ (vorrq_s16): Likewise.
+ (vorrq_s32): Likewise.
+ (vorrq_s64): Likewise.
+ (vorrq_u8): Likewise.
+ (vorrq_u16): Likewise.
+ (vorrq_u32): Likewise.
+ (vorrq_u64): Likewise.
+ (veor_s8): Likewise.
+ (veor_s16): Likewise.
+ (veor_s32): Likewise.
+ (veor_u8): Likewise.
+ (veor_u16): Likewise.
+ (veor_u32): Likewise.
+ (veor_s64): Likewise.
+ (veor_u64): Likewise.
+ (veorq_s8): Likewise.
+ (veorq_s16): Likewise.
+ (veorq_s32): Likewise.
+ (veorq_s64): Likewise.
+ (veorq_u8): Likewise.
+ (veorq_u16): Likewise.
+ (veorq_u32): Likewise.
+ (veorq_u64): Likewise.
+ (vbic_s8): Likewise.
+ (vbic_s16): Likewise.
+ (vbic_s32): Likewise.
+ (vbic_u8): Likewise.
+ (vbic_u16): Likewise.
+ (vbic_u32): Likewise.
+ (vbic_s64): Likewise.
+ (vbic_u64): Likewise.
+ (vbicq_s8): Likewise.
+ (vbicq_s16): Likewise.
+ (vbicq_s32): Likewise.
+ (vbicq_s64): Likewise.
+ (vbicq_u8): Likewise.
+ (vbicq_u16): Likewise.
+ (vbicq_u32): Likewise.
+ (vbicq_u64): Likewise.
+ (vorn_s8): Likewise.
+ (vorn_s16): Likewise.
+ (vorn_s32): Likewise.
+ (vorn_u8): Likewise.
+ (vorn_u16): Likewise.
+ (vorn_u32): Likewise.
+ (vorn_s64): Likewise.
+ (vorn_u64): Likewise.
+ (vornq_s8): Likewise.
+ (vornq_s16): Likewise.
+ (vornq_s32): Likewise.
+ (vornq_s64): Likewise.
+ (vornq_u8): Likewise.
+ (vornq_u16): Likewise.
+ (vornq_u32): Likewise.
+ (vornq_u64): Likewise.
+
+2014-05-08 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+
+ * wide-int.cc (UTItype): Define.
+ (UDWtype): Define for appropriate W_TYPE_SIZE.
+
+2014-05-08 Marc Glisse <marc.glisse@inria.fr>
+
+ PR tree-optimization/59100
+ * tree-ssa-phiopt.c: Include tree-inline.h.
+ (neutral_element_p, absorbing_element_p): New functions.
+ (value_replacement): Handle conditional binary operations with a
+ neutral or absorbing element.
+
+2014-05-08 Richard Biener <rguenther@suse.de>
+
+ * tree-ssa-sccvn.c (vn_get_expr_for): Valueize operands before
+ folding the expression.
+ (valueize_expr): Remove.
+ (visit_reference_op_load): Do not valueize the result of
+ vn_get_expr_for.
+ (simplify_binary_expression): Likewise.
+ (simplify_unary_expression): Likewise.
+
+2014-05-08 Richard Biener <rguenther@suse.de>
+
+ * gimplify.c (gimplify_call_expr): Use saved fnptrtype for
+ looking at TYPE_ARG_TYPES.
+
+2014-05-08 Richard Biener <rguenther@suse.de>
+
+ * gimple-fold.c (gimple_fold_stmt_to_constant_1): Remove
+ pointer propagation special-case.
+
+2014-05-08 Bin Cheng <bin.cheng@arm.com>
+
+ * tree-affine.c (tree_to_aff_combination): Handle MEM_REF for
+ core part of address expressions.
+
+2014-05-08 Alan Modra <amodra@gmail.com>
+
+ PR target/60737
+ * config/rs6000/rs6000.c (expand_block_move): Allow 64-bit
+ loads and stores when -mno-strict-align at any alignment.
+ (expand_block_clear): Similarly. Also correct calculation of
+ instruction count.
+
+2014-05-07 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ PR middle-end/39246
+ * tree-complex.c (expand_complex_move): Keep line info when expanding
+ complex move.
+ * tree-ssa-uninit.c (warn_uninit): New argument. Ignore assignment
+ of complex expression. Use new argument to display correct location
+ for values coming from phi statement.
+ (warn_uninitialized_vars): Adapt to new signature of warn_uninit.
+ (warn_uninitialized_phi): Pass location of phi argument to
+ warn_uninit.
+ * tree-ssa.c (ssa_undefined_value_p): For SSA_NAME initialized by a
+ COMPLEX_EXPR, recurse on each part of the COMPLEX_EXPR.
+
+2014-05-07 Segher Boessenkool <segher@kernel.crashing.org>
+
+ * config/rs6000/predicates.md (indexed_address_mem): New.
+ * config/rs6000/rs6000.md (type): Remove load_ext, load_ext_u,
+ load_ext_ux, load_ux, load_u, store_ux, store_u, fpload_ux, fpload_u,
+ fpstore_ux, fpstore_u.
+ (sign_extend, indexed, update): New.
+ (cell_micro): Adjust.
+ (*zero_extend<mode>di2_internal1, *zero_extendsidi2_lfiwzx,
+ *extendsidi2_lfiwax, *extendsidi2_nocell, *extendsfdf2_fpr,
+ *movsi_internal1, *movsi_internal1_single, *movhi_internal,
+ *movqi_internal, *movcc_internal1, mov<mode>_hardfloat,
+ *mov<mode>_softfloat, *mov<mode>_hardfloat32, *mov<mode>_hardfloat64,
+ *mov<mode>_softfloat64, *movdi_internal32, *movdi_internal64,
+ *mov<mode>_string, *ldmsi8, *ldmsi7, *ldmsi6, *ldmsi5, *ldmsi4,
+ *ldmsi3, *stmsi8, *stmsi7, *stmsi6, *stmsi5, *stmsi4, *stmsi3,
+ *movdi_update1, movdi_<mode>_update, movdi_<mode>_update_stack,
+ *movsi_update1, *movsi_update2, movsi_update, movsi_update_stack,
+ *movhi_update1, *movhi_update2, *movhi_update3, *movhi_update4,
+ *movqi_update1, *movqi_update2, *movqi_update3, *movsf_update1,
+ *movsf_update2, *movsf_update3, *movsf_update4, *movdf_update1,
+ *movdf_update2, load_toc_aix_si, load_toc_aix_di, probe_stack_<mode>,
+ *stmw, *lmw, as well as 10 anonymous patterns): Adjust.
+
+ * config/rs6000/dfp.md (movsd_store, movsd_load): Adjust.
+ * config/rs6000/vsx.md (*vsx_movti_32bit, *vsx_extract_<mode>_load,
+ *vsx_extract_<mode>_store): Adjust.
+ * config/rs6000/rs6000.c (rs6000_adjust_cost, is_microcoded_insn,
+ is_cracked_insn, insn_must_be_first_in_group,
+ insn_must_be_last_in_group): Adjust.
+
+ * config/rs6000/40x.md (ppc403-load, ppc403-store, ppc405-float):
+ Adjust.
+ * config/rs6000/440.md (ppc440-load, ppc440-store, ppc440-fpload,
+ ppc440-fpstore): Adjust.
+ * config/rs6000/476.md (ppc476-load, ppc476-store, ppc476-fpload,
+ ppc476-fpstore): Adjust.
+ * config/rs6000/601.md (ppc601-load, ppc601-store, ppc601-fpload,
+ ppc601-fpstore): Adjust.
+ * config/rs6000/603.md (ppc603-load, ppc603-store, ppc603-fpload):
+ Adjust.
+ * config/rs6000/6xx.md (ppc604-load, ppc604-store, ppc604-fpload):
+ Adjust.
+ * config/rs6000/7450.md (ppc7450-load, ppc7450-store, ppc7450-fpload,
+ ppc7450-fpstore): Adjust.
+ * config/rs6000/7xx.md (ppc750-load, ppc750-store): Adjust.
+ * config/rs6000/8540.md (ppc8540_load, ppc8540_store): Adjust.
+ * config/rs6000/a2.md (ppca2-load, ppca2-fp-load, ppca2-fp-store):
+ Adjust.
+ * config/rs6000/cell.md (cell-load, cell-load-ux, cell-load-ext,
+ cell-fpload, cell-fpload-update, cell-store, cell-store-update,
+ cell-fpstore, cell-fpstore-update): Adjust.
+ * config/rs6000/e300c2c3.md (ppce300c3_load, ppce300c3_fpload,
+ ppce300c3_store, ppce300c3_fpstore): Adjust.
+ * config/rs6000/e500mc.md (e500mc_load, e500mc_fpload, e500mc_store,
+ e500mc_fpstore): Adjust.
+ * config/rs6000/e500mc64.md (e500mc64_load, e500mc64_fpload,
+ e500mc64_store, e500mc64_fpstore): Adjust.
+ * config/rs6000/e5500.md (e5500_load, e5500_fpload, e5500_store,
+ e5500_fpstore): Adjust.
+ * config/rs6000/e6500.md (e6500_load, e6500_fpload, e6500_store,
+ e6500_fpstore): Adjust.
+ * config/rs6000/mpc.md (mpccore-load, mpccore-store, mpccore-fpload):
+ Adjust.
+ * config/rs6000/power4.md (power4-load, power4-load-ext,
+ power4-load-ext-update, power4-load-ext-update-indexed,
+ power4-load-update-indexed, power4-load-update, power4-fpload,
+ power4-fpload-update, power4-store, power4-store-update,
+ power4-store-update-indexed, power4-fpstore, power4-fpstore-update):
+ Adjust.
+ * config/rs6000/power5.md (power5-load, power5-load-ext,
+ power5-load-ext-update, power5-load-ext-update-indexed,
+ power5-load-update-indexed, power5-load-update, power5-fpload,
+ power5-fpload-update, power5-store, power5-store-update,
+ power5-store-update-indexed, power5-fpstore, power5-fpstore-update):
+ Adjust.
+ * config/rs6000/power6.md (power6-load, power6-load-ext,
+ power6-load-update, power6-load-update-indexed,
+ power6-load-ext-update, power6-load-ext-update-indexed, power6-fpload,
+ power6-fpload-update, power6-store, power6-store-update,
+ power6-store-update-indexed, power6-fpstore, power6-fpstore-update):
+ Adjust.
+ * config/rs6000/power7.md (power7-load, power7-load-ext,
+ power7-load-update, power7-load-update-indexed,
+ power7-load-ext-update, power7-load-ext-update-indexed, power7-fpload,
+ power7-fpload-update, power7-store, power7-store-update,
+ power7-store-update-indexed, power7-fpstore, power7-fpstore-update):
+ Adjust.
+ * config/rs6000/power8.md (power8-load, power8-load-update,
+ power8-load-ext, power8-load-ext-update, power8-fpload,
+ power8-fpload-update, power8-store, power8-store-update-indexed,
+ power8-fpstore, power8-fpstore-update): Adjust.
+ * config/rs6000/rs64.md (rs64a-load, rs64a-store, rs64a-fpload):
+ Adjust.
+ * config/rs6000/titan.md (titan_lsu_load, titan_lsu_fpload,
+ titan_lsu_store, titan_lsu_fpstore): Adjust.
+ * config/rs6000/xfpu.md (fp-load, fp-store): Adjust.
+
+2014-05-07 Oleg Endo <olegendo@gcc.gnu.org>
+
+ PR target/60884
+ * config/sh/sh-mem.cc (sh_expand_strlen): Use loop when emitting
+ unrolled byte insns. Emit address increments after move insns.
+
+2014-05-07 David Malcolm <dmalcolm@redhat.com>
+
+ * gimple.h (gimple_builtin_call_types_compatible_p): Accept a
+ const_gimple, rather than a gimple.
+ (gimple_call_builtin_p): Likewise, for the three variants.
+
+ * gimple.c (gimple_builtin_call_types_compatible_p): Likewise.
+ (gimple_call_builtin_p): Likewise, for the three variants.
+
+2014-05-07 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
+
+ PR tree-optimization/61095
+ * tree-ssanames.c (get_nonzero_bits): Fix type extension in wi::shwi.
+
+2014-05-07 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/61034
+ * tree-ssa-alias.c (call_may_clobber_ref_p_1): Export.
+ (maybe_skip_until): Use translate to take into account
+ lattices when trying to do disambiguations.
+ (get_continuation_for_phi_1): Likewise.
+ (get_continuation_for_phi): Adjust for added translate arguments.
+ (walk_non_aliased_vuses): Likewise.
+ * tree-ssa-alias.h (get_continuation_for_phi): Adjust prototype.
+ (walk_non_aliased_vuses): Likewise.
+ (call_may_clobber_ref_p_1): Declare.
+ * tree-ssa-sccvn.c (vn_reference_lookup_3): Also disambiguate against
+ calls. Stop early if we are only supposed to disambiguate.
+ * tree-ssa-pre.c (translate_vuse_through_block): Adjust.
+
+2014-05-07 Joern Rennecke <joern.rennecke@embecosm.com>
+
+ * config/epiphany/epiphany.c (epiphany_handle_interrupt_attribute):
+ Emit an error when the function has arguments.
+
+2014-05-07 Thomas Schwinge <thomas@codesourcery.com>
+
+ * cfgloop.h (unswitch_loops): Remove.
+ * doc/passes.texi: Remove references to loop-unswitch.c
+ * timevar.def (TV_LOOP_UNSWITCH): Remove.
+
+2014-05-07 Evgeny Stupachenko <evstupac@gmail.com>
+
+ * tree-vect-data-refs.c (vect_grouped_load_supported): New
+ check for loads group of length 3.
+ (vect_permute_load_chain): New permutations for loads group of
+ length 3.
+ * tree-vect-stmts.c (vect_model_load_cost): Change cost
+ of vec_perm_shuffle for the new permutations.
+
+2014-05-07 Alan Lawrence <alan.lawrence@arm.com>
+
+ * config/aarch64/arm_neon.h (vtrn1_f32, vtrn1_p8, vtrn1_p16, vtrn1_s8,
+ vtrn1_s16, vtrn1_s32, vtrn1_u8, vtrn1_u16, vtrn1_u32, vtrn1q_f32,
+ vtrn1q_f64, vtrn1q_p8, vtrn1q_p16, vtrn1q_s8, vtrn1q_s16, vtrn1q_s32,
+ vtrn1q_s64, vtrn1q_u8, vtrn1q_u16, vtrn1q_u32, vtrn1q_u64, vtrn2_f32,
+ vtrn2_p8, vtrn2_p16, vtrn2_s8, vtrn2_s16, vtrn2_s32, vtrn2_u8,
+ vtrn2_u16, vtrn2_u32, vtrn2q_f32, vtrn2q_f64, vtrn2q_p8, vtrn2q_p16,
+ vtrn2q_s8, vtrn2q_s16, vtrn2q_s32, vtrn2q_s64, vtrn2q_u8, vtrn2q_u16,
+ vtrn2q_u32, vtrn2q_u64): Replace temporary asm with __builtin_shuffle.
+
+2014-05-07 Thomas Schwinge <thomas@codesourcery.com>
+
+ * loop-unswitch.c: Delete.
+
+2014-05-07 Richard Biener <rguenther@suse.de>
+
+ * config.gcc: Always set need_64bit_hwint to yes.
+
2014-05-07 Chung-Ju Wu <jasonwucj@gmail.com>
* config/nds32/nds32.h (HONOR_REG_ALLOC_ORDER): Have it in favor
* ipa-devirt.c (get_class_context): Allow POD to change to non-POD.
2014-05-05 Radovan Obradovic <robradovic@mips.com>
- Tom de Vries <tom@codesourcery.com>
+ Tom de Vries <tom@codesourcery.com>
- * target.def (call_fusage_contains_non_callee_clobbers): New DEFHOOKPOD.
+ * target.def (call_fusage_contains_non_callee_clobbers): New
+ DEFHOOKPOD.
* doc/tm.texi.in (@node Stack and Calling): Add Miscellaneous Register
Hooks to @menu.
(@node Miscellaneous Register Hooks): New node.
2014-05-05 Richard Biener <rguenther@suse.de>
PR middle-end/61010
- * fold-const.c (fold_binary_loc): Consistently avoid
- canonicalizing X & CST away from a CST that is the mask
- of a mode.
+ * fold-const.c (fold_binary_loc): Consistently avoid canonicalizing
+ X & CST away from a CST that is the mask of a mode.
2014-05-05 Jan-Benedict Glaw <jbglaw@lug-owl.de>
* doc/invoke.texi: Describe -fsanitize=float-divide-by-zero.
-2014-02-26 Kito Cheng <kito@0xlab.org>
+2014-05-02 Kito Cheng <kito@0xlab.org>
* defaults.h (HONOR_REG_ALLOC_ORDER): Change HONOR_REG_ALLOC_ORDER
to a C expression marco.
* doc/invoke.texi: Fix typo.
* tree-vrp.c: Fix typos.
- * gimple.c (infer_nonnull_range): Reorder operands of an &&
- condition.
+ * gimple.c (infer_nonnull_range): Reorder operands of an && condition.
2014-04-29 Zhenqiang Chen <zhenqiang.chen@linaro.org>
2014-04-28 Richard Biener <rguenther@suse.de>
* tree-pass.h (execute_pass_list): Adjust prototype.
- * passes.c (pass_manager::execute_early_local_passes):
- Adjust.
+ * passes.c (pass_manager::execute_early_local_passes): Adjust.
(do_per_function): Change callback signature, push all actual
work to the callbals.
(do_per_function_toporder): Likewise.
2014-04-25 Cary Coutant <ccoutant@google.com>
- PR debug/60929
+ PR debug/60929
* dwarf2out.c (should_move_die_to_comdat): A type definition
- can contain a subprogram definition, but don't move it to a
- comdat unit.
+ can contain a subprogram definition, but don't move it to a
+ comdat unit.
(clone_as_declaration): Copy DW_AT_abstract_origin attribute.
- (generate_skeleton_bottom_up): Remove DW_AT_object_pointer attribute
- from original DIE.
+ (generate_skeleton_bottom_up): Remove DW_AT_object_pointer attribute
+ from original DIE.
(clone_tree_hash): Rename to...
(clone_tree_partial): ...this; change callers. Copy
- DW_TAG_subprogram DIEs as declarations.
+ DW_TAG_subprogram DIEs as declarations.
(copy_decls_walk): Don't copy children of a declaration into a
- type unit.
+ type unit.
2014-04-25 H.J. Lu <hongjiu.lu@intel.com>
2014-04-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
- * config/arm/arm.c (arm_cortex_a8_tune): Initialise
- T16-related fields.
+ * config/arm/arm.c (arm_cortex_a8_tune): Initialise T16-related fields.
2014-04-25 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
clobbers.
2014-04-25 Radovan Obradovic <robradovic@mips.com>
- Tom de Vries <tom@codesourcery.com>
+ Tom de Vries <tom@codesourcery.com>
* rtlanal.c (find_all_hard_reg_sets): Add bool implicit parameter and
handle.
2014-04-24 Michael Meissner <meissner@linux.vnet.ibm.com>
* doc/extend.texi (PowerPC Built-in Functions): Document new
- powerpc extended divide, bcd, pack/unpack 128-bit, builtin
- functions.
+ powerpc extended divide, bcd, pack/unpack 128-bit, builtin functions.
(PowerPC AltiVec/VSX Built-in Functions): Likewise.
* config/rs6000/predicates.md (const_0_to_3_operand): New
support for decimal floating point builtin functions.
(rs6000_expand_ternop_builtin): Add checks for the new builtin
functions that take constant arguments.
- (rs6000_invalid_builtin): Add decimal floating point builtin
- support.
+ (rs6000_invalid_builtin): Add decimal floating point builtin support.
(rs6000_init_builtins): Setup long double, _Decimal64, and
_Decimal128 types for new builtin functions.
(builtin_function_type): Set the unsigned flags appropriately for
builtin functions.
(UNSPEC_CDTBCD): Likewise.
(UNSPEC_CBCDTD): Likewise.
- (UNSPEC_DIVE): Add support for new extended divide builtin
- functions.
+ (UNSPEC_DIVE): Add support for new extended divide builtin functions.
(UNSPEC_DIVEO): Likewise.
(UNSPEC_DIVEU): Likewise.
(UNSPEC_DIVEUO): Likewise.
(addg6s): Add new BCD builtin functions.
(cdtbcd): Likewise.
(cbcdtd): Likewise.
- (UNSPEC_DIV_EXTEND): Add support for new extended divide
- instructions.
+ (UNSPEC_DIV_EXTEND): Add support for new extended divide instructions.
(div_extend): Likewise.
(div<div_extend>_<mode>"): Likewise.
(FP128_64): Add support for new builtin functions to pack/unpack
* config/aarch64/aarch64.c (aarch64_evpc_tbl): Enable for bigendian.
2014-04-24 Radovan Obradovic <robradovic@mips.com>
- Tom de Vries <tom@codesourcery.com>
+ Tom de Vries <tom@codesourcery.com>
* reg-notes.def (REG_NOTE (CALL_DECL)): New reg-note REG_CALL_DECL.
* calls.c (expand_call, emit_library_call_value_1): Add REG_CALL_DECL
* emit-rtl.c (try_split): Same.
2014-04-24 Radovan Obradovic <robradovic@mips.com>
- Tom de Vries <tom@codesourcery.com>
+ Tom de Vries <tom@codesourcery.com>
* common.opt (fuse-caller-save): New option.
2014-04-24 Tejas Belagod <tejas.belagod@arm.com>
- * config/aarch64/aarch64.c (aarch64_evpc_tbl): Reverse order of elements
- for big-endian.
+ * config/aarch64/aarch64.c (aarch64_evpc_tbl): Reverse order of
+ elements for big-endian.
2014-04-24 Richard Biener <rguenther@suse.de>
(is_a_helper <const gimple_statement_catch *>::test): ...this.
(is_a_helper <const gimple_statement_resx>::test): Convert to...
(is_a_helper <const gimple_statement_resx *>::test): ...this.
- (is_a_helper <const gimple_statement_eh_dispatch>::test):
- Convert to...
- (is_a_helper <const gimple_statement_eh_dispatch *>::test):
- ...this.
- (is_a_helper <const gimple_statement_eh_filter>::test): Convert
- to...
+ (is_a_helper <const gimple_statement_eh_dispatch>::test): Convert to...
+ (is_a_helper <const gimple_statement_eh_dispatch *>::test): ...this.
+ (is_a_helper <const gimple_statement_eh_filter>::test): Convert to...
(is_a_helper <const gimple_statement_eh_filter *>::test): ...this.
(is_a_helper <const gimple_statement_omp_atomic_load>::test):
Convert to...
Convert to...
(is_a_helper <const gimple_statement_omp_atomic_store *>::test):
...this.
- (is_a_helper <const gimple_statement_omp_return>::test): Convert
- to...
+ (is_a_helper <const gimple_statement_omp_return>::test): Convert to...
(is_a_helper <const gimple_statement_omp_return *>::test): ...this.
(is_a_helper <const gimple_statement_omp_continue>::test): Convert
to...
(is_a_helper <const gimple_statement_omp_critical *>::test): ...this.
(is_a_helper <const gimple_statement_omp_for>::test): Convert to...
(is_a_helper <const gimple_statement_omp_for *>::test): ...this.
- (is_a_helper <const gimple_statement_omp_taskreg>::test): Convert
- to...
+ (is_a_helper <const gimple_statement_omp_taskreg>::test): Convert to...
(is_a_helper <const gimple_statement_omp_taskreg *>::test): ...this.
(is_a_helper <const gimple_statement_omp_parallel>::test): Convert
to...
(is_a_helper <const gimple_statement_omp_parallel *>::test): ...this.
- (is_a_helper <const gimple_statement_omp_target>::test): Convert
- to...
+ (is_a_helper <const gimple_statement_omp_target>::test): Convert to...
(is_a_helper <const gimple_statement_omp_target *>::test): ...this.
(is_a_helper <const gimple_statement_omp_sections>::test): Convert
to...
(is_a_helper <const gimple_statement_omp_sections *>::test): ...this.
- (is_a_helper <const gimple_statement_omp_single>::test): Convert
- to...
+ (is_a_helper <const gimple_statement_omp_single>::test): Convert to...
(is_a_helper <const gimple_statement_omp_single *>::test): ...this.
- (is_a_helper <const gimple_statement_omp_teams>::test): Convert
- to...
+ (is_a_helper <const gimple_statement_omp_teams>::test): Convert to...
(is_a_helper <const gimple_statement_omp_teams *>::test): ...this.
- (is_a_helper <const gimple_statement_omp_task>::test): Convert
- to...
+ (is_a_helper <const gimple_statement_omp_task>::test): Convert to...
(is_a_helper <const gimple_statement_omp_task *>::test): ...this.
(is_a_helper <const gimple_statement_phi>::test): Convert to...
(is_a_helper <const gimple_statement_phi *>::test): ...this.
- (is_a_helper <const gimple_statement_transaction>::test): Convert
- to...
+ (is_a_helper <const gimple_statement_transaction>::test): Convert to...
(is_a_helper <const gimple_statement_transaction *>::test): ...this.
- (is_a_helper <const gimple_statement_with_ops>::test): Convert
- to...
+ (is_a_helper <const gimple_statement_with_ops>::test): Convert to...
(is_a_helper <const gimple_statement_with_ops *>::test): ...this.
(is_a_helper <gimple_statement_with_ops>::test): Convert to...
(is_a_helper <gimple_statement_with_ops *>::test): ...this.
- (is_a_helper <const gimple_statement_with_memory_ops>::test):
- Convert to...
+ (is_a_helper <const gimple_statement_with_memory_ops>::test): Convert
+ to...
(is_a_helper <const gimple_statement_with_memory_ops *>::test):
...this.
- (is_a_helper <gimple_statement_with_memory_ops>::test): Convert
- to...
+ (is_a_helper <gimple_statement_with_memory_ops>::test): Convert to...
(is_a_helper <gimple_statement_with_memory_ops *>::test): ...this.
(gimple_use_ops): Update for removal of implicit pointer from the
invalidate outputs from statements that do not produce useful
outputs for threading.
-2014-04-23 Venkataramanan Kumar <venkataramanan.kumar@linaro.org>
+2014-04-23 Venkataramanan Kumar <venkataramanan.kumar@linaro.org>
* config/aarch64/aarch64.md (stack_protect_set, stack_protect_test)
(stack_protect_set_<mode>, stack_protect_test_<mode>): Add
2014-04-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
- * config/aarch64/aarch64.md (rev16<mode>2): New pattern.
- (rev16<mode>2_alt): Likewise.
- * config/aarch64/aarch64.c (aarch64_rtx_costs): Handle rev16 case.
- * config/arm/aarch-common.c (aarch_rev16_shright_mask_imm_p): New.
- (aarch_rev16_shleft_mask_imm_p): Likewise.
- (aarch_rev16_p_1): Likewise.
- (aarch_rev16_p): Likewise.
- * config/arm/aarch-common-protos.h (aarch_rev16_p): Declare extern.
- (aarch_rev16_shright_mask_imm_p): Likewise.
- (aarch_rev16_shleft_mask_imm_p): Likewise.
+ * config/aarch64/aarch64.md (rev16<mode>2): New pattern.
+ (rev16<mode>2_alt): Likewise.
+ * config/aarch64/aarch64.c (aarch64_rtx_costs): Handle rev16 case.
+ * config/arm/aarch-common.c (aarch_rev16_shright_mask_imm_p): New.
+ (aarch_rev16_shleft_mask_imm_p): Likewise.
+ (aarch_rev16_p_1): Likewise.
+ (aarch_rev16_p): Likewise.
+ * config/arm/aarch-common-protos.h (aarch_rev16_p): Declare extern.
+ (aarch_rev16_shright_mask_imm_p): Likewise.
+ (aarch_rev16_shleft_mask_imm_p): Likewise.
2014-04-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
- * config/arm/aarch-common-protos.h (alu_cost_table): Add rev field.
- * config/arm/aarch-cost-tables.h (generic_extra_costs): Specify
- rev cost.
- (cortex_a53_extra_costs): Likewise.
- (cortex_a57_extra_costs): Likewise.
- * config/arm/arm.c (cortexa9_extra_costs): Likewise.
- (cortexa7_extra_costs): Likewise.
- (cortexa8_extra_costs): Likewise.
- (cortexa12_extra_costs): Likewise.
- (cortexa15_extra_costs): Likewise.
- (v7m_extra_costs): Likewise.
- (arm_new_rtx_costs): Handle BSWAP.
+ * config/arm/aarch-common-protos.h (alu_cost_table): Add rev field.
+ * config/arm/aarch-cost-tables.h (generic_extra_costs): Specify
+ rev cost.
+ (cortex_a53_extra_costs): Likewise.
+ (cortex_a57_extra_costs): Likewise.
+ * config/arm/arm.c (cortexa9_extra_costs): Likewise.
+ (cortexa7_extra_costs): Likewise.
+ (cortexa8_extra_costs): Likewise.
+ (cortexa12_extra_costs): Likewise.
+ (cortexa15_extra_costs): Likewise.
+ (v7m_extra_costs): Likewise.
+ (arm_new_rtx_costs): Handle BSWAP.
2013-04-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
- * config/arm/arm.c (cortexa8_extra_costs): New table.
- (arm_cortex_a8_tune): New tuning struct.
- * config/arm/arm-cores.def (cortex-a8): Use cortex_a8 tuning struct.
+ * config/arm/arm.c (cortexa8_extra_costs): New table.
+ (arm_cortex_a8_tune): New tuning struct.
+ * config/arm/arm-cores.def (cortex-a8): Use cortex_a8 tuning struct.
2014-04-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
- * config/arm/arm.c (arm_new_rtx_costs): Handle FMA.
+ * config/arm/arm.c (arm_new_rtx_costs): Handle FMA.
2014-04-23 Richard Biener <rguenther@suse.de>
* Makefile.in (OBJS): Remove loop-unswitch.o.
- * loop-unswitch.c: Delete.
* tree-pass.h (make_pass_rtl_unswitch): Remove.
* passes.def (pass_rtl_unswitch): Likewise.
* loop-init.c (gate_rtl_unswitch): Likewise.
(has_32bit_hwmult): Rename to use_32bit_hwmult. Add support for
-mhwmult command line option.
(msp430_hwmult_enabled): Delete.
- (msp43o_output_labelref): Add support for -mhwmult command line
- option.
+ (msp43o_output_labelref): Add support for -mhwmult command line option.
* config/msp430/msp430.md (mulhisi3, umulhisi3, mulsidi3)
(umulsidi3): Likewise.
* config/msp430/msp430.opt (mmcu): Add Report attribute.
* gcc/config/aarch64/aarch64-simd.md (aarch64_s<optab><mode>):
Pattern extended.
- * config/aarch64/aarch64-simd-builtins.def (sqneg): Iterator
- extended.
+ * config/aarch64/aarch64-simd-builtins.def (sqneg): Iterator extended.
(sqabs): Likewise.
* config/aarch64/arm_neon.h (vqneg_s64): New intrinsic.
(vqnegd_s64): Likewise.
2014-04-22 Alex Velenko <Alex.Velenko@arm.com>
- * config/aarch64/aarch64-builtins.c (BUILTIN_VDQF_DF): Macro
- added.
- * config/aarch64/aarch64-simd-builtins.def (frintn): Use added
- macro.
- * config/aarch64/aarch64-simd.md (<frint_pattern>): Comment
- corrected.
+ * config/aarch64/aarch64-builtins.c (BUILTIN_VDQF_DF): Macro added.
+ * config/aarch64/aarch64-simd-builtins.def (frintn): Use added macro.
+ * config/aarch64/aarch64-simd.md (<frint_pattern>): Comment corrected.
* config/aarch64/aarch64.md (<frint_pattern>): Likewise.
* config/aarch64/arm_neon.h (vrnd_f64): Added.
(vrnda_f64): Likewise.
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