+2014-02-25 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
+
+ * config/rs6000/vector.md (*vector_ordered<mode>): Change split to
+ use canonical form for nor<mode>3.
+ (*vector_unordered<mode>): Likewise.
+
+2014-02-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ PR target/55426
+ * config/arm/arm.h (CANNOT_CHANGE_MODE_CLASS): Allow 128 to 64-bit
+ conversions.
+
+2014-02-25 Ilya Tocar <ilya.tocar@intel.com>
+
+ * common/config/i386/i386-common.c (OPTION_MASK_ISA_PREFETCHWT1_SET),
+ (OPTION_MASK_ISA_PREFETCHWT1_UNSET): New.
+ (ix86_handle_option): Handle OPT_mprefetchwt1.
+ * config/i386/cpuid.h (bit_PREFETCHWT1): New.
+ * config/i386/driver-i386.c (host_detect_local_cpu): Detect
+ PREFETCHWT1 CPUID.
+ * config/i386/i386-c.c (ix86_target_macros_internal): Handle
+ OPTION_MASK_ISA_PREFETCHWT1.
+ * config/i386/i386.c (ix86_target_string): Handle mprefetchwt1.
+ (PTA_PREFETCHWT1): New.
+ (ix86_option_override_internal): Handle PTA_PREFETCHWT1.
+ (ix86_valid_target_attribute_inner_p): Handle OPT_mprefetchwt1.
+ * config/i386/i386.h (TARGET_PREFETCHWT1), (TARGET_PREFETCHWT1_P):
+ New.
+ * config/i386/i386.md (prefetch): Check TARGET_PREFETCHWT1
+ (*prefetch_avx512pf_<mode>_: Change into ...
+ (*prefetch_prefetchwt1_<mode>: This.
+ * config/i386/i386.opt (mprefetchwt1): New.
+ * config/i386/xmmintrin.h (_mm_hint): Add _MM_HINT_ET1.
+ (_mm_prefetch): Handle intent to write.
+ * doc/invoke.texi (mprefetchwt1), (mno-prefetchwt1): Doccument.
+
+2014-02-25 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/60291
+ * emit-rtl.c (mem_attrs_htab): Remove.
+ (mem_attrs_htab_hash): Likewise.
+ (mem_attrs_htab_eq): Likewise.
+ (set_mem_attrs): Always allocate new mem-attrs when something
+ changed.
+ (init_emit_once): Do not allocate mem_attrs_htab.
+
+2014-02-25 Richard Biener <rguenther@suse.de>
+
+ PR lto/60319
+ * lto-opts.c (lto_write_options): Output non-explicit conservative
+ -fwrapv, -fno-trapv and -fno-strict-overflow.
+ * lto-wrapper.c (merge_and_complain): Handle merging those options.
+ (run_gcc): And pass them through.
+
+2014-02-25 Andrey Belevantsev <abel@ispras.ru>
+
+ * sel-sched.c (calculate_new_fences): New parameter ptime.
+ Calculate it as a maximum over all fence cycles.
+ (sel_sched_region_2): Adjust the call to calculate_new_fences.
+ Print the final schedule timing when sched_verbose.
+
+2014-02-25 Andrey Belevantsev <abel@ispras.ru>
+
+ PR rtl-optimization/60292
+ * sel-sched.c (fill_vec_av_set): Do not reset target availability
+ bit fot the fence instruction.
+
+2014-02-24 Alangi Derick <alangiderick@gmail.com>
+
+ * calls.h: Fix typo in comment.
+
+2014-02-24 John David Anglin <danglin@gcc.gnu.org>
+
+ * config/pa/pa.c (pa_output_move_double): Don't valididate when
+ adjusting offsetable addresses.
+
+2014-02-24 Guozhi Wei <carrot@google.com>
+
+ * sparseset.h (sparseset_pop): Fix the wrong index.
+
+2014-02-24 Walter Lee <walt@tilera.com>
+
+ * config.gcc (tilepro-*-*): Change to tilepro*-*-*.
+ (tilegx-*-linux*): Change to tilegx*-*-linux*; Support tilegxbe
+ triplet.
+ * common/config/tilegx/tilegx-common.c
+ (TARGET_DEFAULT_TARGET_FLAGS): Define.
+ * config/tilegx/linux.h (ASM_SPEC): Add endian_spec.
+ (LINK_SPEC): Ditto.
+ * config/tilegx/sync.md (atomic_test_and_set): Handle big endian.
+ * config/tilegx/tilegx.c (tilegx_return_in_msb): New.
+ (tilegx_gimplify_va_arg_expr): Handle big endian.
+ (tilegx_expand_unaligned_load): Ditto.
+ (tilegx_expand_unaligned_store): Ditto.
+ (TARGET_RETURN_IN_MSB): New.
+ * config/tilegx/tilegx.h (TARGET_DEFAULT): New.
+ (TARGET_ENDIAN_DEFAULT): New.
+ (TARGET_BIG_ENDIAN): Handle big endian.
+ (BYTES_BIG_ENDIAN): Ditto.
+ (WORDS_BIG_ENDIAN): Ditto.
+ (FLOAT_WORDS_BIG_ENDIAN): Ditto.
+ (ENDIAN_SPEC): New.
+ (EXTRA_SPECS): New.
+ * config/tilegx/tilegx.md (extv): Handle big endian.
+ (extzv): Ditto.
+ (insn_st<n>): Ditto.
+ (insn_st<n>_add<bitsuffix>): Ditto.
+ (insn_stnt<n>): Ditto.
+ (insn_stnt<n>_add<bitsuffix>):Ditto.
+ (vec_interleave_highv8qi): Handle big endian.
+ (vec_interleave_highv8qi_be): New.
+ (vec_interleave_highv8qi_le): New.
+ (insn_v1int_h): Handle big endian.
+ (vec_interleave_lowv8qi): Handle big endian.
+ (vec_interleave_lowv8qi_be): New.
+ (vec_interleave_lowv8qi_le): New.
+ (insn_v1int_l): Handle big endian.
+ (vec_interleave_highv4hi): Handle big endian.
+ (vec_interleave_highv4hi_be): New.
+ (vec_interleave_highv4hi_le): New.
+ (insn_v2int_h): Handle big endian.
+ (vec_interleave_lowv4hi): Handle big endian.
+ (vec_interleave_lowv4hi_be): New.
+ (vec_interleave_lowv4hi_le): New.
+ (insn_v2int_l): Handle big endian.
+ (vec_interleave_highv2si): Handle big endian.
+ (vec_interleave_highv2si_be): New.
+ (vec_interleave_highv2si_le): New.
+ (insn_v4int_h): Handle big endian.
+ (vec_interleave_lowv2si): Handle big endian.
+ (vec_interleave_lowv2si_be): New.
+ (vec_interleave_lowv2si_le): New.
+ (insn_v4int_l): Handle big endian.
+ * config/tilegx/tilegx.opt (mbig-endian): New option.
+ (mlittle-endian): New option.
+ * doc/install.texi: Document tilegxbe-linux.
+ * doc/invoke.texi: Document -mbig-endian and -mlittle-endian.
+
+2014-02-24 Martin Jambor <mjambor@suse.cz>
+
+ PR ipa/60266
+ * ipa-cp.c (propagate_constants_accross_call): Bail out early if
+ there are no parameter descriptors.
+
+2014-02-24 Andrey Belevantsev <abel@ispras.ru>
+
+ PR rtl-optimization/60268
+ * sched-rgn.c (haifa_find_rgns): Move the nr_regions_initial variable
+ initialization to ...
+ (sched_rgn_init): ... here.
+ (schedule_region): Check for SCHED_PRESSURE_NONE earlier.
+
+2014-02-23 David Holsgrove <david.holsgrove@xilinx.com>
+
+ * config/microblaze/microblaze.md: Correct ashrsi_reg / lshrsi_reg
+ names.
+
+2014-02-23 Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+
+ * config/microblaze/microblaze.h: Remove SECONDARY_MEMORY_NEEDED
+ definition.
+
+2014-02-23 David Holsgrove <david.holsgrove@xilinx.com>
+
+ * /config/microblaze/microblaze.c: Add microblaze_asm_output_mi_thunk
+ and define TARGET_ASM_OUTPUT_MI_THUNK and
+ TARGET_ASM_CAN_OUTPUT_MI_THUNK.
+
2014-02-23 David Holsgrove <david.holsgrove@xilinx.com>
* config/microblaze/predicates.md: Add cmp_op predicate.