+2016-10-12 Nathan Sidwell <nathan@acm.org>
+
+ * diagnostic.c (diagnostc_report_diagnostic): Fix formatting.
+
+2016-10-12 Pierre-Marie de Rodat <derodat@adacore.com>
+
+ * dwarf2out.c (int_loc_descriptor): Generate opcodes for another
+ equivalent 32-bit constant (modulo 2**32) when that yields
+ smaller instructions.
+ (size_of_int_loc_descriptor): Update accordingly.
+
+2016-10-12 Pierre-Marie de Rodat <derodat@adacore.com>
+
+ * dwarf2out.c (dwarf2out_early_global_decl): For nested
+ functions, call dwarf2out_decl on the parent function first.
+
+2016-10-12 Richard Biener <rguenther@suse.de>
+
+ * match.pd ((X /[ex] A) * A -> X): Remove unnecessary constraint
+ on the conversion.
+
+2016-10-12 Richard Biener <rguenther@suse.de>
+
+ * tree-ssa-propagate.c
+ (substitute_and_fold_dom_walker::before_dom_children): Do not
+ ignore ASSERT_EXPRs but only preserve them.
+ * tree-vrp.c (remove_range_assertions): Deal with ASSERT_EXPRs
+ that have been propagated into.
+ (vrp_finalize): Enable DCE for substitute_and_fold.
+
+2016-10-12 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/77920
+ * tree-vrp.c (simplify_div_or_mod_using_ranges): Simplify.
+ (simplify_min_or_max_using_ranges): Pass in gsi and use it.
+ (simplify_abs_using_ranges): Likewise.
+ (simplify_conversion_using_ranges): Likewise.
+ (simplify_stmt_using_ranges): Adjust.
+
+2016-10-12 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/77929
+ * tree-ssa-reassoc.c (optimize_range_tests_var_bound): Handle
+ (*ops)[ranges[i].idx]->op != ranges[i].exp case.
+
+2016-10-12 Aaron Sawdey <acsawdey@linux.vnet.ibm.com>
+
+ PR target/77934
+ * config/rs6000/vmx.md (vsx_concat_<mode>): The mtvsrdd instruction
+ needs a base register for arg 1.
+
+2016-10-12 Jakub Jelinek <jakub@redhat.com>
+
+ * common.opt (Wimplicit-fallthrough) Turn into alias to
+ -Wimplicit-fallthrough=3. Remove EnabledBy.
+ (Wimplicit-fallthrough=): New option.
+ * gimplify.c (warn_implicit_fallthrough_r): Use
+ OPT_Wimplicit_fallthrough_ instead of OPT_Wimplicit_fallthrough.
+ * doc/invoke.texi (-Wimplicit-fallthrough): Document as alias
+ to -Wimplicit-fallthrough=3.
+ (-Wimplicit-fallthrough=): Document.
+
+2016-10-11 Eric Botcazou <ebotcazou@adacore.com>
+
+ * config/sparc/sparc.c (emit_scc_insn): Remove direct support for EQ
+ and GEU in DImode if TARGET_SUBXC.
+ * config/sparc/sparc.md (seqdi<W:mode>_zero): Remove TARGET_SUBXC.
+ (seqdi<W:mode>_zero_subxc): Delete.
+ (neg_seqdi<W:mode>_zero): Remove TARGET_VIS3.
+ (neg_seqdi<W:mode>_zero_vis3): Delete.
+ (plus_seqdi<W:mode>_zero): Likewise.
+ (minus_seqdi<W:mode>_zero): Likewise.
+ (plus_plus_sltu<W:mode>): Accept only register.
+ (addx<W:mode>): Likewise.
+ (plus_sltu<W:mode>_vis3): Likewise.
+ (plus_plus_sltu<W:mode>_vis3): Likewise.
+ (neg_sgeu<W:mode>_vis3): Delete.
+ (minus_sgeu<W:mode>_vis3): Likewise.
+ (addxc<W:mode>): Accept only registers.
+ (neg_sltu<W:mode>_subxc): Write %%g0 instead of 0.
+ (minus_neg_sltu<W:mode>_subxc): Accept only register.
+ (neg_plus_sltu<W:mode>_subxc): Likewise.
+ (minus_sltu<W:mode>_subxc): Write %%g0 instead of 0.
+ (minus_minus_sltu<W:mode>_subxc): Accept only register.
+ (sgeu<W:mode>_insn_subxc): Delete.
+ (plus_sgeu<W:mode>_subxc): Likewise.
+ (subxc<W:mode>): Accept only register.
+ (scc splitter): Split always GEU again.
+
+2016-10-11 Jeff Law <law@redhat.com>
+
+ PR tree-optimization/77424
+ * tree-ssa-threadupdate.c (thread_through_all_blocks): Remove
+ dead conditionals. Assert that all e->aux fields are NULL.
+
+2016-10-11 David Malcolm <dmalcolm@redhat.com>
+
+ * print-rtl.c (print_rtx): Rename "i" to "idx". Split out the
+ operand-printing "switch" statement into...
+ (print_rtx_operand_code_0): ...this new function, ...
+ (print_rtx_operand_code_e): ...this new function, ...
+ (print_rtx_operand_codes_E_and_V): ...this new function, ...
+ (print_rtx_operand_code_i): ...this new function, ...
+ (print_rtx_operand_code_r): ...this new function, ...
+ (print_rtx_operand_code_u): ...this new function, ...
+ (print_rtx_operand): ...and this new function.
+
+2016-10-11 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/alpha/alpha-passes.def: New file.
+ * config/alpha/t-alpha: New file.
+ * config/alpha/alpha-protos.h (gcc::context, rtl_opt_pass): Declare.
+ (make_pass_handle_trap_shadows): New prototype.
+ (make_pass_align_insns): Ditto.
+ * config/alpha/alpha.c (alpha_option_override): Don't register
+ passes here.
+ * config.gcc (alpha*-*-*) Add alpha/t-alpha to tmake_file.
+
+2016-10-11 Michael Meissner <meissner@linux.vnet.ibm.com>
+
+ PR target/77924
+ * config/rs6000/rs6000.c (rs6000_init_builtins): Only create the
+ distinct __ibm128 IBM extended double type if long doubles are
+ 128-bits and the default format for long double is IEEE 128-bit.
+
+2016-10-11 Richard Biener <rguenther@suse.de>
+
+ * dwarf2out.c (DEBUG_STR_OFFSETS_SECTION): Remove conditional.
+ (init_sections_and_labels): Use DEBUG_DWO_STR_OFFSETS_SECTION.
+ (verify_die): New function.
+ (dwarf2out_finish): Call it.
+ (output_line_info): Handle case of -gsplit-dwarf without
+ DWARF2_ASM_LINE_DEBUG_INFO.
+
+2016-10-11 Richard Biener <rguenther@suse.de>
+
+ PR debug/77931
+ * gimple-low.c (lower_gimple_bind): Handle arbitrary common
+ sub-chains of BLOCK_VARS and gimple_bind_vars.
+
+2016-10-11 Venkataramanan Kumar <Venkataramanan.kumar@amd.com>
+
+ * config/i386/znver1.md : Fix imov/imovx load type reservations.
+
+2016-10-11 Eric Botcazou <ebotcazou@adacore.com>
+
+ * config/sparc/sparc.opt (msubxc): New option.
+ * doc/invoke.texi (SPARC options): Document it and tidy up.
+ * doc/tm.texi.in (Condition Codes): Adjust SPARC example.
+ * doc/tm.texi: Regenerate.
+ * config/sparc/sparc-modes.def (CC_NOOV): Rename into...
+ (CCNZ): ...this.
+ (CCX_NOOV): Rename into...
+ (CCXNZ): ...this.
+ (CCC): New.
+ (CCXC): Likewise.
+ * config/sparc/predicates.m (fcc_register_operand): Simplify.
+ (fcc0_register_operand): Likewise.
+ (icc_register_operand): New.
+ (icc_or_fcc_register_operand): Simplify.
+ (nz_comparison_operator): New.
+ (c_comparison_operator): Likewise.
+ (noov_compare_operator): Rename into...
+ (icc_comparison_operator): ...this. Use above predicates.
+ (noov_compare64_operator): Rename into...
+ (v9_comparison_operator): ...this and tidy up.
+ (fcc_comparison_operator): New.
+ (icc_or_fcc_comparison_operator): Likewise.
+ (v9_register_compare_operator): Rename info...
+ (v9_register_comparison_operator): ...this.
+ * config/sparc/sparc.c (TARGET_FIXED_CONDITION_CODE_REGS): Define.
+ (sparc_option_override): Remove redundant VIS masks and add MASK_SUBXC
+ for Niagara-7.
+ (sparc_fixed_condition_code_regs): New function.
+ (select_cc_mode): Remove ATTRIBUTE_UNUSED. Adjust for CCNZ/CCXNZ
+ renaming and add support for CCC/CCXC.
+ (output_cbranch): Likewise.
+ (sparc_print_operand): Likewise.
+ (gen_v9_scc): Remove obsolete assertion.
+ (emit_scc_insn): Emit RTL directly for EQ and NE. Add direct support
+ for EQ in DImode if TARGET_SUBXC. Remove test on TARGET_VIS3 for GEU.
+ (output_cbcond): Remove bogus handling of CC modes.
+ (sparc_register_move_cost): Return 100 for NO_REGS.
+ * config/sparc/sparc.md (W): New mode iterator.
+ (length): Adjust for noov_compare64_operator renaming.
+ (cmpsi_sne): New instruction.
+ (cmpdi_sne): Likewise.
+ (seqdi_special): Delete.
+ (seqdi_special): Likewise.
+ (snesi<P:mode>_special): Likewise.
+ (snedi_special): Likewise.
+ (snedi_special_vis3): Likewise.
+ (snesi patterns): Use W iterator.
+ (snedi patterns): Likewise. Add TARGET_SUBXC patterns.
+ (sltu patterns): Likewise.
+ (sgeu patterns): Likewise.
+ (scc splitter): Do not split GEU in DImode if TARGET_SUBXC.
+ (normal_branch): Use icc_comparison_operator predicate.
+ (inverted_branch): Likewise.
+ (cbcond_sp32): Use comparison_operator predicate.
+ (cbcond_sp64): Likewise.
+ (normal_int_branch_sp64): Adjust for renaming
+ (inverted_int_branch_sp64): Likewise.
+ (mov<I:mode>_cc_reg_sp64): Likewise.
+ (movsf_cc_reg_sp6): Likewise.
+ (movdf_cc_reg_sp64): Likewise.
+ (movtf_cc_reg_hq_sp64): Likewise.
+ (movtf_cc_reg_sp64): Likewise.
+ (mov<I:mode>_cc_v9): Use icc_or_fcc_comparison_operator predicate.
+ (movsf_cc_v9): Likewise.
+ (movdf_cc_v9): Likewise.
+ (movtf_cc_hq_v9): Likewise.
+ (movtf_cc_v9): Likewise.
+ (adddi3): Call gen_adddi3_sp32.
+ (adddi3_insn_sp32): Rename to...
+ (adddi3_sp32): ...this. Accept only register_operand as operand #1
+ and use CCCmode for the carry.
+ (addx_extend_sp32): Use CCCmode for the carry.
+ (addx_extend_sp64): Delete.
+ (adddi3_extend_sp32): Use CCCmode for the carry.
+ (cmp_plus patterns): Use CCNZ/CCXNZ mode and add C variants.
+ (subdi3): Call gen_subdi3_sp32.
+ (subdi3_insn_sp32): Rename to...
+ (subdi3_sp32): ...this and use CCmode for the carry.
+ (subx_extend_sp32): Use CCCmode for the carry.
+ (subx_extend_sp64): Delete.
+ (subdi3_extend_sp32): Use CCmode for the carry.
+ (cmp_minus patterns): Use CCNZ/CCXNZ mode and add C variants.
+ (negdi3): Call gen_negdi3_sp32.
+ (negdi3_sp32): Use CCCmode for the carry.
+ (cmp_neg patterns): Use CCNZ/CCXNZ mode and add C variants.
+ (cmp_nz_ashift_1): Use CCNZ mode.
+ (cmp_nz_set_ashift_1): Likewise.
+ (ctrapsi4): Use comparison_operator predicate.
+ (ctrapdi4): Likewise.
+ (trapsi_insn): Use icc_comparison_operator predicate.
+ (trapdi_insn): Likewise.
+ (edge8 patterns): Use CCNZmode.
+ (edge16 patterns): Likewise.
+ (edge32 patterns): Likewise.
+
+2016-10-11 Eric Botcazou <ebotcazou@adacore.com>
+
+ * config/visium/visium-modes.def (CC_NOOV): Rename into...
+ (CCNZ): ...this.
+ (CC_BTST): Rename into...
+ (CCC): ...this.
+ * config/visium/predicates.md (real_add_operand): New.
+ (visium_btst_operator): Rename into...
+ (visium_equality_comparison_operator): ...this.
+ (visium_noov_operator): Rename into...
+ (visium_nz_comparison_operator): ...this.
+ (visium_c_comparison_operator): New.
+ (visium_branch_operator): Adjust and deal with all CC modes.
+ * config/visium/visium.c (visium_adjust_cost): Adjust.
+ (visium_split_double_add): Use the *_set_carry patterns.
+ (visium_select_cc_mode): Add support for CCC mode and adjust.
+ (output_cbranch): Adjust and use the carry-based operators for
+ floating-point comparisons.
+ * config/visium/visium.md (flags_subst_arith): Adjust.
+ (addsi3_insn_set_carry): New instruction.
+ (subsi3_insn_set_carry): Likewise.
+ (negsi2_insn_set_carry): Likewise.
+ (btst): Adjust.
+ (cmp<mode>_sne): Likewise.
+ (cbranch<mode>4): Use ordered_comparison_operator.
+ (cbranch<mode>4_insn): Likewise.
+ (cbranchsi4_btst_insn): Adjust.
+
+2016-10-11 Tom de Vries <tom@codesourcery.com>
+
+ PR middle-end/77558
+ * builtins.c (std_canonical_va_list_type): Remove RECORD_TYPE
+ special-casing.
+
+2016-10-11 Eric Botcazou <ebotcazou@adacore.com>
+
+ * tree.h (build_complex_type): Add second parameter with default.
+ * tree.c (build_complex_type): Add NAMED second parameter and adjust
+ recursive call. Create a TYPE_DECL only if NAMED is true.
+ (build_common_tree_nodes): Pass true in calls to build_complex_type.
+
+2016-10-11 Georg-Johann Lay <avr@gjlay.de>
+
+ New avr-passes.def to register AVR specific passes.
+
+ * config/avr/avr-passes.def: New file.
+ * config/avr/t-avr (PASSES_EXTRA): Add avr-passes.def.
+ * config/avr/avr-protos.h (gcc::context, rtl_opt_pass): Declare.
+ (make_avr_pass_recompute_note): New proto.
+ * config/avr/avr.c (make_avr_pass_recompute_notes): New function.
+ (avr_pass_recompute_notes): Use anonymous namespace.
+ (avr_register_passes): Remove function...
+ (avr_option_override): ...and its call.
+
+2016-10-11 Robert Suchanek <robert.suchanek@imgtec.com>
+
+ * config/mips/mips-cpus.def: Replace PTF_AVOID_BRANCHLIKELY with
+ PTF_AVOID_BRANCHLIKELY_ALWAYS for generic architecture and with
+ PTF_AVOID_BRANCHLIKELY_SPEED for others.
+ (mips2, mips3, mips4): Add PTF_AVOID_BRANCHLIKELY_SIZE to tune
+ flags.
+ * config/mips/mips.c (mips_option_override): Enable the branch
+ likely depending on the tune flags and optimization level.
+ * config/mips/mips.h (PTF_AVOID_BRANCHLIKELY): Remove.
+ (PTF_AVOID_BRANCHLIKELY_SPEED): Define.
+ (PTF_AVOID_BRANCHLIKELY_SIZE): Likewise.
+ (PTF_AVOID_BRANCHLIKELY_ALWAYS): Likewise.
+
+2016-10-11 Richard Biener <rguenther@suse.de>
+
+ * lto-streamer-out.c (collect_block_tree_leafs): New helper.
+ (output_function): Properly stream the whole block tree.
+ * lto-streamer-in.c (input_function): Likewise.
+
2016-10-11 Marek Polacek <polacek@redhat.com>
* Makefile.in (C_COMMON_OBJS): Add c-family/c-warn.o.
2016-10-10 Jeff Law <law@redhat.com>
- PR tree-optimization/71947
+ PR tree-optimization/71947
* tree-ssa-dom.c (cprop_into_stmt): Avoid replacing A with B, then
B with A within a single statement.
* config/aarch64/aarch64-arches.def (AARCH64_ARCH): #undef at the end.
* config/aarch64/aarch64-cores.def (AARCH64_CORE): Likewise.
- * config/aarch64/aarch64-fusion-pairs.def (AARCH64_FUSION_PAIR): Likewise.
- * config/aarch64/aarch64-option-extensions.def (AARCH64_OPT_EXTENSION): Likewise.
- * config/aarch64/aarch64-tuning-flags.def (AARCH64_EXTRA_TUNING_OPTION): Likewise.
+ * config/aarch64/aarch64-fusion-pairs.def (AARCH64_FUSION_PAIR):
+ Likewise.
+ * config/aarch64/aarch64-option-extensions.def (AARCH64_OPT_EXTENSION):
+ Likewise.
+ * config/aarch64/aarch64-tuning-flags.def (AARCH64_EXTRA_TUNING_OPTION):
+ Likewise.
* config/aarch64/aarch64-opts.h (AARCH64_CORE): Don't #undef here.
(AARCH64_ARCH): Likewise.
- * common/config/aarch64/aarch64-common.c (AARCH64_OPT_EXTENSION): Likewise.
+ * common/config/aarch64/aarch64-common.c (AARCH64_OPT_EXTENSION):
+ Likewise.
(AARCH64_CORE): Likewise.
(AARCH64_ARCH): Likewise.
* config/aarch64/aarch64-protos.h (AARCH64_FUSION_PAIR): Likewise.
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