+2017-08-01 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/81181
+ * tree-ssa-pre.c (compute_antic_aux): Defer clean() to ...
+ (compute_antic): ... end of iteration here.
+
+2017-08-01 James Greenhalgh <james.greenhalgh@arm.com>
+
+ * common.opt (ftree-vectorize): No longer set flag_tree_vectorize.
+ (ftree-loop-vectorize): Set as EnabledBy ftree-vectorize.
+ (ftree-slp-vectorize): Likewise.
+ * omp-expand (expand_omp_simd): Remove flag_tree_vectorize, as it
+ can no longer be set independent of flag_tree_loop_vectorize.
+ * omp-general.c (emp_max_vf): Likewise.
+ * opts.c (enable_fdo_optimizations): Remove references to
+ flag_tree_vectorize, these are now implicit.
+ (common_handle_option): Remove handling for OPT_ftree_vectorize,
+ and leave it for the options machinery.
+
+2017-08-01 Martin Liska <mliska@suse.cz>
+
+ PR middle-end/70140
+ * builtins.c (expand_builtin_memcpy_args): Remove.
+ (expand_builtin_memcpy): Call newly added function
+ expand_builtin_memory_copy_args.
+ (expand_builtin_memcpy_with_bounds): Likewise.
+ (expand_builtin_mempcpy): Remove last argument.
+ (expand_builtin_mempcpy_with_bounds): Likewise.
+ (expand_builtin_memory_copy_args): New function created from
+ expand_builtin_mempcpy_args with small modifications.
+ (expand_builtin_mempcpy_args): Remove.
+ (expand_builtin_stpcpy): Remove unused argument.
+ (expand_builtin): Likewise.
+ (expand_builtin_with_bounds): Likewise.
+
+2017-08-01 Uros Bizjak <ubizjak@gmail.com>
+
+ PR target/81641
+ * config/i386/i386.c (ix86_print_operand_address_as): For -masm=intel
+ print "ds:" only for immediates in generic address space.
+
+2017-08-01 Uros Bizjak <ubizjak@gmail.com>
+
+ PR target/81639
+ * config/i386/i386.c (ix86_funciton_naked): New prototype.
+ (ix86_function_ok_for_sibcall): Return false for naked functions.
+
+2017-08-01 Richard Biener <rguenther@suse.de>
+
+ * tree-ssa-pre.c (print_pre_expr): Handle NULL expr.
+ (compute_antic): Seed worklist with exit block predecessors.
+ * cfganal.c (dfs_find_deadend): For a cycle return the source
+ of the edge closing it.
+
+2017-08-01 Tamar Christina <tamar.christina@arm.com>
+
+ * config/aarch64/aarch64.c
+ (aarch64_can_const_movi_rtx_p): Move 0 check.
+
+2017-08-01 Bin Cheng <bin.cheng@arm.com>
+
+ * tree.h (POINTER_TYPE_OVERFLOW_UNDEFINED): Delete.
+ * fold-const.c (fold_comparison, fold_binary_loc): Delete use of
+ above macro.
+ * match.pd: Ditto in address comparison pattern.
+
+2017-08-01 Bin Cheng <bin.cheng@arm.com>
+
+ PR tree-optimization/81627
+ * tree-predcom.c (prepare_finalizers): Always rewrite into loop
+ closed ssa form for store-store chain.
+
+2017-08-01 Bin Cheng <bin.cheng@arm.com>
+
+ PR tree-optimization/81620
+ * tree-predcom.c (add_ref_to_chain): Don't set has_max_use_after
+ for store-store chain.
+
+2017-08-01 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/81588
+ * tree-ssa-reassoc.c (optimize_range_tests_var_bound): If
+ ranges[i].in_p, invert comparison code ccode. For >/>=,
+ swap rhs1 and rhs2 and comparison code unconditionally,
+ for </<= don't do that. Don't swap rhs1/rhs2 again if
+ ranges[i].in_p, instead invert comparison code ccode if
+ opcode or oe->rank is BIT_IOR_EXPR.
+
+ PR target/80846
+ * optabs.def (vec_extract_optab, vec_init_optab): Change from
+ a direct optab to conversion optab.
+ * optabs.c (expand_vector_broadcast): Use convert_optab_handler
+ with GET_MODE_INNER as last argument instead of optab_handler.
+ * expmed.c (extract_bit_field_1): Likewise. Use vector from
+ vector extraction if possible and optab is available.
+ * expr.c (store_constructor): Use convert_optab_handler instead
+ of optab_handler. Use vector initialization from smaller
+ vectors if possible and optab is available.
+ * tree-vect-stmts.c (vectorizable_load): Likewise.
+ * doc/md.texi (vec_extract, vec_init): Document that the optabs
+ now have two modes.
+ * config/i386/i386.c (ix86_expand_vector_init): Handle expansion
+ of vec_init from half-sized vectors with the same element mode.
+ * config/i386/sse.md (ssehalfvecmode): Add V4TI case.
+ (ssehalfvecmodelower, ssescalarmodelower): New mode attributes.
+ (reduc_plus_scal_v8df, reduc_plus_scal_v4df, reduc_plus_scal_v2df,
+ reduc_plus_scal_v16sf, reduc_plus_scal_v8sf, reduc_plus_scal_v4sf,
+ reduc_<code>_scal_<mode>, reduc_umin_scal_v8hi): Add element mode
+ after mode in gen_vec_extract* calls.
+ (vec_extract<mode>): Renamed to ...
+ (vec_extract<mode><ssescalarmodelower>): ... this.
+ (vec_extract<mode><ssehalfvecmodelower>): New expander.
+ (rotl<mode>3, rotr<mode>3, <shift_insn><mode>3, ashrv2di3): Add
+ element mode after mode in gen_vec_init* calls.
+ (VEC_INIT_HALF_MODE): New mode iterator.
+ (vec_init<mode>): Renamed to ...
+ (vec_init<mode><ssescalarmodelower>): ... this.
+ (vec_init<mode><ssehalfvecmodelower>): New expander.
+ * config/i386/mmx.md (vec_extractv2sf): Renamed to ...
+ (vec_extractv2sfsf): ... this.
+ (vec_initv2sf): Renamed to ...
+ (vec_initv2sfsf): ... this.
+ (vec_extractv2si): Renamed to ...
+ (vec_extractv2sisi): ... this.
+ (vec_initv2si): Renamed to ...
+ (vec_initv2sisi): ... this.
+ (vec_extractv4hi): Renamed to ...
+ (vec_extractv4hihi): ... this.
+ (vec_initv4hi): Renamed to ...
+ (vec_initv4hihi): ... this.
+ (vec_extractv8qi): Renamed to ...
+ (vec_extractv8qiqi): ... this.
+ (vec_initv8qi): Renamed to ...
+ (vec_initv8qiqi): ... this.
+ * config/rs6000/vector.md (VEC_base_l): New mode attribute.
+ (vec_init<mode>): Renamed to ...
+ (vec_init<mode><VEC_base_l>): ... this.
+ (vec_extract<mode>): Renamed to ...
+ (vec_extract<mode><VEC_base_l>): ... this.
+ * config/rs6000/paired.md (vec_initv2sf): Renamed to ...
+ (vec_initv2sfsf): ... this.
+ * config/rs6000/altivec.md (splitter, altivec_copysign_v4sf3,
+ vec_unpacku_hi_v16qi, vec_unpacku_hi_v8hi, vec_unpacku_lo_v16qi,
+ vec_unpacku_lo_v8hi, mulv16qi3, altivec_vreve<mode>2): Add
+ element mode after mode in gen_vec_init* calls.
+ * config/aarch64/aarch64-simd.md (vec_init<mode>): Renamed to ...
+ (vec_init<mode><Vel>): ... this.
+ (vec_extract<mode>): Renamed to ...
+ (vec_extract<mode><Vel>): ... this.
+ * config/aarch64/iterators.md (Vel): New mode attribute.
+ * config/s390/s390.c (s390_expand_vec_strlen, s390_expand_vec_movstr):
+ Add element mode after mode in gen_vec_extract* calls.
+ * config/s390/vector.md (non_vec_l): New mode attribute.
+ (vec_extract<mode>): Renamed to ...
+ (vec_extract<mode><non_vec_l>): ... this.
+ (vec_init<mode>): Renamed to ...
+ (vec_init<mode><non_vec_l>): ... this.
+ * config/s390/s390-builtins.def (s390_vlgvb, s390_vlgvh, s390_vlgvf,
+ s390_vlgvf_flt, s390_vlgvg, s390_vlgvg_dbl): Add element mode after
+ vec_extract mode.
+ * config/arm/iterators.md (V_elem_l): New mode attribute.
+ * config/arm/neon.md (vec_extract<mode>): Renamed to ...
+ (vec_extract<mode><V_elem_l>): ... this.
+ (vec_extractv2di): Renamed to ...
+ (vec_extractv2didi): ... this.
+ (vec_init<mode>): Renamed to ...
+ (vec_init<mode><V_elem_l>): ... this.
+ (reduc_plus_scal_<mode>, reduc_plus_scal_v2di, reduc_smin_scal_<mode>,
+ reduc_smax_scal_<mode>, reduc_umin_scal_<mode>,
+ reduc_umax_scal_<mode>, neon_vget_lane<mode>, neon_vget_laneu<mode>):
+ Add element mode after gen_vec_extract* calls.
+ * config/mips/mips-msa.md (vec_init<mode>): Renamed to ...
+ (vec_init<mode><unitmode>): ... this.
+ (vec_extract<mode>): Renamed to ...
+ (vec_extract<mode><unitmode>): ... this.
+ * config/mips/loongson.md (vec_init<mode>): Renamed to ...
+ (vec_init<mode><unitmode>): ... this.
+ * config/mips/mips-ps-3d.md (vec_initv2sf): Renamed to ...
+ (vec_initv2sfsf): ... this.
+ (vec_extractv2sf): Renamed to ...
+ (vec_extractv2sfsf): ... this.
+ (reduc_plus_scal_v2sf, reduc_smin_scal_v2sf, reduc_smax_scal_v2sf):
+ Add element mode after gen_vec_extract* calls.
+ * config/mips/mips.md (unitmode): New mode iterator.
+ * config/spu/spu.c (spu_expand_prologue, spu_allocate_stack,
+ spu_builtin_extract): Add element mode after gen_vec_extract* calls.
+ * config/spu/spu.md (inner_l): New mode attribute.
+ (vec_init<mode>): Renamed to ...
+ (vec_init<mode><inner_l>): ... this.
+ (vec_extract<mode>): Renamed to ...
+ (vec_extract<mode><inner_l>): ... this.
+ * config/sparc/sparc.md (veltmode): New mode iterator.
+ (vec_init<VMALL:mode>): Renamed to ...
+ (vec_init<VMALL:mode><VMALL:veltmode>): ... this.
+ * config/ia64/vect.md (vec_initv2si): Renamed to ...
+ (vec_initv2sisi): ... this.
+ (vec_initv2sf): Renamed to ...
+ (vec_initv2sfsf): ... this.
+ (vec_extractv2sf): Renamed to ...
+ (vec_extractv2sfsf): ... this.
+ * config/powerpcspe/vector.md (VEC_base_l): New mode attribute.
+ (vec_init<mode>): Renamed to ...
+ (vec_init<mode><VEC_base_l>): ... this.
+ (vec_extract<mode>): Renamed to ...
+ (vec_extract<mode><VEC_base_l>): ... this.
+ * config/powerpcspe/paired.md (vec_initv2sf): Renamed to ...
+ (vec_initv2sfsf): ... this.
+ * config/powerpcspe/altivec.md (splitter, altivec_copysign_v4sf3,
+ vec_unpacku_hi_v16qi, vec_unpacku_hi_v8hi, vec_unpacku_lo_v16qi,
+ vec_unpacku_lo_v8hi, mulv16qi3): Add element mode after mode in
+ gen_vec_init* calls.
+
+2017-08-01 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/81297
+ * tree-vrp.c (get_single_symbol): Remove assert, instead drop
+ TREE_OVERFLOW from INTEGER_CSTs.
+
+2017-07-31 Segher Boessenkool <segher@kernel.crashing.org>
+
+ * config/rs6000/rs6000.c (enum rs6000_reg_type): Delete trailing comma.
+
2017-07-31 Carl Love <cel@us.ibm.com>
* config/rs6000/rs6000-c: Add support for built-in functions
vector double vec_xl_be (signed long long, double *);
vector float vec_xl_be (signed long long, float *);
* config/rs6000/altivec.h (vec_xl_be): Add #define.
- * config/rs6000/rs6000-builtin.def (XL_BE_V16QI, XL_BE_V8HI, XL_BE_V4SI,
- XL_BE_V2DI, XL_BE_V4SF, XL_BE_V2DF, XL_BE): Add definitions for the builtins.
+ * config/rs6000/rs6000-builtin.def (XL_BE_V16QI, XL_BE_V8HI, XL_BE_V4SI)
+ XL_BE_V2DI, XL_BE_V4SF, XL_BE_V2DF, XL_BE): Add definitions
+ for the builtins.
* config/rs6000/rs6000.c (altivec_expand_xl_be_builtin): Add function.
- (altivec_expand_builtin): Add switch statement to call altivec_expand_xl_be
- for each builtin.
+ (altivec_expand_builtin): Add switch statement to call
+ altivec_expand_xl_be for each builtin.
(altivec_init_builtins): Add def_builtin for _builtin_vsx_le_be_v8hi,
- __builtin_vsx_le_be_v4si, __builtin_vsx_le_be_v2di, __builtin_vsx_le_be_v4sf,
- __builtin_vsx_le_be_v2df, __builtin_vsx_le_be_v16qi.
+ __builtin_vsx_le_be_v4si, __builtin_vsx_le_be_v2di,
+ __builtin_vsx_le_be_v4sf, __builtin_vsx_le_be_v2df,
+ __builtin_vsx_le_be_v16qi.
* doc/extend.texi: Update the built-in documentation file for the
new built-in functions.
projects / gcc.git / blobdiff