[AArch64] Fix register clobber in, aarch64_ashr_sisd_or_int_<mode>3 split.

[gcc.git] / gcc / ChangeLog

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+2014-06-30  Marcus Shawcroft  <marcus.shawcroft@arm.com>
+
+       PR target/61633
+       * config/aarch64/aarch64.md (*aarch64_ashr_sisd_or_int_<mode>3):
+       Add alternative; make early clobber.  Adjust both split patterns
+       to use operand 0 as the working register.
+
+2014-06-30  Jakub Jelinek  <jakub@redhat.com>
+
+       * ira-build.c (sort_conflict_id_map): Don't call
+       qsort if num is 0, as ira_object_id_map might be NULL, or 1.
+
+2014-06-30  Zhenqiang Chen  <zhenqiang.chen@linaro.org>
+
+       * loop-invariant.c (get_inv_cost): Handle register class.
+       (gain_for_invariant): Check the register pressure of the inv
+       and its overlapped register class, other than all.
+
+2014-06-30  Gerald Pfeifer  <gerald@pfeifer.com>
+
+       * doc/invoke.texi (Optimize Options): Fix descriptions of
+       ipa-cp-loop-hint-bonus and ipa-cp-array-index-hint-bonus.
+
 2014-06-29  David Wohlferd <dw@LimeGreenSocks.com>
 
        * doc/extend.texi (Function Attributes): Update 'naked' attribute