+2014-09-17 Jan Hubicka <hubicka@ucw.cz>
+
+ * ipa-devirt.c (type_pair, default_hashset_traits): New types.
+ (odr_types_equivalent_p): Use pair hash.
+ (odr_subtypes_equivalent_p): Likewise, do structural compare
+ on ODR types that may be mismatched.
+ (warn_odr): Support warning when only one field is given.
+ (odr_types_equivalent_p): Strenghten comparsions made;
+ support VOIDtype.
+ (add_type_duplicate): Update VISITED hash set.
+
+2014-09-17 Sebastian Huber <sebastian.huber@embedded-brains.de>
+
+ * config.gcc (*-*-rtems*): Default to 'rtems' thread model.
+ Enable selection of 'posix' or no thread model.
+
+2014-09-17 Andrew Stubbs <ams@codesourcery.com>
+
+ * config/arm/arm.c (arm_option_override): Reject -mfpu=neon
+ when architecture is older than ARMv7.
+
+2014-09-16 John David Anglin <danglin@gcc.gnu.org>
+
+ PR target/61853
+ * config/pa/pa.c (pa_function_value): Directly handle aggregates
+ that fit exactly in a word or double word.
+
+2014-09-16 Ilya Tocar <ilya.tocar@intel.com>
+
+ * config/i386/driver-i386.c (host_detect_local_cpu): Detect lack of
+ zmm/k regs support.
+
+2014-09-16 Alexander Ivchenko <alexander.ivchenko@intel.com>
+ Maxim Kuznetsov <maxim.kuznetsov@intel.com>
+ Anna Tikhonova <anna.tikhonova@intel.com>
+ Ilya Tocar <ilya.tocar@intel.com>
+ Andrey Turetskiy <andrey.turetskiy@intel.com>
+ Ilya Verbin <ilya.verbin@intel.com>
+ Kirill Yukhin <kirill.yukhin@intel.com>
+ Michael Zolotukhin <michael.v.zolotukhin@intel.com>
+
+ * config/i386/i386.c
+ (ix86_expand_vector_extract): Handle V32HI and V64QI modes.
+ * config/i386/sse.md
+ (define_mode_iterator VI48F_256): New.
+ (define_mode_attr extract_type): Ditto.
+ (define_mode_attr extract_suf): Ditto.
+ (define_mode_iterator AVX512_VEC): Ditto.
+ (define_expand
+ "<extract_type>_vextract<shuffletype><extract_suf>_mask"): Use
+ AVX512_VEC.
+ (define_insn "avx512dq_vextract<shuffletype>64x2_1_maskm"): New.
+ (define_insn
+ "<mask_codefor>avx512dq_vextract<shuffletype>64x2_1<mask_name>"):
+ Ditto.
+ (define_mode_attr extract_type_2): Ditto.
+ (define_mode_attr extract_suf_2): Ditto.
+ (define_mode_iterator AVX512_VEC_2): Ditto.
+ (define_expand
+ "<extract_type_2>_vextract<shuffletype><extract_suf_2>_mask"): Use
+ AVX512_VEC_2 mode iterator.
+ (define_insn "vec_extract_hi_<mode>_maskm"): Ditto.
+ (define_expand "avx512vl_vextractf128<mode>"): Ditto.
+ (define_insn_and_split "vec_extract_lo_<mode>"): Delete.
+ (define_insn "vec_extract_lo_<mode><mask_name>"): New.
+ (define_split for V16FI mode): Ditto.
+ (define_insn_and_split "vec_extract_lo_<mode>"): Delete.
+ (define_insn "vec_extract_lo_<mode><mask_name>"): New.
+ (define_split for VI8F_256 mode): Ditto.
+ (define_insn "vec_extract_hi_<mode><mask_name>"): Add masking.
+ (define_insn_and_split "vec_extract_lo_<mode>"): Delete.
+ (define_insn "vec_extract_lo_<mode><mask_name>"): New.
+ (define_split for VI4F_256 mode): Ditto.
+ (define_insn "vec_extract_lo_<mode>_maskm"): Ditto.
+ (define_insn "vec_extract_hi_<mode>_maskm"): Ditto.
+ (define_insn "vec_extract_hi_<mode><mask_name>"): Add masking.
+ (define_mode_iterator VEC_EXTRACT_MODE): Add V64QI and V32HI modes.
+ (define_insn "vcvtph2ps<mask_name>"): Fix pattern condition.
+ (define_insn "avx512f_vextract<shuffletype>32x4_1_maskm"): Ditto.
+ (define_insn "<mask_codefor>avx512f_vextract<shuffletype>32x4_1<mask_name>"):
+ Update `type' attribute, remove explicit `memory' attribute calculation.
+
+2014-09-16 Kito Cheng <kito@0xlab.org>
+
+ * ira.c (ira): Don't initialize ira_spilled_reg_stack_slots and
+ ira_spilled_reg_stack_slots_num if using lra.
+ (do_reload): Remove release ira_spilled_reg_stack_slots part.
+ * ira-color.c (ira_sort_regnos_for_alter_reg): Add assertion to
+ make sure not using lra.
+ (ira_reuse_stack_slot): Likewise.
+ (ira_mark_new_stack_slot): Likewise.
+
+2014-09-15 Andi Kleen <ak@linux.intel.com>
+
+ * function.c (allocate_struct_function): Force
+ DECL_NO_INSTRUMENT_FUNCTION_ENTRY_EXIT to one when
+ profiling is disabled.
+
+2014-09-15 Trevor Saunders <tsaunders@mozilla.com>
+
+ * cfgrtl.c, combine.c, config/arc/arc.c, config/mcore/mcore.c,
+ config/rs6000/rs6000.c, config/sh/sh.c, cprop.c, dwarf2out.c,
+ emit-rtl.c, final.c, function.c, gcse.c, jump.c, reg-stack.c,
+ reload1.c, reorg.c, resource.c, sel-sched-ir.c: Replace INSN_DELETED_P
+ macro with statically checked member functions.
+ * rtl.h (rtx_insn::deleted): New method.
+ (rtx_insn::set_deleted): Likewise.
+ (rtx_insn::set_undeleted): Likewise.
+ (INSN_DELETED_P): Remove.
+
+2014-09-15 Trevor Saunders <tsaunders@mozilla.com>
+
+ * config/mn10300/mn10300.c (mn10300_insert_setlb_lcc): Assign the
+ result of emit_jump_insn_before to a new variable.
+ * jump.c (mark_jump_label): Change the type of insn to rtx_insn *.
+ (mark_jump_label_1): Likewise.
+ (mark_jump_label_asm): Likewise.
+ * reload1.c (gen_reload): Change type of tem to rtx_insn *.
+ * rtl.h (mark_jump_label): Adjust.
+
+2014-09-15 Jakub Jelinek <jakub@redhat.com>
+
+ * Makefile.in (dg_target_exps): Remove.
+ (check_gcc_parallelize): Change to just an upper bound number.
+ (check-%-subtargets): Always print the non-parallelized goals.
+ (check_p_vars, check_p_comma, check_p_subwork): Remove.
+ (check_p_count, check_p_numbers0, check_p_numbers1, check_p_numbers2,
+ check_p_numbers3, check_p_numbers4, check_p_numbers5,
+ check_p_numbers6): New variables.
+ (check_p_numbers): Set to sequence from 1 to 9999.
+ (check_p_subdirs): Set to sequence from 1 to minimum of
+ $(check_p_count) and either GCC_TEST_PARALLEL_SLOTS env var if set,
+ or 128.
+ (check-%, check-parallel-%): Rewritten so that for parallelized
+ testing each job runs all the *.exp files, with
+ GCC_RUNTEST_PARALLELIZE_DIR set in environment.
+
+2014-09-15 David Malcolm <dmalcolm@redhat.com>
+
+ * config/arc/arc-protos.h (arc_attr_type): Strengthen param from
+ rtx to rtx_insn *.
+ (arc_sets_cc_p): Likewise.
+ * config/arc/arc.c (arc_print_operand): Use methods of
+ "final_sequence" for clarity, and to enable strengthening of
+ locals "jump" and "delay" from rtx to rtx_insn *.
+ (arc_adjust_insn_length): Strengthen local "prev" from rtx to
+ rtx_insn *; use method of rtx_sequence for typesafety.
+ (arc_get_insn_variants): Use insn method of rtx_sequence for
+ typesafety.
+ (arc_pad_return): Likewise.
+ (arc_attr_type): Strengthen param from rtx to rtx_insn *.
+ (arc_sets_cc_p): Likewise. Also, convert a GET_CODE check to a
+ dyn_cast to rtx_sequence *, using insn method for typesafety.
+ * config/arc/arc.h (ADJUST_INSN_LENGTH): Add checked casts to
+ rtx_sequence * and use insn method when invoking get_attr_length.
+ * config/bfin/bfin.c (type_for_anomaly): Strengthen param from rtx
+ to rtx_insn *. Replace a GET_CODE check with a dyn_cast to
+ rtx_sequence *, introducing a local "seq", using its insn method
+ from typesafety and clarity.
+ (add_sched_insns_for_speculation): Strengthen local "next" from
+ rtx to rtx_insn *.
+ * config/c6x/c6x.c (get_insn_side): Likewise for param "insn".
+ (predicate_insn): Likewise.
+ * config/cris/cris-protos.h (cris_notice_update_cc): Likewise for
+ second param.
+ * config/cris/cris.c (cris_notice_update_cc): Likewise.
+ * config/epiphany/epiphany-protos.h
+ (extern void epiphany_insert_mode_switch_use): Likewise for param
+ "insn".
+ (get_attr_sched_use_fpu): Likewise for param.
+ * config/epiphany/epiphany.c (epiphany_insert_mode_switch_use):
+ Likewise for param "insn".
+ * config/epiphany/mode-switch-use.c (insert_uses): Likewise for
+ param "insn" of "target_insert_mode_switch_use" callback.
+ * config/frv/frv.c (frv_insn_unit): Likewise for param "insn".
+ (frv_issues_to_branch_unit_p): Likewise.
+ (frv_pack_insn_p): Likewise.
+ (frv_compare_insns): Strengthen locals "insn1" and "insn2" from
+ const rtx * (i.e. mutable rtx_def * const *) to
+ rtx_insn * const *.
+ * config/i386/i386-protos.h (standard_sse_constant_opcode):
+ Strengthen first param from rtx to rtx_insn *.
+ (output_fix_trunc): Likewise.
+ * config/i386/i386.c (standard_sse_constant_opcode): Likewise.
+ (output_fix_trunc): Likewise.
+ (core2i7_first_cycle_multipass_filter_ready_try): Likewise for
+ local "insn".
+ (min_insn_size): Likewise for param "insn".
+ (get_mem_group): Likewise.
+ (is_cmp): Likewise.
+ (get_insn_path): Likewise.
+ (get_insn_group): Likewise.
+ (count_num_restricted): Likewise.
+ (fits_dispatch_window): Likewise.
+ (add_insn_window): Likewise.
+ (add_to_dispatch_window): Likewise.
+ (debug_insn_dispatch_info_file): Likewise.
+ * config/m32c/m32c-protos.h (m32c_output_compare): Likewise for
+ first param.
+ * config/m32c/m32c.c (m32c_compare_redundant): Likewise for param
+ "cmp" and local "prev".
+ (m32c_output_compare): Likewise for param "insn".
+ * config/m32r/predicates.md (define_predicate "small_insn_p"): Add
+ a checked cast to rtx_insn * on "op" after we know it's an INSN_P.
+ (define_predicate "large_insn_p"): Likewise.
+ * config/m68k/m68k-protos.h (m68k_sched_attr_size): Strengthen
+ param from rtx to rtx_insn *.
+ (attr_op_mem m68k_sched_attr_op_mem): Likewise.
+ * config/m68k/m68k.c (sched_get_attr_size_int): Likewise.
+ (m68k_sched_attr_size): Likewise.
+ (sched_get_opxy_mem_type): Likewise for param "insn".
+ (m68k_sched_attr_op_mem): Likewise.
+ (sched_mem_operand_p): Likewise.
+ * config/mep/mep-protos.h (mep_multi_slot): Likewise for param.
+ * config/mep/mep.c (mep_multi_slot): Likewise.
+ * config/mips/mips-protos.h (mips_output_sync_loop): Likewise for
+ first param.
+ (mips_sync_loop_insns): Likewise.
+ * config/mips/mips.c (mips_print_operand_punctuation): Use insn
+ method of "final_sequence" for typesafety.
+ (mips_process_sync_loop): Strengthen param "insn" from rtx to
+ rtx_insn *.
+ (mips_output_sync_loop): Likewise.
+ (mips_sync_loop_insns): Likewise.
+ (mips_74k_agen_init): Likewise.
+ (mips_sched_init): Use NULL rather than NULL_RTX when working with
+ insns.
+ * config/nds32/nds32-fp-as-gp.c (nds32_symbol_load_store_p):
+ Strengthen param "insn" from rtx to rtx_insn *.
+ * config/nds32/nds32.c (nds32_target_alignment): Likewise for
+ local "insn".
+ * config/pa/pa-protos.h (pa_insn_refs_are_delayed): Likewise for
+ param.
+ * config/pa/pa.c (pa_output_function_epilogue): Likewise for local
+ "insn". Use method of rtx_sequence for typesafety.
+ (branch_to_delay_slot_p): Strengthen param "insn" from rtx to
+ rtx_insn *.
+ (branch_needs_nop_p): Likewise.
+ (use_skip_p): Likewise.
+ (pa_insn_refs_are_delayed): Likewise.
+ * config/rl78/rl78.c (rl78_propogate_register_origins): Likewise
+ for locals "insn", "ninsn".
+ * config/rs6000/rs6000.c (is_microcoded_insn): Likewise for param
+ "insn".
+ (is_cracked_insn): Likewise.
+ (is_branch_slot_insn): Likewise.
+ (is_nonpipeline_insn): Likewise.
+ (insn_terminates_group_p): Likewise.
+ (insn_must_be_first_in_group): Likewise.
+ (insn_must_be_last_in_group): Likewise.
+ (force_new_group): Likewise for param "next_insn".
+ * config/s390/s390.c (s390_get_sched_attrmask): Likewise for param
+ "insn".
+ (s390_sched_score): Likewise.
+ * config/sh/sh-protos.h (output_branch): Likewise for param 2.
+ (rtx sfunc_uses_reg): Likewise for sole param.
+ * config/sh/sh.c (sh_print_operand): Use insn method of
+ final_sequence for typesafety.
+ (output_branch): Strengthen param "insn" from rtx to rtx_insn *.
+ Use insn method of final_sequence for typesafety.
+ (sfunc_uses_reg): Strengthen param "insn" from rtx to rtx_insn *.
+ * config/sparc/sparc-protos.h (eligible_for_call_delay): Likewise
+ for param.
+ (eligible_for_return_delay): Likewise.
+ (eligible_for_sibcall_delay): Likewise.
+ * config/sparc/sparc.c (eligible_for_call_delay): Likewise.
+ (eligible_for_return_delay): Likewise.
+ (eligible_for_sibcall_delay): Likewise.
+ * config/stormy16/stormy16-protos.h
+ (xstormy16_output_cbranch_hi): Likewise for final param.
+ (xstormy16_output_cbranch_si): Likewise.
+ * config/stormy16/stormy16.c (xstormy16_output_cbranch_hi): LIkewise.
+ (xstormy16_output_cbranch_si): Likewise.
+ * config/v850/v850-protos.h (notice_update_cc): Likewise.
+ * config/v850/v850.c (notice_update_cc): Likewise.
+
+ * final.c (get_attr_length_1): Strengthen param "insn" and param
+ of "fallback_fn" from rtx to rtx_insn *, eliminating a checked cast.
+ (get_attr_length): Strengthen param "insn" from rtx to rtx_insn *.
+ (get_attr_min_length): Likewise.
+ (shorten_branches): Likewise for signature of locals "length_fun"
+ and "inner_length_fun". Introduce local rtx_sequence * "seqn"
+ from a checked cast and use its methods for clarity and to enable
+ strengthening local "inner_insn" from rtx to rtx_insn *.
+ * genattr.c (gen_attr): When writing out the prototypes of the
+ various generated "get_attr_" functions, strengthen the params of
+ the non-const functions from rtx to rtx_insn *.
+ Similarly, strengthen the params of insn_default_length,
+ insn_min_length, insn_variable_length_p, insn_current_length.
+ (main): Similarly, strengthen the param of num_delay_slots,
+ internal_dfa_insn_code, insn_default_latency, bypass_p,
+ insn_latency, min_issue_delay, print_reservation,
+ insn_has_dfa_reservation_p and of the "internal_dfa_insn_code" and
+ "insn_default_latency" callbacks. Rename hook_int_rtx_unreachable
+ to hook_int_rtx_insn_unreachable.
+ * genattrtab.c (write_attr_get): When writing out the generated
+ "get_attr_" functions, strengthen the param "insn" from rtx to
+ rtx_insn *, eliminating a checked cast.
+ (make_automaton_attrs): When writing out prototypes of
+ "internal_dfa_insn_code_", "insn_default_latency_" functions
+ and the "internal_dfa_insn_code" and "insn_default_latency"
+ callbacks, strengthen their params from rtx to rtx_insn *
+ * genautomata.c (output_internal_insn_code_evaluation): When
+ writing out code, add a checked cast from rtx to rtx_insn * when
+ invoking DFA_INSN_CODE_FUNC_NAME aka dfa_insn_code.
+ (output_dfa_insn_code_func): Strengthen param of generated
+ function "dfa_insn_code_enlarge" from rtx to rtx_insn *.
+ (output_trans_func): Likewise for generated function
+ "state_transition".
+ (output_internal_insn_latency_func): When writing out generated
+ function "internal_insn_latency", rename params from "insn" and
+ "insn2" to "insn_or_const0" and "insn2_or_const0". Reintroduce
+ locals "insn" and "insn2" as rtx_insn * with checked casts once
+ we've proven that we're not dealing with const0_rtx.
+ (output_insn_latency_func): Strengthen param of generated
+ function "insn_latency" from rtx to rtx_insn *.
+ (output_print_reservation_func): Likewise for generated function
+ "print_reservation".
+ (output_insn_has_dfa_reservation_p): Likewise for generated
+ function "insn_has_dfa_reservation_p".
+ * hooks.c (hook_int_rtx_unreachable): Rename to...
+ (hook_int_rtx_insn_unreachable): ...this, and strengthen param
+ from rtx to rtx_insn *.
+ * hooks.h (hook_int_rtx_unreachable): Likewise.
+ (extern int hook_int_rtx_insn_unreachable): Likewise.
+ * output.h (get_attr_length): Strengthen param from rtx to rtx_insn *.
+ (get_attr_min_length): Likewise.
+ * recog.c (get_enabled_alternatives): Likewise.
+ * recog.h (alternative_mask get_enabled_alternatives): Likewise.
+ * reorg.c (find_end_label): Introduce local rtx "pat" and
+ strengthen local "insn" from rtx to rtx_insn *.
+ (redundant_insn): Use insn method of "seq" rather than element for
+ typesafety; strengthen local "control" from rtx to rtx_insn *.
+ * resource.c (mark_referenced_resources): Add checked cast to
+ rtx_insn * within INSN/JUMP_INSN case.
+ (mark_set_resources): Likewise.
+ * sel-sched.c (estimate_insn_cost): Strengthen param "insn" from
+ rtx to rtx_insn *.
+
+2014-09-15 David Malcolm <dmalcolm@redhat.com>
+
+ * config/rs6000/rs6000.c (rs6000_loop_align_max_skip): Strengthen
+ param "label" from rtx to rtx_insn *.
+ * config/rx/rx.c (rx_max_skip_for_label): Likewise for param "lab"
+ and local "op".
+ * doc/tm.texi (TARGET_ASM_JUMP_ALIGN_MAX_SKIP): Autogenerated changes.
+ (TARGET_ASM_LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP): Likewise.
+ (TARGET_ASM_LOOP_ALIGN_MAX_SKIP): Likewise.
+ (TARGET_ASM_LABEL_ALIGN_MAX_SKIP): Likewise.
+ * final.c (default_label_align_after_barrier_max_skip): Strengthen
+ param from rtx to rtx_insn *.
+ (default_loop_align_max_skip): Likewise.
+ (default_label_align_max_skip): Likewise.
+ (default_jump_align_max_skip): Likewise.
+ * target.def (label_align_after_barrier_max_skip): Likewise.
+ (loop_align_max_skip): Likewise.
+ (label_align_max_skip): Likewise.
+ (jump_align_max_skip): Likewise.
+ * targhooks.h (default_label_align_after_barrier_max_skip):
+ Likewise.
+ (default_loop_align_max_skip): Likewise.
+ (default_label_align_max_skip): Likewise.
+ (default_jump_align_max_skip): Likewise.
+
+2014-09-15 David Malcolm <dmalcolm@redhat.com>
+
+ * config/arc/arc.c (arc_can_follow_jump): Strengthen both params
+ from const_rtx to const rtx_insn *. Update union members from rtx
+ to rtx_insn *.
+ * doc/tm.texi (TARGET_CAN_FOLLOW_JUMP): Autogenerated change.
+ * hooks.c (hook_bool_const_rtx_const_rtx_true): Rename to...
+ (hook_bool_const_rtx_insn_const_rtx_insn_true): ...this, and
+ strengthen both params from const_rtx to const rtx_insn *.
+ * hooks.h (hook_bool_const_rtx_const_rtx_true): Likewise.
+ (hook_bool_const_rtx_insn_const_rtx_insn_true): Likewise.
+ * reorg.c (follow_jumps): Strengthen param "jump" from rtx to
+ rtx_insn *.
+ * target.def (can_follow_jump): Strengthen both params from
+ const_rtx to const rtx_insn *, and update default implementation
+ from hook_bool_const_rtx_const_rtx_true to
+ hook_bool_const_rtx_insn_const_rtx_insn_true.
+
+2014-09-15 David Malcolm <dmalcolm@redhat.com>
+
+ * sched-deps.c (deps_start_bb): Strengthen param "head" and local
+ "insn" from rtx to rtx_insn *.
+ * sched-int.h (deps_start_bb): Likewise for 2nd param.
+
+2014-09-15 Alexander Ivchenko <alexander.ivchenko@intel.com>
+ Maxim Kuznetsov <maxim.kuznetsov@intel.com>
+ Anna Tikhonova <anna.tikhonova@intel.com>
+ Ilya Tocar <ilya.tocar@intel.com>
+ Andrey Turetskiy <andrey.turetskiy@intel.com>
+ Ilya Verbin <ilya.verbin@intel.com>
+ Kirill Yukhin <kirill.yukhin@intel.com>
+ Michael Zolotukhin <michael.v.zolotukhin@intel.com>
+
+ * config/i386/sse.md
+ (define_insn "vcvtph2ps<mask_name>"): Add masking.
+ (define_insn "*vcvtph2ps_load<mask_name>"): Ditto.
+ (define_insn "vcvtph2ps256<mask_name>"): Ditto.
+ (define_expand "vcvtps2ph_mask"): New.
+ (define_insn "*vcvtps2ph<mask_name>"): Add masking.
+ (define_insn "*vcvtps2ph_store<mask_name>"): Ditto.
+ (define_insn "vcvtps2ph256<mask_name>"): Ditto.
+
+2014-09-15 Alexander Ivchenko <alexander.ivchenko@intel.com>
+ Maxim Kuznetsov <maxim.kuznetsov@intel.com>
+ Anna Tikhonova <anna.tikhonova@intel.com>
+ Ilya Tocar <ilya.tocar@intel.com>
+ Andrey Turetskiy <andrey.turetskiy@intel.com>
+ Ilya Verbin <ilya.verbin@intel.com>
+ Kirill Yukhin <kirill.yukhin@intel.com>
+ Michael Zolotukhin <michael.v.zolotukhin@intel.com>
+
+ * config/i386/sse.md (define_mode_iterator VI248_AVX512BW_AVX512VL):
+ New.
+ (define_mode_iterator VI24_AVX512BW_1): Ditto.
+ (define_insn "<mask_codefor>ashr<mode>3<mask_name>"): Ditto.
+ (define_insn "<mask_codefor>ashrv2di3<mask_name>"): Ditto.
+ (define_insn "ashr<VI248_AVX512BW_AVX512VL:mode>3<mask_name>"): Enable
+ also for TARGET_AVX512VL.
+ (define_expand "ashrv2di3"): Update to enable TARGET_AVX512VL.
+
+2014-09-15 Markus Trippelsdorf <markus@trippelsdorf.de>
+
+ * doc/install.texi (Options specification): add
+ --disable-libsanitizer item.
+
+2014-09-14 James Clarke <jrtc27@jrtc27.com>
+ Francois-Xavier Coudert <fxcoudert@gcc.gnu.org>
+
+ PR target/61407
+ * config/darwin-c.c (version_as_macro): Added extra 0 for OS X 10.10
+ and above.
+ * config/darwin-driver.c (darwin_find_version_from_kernel): Removed
+ kernel version check to avoid incrementing it after every major OS X
+ release.
+ (darwin_default_min_version): Avoid static memory buffer.
+
+2014-09-13 Jan Hubicka <hubicka@ucw.cz>
+
+ * tree.c (need_assembler_name_p): Store C++ type mangling only
+ for aggregates.
+
+2014-09-13 Marek Polacek <polacek@redhat.com>
+
+ * tree.c (protected_set_expr_location): Don't check whether T is
+ non-null here.
+
+2014-09-12 DJ Delorie <dj@redhat.com>
+
+ * config/msp430/msp430.md (extendhipsi2): Use 20-bit form of RLAM/RRAM.
+ (extend_and_shift1_hipsi2): Likewise.
+ (extend_and_shift2_hipsi2): Likewise.
+
+2014-09-12 David Malcolm <dmalcolm@redhat.com>
+
+ * config/alpha/alpha.c (alpha_ra_ever_killed): Replace NULL_RTX
+ with NULL when dealing with an insn.
+ * config/sh/sh.c (sh_reorg): Strengthen local "last_float_move"
+ from rtx to rtx_insn *.
+ * rtl.h (reg_set_between_p): Strengthen params 2 and 3 from
+ const_rtx to const rtx_insn *.
+ * rtlanal.c (reg_set_between_p): Likewise, removing a checked cast.
+
+2014-09-12 Trevor Saunders <tsaunders@mozilla.com>
+
+ * hash-table.h (gt_pch_nx): Don't call gt_pch_note_object within an
+ assert.
+
+2014-09-12 Joseph Myers <joseph@codesourcery.com>
+
+ * target.def (libgcc_floating_mode_supported_p): New hook.
+ * targhooks.c (default_libgcc_floating_mode_supported_p): New
+ function.
+ * targhooks.h (default_libgcc_floating_mode_supported_p): Declare.
+ * doc/tm.texi.in (LIBGCC2_HAS_DF_MODE, LIBGCC2_HAS_XF_MODE)
+ (LIBGCC2_HAS_TF_MODE): Remove.
+ (TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P): New @hook.
+ * doc/tm.texi: Regenerate.
+ * genmodes.c (emit_insn_modes_h): Define HAVE_%smode for each
+ machine mode.
+ * system.h (LIBGCC2_HAS_SF_MODE, LIBGCC2_HAS_DF_MODE)
+ (LIBGCC2_HAS_XF_MODE, LIBGCC2_HAS_TF_MODE): Poison.
+ * config/i386/cygming.h (LIBGCC2_HAS_TF_MODE): Remove.
+ * config/i386/darwin.h (LIBGCC2_HAS_TF_MODE): Remove.
+ * config/i386/djgpp.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Define.
+ * config/i386/dragonfly.h (LIBGCC2_HAS_TF_MODE): Remove.
+ * config/i386/freebsd.h (LIBGCC2_HAS_TF_MODE): Remove.
+ * config/i386/gnu-user-common.h (LIBGCC2_HAS_TF_MODE): Remove.
+ * config/i386/i386-interix.h (IX86_NO_LIBGCC_TFMODE): Define.
+ * config/i386/i386.c (ix86_libgcc_floating_mode_supported_p): New
+ function.
+ (TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P): Define.
+ * config/i386/i386elf.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Define.
+ * config/i386/lynx.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Define.
+ * config/i386/netbsd-elf.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Define.
+ * config/i386/netbsd64.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Define.
+ * config/i386/nto.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Define.
+ * config/i386/openbsd.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Define.
+ * config/i386/openbsdelf.h (LIBGCC2_HAS_TF_MODE): Remove.
+ * config/i386/rtemself.h (IX86_NO_LIBGCC_TFMODE): Define.
+ * config/i386/sol2.h (LIBGCC2_HAS_TF_MODE): Remove.
+ * config/i386/vx-common.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Define.
+ * config/ia64/elf.h (IA64_NO_LIBGCC_TFMODE): Define.
+ * config/ia64/freebsd.h (IA64_NO_LIBGCC_TFMODE): Define.
+ * config/ia64/hpux.h (LIBGCC2_HAS_XF_MODE, LIBGCC2_HAS_TF_MODE):
+ Remove.
+ * config/ia64/ia64.c (TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P):
+ New macro.
+ (ia64_libgcc_floating_mode_supported_p): New function.
+ * config/ia64/linux.h (LIBGCC2_HAS_TF_MODE): Remove.
+ * config/ia64/vms.h (IA64_NO_LIBGCC_XFMODE)
+ (IA64_NO_LIBGCC_TFMODE): Define.
+ * config/msp430/msp430.h (LIBGCC2_HAS_DF_MODE): Remove.
+ * config/pdp11/pdp11.c (TARGET_SCALAR_MODE_SUPPORTED_P): New
+ macro.
+ (pdp11_scalar_mode_supported_p): New function.
+ * config/rl78/rl78.h (LIBGCC2_HAS_DF_MODE): Remove.
+ * config/rx/rx.h (LIBGCC2_HAS_DF_MODE): Remove.
+
+2014-09-12 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/63237
+ * gimple-fold.c (get_maxval_strlen): Gimplify string length.
+
+2014-09-12 Marc Glisse <marc.glisse@inria.fr>
+
+ * tree.c (integer_each_onep): New function.
+ * tree.h (integer_each_onep): Declare it.
+ * fold-const.c (fold_binary_loc): Use it for ~A + 1 to -A and
+ -A - 1 to ~A. Disable (X & 1) ^ 1, (X ^ 1) & 1 and ~X & 1 to
+ (X & 1) == 0 for vector and complex.
+
+2014-09-12 Wilco Dijkstra <wilco.dijkstra@arm.com>
+
+ * gcc/config/aarch64/aarch64.c (cortexa57_regmove_cost): New cost table
+ for A57.
+ (cortexa53_regmove_cost): New cost table for A53. Increase GP2FP/FP2GP
+ cost to spilling from integer to FP registers.
+
+2014-09-12 Wilco Dijkstra <wilco.dijkstra@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_register_move_cost): Fix Q register
+ move handling.
+ (generic_regmove_cost): Undo raised FP2FP move cost as Q register moves
+ are now handled correctly.
+
+2014-09-12 Wilco Dijkstra <wilco.dijkstra@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_register_move_cost): Add cost
+ handling of CALLER_SAVE_REGS and POINTER_REGS.
+
+2014-09-12 Wilco Dijkstra <wilco.dijkstra@arm.com>
+
+ * gcc/ree.c (combine_reaching_defs): Ensure inserted copy don't change
+ the number of hard registers.
+
+2014-09-12 Alexander Ivchenko <alexander.ivchenko@intel.com>
+ Maxim Kuznetsov <maxim.kuznetsov@intel.com>
+ Anna Tikhonova <anna.tikhonova@intel.com>
+ Ilya Tocar <ilya.tocar@intel.com>
+ Andrey Turetskiy <andrey.turetskiy@intel.com>
+ Ilya Verbin <ilya.verbin@intel.com>
+ Kirill Yukhin <kirill.yukhin@intel.com>
+ Michael Zolotukhin <michael.v.zolotukhin@intel.com>
+
+ * config/i386/sse.md
+ (define_mode_iterator VI48_AVX512VL): New.
+ (define_expand "<avx512>_vternlog<mode>_maskz"): Rename from
+ "avx512f_vternlog<mode>_maskz" and update mode iterator.
+ (define_insn "<avx512>_vternlog<mode><sd_maskz_name>"): Rename
+ from "avx512f_vternlog<mode><sd_maskz_name>" and update mode iterator.
+ (define_insn "<avx512>_vternlog<mode>_mask"): Rename from
+ "avx512f_vternlog<mode>_mask" and update mode iterator.
+ (define_insn "<mask_codefor><avx512>_align<mode><mask_name>"): Rename
+ from "<mask_codefor>avx512f_align<mode><mask_name>" and update mode
+ iterator.
+ (define_insn "<avx512>_<rotate>v<mode><mask_name>"): Rename from
+ "avx512f_<rotate>v<mode><mask_name>" and update mode iterator.
+ (define_insn "<avx512>_<rotate><mode><mask_name>"): Rename from
+ "avx512f_<rotate><mode><mask_name>" and update mode iterator.
+ (define_insn "clz<mode>2<mask_name>"): Use VI48_AVX512VL mode iterator.
+ (define_insn "<mask_codefor>conflict<mode><mask_name>"): Ditto.
+
+2014-09-12 Alexander Ivchenko <alexander.ivchenko@intel.com>
+ Maxim Kuznetsov <maxim.kuznetsov@intel.com>
+ Anna Tikhonova <anna.tikhonova@intel.com>
+ Ilya Tocar <ilya.tocar@intel.com>
+ Andrey Turetskiy <andrey.turetskiy@intel.com>
+ Ilya Verbin <ilya.verbin@intel.com>
+ Kirill Yukhin <kirill.yukhin@intel.com>
+ Michael Zolotukhin <michael.v.zolotukhin@intel.com>
+
+ * config/i386/sse.md (VI128_256): Delete.
+ (define_mode_iterator VI124_256): New.
+ (define_mode_iterator VI124_256_AVX512F_AVX512BW): Ditto.
+ (define_expand "<code><mode>3<mask_name><round_name>"): Delete.
+ (define_expand "<code><VI124_256_AVX512F_AVX512BW:mode>3"): New.
+ (define_insn "*avx2_<code><VI124_256:mode>3"): Rename from
+ "*avx2_<code><mode>3<mask_name><round_name>" and update mode iterator.
+ (define_expand "<code><VI48_AVX512VL:mode>3_mask"): New.
+ (define_insn "*avx512bw_<code><VI48_AVX512VL:mode>3<mask_name>"): Ditto.
+ (define_insn "<mask_codefor><code><mode>3<mask_name>"): Update mode
+ iterator.
+ (define_expand "<code><VI8_AVX2:mode>3"): Update pettern generation
+ in presence of AVX-512.
+
+2014-09-12 Alexander Ivchenko <alexander.ivchenko@intel.com>
+ Maxim Kuznetsov <maxim.kuznetsov@intel.com>
+ Anna Tikhonova <anna.tikhonova@intel.com>
+ Ilya Tocar <ilya.tocar@intel.com>
+ Andrey Turetskiy <andrey.turetskiy@intel.com>
+ Ilya Verbin <ilya.verbin@intel.com>
+ Kirill Yukhin <kirill.yukhin@intel.com>
+ Michael Zolotukhin <michael.v.zolotukhin@intel.com>
+
+ * config/i386/sse.md
+ (define_expand "<avx512>_gathersi<mode>"): Rename from
+ "avx512f_gathersi<mode>".
+ (define_insn "*avx512f_gathersi<mode>"): Use VI48F.
+ (define_insn "*avx512f_gathersi<mode>_2"): Ditto.
+ (define_expand "<avx512>_gatherdi<mode>"): Rename from
+ "avx512f_gatherdi<mode>".
+ (define_insn "*avx512f_gatherdi<mode>"): Use VI48F.
+ (define_insn "*avx512f_gatherdi<mode>_2"): Use VI48F, add 128/256-bit
+ wide versions.
+ (define_expand "<avx512>_scattersi<mode>"): Rename from
+ "avx512f_scattersi<mode>".
+ (define_insn "*avx512f_scattersi<mode>"): Use VI48F.
+ (define_expand "<avx512>_scatterdi<mode>"): Rename from
+ "avx512f_scatterdi<mode>".
+ (define_insn "*avx512f_scatterdi<mode>"): Use VI48F.
+
+2014-09-12 Richard Sandiford <richard.sandiford@arm.com>
+
+ * ira.h (ira_finish_once): Delete.
+ * ira-int.h (target_ira_int::~target_ira_int): Declare.
+ (target_ira_int::free_ira_costs): Likewise.
+ (target_ira_int::free_register_move_costs): Likewise.
+ (ira_finish_costs_once): Delete.
+ * ira.c (free_register_move_costs): Replace with...
+ (target_ira_int::free_register_move_costs): ...this new function.
+ (target_ira_int::~target_ira_int): Define.
+ (ira_init): Call free_register_move_costs as a member function rather
+ than a global function.
+ (ira_finish_once): Delete.
+ * ira-costs.c (free_ira_costs): Replace with...
+ (target_ira_int::free_ira_costs): ...this new function.
+ (ira_init_costs): Call free_ira_costs as a member function rather
+ than a global function.
+ (ira_finish_costs_once): Delete.
+ * target-globals.c (target_globals::~target_globals): Call the
+ target_ira_int destructor.
+ * toplev.c: Include lra.h.
+ (finalize): Call lra_finish_once rather than ira_finish_once.
+
+2014-09-11 Jan Hubicka <hubicka@ucw.cz>
+
+ * common.opt (flto-odr-type-merging): New flag.
+ * ipa-deivrt.c (hash_type_name): Use ODR names for hasing if availale.
+ (types_same_for_odr): Likewise.
+ (odr_subtypes_equivalent_p): Likewise.
+ (add_type_duplicate): Do not walk type variants.
+ (register_odr_type): New function.
+ * ipa-utils.h (register_odr_type): Declare.
+ (odr_type_p): New function.
+ * langhooks.c (lhd_set_decl_assembler_name): Do not compute
+ TYPE_DECLs
+ * doc/invoke.texi (-flto-odr-type-merging): Document.
+ * tree.c (need_assembler_name_p): Compute ODR names when asked
+ for it.
+ * tree.h (DECL_ASSEMBLER_NAME): Update comment.
+
+2014-09-11 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR target/63228
+ * config/i386/i386.c (ix86_option_override_internal): Also turn
+ off OPTION_MASK_ABI_X32 for -m16.
+
+2014-09-11 Segher Boessenkool <segher@kernel.crashing.org>
+
+ * config/rs6000/rs6000.md (rs6000_mftb_<mode>): Use mode iterator
+ GPR instead of P.
+
+2014-09-11 Marc Glisse <marc.glisse@inria.fr>
+
+ PR target/58757
+ * ginclude/float.h (FLT_TRUE_MIN, DBL_TRUE_MIN, LDBL_TRUE_MIN):
+ Directly forward to __*_DENORM_MIN__.
+
+2014-09-11 David Malcolm <dmalcolm@redhat.com>
+
+ * rtl.h (LABEL_REF_LABEL): New macro.
+
+ * alias.c (rtx_equal_for_memref_p): Use LABEL_REF_LABEL in place
+ of XEXP (, 0), where we know that we have a LABEL_REF.
+ * cfgbuild.c (make_edges): Likewise.
+ (purge_dead_tablejump_edges): Likewise.
+ * cfgexpand.c (convert_debug_memory_address): Likewise.
+ * cfgrtl.c (patch_jump_insn): Likewise.
+ * combine.c (distribute_notes): Likewise.
+ * cse.c (hash_rtx_cb): Likewise.
+ (exp_equiv_p): Likewise.
+ (fold_rtx): Likewise.
+ (check_for_label_ref): Likewise.
+ * cselib.c (rtx_equal_for_cselib_1): Likewise.
+ (cselib_hash_rtx): Likewise.
+ * emit-rtl.c (mark_label_nuses): Likewise.
+ * explow.c (convert_memory_address_addr_space): Likewise.
+ * final.c (output_asm_label): Likewise.
+ (output_addr_const): Likewise.
+ * gcse.c (add_label_notes): Likewise.
+ * genconfig.c (walk_insn_part): Likewise.
+ * genrecog.c (validate_pattern): Likewise.
+ * ifcvt.c (cond_exec_get_condition): Likewise.
+ (noce_emit_store_flag): Likewise.
+ (noce_get_alt_condition): Likewise.
+ (noce_get_condition): Likewise.
+ * jump.c (maybe_propagate_label_ref): Likewise.
+ (mark_jump_label_1): Likewise.
+ (redirect_exp_1): Likewise.
+ (rtx_renumbered_equal_p): Likewise.
+ * lra-constraints.c (operands_match_p): Likewise.
+ * reload.c (operands_match_p): Likewise.
+ (find_reloads): Likewise.
+ * reload1.c (set_label_offsets): Likewise.
+ * reorg.c (get_branch_condition): Likewise.
+ * rtl.c (rtx_equal_p_cb): Likewise.
+ (rtx_equal_p): Likewise.
+ * rtlanal.c (reg_mentioned_p): Likewise.
+ (rtx_referenced_p): Likewise.
+ (get_condition): Likewise.
+ * sched-vis.c (print_value): Likewise.
+ * varasm.c (const_hash_1): Likewise.
+ (compare_constant): Likewise.
+ (const_rtx_hash_1): Likewise.
+ (output_constant_pool_1): Likewise.
+
+2014-09-11 Segher Boessenkool <segher@kernel.crashing.org>
+
+ * config/rs6000/htm.md (tabort, tabortdc, tabortdci, tabortwc,
+ tabortwci, tbegin, tcheck, tend, trechkpt, treclaim, tsr): Use xor
+ instead of minus.
+ * config/rs6000/vector.md (cr6_test_for_zero_reverse,
+ cr6_test_for_lt_reverse): Ditto.
+
+2014-09-11 Paolo Carlini <paolo.carlini@oracle.com>
+
+ PR c++/61489
+ * doc/invoke.texi ([-Wmissing-field-initializers]): Update.
+
+2014-09-11 Alan Lawrence <alan.lawrence@arm.com>
+
+ * config/aarch64/aarch64-builtins.c (aarch64_types_unop_su_qualifiers,
+ TYPES_REINTERP_SU, aarch64_types_unop_sp_qualifiers, TYPE_REINTERP_SP,
+ aarch64_types_unop_us_qualifiers, TYPES_REINTERP_US,
+ aarch64_types_unop_ps_qualifiers, TYPES_REINTERP_PS, BUILTIN_VD):
+ Delete.
+
+ (aarch64_fold_builtin): Remove all reinterpret cases.
+
+ * config/aarch64/aarch64-protos.h (aarch64_simd_reinterpret): Delete.
+
+ * config/aarch64/aarch64-simd-builtins.def (reinterpret*) : Delete.
+
+ * config/aarch64/aarch64-simd.md (aarch64_reinterpretv8qi<mode>,
+ aarch64_reinterpretv4hi<mode>, aarch64_reinterpretv2si<mode>,
+ aarch64_reinterpretv2sf<mode>, aarch64_reinterpretdi<mode>,
+ aarch64_reinterpretv1df<mode>, aarch64_reinterpretv16qi<mode>,
+ aarch64_reinterpretv8hi<mode>, aarch64_reinterpretv4si<mode>,
+ aarch64_reinterpretv4sf<mode>, aarch64_reinterpretv2di<mode>,
+ aarch64_reinterpretv2df<mode>): Delete.
+
+ * config/aarch64/aarch64.c (aarch64_simd_reinterpret): Delete.
+
+ * config/aarch64/arm_neon.h (vreinterpret_p8_f64,
+ vreinterpret_p16_f64, vreinterpret_f32_f64, vreinterpret_f64_f32,
+ vreinterpret_f64_p8, vreinterpret_f64_p16, vreinterpret_f64_s8,
+ vreinterpret_f64_s16, vreinterpret_f64_s32, vreinterpret_f64_u8,
+ vreinterpret_f64_u16, vreinterpret_f64_u32, vreinterpret_s64_f64,
+ vreinterpret_u64_f64, vreinterpret_s8_f64, vreinterpret_s16_f64,
+ vreinterpret_s32_f64, vreinterpret_u8_f64, vreinterpret_u16_f64,
+ vreinterpret_u32_f64): Use cast.
+
+ * config/aarch64/iterators.md (VD_RE): Delete.
+
+2014-09-11 Alan Lawrence <alan.lawrence@arm.com>
+
+ * config/aarch64/arm_neon.h (aarch64_vset_lane_any): New (*2).
+ (vset_lane_f32, vset_lane_f64, vset_lane_p8, vset_lane_p16,
+ vset_lane_s8, vset_lane_s16, vset_lane_s32, vset_lane_s64,
+ vset_lane_u8, vset_lane_u16, vset_lane_u32, vset_lane_u64,
+ vsetq_lane_f32, vsetq_lane_f64, vsetq_lane_p8, vsetq_lane_p16,
+ vsetq_lane_s8, vsetq_lane_s16, vsetq_lane_s32, vsetq_lane_s64,
+ vsetq_lane_u8, vsetq_lane_u16, vsetq_lane_u32, vsetq_lane_u64):
+ Replace inline assembler with __aarch64_vset_lane_any.
+
+2014-09-11 James Greenhalgh <james.greenhalgh@arm.com>
+
+ * config/aarch64/arm_neon.h (vmull_high_lane_s16): Fix argument
+ types.
+ (vmull_high_lane_s32): Likewise.
+ (vmull_high_lane_u16): Likewise.
+ (vmull_high_lane_u32): Likewise.
+
+2014-09-11 Jason Merrill <jason@redhat.com>
+
+ PR c++/58678
+ * ipa-devirt.c (ipa_devirt): Don't check DECL_COMDAT.
+
+2014-09-11 Georg-Johann Lay <avr@gjlay.de>
+
+ PR target/63223
+ * config/avr/avr.md (*tablejump.3byte-pc): New insn.
+ (*tablejump): Restrict to !AVR_HAVE_EIJMP_EICALL. Add void clobber.
+ (casesi): Expand to *tablejump.3byte-pc if AVR_HAVE_EIJMP_EICALL.
+
+2014-09-11 Alexander Ivchenko <alexander.ivchenko@intel.com>
+ Maxim Kuznetsov <maxim.kuznetsov@intel.com>
+ Anna Tikhonova <anna.tikhonova@intel.com>
+ Ilya Tocar <ilya.tocar@intel.com>
+ Andrey Turetskiy <andrey.turetskiy@intel.com>
+ Ilya Verbin <ilya.verbin@intel.com>
+ Kirill Yukhin <kirill.yukhin@intel.com>
+ Michael Zolotukhin <michael.v.zolotukhin@intel.com>
+
+ * config/i386/sse.md
+ (define_expand "<avx512>_vpermi2var<VI48F:mode>3_maskz"): Rename from
+ "avx512f_vpermi2var<mode>3_maskz" and update mode iterator.
+ (define_expand "<avx512>_vpermi2var<VI2_AVX512VL:mode>3_maskz"):
+ New.
+ (define_insn "<avx512>_vpermi2var<VI48F:mode>3<sd_maskz_name>"): Rename
+ from "avx512f_vpermi2var<mode>3<sd_maskz_name>" and update mode
+ iterator.
+ (define_insn "<avx512>_vpermi2var<VI2_AVX512VL:mode>3<sd_maskz_name>"):
+ New.
+ (define_insn "<avx512>_vpermi2var<VI48F:mode>3_mask"): Rename from
+ "avx512f_vpermi2var<mode>3_mask" and update mode iterator.
+ (define_insn "<avx512>_vpermi2var<VI2_AVX512VL:mode>3_mask"): New.
+ (define_expand "<avx512>_vpermt2var<VI48F:mode>3_maskz"): Rename from
+ "avx512f_vpermt2var<mode>3_maskz" and update mode iterator.
+ (define_expand "<avx512>_vpermt2var<VI2_AVX512VL:mode>3_maskz"): New.
+ (define_insn "<avx512>_vpermt2var<VI48F:mode>3<sd_maskz_name>"): Rename
+ from "avx512f_vpermt2var<mode>3<sd_maskz_name>" and update mode
+ iterator.
+ (define_insn "<avx512>_vpermt2var<VI2_AVX512VL:mode>3<sd_maskz_name>"):
+ New.
+ (define_insn "<avx512>_vpermt2var<VI48F:mode>3_mask"): Rename from
+ "avx512f_vpermt2var<mode>3_mask" and update mode iterator.
+ (define_insn "<avx512>_vpermt2var<VI2_AVX512VL:mode>3_mask"): New.
+
+2014-09-10 Jan Hubicka <hubicka@ucw.cz>
+
+ * varpool.c (varpool_node::ctor_useable_for_folding_p): Do not try
+ to access removed nodes.
+
+2014-09-10 Jan Hubicka <hubicka@ucw.cz>
+
+ PR tree-optimization/63186
+ * ipa-split.c (test_nonssa_use): Skip nonforced labels.
+ (mark_nonssa_use): Likewise.
+ (verify_non_ssa_vars): Verify all header blocks for label
+ definitions.
+
+2014-09-11 Alexander Ivchenko <alexander.ivchenko@intel.com>
+ Maxim Kuznetsov <maxim.kuznetsov@intel.com>
+ Anna Tikhonova <anna.tikhonova@intel.com>
+ Ilya Tocar <ilya.tocar@intel.com>
+ Andrey Turetskiy <andrey.turetskiy@intel.com>
+ Ilya Verbin <ilya.verbin@intel.com>
+ Kirill Yukhin <kirill.yukhin@intel.com>
+ Michael Zolotukhin <michael.v.zolotukhin@intel.com>
+
+ * config/i386/sse.md
+ (define_mode_attr avx2_avx512): Rename from avx2_avx512bw.
+ (define_mode_iterator VI48F_256_512): Extend to AVX-512VL.
+ (define_insn "<avx2_avx512>_permvar<mode><mask_name>"): Rename from
+ "<avx2_avx512f>_permvar<mode><mask_name>".
+ (define_insn "<avx512>_permvar<mode><mask_name>"): New.
+ (define_insn "<avx2_avx512>_ashrv<VI48_AVX512F_AVX512VL:mode><mask_name>"):
+ Rename from "<avx2_avx512f>_ashrv<mode><mask_name>".
+ (define_insn "<avx2_avx512>_ashrv<VI2_AVX512VL:mode><mask_name>"):
+ Ditto.
+ (define_insn "<avx2_avx512>_<shift_insn>v<VI48_AVX512F:mode><mask_name>"):
+ Rename from "<avx2_avx512bw>_<shift_insn>v<mode><mask_name>".
+ (define_insn "<avx2_avx512>_<shift_insn>v<VI2_AVX512VL:mode><mask_name>"):
+ Rename from "<avx2_avx512bw>_<shift_insn>v<mode><mask_name>".
+
+2014-09-10 Michael Meissner <meissner@linux.vnet.ibm.com>
+
+ * config/rs6000/vsx.md (vsx_fmav4sf4): Use correct constraints for
+ V2DF, V4SF, DF, and DI modes.
+ (vsx_fmav2df2): Likewise.
+ (vsx_float_fix_<mode>2): Likewise.
+ (vsx_reduc_<VEC_reduc_name>_v2df_scalar): Likewise.
+
+2014-09-10 Xinliang David Li <davidxl@google.com>
+
+ PR target/63209
+ * config/arm/arm.md (movcond_addsi): Handle case where source
+ and target operands are the same.
+
+2014-09-10 David Malcolm <dmalcolm@redhat.com>
+
+ * final.c (this_is_asm_operands): Strengthen this variable from
+ rtx to const rtx_insn *.
+ * output.h (this_is_asm_operands): Likewise.
+ * rtl-error.c (location_for_asm): Strengthen param "insn" from
+ const_rtx to const rtx_insn *.
+ (diagnostic_for_asm): Likewise.
+ * rtl-error.h (error_for_asm): Likewise.
+ (warning_for_asm): Likewise.
+
+2014-09-10 David Malcolm <dmalcolm@redhat.com>
+
+ * genextract.c (print_header): When writing out insn_extract to
+ insn-extract.c, strengthen the param "insn" from rtx to rtx_insn *.
+ * recog.h (insn_extract): Strengthen the param from rtx to
+ rtx_insn *.
+
+2014-09-10 Mike Stump <mikestump@comcast.net>
+
+ * doc/install.texi (Prerequisites): Note Tcl 8.6 bug fixed in
+ 8.6.1.
+
+2014-09-10 Martin Jambor <mjambor@suse.cz>
+
+ * cgraphunit.c (expand_thunk): If not expanding, set analyzed flag.
+ (analyze): Do not set analyze flag if expand_thunk returns false;.
+ (create_wrapper): Likewise.
+ * cgraphclones.c (duplicate_thunk_for_node): Likewise.
+
+2014-09-10 Martin Jambor <mjambor@suse.cz>
+
+ PR ipa/61654
+ * cgraphclones.c (duplicate_thunk_for_node): Copy arguments of the
+ new decl properly. Analyze the new thunk if it is expanded.
+
+2014-09-10 Andreas Schwab <schwab@suse.de>
+
+ * coretypes.h (struct _dont_use_rtx_insn_here_, rtx_insn)
+ [USED_FOR_TARGET]: Define.
+
+2014-09-10 Matthew Fortune <matthew.fortune@imgtec.com>
+
+ * config/mips/mips.c (mips_secondary_reload_class): Handle
+ regno < 0 case.
+
+2014-09-10 Robert Suchanek <robert.suchanek@imgtec.com>
+
+ * lra-lives.c (process_bb_lives): Replace assignment with bitwise OR
+ assignment.
+
+2014-09-10 Jakub Jelinek <jakub@redhat.com>
+
+ * flag-types.h (enum sanitize_code): Add SANITIZE_NONNULL_ATTRIBUTE
+ and SANITIZE_RETURNS_NONNULL_ATTRIBUTE, or them into SANITIZE_UNDEFINED.
+ * opts.c (common_handle_option): Handle SANITIZE_NONNULL_ATTRIBUTE and
+ SANITIZE_RETURNS_NONNULL_ATTRIBUTE and disable
+ flag_delete_null_pointer_checks for them.
+ * sanitizer.def (BUILT_IN_UBSAN_HANDLE_NONNULL_ARG,
+ BUILT_IN_UBSAN_HANDLE_NONNULL_ARG_ABORT,
+ BUILT_IN_UBSAN_HANDLE_NONNULL_RETURN,
+ BUILT_IN_UBSAN_HANDLE_NONNULL_RETURN_ABORT): New.
+ * ubsan.c (instrument_bool_enum_load): Set *gsi back to
+ stmt's iterator.
+ (instrument_nonnull_arg, instrument_nonnull_return): New functions.
+ (pass_ubsan::gate): Return true even for SANITIZE_NONNULL_ATTRIBUTE
+ or SANITIZE_RETURNS_NONNULL_ATTRIBUTE.
+ (pass_ubsan::execute): Call instrument_nonnull_{arg,return}.
+ * doc/invoke.texi (-fsanitize=nonnull-attribute,
+ -fsanitize=returns-nonnull-attribute): Document.
+
+ * ubsan.h (struct ubsan_mismatch_data): Removed.
+ (ubsan_create_data): Remove MISMATCH argument, add LOCCNT argument.
+ * ubsan.c (ubsan_source_location): For unknown locations,
+ pass { NULL, 0, 0 } instead of { "<unknown>", x, y }.
+ (ubsan_create_data): Remove MISMATCH argument, add LOCCNT argument.
+ Allow more than one location and arbitrary extra arguments passed
+ in ... instead of through MISMATCH pointer.
+ (ubsan_instrument_unreachable, ubsan_expand_bounds_ifn,
+ ubsan_expand_null_ifn, ubsan_build_overflow_builtin,
+ instrument_bool_enum_load, ubsan_instrument_float_cast): Adjust
+ callers.
+
+2014-09-10 Alexander Ivchenko <alexander.ivchenko@intel.com>
+ Maxim Kuznetsov <maxim.kuznetsov@intel.com>
+ Anna Tikhonova <anna.tikhonova@intel.com>
+ Ilya Tocar <ilya.tocar@intel.com>
+ Andrey Turetskiy <andrey.turetskiy@intel.com>
+ Ilya Verbin <ilya.verbin@intel.com>
+ Kirill Yukhin <kirill.yukhin@intel.com>
+ Michael Zolotukhin <michael.v.zolotukhin@intel.com>
+
+ * config/i386/sse.md
+ (define_mode_iterator VI48F): New.
+ (define_insn "<avx512>_compress<mode>_mask"): Rename from
+ "avx512f_compress<mode>_mask" and update mode iterator.
+ (define_insn "<avx512>_compressstore<mode>_mask"): Rename from
+ "avx512f_compressstore<mode>_mask" and update mode iterator.
+ (define_expand "<avx512>_expand<mode>_maskz"): Rename from
+ "avx512f_expand<mode>_maskz" and update mode iterator.
+ (define_insn "<avx512>_expand<mode>_mask"): Rename from
+ "avx512f_expand<mode>_mask" and update mode iterator.
+
+2014-09-10 Alexander Ivchenko <alexander.ivchenko@intel.com>
+ Maxim Kuznetsov <maxim.kuznetsov@intel.com>
+ Anna Tikhonova <anna.tikhonova@intel.com>
+ Ilya Tocar <ilya.tocar@intel.com>
+ Andrey Turetskiy <andrey.turetskiy@intel.com>
+ Ilya Verbin <ilya.verbin@intel.com>
+ Kirill Yukhin <kirill.yukhin@intel.com>
+ Michael Zolotukhin <michael.v.zolotukhin@intel.com>
+
+ * config/i386/i386.c
+ (ix86_expand_args_builtin): Handle avx512dq_rangepv8df_mask_round,
+ avx512dq_rangepv16sf_mask_round, avx512dq_rangepv4df_mask,
+ avx512dq_rangepv8sf_mask, avx512dq_rangepv2df_mask,
+ avx512dq_rangepv4sf_mask.
+ * config/i386/sse.md
+ (define_c_enum "unspec"): Add UNSPEC_REDUCE, UNSPEC_FPCLASS,
+ UNSPEC_RANGE.
+ (define_insn "<mask_codefor>reducep<mode><mask_name>"): New.
+ (define_insn "reduces<mode>"): Ditto.
+ (define_insn "avx512dq_rangep<mode><mask_name><round_saeonly_name>"):
+ Ditto.
+ (define_insn "avx512dq_ranges<mode><round_saeonly_name>"): Ditto.
+ (define_insn "avx512dq_fpclass<mode><mask_scalar_merge_name>"): Ditto.
+ (define_insn "avx512dq_vmfpclass<mode>"): Ditto..
+
+2014-09-10 Alexander Ivchenko <alexander.ivchenko@intel.com>
+ Maxim Kuznetsov <maxim.kuznetsov@intel.com>
+ Anna Tikhonova <anna.tikhonova@intel.com>
+ Ilya Tocar <ilya.tocar@intel.com>
+ Andrey Turetskiy <andrey.turetskiy@intel.com>
+ Ilya Verbin <ilya.verbin@intel.com>
+ Kirill Yukhin <kirill.yukhin@intel.com>
+ Michael Zolotukhin <michael.v.zolotukhin@intel.com>
+
+ * config/i386/i386.c
+ (avx512f_vgetmantv2df_round): Rename from "avx512f_getmantv2df_round".
+ (avx512f_vgetmantv4sf_round): Rename from "avx512f_vgetmantv4sf_round".
+ (ix86_expand_args_builtin): Handle avx512vl_getmantv8sf_mask,
+ avx512vl_getmantv4df_mask, avx512vl_getmantv4sf_mask,
+ avx512vl_getmantv2df_mask.
+ (ix86_expand_round_builtin): Handle avx512f_vgetmantv2df_round,
+ avx512f_vgetmantv4sf_round.
+ * config/i386/sse.md
+ (define_insn "<avx512>_storeu<ssemodesuffix><avxsizesuffix>_mask"):
+ Rename from "avx512f_storeu<ssemodesuffix>512_mask" and update
+ mode iterator.
+ (define_insn "<mask_codefor>rcp14<mode><mask_name>"): Use VF_AVX512VL.
+ (define_insn "<mask_codefor>rsqrt14<mode><mask_name>"): Ditto.
+ (define_insn "<avx512>_scalef<mode><mask_name><round_name>"): Rename
+ from "avx512f_scalef<mode><mask_name><round_name>" and update mode
+ iterator..
+ (define_insn "<avx512>_getexp<mode><mask_name><round_saeonly_name>"):
+ Rename from "avx512f_getexp<mode><mask_name><round_saeonly_name>" and
+ update mode iterator.
+ (define_expand
+ "<avx512>_fixupimm<mode>_maskz<round_saeonly_expand_name>"): Rename from
+ "avx512f_fixupimm<mode>_maskz<round_saeonly_expand_name>" and update
+ mode iterator.
+ (define_insn
+ "<avx512>_fixupimm<mode><sd_maskz_name><round_saeonly_name>"): Rename
+ from "avx512f_fixupimm<mode><sd_maskz_name><round_saeonly_name>" and
+ update mode iterator.
+ (define_insn "<avx512>_fixupimm<mode>_mask<round_saeonly_name>"): Rename
+ from "avx512f_fixupimm<mode>_mask<round_saeonly_name>" and update mode
+ iterator..
+ (define_insn
+ "<avx512>_rndscale<mode><mask_name><round_saeonly_name>"): rename from
+ "avx512f_rndscale<mode><mask_name><round_saeonly_name>" and update
+ mode iterator..
+ (define_insn "<avx512>_getmant<mode><mask_name><round_saeonly_name>"):
+ Rename from "avx512f_getmant<mode><mask_name><round_saeonly_name>" and
+ update mode iterator.
+ (define_insn "avx512f_vgetmant<mode><round_saeonly_name>"): Rename from
+ "avx512f_getmant<mode><round_saeonly_name>".
+
+2014-09-10 Jan Hubicka <hubicka@ucw.cz>
+
+ PR ipa/63166
+ * ipa-prop.c (compute_known_type_jump_func): Fix conditional.
+
+2014-09-10 Alexander Ivchenko <alexander.ivchenko@intel.com>
+ Maxim Kuznetsov <maxim.kuznetsov@intel.com>
+ Anna Tikhonova <anna.tikhonova@intel.com>
+ Ilya Tocar <ilya.tocar@intel.com>
+ Andrey Turetskiy <andrey.turetskiy@intel.com>
+ Ilya Verbin <ilya.verbin@intel.com>
+ Kirill Yukhin <kirill.yukhin@intel.com>
+ Michael Zolotukhin <michael.v.zolotukhin@intel.com>
+
+ * config/i386/sse.md (define_mode_iterator VF_AVX512VL): New.
+ (define_mode_iterator FMAMODEM): Allow 128/256bit EVEX version.
+ (define_mode_iterator FMAMODE_AVX512): New.
+ (define_mode_iterator FMAMODE): Remove conditions.
+ (define_expand "fma4i_fmadd_<mode>"): Use FMAMODE_AVX512 mode iterator.
+ (define_expand "<avx512>_fmadd_<mode>_maskz<round_expand_name>"): Rename
+ from "<avx512>_fmadd_<mode>_maskz<round_expand_name>" and use VF_AVX512VL
+ mode iterator.
+ (define_mode_iterator FMAMODE_NOVF512): Remove.
+ (define_insn "*fma_fmadd_<mode>"): Rename from
+ "<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name><round_name>" and use
+ FMAMODE mode iterator.
+ (define_mode_iterator VF_SF_AVX512VL): New.
+ (define_insn "<sd_mask_codefor>fma_fmadd_<mode><sd_maskz_name><round_name>"):
+ Use VF_SF_AVX512VL mode iterator.
+ (define_insn "<avx512>_fmadd_<mode>_mask<round_name>"): Rename from
+ "avx512f_fmadd_<mode>_mask<round_name>" and use VF_AVX512VL mode
+ iterator.
+ (define_insn "<avx512>_fmadd_<mode>_mask3<round_name>"): Rename from
+ "avx512f_fmadd_<mode>_mask3<round_name>" and use VF_AVX512VL mode
+ iterator.
+ (define_insn "*fma_fmsub_<mode>"): Rename from
+ "<sd_mask_codefor>fma_fmsub_<mode><sd_maskz_name><round_name>" and use
+ FMAMODE mode iterator.
+ (define_insn "<sd_mask_codefor>fma_fmsub_<mode><sd_maskz_name><round_name>"):
+ Use VF_SF_AVX512VL mode iterator.
+ (define_insn "<avx512>_fmsub_<mode>_mask<round_name>"): Rename from
+ "avx512f_fmsub_<mode>_mask<round_name>" and use VF_AVX512VL mode
+ iterator.
+ (define_insn "<avx512>_fmsub_<mode>_mask3<round_name>"): Rename from
+ "avx512f_fmsub_<mode>_mask3<round_name>" and use VF_AVX512VL mode
+ iterator.
+ (define_insn "*fma_fnmadd_<mode>"): Rename from
+ "<sd_mask_codefor>fma_fnmadd_<mode><sd_maskz_name><round_name>" and
+ use FMAMODE mode iterator.
+ (define_insn "<sd_mask_codefor>fma_fnmadd_<mode><sd_maskz_name><round_name>"):
+ Use VF_SF_AVX512VL mode iterator.
+ (define_insn "<avx512>_fnmadd_<mode>_mask<round_name>"): Rename from
+ "avx512f_fnmadd_<mode>_mask<round_name>" and use VF_AVX512VL mode
+ iterator.
+ (define_insn "<avx512>_fnmadd_<mode>_mask3<round_name>"): Rename from
+ "avx512f_fnmadd_<mode>_mask3<round_name>" and use VF_AVX512VL mode
+ iterator.
+ (define_insn "*fma_fnmsub_<mode>"): Rename from
+ "<sd_mask_codefor>fma_fnmsub_<mode><sd_maskz_name><round_name>" and use
+ FMAMODE mode iterator.
+ (define_insn "<sd_mask_codefor>fma_fnmsub_<mode><sd_maskz_name><round_name>"):
+ Use VF_SF_AVX512VL mode iterator.
+ (define_insn "<avx512>_fnmsub_<mode>_mask<round_name>"): Rename from
+ "avx512f_fnmsub_<mode>_mask<round_name>" and use VF_AVX512VL mode
+ iterator.
+ (define_insn "<avx512>_fnmsub_<mode>_mask3<round_name>"): Rename from
+ "avx512f_fnmsub_<mode>_mask3<round_name>" and use VF_AVX512VL mode
+ iterator.
+ (define_expand "<avx512>_fmaddsub_<mode>_maskz<round_expand_name>"):
+ Rename from "avx512f_fmaddsub_<mode>_maskz<round_expand_name>" and
+ use VF_AVX512VL mode iterator.
+ (define_insn "*fma_fmaddsub_<mode>"): Rename from
+ "<sd_mask_codefor>fma_fmaddsub_<mode><sd_maskz_name><round_name>" and
+ remove subst usage.
+ (define_insn "<sd_mask_codefor>fma_fmaddsub_<mode><sd_maskz_name><round_name>"):
+ Use VF_SF_AVX512VL mode iterator.
+ (define_insn "<avx512>_fmaddsub_<mode>_mask<round_name>"): Rename from
+ "avx512f_fmaddsub_<mode>_mask<round_name>" and use VF_AVX512VL mode
+ iterator.
+ (define_insn "<avx512>_fmaddsub_<mode>_mask3<round_name>"): Rename from
+ "avx512f_fmaddsub_<mode>_mask3<round_name>" and use VF_AVX512VL mode
+ iterator.
+ (define_insn "*fma_fmsubadd_<mode>"): Rename from
+ "<sd_mask_codefor>fma_fmsubadd_<mode><sd_maskz_name><round_name>" and
+ remove usage of subst.
+ (define_insn "<sd_mask_codefor>fma_fmsubadd_<mode><sd_maskz_name><round_name>"):
+ Use VF_SF_AVX512VL mode iterator.
+ (define_insn "<avx512>_fmsubadd_<mode>_mask<round_name>"): Rename from
+ "avx512f_fmsubadd_<mode>_mask<round_name>" and use VF_AVX512VL mode
+ iterator.
+ (define_insn "<avx512>_fmsubadd_<mode>_mask3<round_name>"): Rename from
+ "avx512f_fmsubadd_<mode>_mask3<round_name>" and use VF_AVX512VL mode
+ iterator.
+
+2014-09-10 Kugan Vivekanandarajah <kuganv@linaro.org>
+
+ Revert r213751:
+ * calls.c (precompute_arguments): Check
+ promoted_for_signed_and_unsigned_p and set the promoted mode.
+ (promoted_for_signed_and_unsigned_p): New function.
+ (expand_expr_real_1): Check promoted_for_signed_and_unsigned_p
+ and set the promoted mode.
+ * expr.h (promoted_for_signed_and_unsigned_p): New function definition.
+ * cfgexpand.c (expand_gimple_stmt_1): Call emit_move_insn if
+ SUBREG is promoted with SRP_SIGNED_AND_UNSIGNED.
+
+2014-09-09 Manuel López-Ibáñez <manu@gcc.gnu.org>
+
+ * opth-gen.awk: Generate mapping from cpp message reasons to the
+ options that enable them.
+ * doc/options.texi (CppReason): Document.
+
+2014-09-09 Manuel López-Ibáñez <manu@gcc.gnu.org>
+
+ * doc/invoke.texi (Wnormalized=): Update.
+
+2014-09-09 Segher Boessenkool <segher@kernel.crashing.org>
+
+ PR target/63195
+ * config/rs6000/rs6000.md (*bool<mode>3): Allow only register
+ operands. Split off the constant operand alternative to ...
+ (*bool<mode>3_imm): New.
+
+2014-09-09 David Malcolm <dmalcolm@redhat.com>
+
+ * rtl.h (single_set_2): Strengthen first param from const_rtx to
+ const rtx_insn *, and move prototype to above...
+ (single_set): ...this. Convert this from a macro to an inline
+ function, enforcing the requirement that the param is a const
+ rtx_insn *.
+ (find_args_size_adjust): Strengthen param from rtx to rtx_insn *.
+
+ * config/arm/aarch-common-protos.h (aarch_crypto_can_dual_issue):
+ Strengthen both params from rtx to rtx_insn *.
+ * config/arm/aarch-common.c (aarch_crypto_can_dual_issue):
+ Likewise; introduce locals "producer_set", "consumer_set", using
+ them in place of "producer" and "consumer" when dealing with SET
+ rather than insn.
+ * config/avr/avr.c (avr_out_plus): Add checked cast to rtx_insn *
+ when invoking single_set in region guarded by INSN_P.
+ (avr_out_bitop): Likewise.
+ (_reg_unused_after): Introduce local rtx_sequence * "seq" in
+ region guarded by GET_CODE check, using methods to strengthen
+ local "this_insn" from rtx to rtx_insn *, and for clarity.
+ * config/avr/avr.md (define_insn_and_split "xload8<mode>_A"):
+ Strengthen local "insn" from rtx to rtx_insn *.
+ (define_insn_and_split "xload<mode>_A"): Likewise.
+ * config/bfin/bfin.c (trapping_loads_p): Likewise for param
+ "insn".
+ (find_load): Likewise for return type.
+ (workaround_speculation): Likewise for both locals named
+ "load_insn".
+ * config/cris/cris.c (cris_cc0_user_requires_cmp): Likewise for
+ local "cc0_user".
+ * config/cris/cris.md (define_peephole2 ; moversideqi): Likewise
+ for local "prev".
+ * config/h8300/h8300-protos.h (notice_update_cc): Likewise for
+ param 2.
+ * config/h8300/h8300.c (notice_update_cc): Likewise.
+ * config/i386/i386.c (ix86_flags_dependent): Likewise for params
+ "insn" and "dep_insn".
+ (exact_store_load_dependency): Likewise for both params.
+ (ix86_macro_fusion_pair_p): Eliminate local named "single_set"
+ since this now clashes with inline function. Instead, delay
+ calling single_set until the point where its needed, and then
+ assign the result to "compare_set" and rework the conditional that
+ follows.
+ * config/ia64/ia64.md (define_expand "tablejump"): Strengthen
+ local "last" from rtx to rtx_insn *.
+ * config/mips/mips-protos.h (mips_load_store_insns): Likewise for
+ second param.
+ (mips_store_data_bypass_p): Likewise for both params.
+ * config/mips/mips.c (mips_load_store_insns): Likewise for second
+ param.
+ (mips_store_data_bypass_p): Likewise for both params.
+ (mips_orphaned_high_part_p): Likewise for param "insn".
+ * config/mn10300/mn10300.c (extract_bundle): Likewise.
+ (mn10300_bundle_liw): Likewise for locals "r", "insn1", "insn2".
+ Introduce local rtx "insn2_pat".
+ * config/rl78/rl78.c (move_elim_pass): Likewise for locals "insn",
+ "ninsn".
+ (rl78_remove_unused_sets): Likewise for locals "insn", "ninsn".
+ Introduce local rtx "set", using it in place of "insn" for the
+ result of single_set. This appears to fix a bug, since the call
+ to find_regno_note on a SET does nothing.
+ * config/rs6000/rs6000.c (set_to_load_agen): Strengthen both
+ params from rtx to rtx_insn *.
+ (set_to_load_agen): Likewise.
+ * config/s390/s390.c (s390_label_align): Likewise for local
+ "prev_insn". Introduce new rtx locals "set" and "src", using
+ them in place of "prev_insn" for the results of single_set
+ and SET_SRC respectively.
+ (s390_swap_cmp): Strengthen local "jump" from rtx to rtx_insn *.
+ Introduce new rtx local "set" using in place of "jump" for the
+ result of single_set. Use SET_SRC (set) rather than plain
+ XEXP (set, 1).
+ * config/sh/sh.c (noncall_uses_reg): Strengthen param 2from
+ rtx to rtx_insn *.
+ (noncall_uses_reg): Likewise.
+ (reg_unused_after): Introduce local rtx_sequence * "seq" in region
+ guarded by GET_CODE check, using its methods for clarity, and to
+ enable strengthening local "this_insn" from rtx to rtx_insn *.
+ * config/sh/sh.md (define_expand "mulhisi3"): Strengthen local
+ "insn" from rtx to rtx_insn *.
+ (define_expand "umulhisi3"): Likewise.
+ (define_expand "smulsi3_highpart"): Likewise.
+ (define_expand "umulsi3_highpart"): Likewise.
+ * config/sparc/sparc.c (sparc_do_work_around_errata): Likewise for
+ local "after". Replace GET_CODE check with a dyn_cast,
+ introducing new local rtx_sequence * "seq", using insn method for
+ typesafety.
+
+ * dwarf2cfi.c (dwarf2out_frame_debug): Strengthen param "insn"
+ from rtx to rtx_insn *. Introduce local rtx "pat", using it in
+ place of "insn" once we're dealing with patterns rather than the
+ input insn.
+ (scan_insn_after): Strengthen param "insn" from rtx to rtx_insn *.
+ (scan_trace): Likewise for local "elt", updating lookups within
+ sequence to use insn method rather than element method.
+ * expr.c (find_args_size_adjust): Strengthen param "insn" from rtx
+ to rtx_insn *.
+ * gcse.c (gcse_emit_move_after): Likewise for local "new_rtx".
+ * ifcvt.c (noce_try_abs): Likewise for local "insn".
+ * ira.c (fix_reg_equiv_init): Add checked cast to rtx_insn * when
+ invoking single_set.
+ * lra-constraints.c (insn_rhs_dead_pseudo_p): Strengthen param
+ "insn" from rtx to rtx_insn *.
+ (skip_usage_debug_insns): Likewise for return type, adding a
+ checked cast.
+ (check_secondary_memory_needed_p): Likewise for local "insn".
+ (inherit_reload_reg): Likewise.
+ * modulo-sched.c (sms_schedule): Likewise for local "count_init".
+ * recog.c (peep2_attempt): Likewise for local "old_insn", adding
+ checked casts.
+ (store_data_bypass_p): Likewise for both params.
+ (if_test_bypass_p): Likewise.
+ * recog.h (store_data_bypass_p): Likewise for both params.
+ (if_test_bypass_p): Likewise.
+ * reload.c (find_equiv_reg): Likewise for local "where".
+ * reorg.c (delete_jump): Likewise for param "insn".
+ * rtlanal.c (single_set_2): Strenghen param "insn" from const_rtx
+ to const rtx_insn *.
+ * store-motion.c (replace_store_insn): Likewise for param "del".
+ (delete_store): Strengthen local "i" from rtx to rtx_insn_list *,
+ and use its methods for clarity, and to strengthen local "del"
+ from rtx to rtx_insn *.
+ (build_store_vectors): Use insn method of "st" when calling
+ replace_store_insn for typesafety and clarity.
+
+2014-09-09 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
+
+ * config/rs6000/rs6000.c (rtx_is_swappable_p): Add
+ UNSPEC_VSX_CVDPSPN as an unswappable operand, and add commentary
+ on how to make it legal in future.
+
+2014-09-09 David Malcolm <dmalcolm@redhat.com>
+
+ * caller-save.c (rtx saveinsn): Strengthen this variable from rtx
+ to rtx_insn *.
+ (restinsn): Likewise.
+ * config/aarch64/aarch64-protos.h (aarch64_simd_attr_length_move):
+ Likewise for param.
+ * config/aarch64/aarch64.c (aarch64_simd_attr_length_move):
+ Likewise.
+ * config/arc/arc-protos.h (arc_adjust_insn_length): Likewise for
+ first param.
+ (arc_hazard): Likewise for both params.
+ * config/arc/arc.c (arc600_corereg_hazard): Likewise, adding
+ checked casts to rtx_sequence * and uses of the insn method for
+ type-safety.
+ (arc_hazard): Strengthen both params from rtx to rtx_insn *.
+ (arc_adjust_insn_length): Likewise for param "insn".
+ (struct insn_length_parameters_s): Likewise for first param of
+ "get_variants" callback field.
+ (arc_get_insn_variants): Likewise for first param and local
+ "inner". Replace a check of GET_CODE with a dyn_cast to
+ rtx_sequence *, using methods for type-safety and clarity.
+ * config/arc/arc.h (ADJUST_INSN_LENGTH): Use casts to
+ rtx_sequence * and uses of the insn method for type-safety when
+ invoking arc_adjust_insn_length.
+ * config/arm/arm-protos.h (arm_attr_length_move_neon): Likewise
+ for param.
+ (arm_address_offset_is_imm): Likewise.
+ (struct tune_params): Likewise for params 1 and 3 of the
+ "sched_adjust_cost" callback field.
+ * config/arm/arm.c (cortex_a9_sched_adjust_cost): Likewise for
+ params 1 and 3 ("insn" and "dep").
+ (xscale_sched_adjust_cost): Likewise.
+ (fa726te_sched_adjust_cost): Likewise.
+ (cortexa7_older_only): Likewise for param "insn".
+ (cortexa7_younger): Likewise.
+ (arm_attr_length_move_neon): Likewise.
+ (arm_address_offset_is_imm): Likewise.
+ * config/avr/avr-protos.h (avr_notice_update_cc): Likewise.
+ * config/avr/avr.c (avr_notice_update_cc): Likewise.
+ * config/bfin/bfin.c (hwloop_pattern_reg): Likewise.
+ (workaround_speculation): Likewise for local "last_condjump".
+ * config/c6x/c6x.c (shadow_p): Likewise for param "insn".
+ (shadow_or_blockage_p): Likewise.
+ (get_unit_reqs): Likewise.
+ (get_unit_operand_masks): Likewise.
+ (c6x_registers_update): Likewise.
+ (returning_call_p): Likewise.
+ (can_use_callp): Likewise.
+ (convert_to_callp): Likewise.
+ (find_last_same_clock): Likwise for local "t".
+ (reorg_split_calls): Likewise for local "shadow".
+ (hwloop_pattern_reg): Likewise for param "insn".
+ * config/frv/frv-protos.h (frv_final_prescan_insn): Likewise.
+ * config/frv/frv.c (frv_final_prescan_insn): Likewise.
+ (frv_extract_membar): Likewise.
+ (frv_optimize_membar_local): Strengthen param "last_membar" from
+ rtx * to rtx_insn **.
+ (frv_optimize_membar_global): Strengthen param "membar" from rtx
+ to rtx_insn *.
+ (frv_optimize_membar): Strengthen local "last_membar" from rtx *
+ to rtx_insn **.
+ * config/ia64/ia64-protos.h (ia64_st_address_bypass_p): Strengthen
+ both params from rtx to rtx_insn *.
+ (ia64_ld_address_bypass_p): Likewise.
+ * config/ia64/ia64.c (ia64_safe_itanium_class): Likewise for param
+ "insn".
+ (ia64_safe_type): Likewise.
+ (group_barrier_needed): Likewise.
+ (safe_group_barrier_needed): Likewise.
+ (ia64_single_set): Likewise.
+ (is_load_p): Likewise.
+ (record_memory_reference): Likewise.
+ (get_mode_no_for_insn): Likewise.
+ (important_for_bundling_p): Likewise.
+ (unknown_for_bundling_p): Likewise.
+ (ia64_st_address_bypass_p): Likewise for both params.
+ (ia64_ld_address_bypass_p): Likewise.
+ (expand_vselect): Introduce new local rtx_insn * "insn", using it
+ in place of rtx "x" after the emit_insn call.
+ * config/i386/i386-protos.h (x86_extended_QIreg_mentioned_p):
+ Strengthen param from rtx to rtx_insn *.
+ (ix86_agi_dependent): Likewise for both params.
+ (ix86_attr_length_immediate_default): Likewise for param 1.
+ (ix86_attr_length_address_default): Likewise for param.
+ (ix86_attr_length_vex_default): Likewise for param 1.
+ * config/i386/i386.c (ix86_attr_length_immediate_default):
+ Likewise for param "insn".
+ (ix86_attr_length_address_default): Likewise.
+ (ix86_attr_length_vex_default): Likewise.
+ (ix86_agi_dependent): Likewise for both params.
+ (x86_extended_QIreg_mentioned_p): Likewise for param "insn".
+ (vselect_insn): Likewise for this variable.
+ * config/m68k/m68k-protos.h (m68k_sched_attr_opx_type): Likewise
+ for param 1.
+ (m68k_sched_attr_opy_type): Likewise.
+ * config/m68k/m68k.c (sched_get_operand): Likewise.
+ (sched_attr_op_type): Likewise.
+ (m68k_sched_attr_opx_type): Likewise.
+ (m68k_sched_attr_opy_type): Likewise.
+ (sched_get_reg_operand): Likewise.
+ (sched_get_mem_operand): Likewise.
+ (m68k_sched_address_bypass_p): Likewise for both params.
+ (sched_get_indexed_address_scale): Likewise.
+ (m68k_sched_indexed_address_bypass_p): Likewise.
+ * config/m68k/m68k.h (m68k_sched_address_bypass_p): Likewise.
+ (m68k_sched_indexed_address_bypass_p): Likewise.
+ * config/mep/mep.c (mep_jmp_return_reorg): Strengthen locals
+ "label", "ret" from rtx to rtx_insn *, adding a checked cast and
+ removing another.
+ * config/mips/mips-protos.h (mips_linked_madd_p): Strengthen both
+ params from rtx to rtx_insn *.
+ (mips_fmadd_bypass): Likewise.
+ * config/mips/mips.c (mips_fmadd_bypass): Likewise.
+ (mips_linked_madd_p): Likewise.
+ (mips_macc_chains_last_hilo): Likewise for this variable.
+ (mips_macc_chains_record): Likewise for param.
+ (vr4130_last_insn): Likewise for this variable.
+ (vr4130_swap_insns_p): Likewise for both params.
+ (mips_ls2_variable_issue): Likewise for param.
+ (mips_need_noat_wrapper_p): Likewise for param "insn".
+ (mips_expand_vselect): Add a new local rtx_insn * "insn", using it
+ in place of "x" after the emit_insn.
+ * config/pa/pa-protos.h (pa_fpstore_bypass_p): Strengthen both
+ params from rtx to rtx_insn *.
+ * config/pa/pa.c (pa_fpstore_bypass_p): Likewise.
+ (pa_combine_instructions): Introduce local "par" for result of
+ gen_rtx_PARALLEL, moving decl and usage of new_rtx for after call
+ to make_insn_raw.
+ (pa_can_combine_p): Strengthen param "new_rtx" from rtx to rtx_insn *.
+ * config/rl78/rl78.c (insn_ok_now): Likewise for param "insn".
+ (rl78_alloc_physical_registers_op1): Likewise.
+ (rl78_alloc_physical_registers_op2): Likewise.
+ (rl78_alloc_physical_registers_ro1): Likewise.
+ (rl78_alloc_physical_registers_cmp): Likewise.
+ (rl78_alloc_physical_registers_umul): Likewise.
+ (rl78_alloc_address_registers_macax): Likewise.
+ (rl78_alloc_physical_registers): Likewise for locals "insn", "curr".
+ * config/s390/predicates.md (execute_operation): Likewise for
+ local "insn".
+ * config/s390/s390-protos.h (s390_agen_dep_p): Likewise for both
+ params.
+ * config/s390/s390.c (s390_safe_attr_type): Likewise for param.
+ (addr_generation_dependency_p): Likewise for param "insn".
+ (s390_agen_dep_p): Likewise for both params.
+ (s390_fpload_toreg): Likewise for param "insn".
+ * config/sh/sh-protos.h (sh_loop_align): Likewise for param.
+ * config/sh/sh.c (sh_loop_align): Likewise for param and local
+ "next".
+ * config/sh/sh.md (define_peephole2): Likewise for local "insn2".
+ * config/sh/sh_treg_combine.cc
+ (sh_treg_combine::make_inv_ccreg_insn): Likewise for return type
+ and local "i".
+ (sh_treg_combine::try_eliminate_cstores): Likewise for local "i".
+ * config/stormy16/stormy16.c (combine_bnp): Likewise for locals
+ "and_insn", "load", "shift".
+ * config/tilegx/tilegx.c (match_pcrel_step2): Likewise for param
+ "insn".
+ * final.c (final_scan_insn): Introduce local rtx_insn * "other"
+ for XEXP (note, 0) of the REG_CC_SETTER note.
+ (cleanup_subreg_operands): Strengthen param "insn" from rtx to
+ rtx_insn *, eliminating a checked cast made redundant by this.
+ * gcse.c (process_insert_insn): Strengthen local "insn" from rtx
+ to rtx_insn *.
+ * genattr.c (main): When writing out the prototype to
+ const_num_delay_slots, strengthen the param from rtx to
+ rtx_insn *.
+ * genattrtab.c (write_const_num_delay_slots): Likewise when
+ writing out the implementation of const_num_delay_slots.
+ * hw-doloop.h (struct hw_doloop_hooks): Strengthen the param
+ "insn" of callback field "end_pattern_reg" from rtx to rtx_insn *.
+ * ifcvt.c (noce_emit_store_flag): Eliminate local rtx "tmp" in
+ favor of new rtx locals "src" and "set" and new local rtx_insn *
+ "insn" and "seq".
+ (noce_emit_move_insn): Strengthen locals "seq" and "insn" from rtx
+ to rtx_insn *.
+ (noce_emit_cmove): Eliminate local rtx "tmp" in favor of new rtx
+ locals "cond", "if_then_else", "set" and new rtx_insn * locals
+ "insn" and "seq".
+ (noce_try_cmove_arith): Strengthen locals "insn_a" and "insn_b",
+ "last" from rtx to rtx_insn *. Likewise for a local "tmp",
+ renaming to "tmp_insn". Eliminate the other local rtx "tmp" from
+ the top-level scope, replacing with new more tightly-scoped rtx
+ locals "reg", "pat", "mem" and rtx_insn * "insn", "copy_of_a",
+ "new_insn", "copy_of_insn_b", and make local rtx "set" more
+ tightly-scoped.
+ * ira-int.h (ira_setup_alts): Strengthen param "insn" from rtx to
+ rtx_insn *.
+ * ira.c (setup_prohibited_mode_move_regs): Likewise for local
+ "move_insn".
+ (ira_setup_alts): Likewise for param "insn".
+ * lra-constraints.c (emit_inc): Likewise for local "add_insn".
+ * lra.c (emit_add3_insn): Split local rtx "insn" in two, an rtx
+ and an rtx_insn *.
+ (lra_emit_add): Eliminate top-level local rtx "insn" in favor of
+ new more-tightly scoped rtx locals "add3_insn", "insn",
+ "add2_insn" and rtx_insn * "move_insn".
+ * postreload-gcse.c (eliminate_partially_redundant_load): Add
+ checked cast on result of gen_move_insn when invoking
+ extract_insn.
+ * recog.c (insn_invalid_p): Strengthen param "insn" from rtx to
+ rtx_insn *.
+ (verify_changes): Add a checked cast on "object" when invoking
+ insn_invalid_p.
+ (extract_insn_cached): Strengthen param "insn" from rtx to
+ rtx_insn *.
+ (extract_constrain_insn_cached): Likewise.
+ (extract_insn): Likewise.
+ * recog.h (insn_invalid_p): Likewise for param 1.
+ (recog_memoized): Likewise for param.
+ (extract_insn): Likewise.
+ (extract_constrain_insn_cached): Likewise.
+ (extract_insn_cached): Likewise.
+ * reload.c (can_reload_into): Likewise for local "test_insn".
+ * reload.h (cleanup_subreg_operands): Likewise for param.
+ * reload1.c (emit_insn_if_valid_for_reload): Rename param from
+ "insn" to "pat", reintroducing "insn" as an rtx_insn * on the
+ result of emit_insn. Remove a checked cast made redundant by this
+ change.
+ * sel-sched-ir.c (sel_insn_rtx_cost): Strengthen param "insn" from
+ rtx to rtx_insn *.
+ * sel-sched.c (get_reg_class): Likewise.
+
+2014-09-09 Marcus Shawcroft <marcus.shawcroft@arm.com>
+ Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+
+ * config/aarch64/aarch64-elf-raw.h (ENDFILE_SPEC): Add crtfastmath.o.
+ * config/aarch64/aarch64-linux.h (GNU_USER_TARGET_MATH_ENDFILE_SPEC):
+ Define.
+ (ENDFILE_SPEC): Define and use GNU_USER_TARGET_MATH_ENDFILE_SPEC.
+
+2014-09-09 David Malcolm <dmalcolm@redhat.com>
+
+ * rtl.h (INSN_LOCATION): Strengthen param from const_rtx to
+ const rtx_insn *, and from rtx to rtx_insn * for the other
+ overloaded variant.
+ (RTL_LOCATION): Add a checked cast to rtx_insn * when invoking
+ INSN_LOCATION, since we know INSN_P holds.
+ (insn_line): Strengthen param from const_rtx to const rtx_insn *.
+ (insn_file): Likewise.
+ (insn_scope): Likewise.
+ (insn_location): Likewise.
+
+ * config/mips/mips.c (mips16_gp_pseudo_reg): Strengthen local
+ "insn" from rtx to rtx_insn *, introducing a new local rtx "set"
+ for the result of gen_load_const_gp.
+ * config/rs6000/rs6000-protos.h (output_call): Strengthen first
+ param from rtx to rtx_insn *.
+ * config/rs6000/rs6000.c (output_call): Likewise.
+ * dwarf2out.c (dwarf2out_var_location): Likewise for local "prev",
+ introducing a checked cast to rtx_sequence * and use of the insn
+ method.
+ * emit-rtl.c (emit_copy_of_insn_after): Strengthen both params
+ from rtx to rtx_insn *.
+ (insn_scope): Strengthen param from const_rtx to const rtx_insn *.
+ (insn_line): Likewise.
+ (insn_file): Likewise.
+ (insn_location): Likewise.
+ * emit-rtl.h (emit_copy_of_insn_after): Strengthen both params
+ from rtx to rtx_insn *.
+ * print-rtl.c (print_rtx): Introduce local "in_insn" via a checked
+ cast, using it for calls to INSN_HAS_LOCATION and insn_location.
+ * recog.c (peep2_attempt): Introduce local rtx_insn * "peepinsn"
+ via a checked cast.
+ * reorg.c (relax_delay_slots): Strengthen locals named "after"
+ from rtx to rtx_insn *; use methods of "pat" for type-safety.
+
2014-09-09 David Malcolm <dmalcolm@redhat.com>
* combine.c (try_combine): Eliminate checked cast on result of
projects / gcc.git / blobdiff