+2020-03-04 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/94001
+ * tree-tailcall.c (process_assignment): Before comparing op1 to
+ *ass_var, verify *ass_var is non-NULL.
+
+2020-03-04 Kito Cheng <kito.cheng@sifive.com>
+
+ PR target/93995
+ * config/riscv/riscv.c (riscv_emit_float_compare): Using NE to compare
+ the result of IOR.
+
+2020-03-03 Dennis Zhang <dennis.zhang@arm.com>
+
+ * config/arm/arm_bf16.h (vcvtah_f32_bf16, vcvth_bf16_f32): New.
+ * config/arm/arm_neon.h (vcvt_f32_bf16, vcvtq_low_f32_bf16): New.
+ (vcvtq_high_f32_bf16, vcvt_bf16_f32): New.
+ (vcvtq_low_bf16_f32, vcvtq_high_bf16_f32): New.
+ * config/arm/arm_neon_builtins.def (vbfcvt, vbfcvt_high): New entries.
+ (vbfcvtv4sf, vbfcvtv4sf_high): Likewise.
+ * config/arm/iterators.md (VBFCVT, VBFCVTM): New mode iterators.
+ (V_bf_low, V_bf_cvt_m): New mode attributes.
+ * config/arm/neon.md (neon_vbfcvtv4sf<VBFCVT:mode>): New.
+ (neon_vbfcvtv4sf_highv8bf, neon_vbfcvtsf): New.
+ (neon_vbfcvt<VBFCVT:mode>, neon_vbfcvt_highv8bf): New.
+ (neon_vbfcvtbf_cvtmode<mode>, neon_vbfcvtbf): New
+ * config/arm/unspecs.md (UNSPEC_BFCVT, UNSPEC_BFCVT_HIG): New.
+
+2020-03-03 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/93582
+ * tree-ssa-sccvn.h (vn_reference_lookup): Add mask argument.
+ * tree-ssa-sccvn.c (struct vn_walk_cb_data): Add mask and masked_result
+ members, initialize them in the constructor and if mask is non-NULL,
+ artificially push_partial_def {} for the portions of the mask that
+ contain zeros.
+ (vn_walk_cb_data::finish): If mask is non-NULL, set masked_result to
+ val and return (void *)-1. Formatting fix.
+ (vn_reference_lookup_pieces): Adjust vn_walk_cb_data initialization.
+ Formatting fix.
+ (vn_reference_lookup): Add mask argument. If non-NULL, don't call
+ fully_constant_vn_reference_p nor vn_reference_lookup_1 and return
+ data.mask_result.
+ (visit_nary_op): Handle BIT_AND_EXPR of a memory load and INTEGER_CST
+ mask.
+ (visit_stmt): Formatting fix.
+
+2020-03-03 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/93946
+ * alias.h (refs_same_for_tbaa_p): Declare.
+ * alias.c (refs_same_for_tbaa_p): New function.
+ * tree-ssa-alias.c (ao_ref_alias_set): For a NULL ref return
+ zero.
+ * tree-ssa-scopedtables.h
+ (avail_exprs_stack::lookup_avail_expr): Add output argument
+ giving access to the hashtable entry.
+ * tree-ssa-scopedtables.c (avail_exprs_stack::lookup_avail_expr):
+ Likewise.
+ * tree-ssa-dom.c: Include alias.h.
+ (dom_opt_dom_walker::optimize_stmt): Validate TBAA state before
+ removing redundant store.
+ * tree-ssa-sccvn.h (vn_reference_s::base_set): New member.
+ (ao_ref_init_from_vn_reference): Adjust prototype.
+ (vn_reference_lookup_pieces): Likewise.
+ (vn_reference_insert_pieces): Likewise.
+ * tree-ssa-sccvn.c: Track base alias set in addition to alias
+ set everywhere.
+ (eliminate_dom_walker::eliminate_stmt): Also check base alias
+ set when removing redundant stores.
+ (visit_reference_op_store): Likewise.
+ * dse.c (record_store): Adjust valdity check for redundant
+ store removal.
+
+2020-03-03 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/26877
+ * config/s390/s390.h (OPTION_DEFAULT_SPECS): Reorder.
+
+ PR rtl-optimization/94002
+ * explow.c (plus_constant): Punt if cst has VOIDmode and
+ get_pool_mode is different from mode.
+
+2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * config/arc/arc.c (leigitimate_small_data_address_p): Check if an
+ address has an offset which fits the scalling constraint for a
+ load/store operation.
+ (legitimate_scaled_address_p): Update use
+ leigitimate_small_data_address_p.
+ (arc_print_operand): Likewise.
+ (arc_legitimate_address_p): Likewise.
+ (legitimate_small_data_address_p): Likewise.
+
+2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * config/arc/arc.md (fmasf4_fpu): Use accl_operand predicate.
+ (fnmasf4_fpu): Likewise.
+
+2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * config/arc/arc.md (adddi3): Early expand the 64bit operation into
+ 32bit ops.
+ (subdi3): Likewise.
+ (adddi3_i): Remove pattern.
+ (subdi3_i): Likewise.
+
+2020-03-03 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * config/arc/arc.md (eh_return): Add length info.
+
+2020-03-02 David Malcolm <dmalcolm@redhat.com>
+
+ * doc/invoke.texi (-fanalyzer-show-duplicate-count): New.
+
+2020-03-02 David Malcolm <dmalcolm@redhat.com>
+
+ * doc/invoke.texi (Static Analyzer Options): Add
+ -Wanalyzer-stale-setjmp-buffer to the list of options enabled
+ by -fanalyzer.
+
+2020-03-02 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/93997
+ * config/i386/i386.md (movstrict<mode>): Allow only
+ registers with VALID_INT_MODE_P modes.
+
+2020-03-02 Andrew Stubbs <ams@codesourcery.com>
+
+ * config/gcn/gcn-valu.md (dpp_move<mode>): New.
+ (reduc_insn): Use 'U' and 'B' operand codes.
+ (reduc_<reduc_op>_scal_<mode>): Allow all types.
+ (reduc_<reduc_op>_scal_v64di): Delete.
+ (*<reduc_op>_dpp_shr_<mode>): Allow all 1reg types.
+ (*plus_carry_dpp_shr_v64si): Change to ...
+ (*plus_carry_dpp_shr_<mode>): ... this and allow all 1reg int types.
+ (mov_from_lane63_v64di): Change to ...
+ (mov_from_lane63_<mode>): ... this, and allow all 64-bit modes.
+ * config/gcn/gcn.c (gcn_expand_dpp_shr_insn): Increase buffer size.
+ Support UNSPEC_MOV_DPP_SHR output formats.
+ (gcn_expand_reduc_scalar): Add "use_moves" reductions.
+ Add "use_extends" reductions.
+ (print_operand_address): Add 'I' and 'U' codes.
+ * config/gcn/gcn.md (unspec): Add UNSPEC_MOV_DPP_SHR.
+
+2020-03-02 Martin Liska <mliska@suse.cz>
+
+ * lto-wrapper.c: Fix typo in comment about
+ C++ standard version.
+
+2020-03-01 Martin Sebor <msebor@redhat.com>
+
+ PR c++/92721
+ * calls.c (init_attr_rdwr_indices): Correctly handle attribute.
+
+2020-03-01 Martin Sebor <msebor@redhat.com>
+
+ PR middle-end/93829
+ * tree-ssa-strlen.c (count_nonzero_bytes): Set the size to that
+ of a pointer in the outermost ADDR_EXPRs.
+
+2020-02-28 Jeff Law <law@redhat.com>
+
+ * config/v850/v850.h (STATIC_CHAIN_REGNUM): Change to r19.
+ * config/v850/v850.c (v850_asm_trampoline_template): Update
+ accordingly.
+
+2020-02-28 Michael Meissner <meissner@linux.ibm.com>
+
+ PR target/93937
+ * config/rs6000/vsx.md (vsx_extract_<mode>_<VS_scalar>mode_var):
+ Delete insn.
+
+2020-02-28 Martin Liska <mliska@suse.cz>
+
+ PR other/93965
+ * configure.ac: Improve detection of ld_date by requiring
+ either two dashes or none.
+ * configure: Regenerate.
+
+2020-02-28 Vladimir Makarov <vmakarov@redhat.com>
+
+ PR rtl-optimization/93564
+ * ira-color.c (assign_hard_reg): Prefer smaller hard regno when we
+ do not honor reg alloc order.
+
+2020-02-27 Joel Hutton <Joel.Hutton@arm.com>
+
+ PR target/87612
+ * config/aarch64/aarch64.c (aarch64_override_options): Fix
+ misleading warning string.
+
+2020-02-27 Martin Sebor <msebor@redhat.com>
+
+ * doc/invoke.texi (-Wbuiltin-declaration-mismatch): Fix a typo.
+
+2020-02-27 Michael Meissner <meissner@linux.ibm.com>
+
+ PR target/93932
+ * config/rs6000/vsx.md (vsx_extract_<mode>_var, VSX_D iterator):
+ Split the insn into two parts. This insn only does variable
+ extract from a register.
+ (vsx_extract_<mode>_var_load, VSX_D iterator): New insn, do
+ variable extract from memory.
+ (vsx_extract_v4sf_var): Split the insn into two parts. This insn
+ only does variable extract from a register.
+ (vsx_extract_v4sf_var_load): New insn, do variable extract from
+ memory.
+ (vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): Split the insn
+ into two parts. This insn only does variable extract from a
+ register.
+ (vsx_extract_<mode>_var_load, VSX_EXTRACT_I iterator): New insn,
+ do variable extract from memory.
+
+2020-02-27 Martin Jambor <mjambor@suse.cz>
+ Feng Xue <fxue@os.amperecomputing.com>
+
+ PR ipa/93707
+ * ipa-cp.c (same_node_or_its_all_contexts_clone_p): Replaced with
+ new function calls_same_node_or_its_all_contexts_clone_p.
+ (cgraph_edge_brings_value_p): Use it.
+ (cgraph_edge_brings_value_p): Likewise.
+ (self_recursive_pass_through_p): Return false if caller is a clone.
+ (self_recursive_agg_pass_through_p): Likewise.
+
+2020-02-27 Jan Hubicka <hubicka@ucw.cz>
+
+ PR middle-end/92152
+ * alias.c (ends_tbaa_access_path_p): Break out from ...
+ (component_uses_parent_alias_set_from): ... here.
+ * alias.h (ends_tbaa_access_path_p): Declare.
+ * tree-ssa-alias.c (access_path_may_continue_p): Break out from ...;
+ handle trailing arrays past end of tbaa access path.
+ (aliasing_component_refs_p): ... here; likewise.
+ (nonoverlapping_refs_since_match_p): Track TBAA segment of the access
+ path; disambiguate also past end of it.
+ (nonoverlapping_component_refs_p): Use only TBAA segment of the access
+ path.
+
+2020-02-27 Mihail Ionescu <mihail.ionescu@arm.com>
+
+ * (__ARM_NUM_LANES, __arm_lane, __arm_lane_q): Move to the
+ beginning of the file.
+ (vcreate_bf16, vcombine_bf16): New.
+ (vdup_n_bf16, vdupq_n_bf16): New.
+ (vdup_lane_bf16, vdup_laneq_bf16): New.
+ (vdupq_lane_bf16, vdupq_laneq_bf16): New.
+ (vduph_lane_bf16, vduph_laneq_bf16): New.
+ (vset_lane_bf16, vsetq_lane_bf16): New.
+ (vget_lane_bf16, vgetq_lane_bf16): New.
+ (vget_high_bf16, vget_low_bf16): New.
+ (vreinterpret_bf16_u8, vreinterpretq_bf16_u8): New.
+ (vreinterpret_bf16_u16, vreinterpretq_bf16_u16): New.
+ (vreinterpret_bf16_u32, vreinterpretq_bf16_u32): New.
+ (vreinterpret_bf16_u64, vreinterpretq_bf16_u64): New.
+ (vreinterpret_bf16_s8, vreinterpretq_bf16_s8): New.
+ (vreinterpret_bf16_s16, vreinterpretq_bf16_s16): New.
+ (vreinterpret_bf16_s32, vreinterpretq_bf16_s32): New.
+ (vreinterpret_bf16_s64, vreinterpretq_bf16_s64): New.
+ (vreinterpret_bf16_p8, vreinterpretq_bf16_p8): New.
+ (vreinterpret_bf16_p16, vreinterpretq_bf16_p16): New.
+ (vreinterpret_bf16_p64, vreinterpretq_bf16_p64): New.
+ (vreinterpret_bf16_f32, vreinterpretq_bf16_f32): New.
+ (vreinterpret_bf16_f64, vreinterpretq_bf16_f64): New.
+ (vreinterpretq_bf16_p128): New.
+ (vreinterpret_s8_bf16, vreinterpretq_s8_bf16): New.
+ (vreinterpret_s16_bf16, vreinterpretq_s16_bf16): New.
+ (vreinterpret_s32_bf16, vreinterpretq_s32_bf16): New.
+ (vreinterpret_s64_bf16, vreinterpretq_s64_bf16): New.
+ (vreinterpret_u8_bf16, vreinterpretq_u8_bf16): New.
+ (vreinterpret_u16_bf16, vreinterpretq_u16_bf16): New.
+ (vreinterpret_u32_bf16, vreinterpretq_u32_bf16): New.
+ (vreinterpret_u64_bf16, vreinterpretq_u64_bf16): New.
+ (vreinterpret_p8_bf16, vreinterpretq_p8_bf16): New.
+ (vreinterpret_p16_bf16, vreinterpretq_p16_bf16): New.
+ (vreinterpret_p64_bf16, vreinterpretq_p64_bf16): New.
+ (vreinterpret_f32_bf16, vreinterpretq_f32_bf16): New.
+ (vreinterpretq_p128_bf16): New.
+ * config/arm/arm_neon_builtins.def (VDX): Add V4BF.
+ (V_elem): Likewise.
+ (V_elem_l): Likewise.
+ (VD_LANE): Likewise.
+ (VQX) Add V8BF.
+ (V_DOUBLE): Likewise.
+ (VDQX): Add V4BF and V8BF.
+ (V_two_elem, V_three_elem, V_four_elem): Likewise.
+ (V_reg): Likewise.
+ (V_HALF): Likewise.
+ (V_double_vector_mode): Likewise.
+ (V_cmp_result): Likewise.
+ (V_uf_sclr): Likewise.
+ (V_sz_elem): Likewise.
+ (Is_d_reg): Likewise.
+ (V_mode_nunits): Likewise.
+ * config/arm/neon.md (neon_vdup_lane): Enable for BFloat16.
+
+2020-02-27 Andrew Stubbs <ams@codesourcery.com>
+
+ * config/gcn/gcn-valu.md (VEC_SUBDWORD_MODE): New mode iterator.
+ (<expander><mode>2<exec>): Change modes to VEC_ALL1REG_INT_MODE.
+ (<expander><mode>3<exec>): Likewise.
+ (<expander><mode>3): New.
+ (v<expander><mode>3): New.
+ (<expander><mode>3): New.
+ (<expander><mode>3<exec>): Rename to ...
+ (<expander>v64si3<exec>): ... this, and change modes to V64SI.
+ * config/gcn/gcn.md (mnemonic): Use '%B' for not.
+
+2020-02-27 Alexandre Oliva <oliva@adacore.com>
+
+ * config/vx-common.h (NO_DOLLAR_IN_LABEL, NO_DOT_IN_LABEL): Leave
+ them alone on vx7.
+
+2020-02-27 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/93508
+ * tree-ssa-sccvn.c (vn_reference_lookup_3): Handle _CHK like
+ non-_CHK variants. Valueize their length arguments.
+
+2020-02-27 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/93953
+ * tree-vect-slp.c (slp_copy_subtree): Avoid keeping a reference
+ to the hash-map entry.
+
+2020-02-27 Andrew Stubbs <ams@codesourcery.com>
+
+ * config/gcn/gcn.md (mov<mode>): Add transformations for BI subregs.
+
+2020-02-27 Mark Williams <mwilliams@fb.com>
+
+ * dwarf2out.c (file_name_acquire): Call remap_debug_filename.
+ * lto-opts.c (lto_write_options): Drop -fdebug-prefix-map,
+ -ffile-prefix-map and -fmacro-prefix-map.
+ * lto-streamer-out.c: Include file-prefix-map.h.
+ (lto_output_location): Remap the file part of locations.
+
+2020-02-27 Jakub Jelinek <jakub@redhat.com>
+
+ PR c/93949
+ * gimplify.c (gimplify_init_constructor): Don't promote readonly
+ DECL_REGISTER variables to TREE_STATIC.
+
+ PR tree-optimization/93582
+ PR tree-optimization/93945
+ * tree-ssa-sccvn.c (vn_reference_lookup_3): Handle memset with
+ non-zero INTEGER_CST second argument and ref->offset or ref->size
+ not a multiple of BITS_PER_UNIT.
+
+2020-02-27 Jonathan Wakely <jwakely@redhat.com>
+
+ * doc/install.texi (Binaries): Update description of BullFreeware.
+
+2020-02-26 Sandra Loosemore <sandra@codesourcery.com>
+
+ PR c++/90467
+
+ * doc/invoke.texi (Option Summary): Re-alphabetize warnings in
+ C++ Language Options, Warning Options, and Static Analyzer
+ Options lists. Document negative form of options enabled by
+ default. Move some things around to more accurately sort
+ warnings by category.
+ (C++ Dialect Options, Warning Options, Static Analyzer
+ Options): Document negative form of options when enabled by
+ default. Move some things around to more accurately sort
+ warnings by category. Add some missing index entries.
+ Light copy-editing.
+
+2020-02-26 Carl Love <cel@us.ibm.com>
+
+ PR target/91276
+ * doc/extend.texi (PowerPC AltiVec Built-in Functions available on
+ ISA 2.07): The builtin-function name __builtin_crypto_vpmsumb is only
+ for the vector unsigned short arguments. It is also listed as the
+ name of the built-in for arguments vector unsigned short,
+ vector unsigned int and vector unsigned long long built-ins. The
+ name of the builtins for these arguments should be:
+ __builtin_crypto_vpmsumh, __builtin_crypto_vpmsumw and
+ __builtin_crypto_vpmsumd respectively.
+
+2020-02-26 Richard Biener <rguenther@suse.de>
+
+ * tree-vect-slp.c (vect_print_slp_tree): Also dump ref count
+ and load permutation.
+
+2020-02-26 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR middle-end/93843
+ * optabs-tree.c (supportable_convert_operation): Reject types with
+ scalar modes.
+
+2020-02-26 David Malcolm <dmalcolm@redhat.com>
+
+ * Makefile.in (ANALYZER_OBJS): Add analyzer/bar-chart.o.
+
+2020-02-26 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/93820
+ * gimple-ssa-store-merging.c (check_no_overlap): Change RHS_CODE
+ argument to ALL_INTEGER_CST_P boolean.
+ (imm_store_chain_info::try_coalesce_bswap): Adjust caller.
+ (imm_store_chain_info::coalesce_immediate_stores): Likewise. Handle
+ adjacent INTEGER_CST store into merged_store->only_constants like
+ overlapping one.
+
+2020-02-25 Jakub Jelinek <jakub@redhat.com>
+
+ PR other/93912
+ * config/sh/sh.c (expand_cbranchdi4): Fix comment typo, probablity
+ -> probability.
+ * cfghooks.c (verify_flow_info): Likewise.
+ * predict.c (combine_predictions_for_bb): Likewise.
+ * bb-reorder.c (connect_better_edge_p): Likewise. Fix comment typo,
+ sucessor -> successor.
+ (find_traces_1_round): Fix comment typo, destinarion -> destination.
+ * omp-expand.c (expand_oacc_for): Fix comment typo, sucessors ->
+ successors.
+ * tree-ssa-loop-ch.c (should_duplicate_loop_header_p): Fix dump
+ message typo, sucessors -> successors.
+
+2020-02-25 Martin Sebor <msebor@redhat.com>
+
+ * doc/extend.texi (attribute access): Correct an example.
+
+2020-02-25 Mihail Ionescu <mihail.ionescu@arm.com>
+
+ * config/aarch64/aarch64-builtins.c (aarch64_scalar_builtin_types):
+ Add simd_bf.
+ (aarch64_init_simd_builtin_scalar_types): Register simd_bf.
+ (VAR15, VAR16): New.
+ * config/aarch64/iterators.md (VALLDIF): Enable for V4BF and V8BF.
+ (VD): Enable for V4BF.
+ (VDC): Likewise.
+ (VQ): Enable for V8BF.
+ (VQ2): Likewise.
+ (VQ_NO2E): Likewise.
+ (VDBL, Vdbl): Add V4BF.
+ (V_INT_EQUIV, v_int_equiv): Add V4BF and V8BF.
+ * config/aarch64/arm_neon.h (bfloat16x4x2_t): New typedef.
+ (bfloat16x8x2_t): Likewise.
+ (bfloat16x4x3_t): Likewise.
+ (bfloat16x8x3_t): Likewise.
+ (bfloat16x4x4_t): Likewise.
+ (bfloat16x8x4_t): Likewise.
+ (vcombine_bf16): New.
+ (vld1_bf16, vld1_bf16_x2): New.
+ (vld1_bf16_x3, vld1_bf16_x4): New.
+ (vld1q_bf16, vld1q_bf16_x2): New.
+ (vld1q_bf16_x3, vld1q_bf16_x4): New.
+ (vld1_lane_bf16): New.
+ (vld1q_lane_bf16): New.
+ (vld1_dup_bf16): New.
+ (vld1q_dup_bf16): New.
+ (vld2_bf16): New.
+ (vld2q_bf16): New.
+ (vld2_dup_bf16): New.
+ (vld2q_dup_bf16): New.
+ (vld3_bf16): New.
+ (vld3q_bf16): New.
+ (vld3_dup_bf16): New.
+ (vld3q_dup_bf16): New.
+ (vld4_bf16): New.
+ (vld4q_bf16): New.
+ (vld4_dup_bf16): New.
+ (vld4q_dup_bf16): New.
+ (vst1_bf16, vst1_bf16_x2): New.
+ (vst1_bf16_x3, vst1_bf16_x4): New.
+ (vst1q_bf16, vst1q_bf16_x2): New.
+ (vst1q_bf16_x3, vst1q_bf16_x4): New.
+ (vst1_lane_bf16): New.
+ (vst1q_lane_bf16): New.
+ (vst2_bf16): New.
+ (vst2q_bf16): New.
+ (vst3_bf16): New.
+ (vst3q_bf16): New.
+ (vst4_bf16): New.
+ (vst4q_bf16): New.
+
+2020-02-25 Mihail Ionescu <mihail.ionescu@arm.com>
+
+ * config/aarch64/iterators.md (VDQF_F16) Add V4BF and V8BF.
+ (VALL_F16): Likewise.
+ (VALLDI_F16): Likewise.
+ (Vtype): Likewise.
+ (Vetype): Likewise.
+ (vswap_width_name): Likewise.
+ (VSWAP_WIDTH): Likewise.
+ (Vel): Likewise.
+ (VEL): Likewise.
+ (q): Likewise.
+ * config/aarch64/arm_neon.h (vset_lane_bf16, vsetq_lane_bf16): New.
+ (vget_lane_bf16, vgetq_lane_bf16): New.
+ (vcreate_bf16): New.
+ (vdup_n_bf16, vdupq_n_bf16): New.
+ (vdup_lane_bf16, vdup_laneq_bf16): New.
+ (vdupq_lane_bf16, vdupq_laneq_bf16): New.
+ (vduph_lane_bf16, vduph_laneq_bf16): New.
+ (vreinterpret_bf16_u8, vreinterpretq_bf16_u8): New.
+ (vreinterpret_bf16_u16, vreinterpretq_bf16_u16): New.
+ (vreinterpret_bf16_u32, vreinterpretq_bf16_u32): New.
+ (vreinterpret_bf16_u64, vreinterpretq_bf16_u64): New.
+ (vreinterpret_bf16_s8, vreinterpretq_bf16_s8): New.
+ (vreinterpret_bf16_s16, vreinterpretq_bf16_s16): New.
+ (vreinterpret_bf16_s32, vreinterpretq_bf16_s32): New.
+ (vreinterpret_bf16_s64, vreinterpretq_bf16_s64): New.
+ (vreinterpret_bf16_p8, vreinterpretq_bf16_p8): New.
+ (vreinterpret_bf16_p16, vreinterpretq_bf16_p16): New.
+ (vreinterpret_bf16_p64, vreinterpretq_bf16_p64): New
+ (vreinterpret_bf16_f16, vreinterpretq_bf16_f16): New
+ (vreinterpret_bf16_f32, vreinterpretq_bf16_f32): New.
+ (vreinterpret_bf16_f64, vreinterpretq_bf16_f64): New.
+ (vreinterpretq_bf16_p128): New.
+ (vreinterpret_s8_bf16, vreinterpretq_s8_bf16): New.
+ (vreinterpret_s16_bf16, vreinterpretq_s16_bf16): New.
+ (vreinterpret_s32_bf16, vreinterpretq_s32_bf16): New.
+ (vreinterpret_s64_bf16, vreinterpretq_s64_bf16): New.
+ (vreinterpret_u8_bf16, vreinterpretq_u8_bf16): New.
+ (vreinterpret_u16_bf16, vreinterpretq_u16_bf16): New.
+ (vreinterpret_u32_bf16, vreinterpretq_u32_bf16): New.
+ (vreinterpret_u64_bf16, vreinterpretq_u64_bf16): New.
+ (vreinterpret_p8_bf16, vreinterpretq_p8_bf16): New.
+ (vreinterpret_p16_bf16, vreinterpretq_p16_bf16): New.
+ (vreinterpret_p64_bf16, vreinterpretq_p64_bf16): New.
+ (vreinterpret_f32_bf16, vreinterpretq_f32_bf16): New.
+ (vreinterpret_f64_bf16,vreinterpretq_f64_bf16): New.
+ (vreinterpret_f16_bf16,vreinterpretq_f16_bf16): New.
+ (vreinterpretq_p128_bf16): New.
+
+2020-02-25 Dennis Zhang <dennis.zhang@arm.com>
+
+ * config/arm/arm_neon.h (vbfdot_f32, vbfdotq_f32): New
+ (vbfdot_lane_f32, vbfdotq_laneq_f32): New.
+ (vbfdot_laneq_f32, vbfdotq_lane_f32): New.
+ * config/arm/arm_neon_builtins.def (vbfdot): New entry.
+ (vbfdot_lanev4bf, vbfdot_lanev8bf): Likewise.
+ * config/arm/iterators.md (VSF2BF): New attribute.
+ * config/arm/neon.md (neon_vbfdot<VCVTF:mode>): New entry.
+ (neon_vbfdot_lanev4bf<VCVTF:mode>): Likewise.
+ (neon_vbfdot_lanev8bf<VCVTF:mode>): Likewise.
+
+2020-02-25 Christophe Lyon <christophe.lyon@linaro.org>
+
+ * config/arm/arm.md (required_for_purecode): New attribute.
+ (enabled): Handle required_for_purecode.
+ * config/arm/thumb1.md (thumb1_movsi_insn): Add alternative to
+ work with -mpure-code.
+
+2020-02-25 Jakub Jelinek <jakub@redhat.com>
+
+ PR rtl-optimization/93908
+ * combine.c (find_split_point): For store into ZERO_EXTRACT, and src
+ with mask.
+
2019-02-25 Eric Botcazou <ebotcazou@adacore.com>
* dwarf2out.c (dwarf2out_size_function): Run in early-DWARF mode.
projects / gcc.git / blobdiff