+2018-05-24 Richard Sandiford <richard.sandiford@linaro.org>
+
+ * gimple-match.h (gimple_match_op): New class.
+ (mprts_hook): Replace parameters with a gimple_match_op *.
+ (maybe_build_generic_op): Likewise.
+ (gimple_simplified_result_is_gimple_val): Replace parameters with
+ a const gimple_match_op *.
+ (gimple_simplify): Replace code_helper * and tree * parameters with
+ a gimple_match_op * parameter.
+ (gimple_resimplify1): Replace code_helper *, tree and tree *
+ parameters with a gimple_match_op * parameter.
+ (gimple_resimplify2): Likewise.
+ (gimple_resimplify3): Likewise.
+ (maybe_push_res_to_seq): Replace code_helper, tree and tree *
+ parameters with a gimple_match_op * parameter.
+ * gimple-match-head.c (gimple_simplify): Change prototypes of
+ auto-generated functions to take a gimple_match_op * instead of
+ separate code_helper * and tree * parameters. Make the same
+ change in the top-level overload and update calls to the
+ gimple_resimplify routines. Update calls to the auto-generated
+ functions and to maybe_push_res_to_seq in the publicly-facing
+ operation-specific gimple_simplify overloads.
+ (gimple_match_op::MAX_NUM_OPS): Define.
+ (gimple_resimplify1): Replace rcode and ops with a single res_op
+ parameter. Update call to gimple_simplify.
+ (gimple_resimplify2): Likewise.
+ (gimple_resimplify3): Likewise.
+ (mprts_hook): Replace parameters with a gimple_match_op *.
+ (maybe_build_generic_op): Likewise.
+ (build_call_internal): Replace type, nargs and ops with
+ a gimple_match_op *.
+ (maybe_push_res_to_seq): Replace res_code, type and ops parameters
+ with a single gimple_match_op *. Update calls to mprts_hook,
+ build_call_internal and gimple_simplified_result_is_gimple_val.
+ Factor out code that is common to the tree_code and combined_fn cases.
+ * genmatch.c (expr::gen_transform): Replace tem_code and
+ tem_ops with a gimple_match_op called tem_op. Update calls
+ to the gimple_resimplify functions and maybe_push_res_to_seq.
+ (dt_simplify::gen_1): Manipulate res_op instead of res_code and
+ res_ops. Update call to the gimple_resimplify functions.
+ (dt_simplify::gen): Pass res_op instead of res_code and res_ops.
+ (decision_tree::gen): Make the functions take a gimple_match_op *
+ called res_op instead of separate res_code and res_ops parameters.
+ Update call accordingly.
+ * gimple-fold.c (replace_stmt_with_simplification): Replace rcode
+ and ops with a single res_op parameter. Update calls to
+ maybe_build_generic_op and maybe_push_res_to_seq.
+ (fold_stmt_1): Update calls to gimple_simplify and
+ replace_stmt_with_simplification.
+ (gimple_fold_stmt_to_constant_1): Update calls to gimple_simplify
+ and gimple_simplified_result_is_gimple_val.
+ * tree-cfgcleanup.c (cleanup_control_expr_graph): Update call to
+ gimple_simplify.
+ * tree-ssa-sccvn.c (vn_lookup_simplify_result): Replace parameters
+ with a gimple_match_op *.
+ (vn_nary_build_or_lookup): Likewise. Update call to
+ vn_nary_build_or_lookup_1.
+ (vn_nary_build_or_lookup_1): Replace rcode, type and ops with a
+ gimple_match_op *. Update calls to the gimple_resimplify routines
+ and to gimple_simplified_result_is_gimple_val.
+ (vn_nary_simplify): Update call to vn_nary_build_or_lookup_1.
+ Use gimple_match_op::MAX_NUM_OPS instead of a hard-coded 3.
+ (vn_reference_lookup_3): Update call to vn_nary_build_or_lookup.
+ (visit_nary_op): Likewise.
+ (visit_reference_op_load): Likewise.
+
+2018-05-23 Luis Machado <luis.machado@linaro.org>
+
+ * tree-ssa-loop-prefetch.c (should_issue_prefetch_p): Use correct type
+ modifier for printing the step amount.
+
+2018-05-23 Jozef Lawrynowicz <jozef.l@somniumtech.com>
+
+ PR target/78849
+ * gcc/tree.c (build_common_tree_nodes): Dont set TYPE_SIZE for __intN
+ types.
+
+2018-05-23 Segher Boessenkool <segher@kernel.crashing.org>
+
+ * doc/sourcebuild.texi (Endianness): New subsubsection.
+
+2018-05-23 Luis Machado <luis.machado@linaro.org>
+
+ * config/aarch64/aarch64-protos.h (cpu_prefetch_tune)
+ <prefetch_dynamic_strides>: New const bool field.
+ * config/aarch64/aarch64.c (generic_prefetch_tune): Update to include
+ prefetch_dynamic_strides.
+ (exynosm1_prefetch_tune): Likewise.
+ (thunderxt88_prefetch_tune): Likewise.
+ (thunderx_prefetch_tune): Likewise.
+ (thunderx2t99_prefetch_tune): Likewise.
+ (qdf24xx_prefetch_tune): Likewise. Set prefetch_dynamic_strides to
+ false.
+ (aarch64_override_options_internal): Update to set
+ PARAM_PREFETCH_DYNAMIC_STRIDES.
+ * doc/invoke.texi (prefetch-dynamic-strides): Document new option.
+ * params.def (PARAM_PREFETCH_DYNAMIC_STRIDES): New.
+ * params.h (PARAM_PREFETCH_DYNAMIC_STRIDES): Define.
+ * tree-ssa-loop-prefetch.c (should_issue_prefetch_p): Account for
+ prefetch-dynamic-strides setting.
+
+2018-05-23 Luis Machado <luis.machado@linaro.org>
+
+ * config/aarch64/aarch64-protos.h (cpu_prefetch_tune)
+ <minimum_stride>: New const int field.
+ * config/aarch64/aarch64.c (generic_prefetch_tune): Update to include
+ minimum_stride field defaulting to -1.
+ (exynosm1_prefetch_tune): Likewise.
+ (thunderxt88_prefetch_tune): Likewise.
+ (thunderx_prefetch_tune): Likewise.
+ (thunderx2t99_prefetch_tune): Likewise.
+ (qdf24xx_prefetch_tune) <minimum_stride>: Set to 2048.
+ <default_opt_level>: Set to 3.
+ (aarch64_override_options_internal): Update to set
+ PARAM_PREFETCH_MINIMUM_STRIDE.
+ * doc/invoke.texi (prefetch-minimum-stride): Document new option.
+ * params.def (PARAM_PREFETCH_MINIMUM_STRIDE): New.
+ * params.h (PARAM_PREFETCH_MINIMUM_STRIDE): Define.
+ * tree-ssa-loop-prefetch.c (should_issue_prefetch_p): Return false if
+ stride is constant and is below the minimum stride threshold.
+
+2018-05-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * config/arm/arm-cpus.in (mode26): Delete.
+ (armv4): Delete mode26 reference.
+ * config/arm/arm.c (arm_configure_build_target): Delete use of
+ isa_bit_mode26.
+
+2018-05-23 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/i386/i386.md (*floatuns<SWI48:mode><MODEF:mode>2_avx512):
+ New insn pattern.
+ (floatunssi<mode>2): Also enable for AVX512F and TARGET_SSE_MATH.
+ Rewrite expander pattern. Emit gen_floatunssi<mode>2_i387_with_xmm
+ for non-SSE modes.
+ (floatunsdisf2): Rewrite expander pattern. Hanlde TARGET_AVX512F.
+ (floatunsdidf2): Ditto.
+
+2018-05-23 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/i386/i386.md (fixuns_trunc<mode>di2): New insn pattern.
+ (fixuns_trunc<mode>si2_avx512f): Ditto.
+ (*fixuns_trunc<mode>si2_avx512f_zext): Ditto.
+ (fixuns_trunc<mode>si2): Also enable for AVX512F and TARGET_SSE_MATH.
+ Emit fixuns_trunc<mode>si2_avx512f for AVX512F targets.
+
+2018-05-23 Alexander Monakov <amonakov@ispras.ru>
+
+ PR rtl-optimization/79985
+ * df-scan.c (df_insn_refs_collect): Remove special case for
+ global registers and asm statements.
+
+2018-05-23 Alexander Monakov <amonakov@ispras.ru>
+
+ * extend.texi (Global Register Variables): Rewrite the bullet list.
+ Note that the register is available for allocation. Note that access
+ via inline asm must use constraints. Add note about async-signal
+ handlers. Remove paragraph about automagic register selection.
+
+2018-05-23 Richard Biener <rguenther@suse.de>
+
+ * tree-ssa-sccvn.c (vn_reference_lookup_3): Remove restriction
+ of fixed offset from memset VN.
+
+2018-05-23 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ * gimple-ssa-strength-reduction.c (struct slsr_cand_d): Add
+ first_interp field.
+ (alloc_cand_and_find_basis): Initialize first_interp field.
+ (slsr_process_mul): Modify first_interp field.
+ (slsr_process_add): Likewise.
+ (slsr_process_cast): Modify first_interp field for each new
+ interpretation.
+ (slsr_process_copy): Likewise.
+ (dump_candidate): Dump first_interp field.
+ (replace_mult_candidate): Process all interpretations, not just
+ subsequent ones.
+ (replace_rhs_if_not_dup): Likewise.
+ (replace_one_candidate): Likewise.
+
+2018-05-23 Wilco Dijkstra <wdijkstr@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_use_frame_pointer):
+ Add new boolean.
+ (aarch64_needs_frame_chain): New function.
+ (aarch64_parse_override_string): Set aarch64_use_frame_pointer.
+
+2018-05-23 Sudakshina Das <sudi.das@arm.com>
+
+ PR target/84882
+ * common/config/aarch64/aarch64-common.c (aarch64_handle_option):
+ Check val before adding MASK_STRICT_ALIGN to opts->x_target_flags.
+ * config/aarch64/aarch64.opt (mstrict-align): Remove RejectNegative.
+ * config/aarch64/aarch64.c (aarch64_attributes): Mark allow_neg
+ as true for strict-align.
+ (aarch64_can_inline_p): Perform checks even when callee has no
+ attributes to check for strict alignment.
+ * doc/extend.texi (AArch64 Function Attributes): Document
+ no-strict-align.
+ * doc/invoke.texi: (AArch64 Options): Likewise.
+
+2018-05-23 Richard Sandiford <richard.sandiford@linaro.org>
+
+ PR tree-optimization/85853
+ * tree-vect-slp.c (vect_slp_analyze_node_operations): Split out
+ the handling of the root of the node to...
+ (vect_slp_analyze_node_operations_1): ...this new function,
+ and run the whole thing with the child nodes' def types
+ set according to their SLP node's def type.
+
+2018-05-23 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/85874
+ * tree-data-ref.c (create_runtime_alias_checks): Defer
+ and ignore overflow warnings.
+
+2018-05-23 Yury Gribov <tetra2005@gmail.com>
+
+ PR tree-optimization/85822
+ * tree-vrp.c (is_masked_range_test): Fix handling of negative
+ constants.
+
+2018-05-23 Richard Biener <rguenther@suse.de>
+
+ * tree-ssa-sccvn.c (vn_reference_lookup_3): Handle arbitrary
+ memset constants via native_interpret_expr.
+
+2018-05-22 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR target/85345
+ * cgraph.h (cgraph_node::create): Set ifunc_resolver for ifunc
+ attribute.
+ (cgraph_node::create_alias): Likewise.
+ (cgraph_node::get_availability): Check ifunc_resolver instead
+ of looking up ifunc attribute.
+ * cgraphunit.c (maybe_diag_incompatible_alias): Likewise.
+ * varasm.c (do_assemble_alias): Likewise.
+ (assemble_alias): Likewise.
+ (default_binds_local_p_3): Likewise.
+ * cgraph.h (cgraph_node): Add ifunc_resolver.
+ (cgraph_node::only_called_directly_or_aliased_p): Return false
+ for IFUNC resolver.
+ * lto-cgraph.c (input_node): Set ifunc_resolver for ifunc
+ attribute.
+ * symtab.c (symtab_node::verify_base): Verify that ifunc_resolver
+ is equivalent to lookup_attribute ("ifunc", DECL_ATTRIBUTES (decl)).
+ (symtab_node::binds_to_current_def_p): Check ifunc_resolver
+ instead of looking up ifunc attribute.
+
+2018-05-22 Luis Machado <luis.machado@linaro.org>
+
+ * config/aarch64/aarch64.md (*ashift<mode>_extv_bfiz): New pattern.
+
+2018-05-22 Martin Sebor <msebor@redhat.com>
+
+ PR middle-end/85359
+ * builtins.c (expand_builtin_strcpy): Call maybe_warn_nonstring_arg
+ only when expasion succeeds.
+ (expand_builtin_strcmp): Same.
+ (expand_builtin_strncmp): Same.
+
+2018-05-22 Martin Sebor <msebor@redhat.com>
+
+ * calls.c (maybe_warn_nonstring_arg): Fix a typo in a comment.
+
+2018-05-22 Jackson Woodruff <jackson.woodruff@arm.com>
+ Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * config/aarch64/aarch64-ldpstp.md: Replace uses of
+ aarch64_mem_pair_operand with memory_operand and delete operand swapping
+ code.
+ * config/aarch64/aarch64.c (aarch64_operands_ok_for_ldpstp):
+ Add check for legitimate_address.
+ (aarch64_gen_adjusted_ldpstp): Swap operands where appropriate.
+ (aarch64_swap_ldrstr_operands): New.
+ * config/aarch64/aarch64-protos.h (aarch64_swap_ldrstr_operands):
+ Define prototype.
+
+2018-05-22 Jackson Woodruff <jackson.woodruff@arm.com>
+ Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * config/aarch64/aarch64.md: New patterns to generate stp
+ and ldp.
+ (store_pair_sw, store_pair_dw): New patterns to generate stp for
+ single words and double words.
+ (load_pair_sw, load_pair_dw): Likewise.
+ (store_pair_sf, store_pair_df, store_pair_si, store_pair_di):
+ Delete.
+ (load_pair_sf, load_pair_df, load_pair_si, load_pair_di):
+ Delete.
+ * config/aarch64/aarch64-ldpstp.md: Modify peephole
+ for different mode ldpstp and add peephole for merged zero stores.
+ Likewise for loads.
+ * config/aarch64/aarch64.c (aarch64_operands_ok_for_ldpstp):
+ Add size check.
+ (aarch64_gen_store_pair): Rename calls to match new patterns.
+ (aarch64_gen_load_pair): Rename calls to match new patterns.
+ * config/aarch64/aarch64-simd.md (load_pair<mode>): Rename to...
+ (load_pair<DREG:mode><DREG2:mode>): ... This.
+ (store_pair<mode>): Rename to...
+ (vec_store_pair<DREG:mode><DREG2:mode>): ... This.
+ * config/aarch64/iterators.md (DREG, DREG2, DX2, SX, SX2, DSX):
+ New mode iterators.
+ (V_INT_EQUIV): Handle SImode.
+ * config/aarch64/predicates.md (aarch64_reg_zero_or_fp_zero):
+ New predicate.
+
+2018-05-22 Martin Sebor <msebor@redhat.com>
+
+ PR c/85623
+ * calls.c (maybe_warn_nonstring_arg): Use string length to set
+ or ajust the presumed bound on an operation to avoid unnecessary
+ warnings.
+
+2018-05-22 Martin Sebor <msebor@redhat.com>
+
+ PR tree-optimization/85826
+ * gimple-ssa-warn-restrict.c (builtin_memref::builtin_memref): Avoid
+ assuming that a DECL necesarily has a constant size.
+
+2018-05-22 Richard Sandiford <richard.sandiford@linaro.org>
+
+ PR middle-end/85862
+ * internal-fn.c (expand_direct_optab_fn): Cope with a null lhs.
+
+2018-05-22 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/85834
+ * tree-ssa-sccvn.c (vn_reference_lookup_3): Properly handle
+ non-constant and non-zero memset arguments.
+
+2018-05-22 Martin Liska <mliska@suse.cz>
+
+ PR ipa/85607
+ * ipa-icf.c (sem_item::add_type): Do not ICE for incomplete types.
+
+2018-05-22 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/85863
+ * tree-vect-stmts.c (vect_is_simple_cond): Only widen invariant
+ comparisons when vectype is specified.
+ (vectorizable_condition): Do not specify vectype for
+ vect_is_simple_cond when SLP vectorizing.
+
+2018-05-21 Michael Meissner <meissner@linux.ibm.com>
+
+ PR target/85657
+ * config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): Do not
+ define __ibm128 as long double.
+ * config/rs6000/rs6000.c (rs6000_init_builtins): Create __ibm128
+ as a distinct type when IEEE 128-bit support is enabled.
+ (init_float128_ieee): Fix up conversions between IFmode and IEEE
+ 128-bit types to use the correct functions.
+ (rs6000_expand_float128_convert): Use explicit FLOAT_EXTEND to
+ convert between 128-bit floating point types that have different
+ modes but the same representation, instead of using gen_lowpart to
+ makean alias.
+ * config/rs6000/rs6000.md (IFKF): New iterator for IFmode and
+ KFmode.
+ (IFKF_reg): New attributes to give the register constraints for
+ IFmode and KFmode.
+ (extend<mode>tf2_internal): New insns to mark an explicit
+ conversion between 128-bit floating point types that have a
+ different mode but share the same representation.
+
+2018-05-21 Richard Sandiford <richard.sandiford@linaro.org>
+
+ PR tree-optimization/85814
+ * tree-ssa-strlen.c (get_stridx_plus_constant): Cope with
+ a null return from get_strinfo when unsharing the next
+ strinfo in the chain.
+
+2018-05-21 Vladimir Mezentsev <vladimir.mezentsev@oracle.com>
+
+ PR gcc/84923
+ * varasm.c (weak_finish): Clean up weak_decls.
+
+2018-05-21 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * config/aarch64/aarch64.md ("unspec"): Define UNSPEC_SABAL,
+ UNSPEC_SABDL2, UNSPEC_SADALP, UNSPEC_UABAL, UNSPEC_UABDL2,
+ UNSPEC_UADALP values.
+ * config/aarch64/iterators.md (ABAL): New int iterator.
+ (ABDL2): Likewise.
+ (ADALP): Likewise.
+ (sur): Add mappings for the above.
+ * config/aarch64/aarch64-simd.md (aarch64_<sur>abdl2<mode>_3):
+ New define_insn.
+ (aarch64_<sur>abal<mode>_4): Likewise.
+ (aarch64_<sur>adalp<mode>_3): Likewise.
+ (<sur>sadv16qi): New define_expand.
+
+2018-05-21 Alexander Nesterovskiy <alexander.nesterovskiy@intel.com>
+
+ * config/i386/i386.md (*movsf_internal): AVX falsedep fix.
+ (*movdf_internal): Ditto.
+ (*rcpsf2_sse): Ditto.
+ (*rsqrtsf2_sse): Ditto.
+ (*sqrt<mode>2_sse): Ditto.
+
+2018-05-21 Tamar Christina <tamar.christina@arm.com>
+
+ * config/aarch64/aarch64-simd.md (aarch64_eor3qv8hi): Change to
+ eor3q<mode>4.
+ (aarch64_bcaxqv8hi): Change to bcaxq<mode>4.
+ * config/aarch64/aarch64-simd-builtins.def (veor3q_u8, veor3q_u32,
+ veor3q_u64, veor3q_s8, veor3q_s16, veor3q_s32, veor3q_s64, vbcaxq_u8,
+ vbcaxq_u32, vbcaxq_u64, vbcaxq_s8, vbcaxq_s16, vbcaxq_s32,
+ vbcaxq_s64): New.
+ * config/aarch64/arm_neon.h: Likewise.
+ * config/aarch64/iterators.md (VQ_I): New.
+
+2018-05-21 Alexey Brodkin <abrodkin@synopsys.com>
+
+ * config.gcc: Add arc/t-multilib-linux to tmake_file for
+ arc*-*-linux*.
+ * config/arc/t-multilib-linux: Specify MULTILIB_OPTIONS and
+ MULTILIB_DIRNAMES
+
+2018-05-20 Chung-Ju Wu <jasonwucj@gmail.com>
+
+ * config/nds32/constraints.md (S): New constraint.
+ * config/nds32/nds32.md (call_internal): Use constraint S.
+ (call_value_internal): Likewise.
+ (sibcall_internal): Likewise.
+ (sibcall_value_internal): Likewise.
+
+2018-05-20 Kito Cheng <kito.cheng@gmail.com>
+ Chung-Ju Wu <jasonwucj@gmail.com>
+
+ * config/nds32/nds32.c (nds32_register_move_cost): Take garywolf cpu
+ into consideration.
+
+2018-05-20 Kito Cheng <kito.cheng@gmail.com>
+ Chung-Ju Wu <jasonwucj@gmail.com>
+
+ * config/nds32/nds32-cost.c (rtx_cost_model_t): New structure.
+ (insn_size_16bit, insn_size_32bit): New variables for cost evaluation.
+ (nds32_rtx_costs_impl): Simplify.
+ (nds32_address_cost_impl): Simplify.
+ (nds32_init_rtx_costs): New function.
+ (nds32_rtx_costs_speed_prefer): Likewise.
+ (nds32_rtx_costs_size_prefer): Likewise.
+ (nds32_address_cost_speed_prefer): Likewise.
+ (nds32_address_cost_speed_fwprop): Likewise.
+ (nds32_address_cost_size_prefer): Likewise.
+ * config/nds32/nds32-protos.h (nds32_init_rtx_costs): Declare.
+ * config/nds32/nds32.c (nds32_option_override): Use
+ nds32_init_rtx_costs function.
+
+2018-05-20 Chung-Ju Wu <jasonwucj@gmail.com>
+
+ * config/nds32/nds32.c (nds32_asm_file_start): Output pipeline model.
+ * config/nds32/nds32.h (TARGET_PIPELINE_N7): Define.
+ (TARGET_PIPELINE_N8): Likewise.
+ (TARGET_PIPELINE_N10): Likewise.
+ (TARGET_PIPELINE_N13): Likewise.
+ (TARGET_PIPELINE_GRAYWOLF): Likewise.
+
+2018-05-19 Monk Chiang <sh.chiang04@gmail.com>
+
+ * config/nds32/nds32-fpu.md: Update copyright year.
+
+2018-05-19 Chung-Ju Wu <jasonwucj@gmail.com>
+
+ * config/nds32/nds32.h (ASM_SPEC): Adjust spec rule.
+
+2018-05-19 Chung-Ju Wu <jasonwucj@gmail.com>
+
+ * config/nds32/nds32.c
+ (nds32_md_asm_adjust): Consider flag_inline_asm_r15 variable.
+ * config/nds32/nds32.opt (minline-asm-r15): New option.
+
+2018-05-19 Chung-Ju Wu <jasonwucj@gmail.com>
+
+ * common/config/nds32/nds32-common.c (TARGET_DEFAULT_TARGET_FLAGS): Add
+ MASK_HW_ABS.
+ * config/nds32/nds32.md (abssi2): New pattern.
+
+2018-05-19 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/i386/i386.md (rex64namesuffix): New mode attribute.
+ * config/i386/sse.md (sse_cvtsi2ss<rex64namesuffix><round_name>):
+ Merge insn pattern from sse_cvtsi2ss<round_name> and
+ sse_cvtsi2ssq<round_name> using SWI48 mode iterator.
+ (sse_cvtss2si<rex64namesuffix><round_name>): Merge insn pattern
+ from sse_cvtss2si<round_name> and sse_cvtss2siq<round_name>
+ using SWI48 mode iterator.
+ (sse_cvtss2si<rex64namesuffix>_2): Merge insn pattern from
+ sse_cvtss2si_2 and sse_cvtss2siq_2 using SWI48 mode iterator.
+ (sse_cvttss2si<rex64namesuffix><round_saeonly_name>): Merge insn
+ pattern from sse_cvttss2si<round_saeonly_name>
+ and sse_cvttss2siq<round_saeonly_name> using SWI48 mode iterator.
+ (avx512f_vcvtss2usi<rex64namesuffix><round_name>): Merge insn pattern
+ from avx512f_vcvtss2usi<round_name> and avx512f_vcvtss2usiq<round_name>
+ using SWI48 mode iterator.
+ (avx512f_vcvttss2usi<rex64namesuffix><round_saeonly_name>): Merge
+ insn pattern from avx512f_vcvttss2usi<round_saeonly_name> and
+ avx512f_vcvttss2usiq<round_saeonly_name> using SWI48 mode iterator.
+ (avx512f_vcvtsd2usi<rex64namesuffix><round_name>): Merge insn pattern
+ from avx512f_vcvtsd2usi<round_name> and avx512f_vcvtsd2usiq<round_name>
+ using SWI48 mode iterator.
+ (avx512f_vcvttsd2usi<rex64namesuffix><round_saeonly_name>): Merge
+ insn pattern from avx512f_vcvttsd2usi<round_saeonly_name> and
+ avx512f_vcvttsd2usiq<round_saeonly_name> using SWI48 mode iterator.
+ (sse2_cvtsd2si<rex64namesuffix><round_name>): Merge insn pattern from
+ sse2_cvtsd2si<round_name> and sse2_cvtsd2siq<round_name> using
+ SWI48 mode iterator.
+ (sse2_cvtsd2si<rex64namesuffix>_2): Merge insn pattern from
+ sse2_cvtsd2si_2 and sse2_cvtsd2siq_2 using SWI48 mode iterator.
+ (sse_cvttsd2si<rex64namesuffix><round_saeonly_name>): Merge insn
+ pattern from sse_cvttsd2si<round_saeonly_name>
+ and sse_cvttsd2siq<round_saeonly_name> using SWI48 mode iterator.
+
+2018-05-19 Chung-Ju Wu <jasonwucj@gmail.com>
+
+ * config/nds32/nds32-md-auxiliary.c
+ (nds32_valid_smw_lwm_base_p): Refine.
+ (nds32_output_smw_single_word): Refine.
+ (nds32_output_smw_double_word): New.
+ * config/nds32/nds32-protos.h (nds32_output_smw_double_word): New.
+
+2018-05-19 Chung-Ju Wu <jasonwucj@gmail.com>
+
+ * config/nds32/nds32-md-auxiliary.c (nds32_output_stack_push): Refine.
+ (nds32_output_stack_pop): Refine.
+ (nds32_expand_unaligned_load): Refine.
+ (nds32_expand_unaligned_store): Refine.
+
+2018-05-19 Kuan-Lin Chen <kuanlinchentw@gmail.com>
+ Chung-Ju Wu <jasonwucj@gmail.com>
+
+ * config/nds32/constants.md: Add TP_REGNUM constant.
+ (unspec_element): Add UNSPEC_GOTINIT, UNSPEC_GOT, UNSPEC_GOTOFF,
+ UNSPEC_PLT, UNSPEC_TLSGD, UNSPEC_TLSLD, UNSPEC_TLSIE, UNSPEC_TLSLE and
+ UNSPEC_ADD32.
+ * config/nds32/nds32-doubleword.md: Consider flag_pic.
+ * config/nds32/nds32-dspext.md (mov<mode>): Expand TLS and PIC cases.
+ * config/nds32/nds32-predicates.c (nds32_const_unspec_p): New.
+ * config/nds32/nds32-md-auxiliary.c: Implementation that support TLS
+ and PIC code generation.
+ * config/nds32/nds32-protos.h: Declarations that support TLS and PIC
+ code generation.
+ * config/nds32/nds32-relax-opt.c: Consider TLS and PIC for relax
+ optimization.
+ * config/nds32/nds32.md: Support TLS and PIC.
+ * config/nds32/nds32.c: Support TLS and PIC.
+ * config/nds32/nds32.h (nds32_relax_insn_type): New enum type.
+ * config/nds32/predicates.md (nds32_nonunspec_symbolic_operand): New
+ predicate.
+
+2018-05-19 Chung-Ju Wu <jasonwucj@gmail.com>
+
+ * config/nds32/nds32-predicates.c (const_vector_to_hwint): Use machine
+ mode with E_ prefix.
+
+2018-05-19 Kuan-Lin Chen <kuanlinchentw@gmail.com>
+ Chung-Ju Wu <jasonwucj@gmail.com>
+
+ * config/nds32/constants.md (unspec_element): Add UNSPEC_ICT.
+ * config/nds32/nds32-md-auxiliary.c
+ (symbolic_reference_mentioned_p): New.
+ (nds32_legitimize_ict_address): New.
+ (nds32_expand_ict_move): New.
+ (nds32_indirect_call_referenced_p): New.
+ (nds32_symbol_binds_local_p): Delete.
+ (nds32_long_call_p): Modify.
+ * config/nds32/nds32-opts.h (nds32_ict_model_type): New enum type.
+ * config/nds32/nds32-protos.h
+ (symbolic_reference_mentioned_p): Declare.
+ (nds32_legitimize_ict_address): Declare.
+ (nds32_expand_ict_move): Declare.
+ (nds32_indirect_call_referenced_p): Declare.
+ * config/nds32/nds32-relax-opt.c (nds32_ict_const_p): New.
+ (nds32_relax_group): Use nds32_ict_const_p as condition.
+ * config/nds32/nds32.c (nds32_attribute_table): Add "indirect_call".
+ (nds32_asm_file_start): Output ict_model directive in asm code.
+ (nds32_legitimate_address_p): Consider indirect call.
+ (nds32_print_operand): Consider indirect call.
+ (nds32_print_operand_address): Consider indirect call.
+ (nds32_insert_attributes): Handle "indirect_call" attribute.
+ (TARGET_LEGITIMATE_ADDRESS_P): Define.
+ (TARGET_LEGITIMATE_CONSTANT_P): Define.
+ (TARGET_CANNOT_FORCE_CONST_MEM): Define.
+ (TARGET_DELEGITIMIZE_ADDRESS): Define.
+ (TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA): Define.
+ * config/nds32/nds32.h (SYMBOLIC_CONST_P): Define.
+ (TARGET_ICT_MODEL_SMALL): Define.
+ (TARGET_ICT_MODEL_LARGE): Define.
+ * config/nds32/nds32.md (movsi): Consider ict model.
+ (call, call_value): Consider ict model.
+ (sibcall, sibcall_value): Consider ict model.
+ * config/nds32/nds32.opt (mict-model): New option.
+ * config/nds32/predicates.md (nds32_symbolic_operand): Consider ict
+ model.
+
+2018-05-18 Kito Cheng <kito.cheng@gmail.com>
+ Monk Chiang <sh.chiang04@gmail.com>
+ Jim Wilson <jimw@sifive.com>
+
+ * common/config/riscv/riscv-common.c (riscv_parse_arch_string):
+ Add support to parse rv32e*. Clear MASK_RVE for rv32i and rv64i.
+ * config.gcc (riscv*-*-*): Add support for rv32e* and ilp32e.
+ * config/riscv/riscv-c.c (riscv_cpu_cpp_builtins): Define
+ __riscv_32e when TARGET_RVE. Handle ABI_ILP32E as soft-float ABI.
+ * config/riscv/riscv-opts.h (riscv_abi_type): Add ABI_ILP32E.
+ * config/riscv/riscv.c (riscv_compute_frame_info): When TARGET_RVE,
+ compute save_libcall_adjustment properly.
+ (riscv_option_override): Call error if TARGET_RVE and not ABI_ILP32E.
+ (riscv_conditional_register_usage): Handle TARGET_RVE and ABI_ILP32E.
+ * config/riscv/riscv.h (UNITS_PER_FP_ARG): Handle ABI_ILP32E.
+ (STACK_BOUNDARY, ABI_STACK_BOUNDARY): Handle TARGET_RVE.
+ (GP_REG_LAST, MAX_ARGS_IN_REGISTERS): Likewise.
+ (ABI_SPEC): Handle mabi=ilp32e.
+ * config/riscv/riscv.opt (abi_type): Add ABI_ILP32E.
+ (RVE): Add RVE mask.
+ * doc/invoke.texi (RISC-V options) <-mabi>: Add ilp32e info.
+ <-march>: Add rv32e as an example.
+
+2018-05-18 Marc Glisse <marc.glisse@inria.fr>
+
+ PR c++/82899
+ * tree-ssa-structalias.c (create_variable_info_for_1): Extra argument.
+ (intra_create_variable_infos): Handle C++ constructors.
+
+2018-05-18 Martin Liska <mliska@suse.cz>
+
+ * passes.def: Remove a redundant pass.
+
+2018-05-18 Eric Botcazou <ebotcazou@adacore.com>
+
+ PR bootstrap/85838
+ * config/sparc/sparc.c (sparc_expand_builtin): Always initialize op[0].
+
+2018-05-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * config/arm/arm-cpus.in (armv3m, mode32): Delete features.
+ (ARMv4): Update.
+ (ARMv2, ARMv3, ARMv3m): Delete fgroups.
+ (ARMv6m): Update.
+ (armv2, armv2a, armv3, armv3m): Delete architectures.
+ (arm2, arm250, arm3, arm6, arm60, arm600, arm610, arm620,
+ arm7, arm7d, arm7di, arm70, arm700, arm700i, arm710, arm720,
+ arm710c, arm7100, arm7500, arm7500fe, arm7m, arm7dm, arm7dmi):
+ Delete cpus.
+ * config/arm/arm.md (maddsidi4): Remove check for arm_arch3m.
+ (*mulsidi3adddi): Likewise.
+ (mulsidi3): Likewise.
+ (*mulsidi3_nov6): Likewise.
+ (umulsidi3): Likewise.
+ (umulsidi3_nov6): Likewise.
+ (umaddsidi4): Likewise.
+ (*umulsidi3adddi): Likewise.
+ (smulsi3_highpart): Likewise.
+ (*smulsi3_highpart_nov6): Likewise.
+ (umulsi3_highpart): Likewise.
+ (*umulsi3_highpart_nov6): Likewise.
+ * config/arm/arm.h (arm_arch3m): Delete.
+ * config/arm/arm.c (arm_arch3m): Delete.
+ (arm_option_override_internal): Update armv3-related comment.
+ (arm_configure_build_target): Delete use of isa_bit_mode32.
+ (arm_option_reconfigure_globals): Delete set of arm_ach3m.
+ (arm_rtx_costs_internal): Delete check of arm_arch3m.
+ * config/arm/arm-fixed.md (mulsq3): Delete check for arm_arch3m.
+ (mulsa3): Likewise.
+ (mulusa3): Likewise.
+ * config/arm/arm-protos.h (arm_arch3m): Delete.
+ * config/arm/arm-tables.opt: Regenerate.
+ * config/arm/arm-tune.md: Likewise.
+ * config/arm/t-arm-elf (all_early_nofp): Delete mentions of
+ deleted architectures.
+
+2018-05-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * config/arm/arm-cpus.in (armv5, armv5e): Delete features.
+ (armv5t, armv5te): New features.
+ (ARMv5, ARMv5e): Delete fgroups.
+ (ARMv5t, ARMv5te): Adjust for above changes.
+ (ARMv6m): Likewise.
+ (armv5, armv5e): Delete arches.
+ * config/arm/arm.md (*call_reg_armv5): Use arm_arch5t instead of
+ arm_arch5.
+ (*call_reg_arm): Likewise.
+ (*call_value_reg_armv5): Likewise.
+ (*call_value_reg_arm): Likewise.
+ (*call_symbol): Likewise.
+ (*call_value_symbol): Likewise.
+ (*sibcall_insn): Likewise.
+ (*sibcall_value_insn): Likewise.
+ (clzsi2): Likewise.
+ (prefetch): Likewise.
+ (define_split and define_peephole2 dependent on arm_arch5):
+ Likewise.
+ * config/arm/arm.h (TARGET_LDRD): Use arm_arch5te instead of
+ arm_arch5e.
+ (TARGET_ARM_QBIT): Likewise.
+ (TARGET_DSP_MULTIPLY): Likewise.
+ (enum base_architecture): Delete BASE_ARCH_5, BASE_ARCH_5E.
+ (arm_arch5, arm_arch5e): Delete.
+ (arm_arch5t, arm_arch5te): Declare.
+ * config/arm/arm.c (arm_arch5, arm_arch5e): Delete.
+ (arm_arch5t): Declare.
+ (arm_option_reconfigure_globals): Update for the above.
+ (arm_options_perform_arch_sanity_checks): Update comment, replace
+ use of arm_arch5 with arm_arch5t.
+ (use_return_insn): Likewise.
+ (arm_emit_call_insn): Likewise.
+ (output_return_instruction): Likewise.
+ (arm_final_prescan_insn): Likewise.
+ (arm_coproc_builtin_available): Likewise.
+ * config/arm/arm-c.c (arm_cpu_builtins): Replace arm_arch5 and
+ arm_arch5e with arm_arch5t and arm_arch5te.
+ * config/arm/arm-protos.h (arm_arch5, arm_arch5e): Delete.
+ (arm_arch5t, arm_arch5te): Declare.
+ * config/arm/arm-tables.opt: Regenerate.
+ * config/arm/t-arm-elf: Remove references to armv5, armv5e.
+ * config/arm/t-multilib: Likewise.
+ * config/arm/thumb1.md (*call_reg_thumb1_v5): Check arm_arch5t
+ instead of arm_arch5.
+ (*call_reg_thumb1): Likewise.
+ (*call_value_reg_thumb1_v5): Likewise.
+ (*call_value_reg_thumb1): Likewise.
+ * config/arm/vxworks.h (TARGET_OS_CPP_BUILTINS): Remove now
+ unreachable path.
+ * doc/invoke.texi (ARM Options): Remove references to armv5, armv5e.
+
+2018-05-18 Martin Liska <mliska@suse.cz>
+
+ PR gcov-profile/84846
+ * doc/gcov.texi: Document -t option of gcov tool.
+
+2018-05-18 Martin Liska <mliska@suse.cz>
+
+ PR gcov-profile/84846
+ * gcov.c (print_usage): Add new -t option.
+ (process_args): Handle the option.
+ (generate_results): Use stdout as output when requested by
+ the option.
+
+2018-05-18 Martin Liska <mliska@suse.cz>
+
+ PR gcov-profile/84846
+ * coverage.c (coverage_init): Write PWD to .gcno file.
+ * doc/gcov.texi: Document how working directory is printed.
+ * gcov-dump.c (dump_gcov_file): Print PWD.
+ * gcov.c (output_intermediate_file): Likewise.
+ (read_graph_file): Read PWD string.
+ (output_lines): Print PWD.
+
+2018-05-18 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
+
+ PR middle-end/85817
+ * ipa-pure-const.c (malloc_candidate_p): Remove the check integer_zerop
+ for retval and return false if all args to phi are zero.
+
+2018-05-18 Richard Biener <rguenther@suse.de>
+
+ * gimple-ssa-evrp.c (class evrp_folder): Add simplify_stmt_using_ranges
+ method.
+ (evrp_dom_walker::before_dom_children): Call it.
+
+2018-05-18 Richard Biener <rguenther@suse.de>
+
+ * tree-dfa.c (get_ref_base_and_extent): Use range-info to refine
+ results when processing array refs with variable index.
+
+2018-05-18 Toon Moene <toon@moene.org>
+
+ * doc/invoke.texi: Move -floop-unroll-and-jam documentation
+ directly after that of -floop-interchange. Indicate that both
+ options are enabled by default when specifying -O3.
+
+2018-05-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * config/aarch64/aarch64-simd.md (vec_set<mode>): Use VALL_F16 mode
+ iterator. Delete separate integer-mode vec_set<mode> expander.
+ (aarch64_simd_vec_setv2di): Delete.
+ (vec_setv2di): Delete.
+ (aarch64_simd_vec_set<mode>): Delete all other patterns with that name.
+ Use VALL_F16 mode iterator. Add LD1 alternative and use vwcore for
+ the "w, r" alternative.
+
+2018-05-18 Martin Liska <mliska@suse.cz>
+
+ * passes.def: Add pass_lower_switch and pass_lower_switch_O0.
+ * tree-pass.h (make_pass_lower_switch_O0): New function.
+ * tree-switch-conversion.c (node_has_low_bound): Remove.
+ (node_has_high_bound): Likewise.
+ (node_is_bounded): Likewise.
+ (class pass_lower_switch): Make it a template type and create
+ two instances.
+ (pass_lower_switch::execute): Add template argument.
+ (make_pass_lower_switch): New function.
+ (make_pass_lower_switch_O0): New function.
+ (do_jump_if_equal): Remove.
+ (emit_case_nodes): Simplify to just handle all 3 cases and leave
+ all the hard work to tree optimization passes.
+
+2018-05-18 Martin Liska <mliska@suse.cz>
+
+ * dbgcnt.c (limit_low): Renamed from limit.
+ (limit_high): New variable.
+ (dbg_cnt_is_enabled): Check for upper limit.
+ (dbg_cnt): Adjust dumping.
+ (dbg_cnt_set_limit_by_index): Add new argument for high
+ value.
+ (dbg_cnt_set_limit_by_name): Likewise.
+ (dbg_cnt_process_single_pair): Parse new format.
+ (dbg_cnt_process_opt): Use strtok.
+ (dbg_cnt_list_all_counters): Remove 'value' and add
+ 'limit_high'.
+ * doc/invoke.texi: Document changes.
+
+2018-05-18 Richard Sandiford <richard.sandiford@linaro.org>
+
+ * doc/sourcebuild.texi (scalar_all_fma): Document.
+ * tree.def (FMA_EXPR): Delete.
+ * internal-fn.def (FMA, FMS, FNMA, FNMS): New internal functions.
+ * internal-fn.c (ternary_direct): New macro.
+ (expand_ternary_optab_fn): Likewise.
+ (direct_ternary_optab_supported_p): Likewise.
+ * Makefile.in (build/genmatch.o): Depend on case-fn-macros.h.
+ * builtins.c (fold_builtin_fma): Delete.
+ (fold_builtin_3): Don't call it.
+ * cfgexpand.c (expand_debug_expr): Remove FMA_EXPR handling.
+ * expr.c (expand_expr_real_2): Likewise.
+ * fold-const.c (operand_equal_p): Likewise.
+ (fold_ternary_loc): Likewise.
+ * gimple-pretty-print.c (dump_ternary_rhs): Likewise.
+ * gimple.c (DEFTREECODE): Likewise.
+ * gimplify.c (gimplify_expr): Likewise.
+ * optabs-tree.c (optab_for_tree_code): Likewise.
+ * tree-cfg.c (verify_gimple_assign_ternary): Likewise.
+ * tree-eh.c (operation_could_trap_p): Likewise.
+ (stmt_could_throw_1_p): Likewise.
+ * tree-inline.c (estimate_operator_cost): Likewise.
+ * tree-pretty-print.c (dump_generic_node): Likewise.
+ (op_code_prio): Likewise.
+ * tree-ssa-loop-im.c (stmt_cost): Likewise.
+ * tree-ssa-operands.c (get_expr_operands): Likewise.
+ * tree.c (commutative_ternary_tree_code, add_expr): Likewise.
+ * fold-const-call.h (fold_fma): Delete.
+ * fold-const-call.c (fold_const_call_ssss): Handle CFN_FMS,
+ CFN_FNMA and CFN_FNMS.
+ (fold_fma): Delete.
+ * genmatch.c (combined_fn): New enum.
+ (commutative_ternary_tree_code): Remove FMA_EXPR handling.
+ (commutative_op): New function.
+ (commutate): Use it. Handle more than 2 operands.
+ (dt_operand::gen_gimple_expr): Use commutative_op.
+ (parser::parse_expr): Allow :c to be used with non-binary
+ operators if the commutative operand is known.
+ * gimple-ssa-backprop.c (backprop::process_builtin_call_use): Handle
+ CFN_FMS, CFN_FNMA and CFN_FNMS.
+ (backprop::process_assign_use): Remove FMA_EXPR handling.
+ * hsa-gen.c (gen_hsa_insns_for_operation_assignment): Likewise.
+ (gen_hsa_fma): New function.
+ (gen_hsa_insn_for_internal_fn_call): Use it for IFN_FMA, IFN_FMS,
+ IFN_FNMA and IFN_FNMS.
+ * match.pd: Add folds for IFN_FMS, IFN_FNMA and IFN_FNMS.
+ * gimple-fold.h (follow_all_ssa_edges): Declare.
+ * gimple-fold.c (follow_all_ssa_edges): New function.
+ * tree-ssa-math-opts.c (convert_mult_to_fma_1): Use the
+ gimple_build interface and use follow_all_ssa_edges to fold the result.
+ (convert_mult_to_fma): Use direct_internal_fn_suppoerted_p
+ instead of checking for optabs directly.
+ * config/i386/i386.c (ix86_add_stmt_cost): Recognize FMAs as calls
+ rather than FMA_EXPRs.
+ * config/rs6000/rs6000.c (rs6000_gimple_fold_builtin): Create a
+ call to IFN_FMA instead of an FMA_EXPR.
+
+2018-05-17 Jim Wilson <jimw@sifive.com>
+
+ * expr.c (do_tablejump): When converting index to Pmode, if we have a
+ sign extended promoted subreg, and the range does not have the sign bit
+ set, then do a sign extend.
+
+ * config/riscv/riscv.c (riscv_extend_comparands): In unsigned QImode
+ test, check for sign extended subreg and/or constant operands, and
+ do a sign extend in that case.
+
+2018-05-17 Steve Ellcey <sellcey@cavium.com>
+
+ * config/aarch64/thunderx2t99.md (thunderx2t99_ls_both): Delete.
+ (thunderx2t99_multiple): Delete psuedo-units from used cpus.
+ Add untyped.
+ (thunderx2t99_alu_shift): Remove alu_shift_reg, alus_shift_reg.
+ Change logics_shift_reg to logics_shift_imm.
+ (thunderx2t99_fp_loadpair_basic): Delete.
+ (thunderx2t99_fp_storepair_basic): Delete.
+ (thunderx2t99_asimd_int): Add neon_sub and neon_sub_q types.
+ (thunderx2t99_asimd_polynomial): Delete.
+ (thunderx2t99_asimd_fp_simple): Add neon_fp_mul_s_scalar_q
+ and neon_fp_mul_d_scalar_q.
+ (thunderx2t99_asimd_fp_conv): Add *int_to_fp* types.
+ (thunderx2t99_asimd_misc): Delete neon_dup and neon_dup_q.
+ (thunderx2t99_asimd_recip_step): Add missing *sqrt* types.
+ (thunderx2t99_asimd_lut): Add missing tbl types.
+ (thunderx2t99_asimd_ext): Delete.
+ (thunderx2t99_asimd_load1_1_mult): Delete.
+ (thunderx2t99_asimd_load1_2_mult): Delete.
+ (thunderx2t99_asimd_load1_ldp): New.
+ (thunderx2t99_asimd_load1): New.
+ (thunderx2t99_asimd_load2): Add missing *load2* types.
+ (thunderx2t99_asimd_load3): New.
+ (thunderx2t99_asimd_load4): New.
+ (thunderx2t99_asimd_store1_1_mult): Delete.
+ (thunderx2t99_asimd_store1_2_mult): Delete.
+ (thunderx2t99_asimd_store2_mult): Delete.
+ (thunderx2t99_asimd_store2_onelane): Delete.
+ (thunderx2t99_asimd_store_stp): New.
+ (thunderx2t99_asimd_store1): New.
+ (thunderx2t99_asimd_store2): New.
+ (thunderx2t99_asimd_store3): New.
+ (thunderx2t99_asimd_store4): New.
+
+2018-05-17 Jerome Lambourg <lambourg@adacore.com>
+
+ * config/arm/arm_cmse.h (cmse_nsfptr_create, cmse_is_nsfptr): Remove
+ #include <stdint.h>. Replace intptr_t with __INTPTR_TYPE__.
+
+2018-05-17 Pat Haugen <pthaugen@us.ibm.com>
+ Segher Boessenkool <segher@kernel.crashing.org>
+
+ PR target/85698
+ * config/rs6000/rs6000.c (rs6000_output_move_128bit): Check dest
+ operand.
+
+2018-05-17 Richard Biener <rguenther@suse.de>
+
+ * tree-ssa-dse.c (dse_classify_store): Fix iterator increment
+ for pruning loop and prune defs feeding only already visited PHIs.
+
+2018-05-17 Richard Biener <rguenther@suse.de>
+
+ * tree-ssa-sccvn.c (vn_reference_lookup_3): Improve memset handling.
+
+2018-05-17 Bin Cheng <bin.cheng@arm.com>
+ Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/85793
+ * tree-vect-stmts.c (vectorizable_load): Handle 1 element-wise load
+ for VMAT_ELEMENTWISE.
+
+2018-05-17 Richard Sandiford <richard.sandiford@linaro.org>
+
+ * internal-fn.h (lookup_internal_fn): Declare
+ * internal-fn.c (lookup_internal_fn): New function.
+ * gimple.c (gimple_build_call_from_tree): Handle calls to
+ internal functions.
+ * gimple-pretty-print.c (dump_gimple_call): Print "." before
+ internal function names.
+ * tree-pretty-print.c (dump_generic_node): Likewise.
+ * tree-ssa-scopedtables.c (expr_hash_elt::print): Likewise.
+
+2018-05-17 Richard Sandiford <richard.sandiford@linaro.org>
+
+ * gimple-fold.h (gimple_build): Make the function forms take
+ combined_fn rather than built_in_function.
+ (gimple_simplify): Likewise.
+ * gimple-match-head.c (gimple_simplify): Likewise.
+ * gimple-fold.c (gimple_build): Likewise.
+ * tree-vect-loop.c (get_initial_def_for_reduction): Use gimple_build
+ rather than gimple_build_call_internal.
+ (get_initial_defs_for_reduction): Likewise.
+ (vect_create_epilog_for_reduction): Likewise.
+ (vectorizable_live_operation): Likewise.
+
+2018-05-17 Martin Liska <mliska@suse.cz>
+
+ * gimple-ssa-sprintf.c (format_directive): Do not use
+ space in between 'G_' and '('.
+
+2018-05-17 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/85323
+ * config/i386/i386.c (ix86_fold_builtin): Handle masked shifts
+ even if the mask is not all ones.
+
+ PR target/85323
+ * config/i386/i386.c (ix86_fold_builtin): Fold shift builtins by
+ vector.
+ (ix86_gimple_fold_builtin): Likewise.
+
+ PR target/85323
+ * config/i386/i386.c: Include tree-vector-builder.h.
+ (ix86_vector_shift_count): New function.
+ (ix86_fold_builtin): Fold shift builtins by scalar count.
+ (ix86_gimple_fold_builtin): Likewise.
+
+ * config/i386/avx512fintrin.h (_mm512_set_epi16, _mm512_set_epi8,
+ _mm512_setzero): New intrinsics.
+
+2018-05-17 James Greenhalgh <james.greenhalgh@arm.com>
+ Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_expand_vector_init): Modify
+ code generation for cases where splatting a value is not useful.
+ * simplify-rtx.c (simplify_ternary_operation): Simplify
+ vec_merge across a vec_duplicate and a paradoxical subreg forming a vector
+ mode to a vec_concat.
+
+2018-05-17 Olga Makhotina <olga.makhotina@intel.com>
+
+ * config.gcc: Support "goldmont-plus".
+ * config/i386/driver-i386.c (host_detect_local_cpu): Detect
+ "goldmont-plus".
+ * config/i386/i386-c.c (ix86_target_macros_internal): Handle
+ PROCESSOR_GOLDMONT_PLUS.
+ * config/i386/i386.c (m_GOLDMONT_PLUS): Define.
+ (processor_target_table): Add "goldmont-plus".
+ (PTA_GOLDMONT_PLUS): Define.
+ (ix86_lea_outperforms): Add TARGET_GOLDMONT_PLUS.
+ (get_builtin_code_for_version): Handle PROCESSOR_GOLDMONT_PLUS.
+ (fold_builtin_cpu): Add M_INTEL_GOLDMONT_PLUS.
+ (fold_builtin_cpu): Add "goldmont-plus".
+ (ix86_add_stmt_cost): Add TARGET_GOLDMONT_PLUS.
+ (ix86_option_override_internal): Add "goldmont-plus".
+ * config/i386/i386.h (processor_costs): Define TARGET_GOLDMONT_PLUS.
+ (processor_type): Add PROCESSOR_GOLDMONT_PLUS.
+ * config/i386/x86-tune.def: Add m_GOLDMONT_PLUS.
+ * doc/invoke.texi: Add goldmont-plus as x86 -march=/-mtune= CPU type.
+
+2018-05-17 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/85757
+ * tree-ssa-dse.c (dse_classify_store): Record a PHI def and
+ remove defs that only feed that PHI from further processing.
+
+2018-05-16 Jim Wilson <jimw@sifive.com>
+
+ * config/riscv/riscv.md (<optab>si3_mask, <optab>si3_mask_1): Prepend
+ asterisk to name.
+ (<optab>di3_mask, <optab>di3_mask_1): Likewise.
+
+2018-05-16 Mark Wielaard <mark@klomp.org>
+
+ * dwarf2out.c (count_index_strings): New function.
+ (output_indirect_strings): Call count_index_strings and generate
+ header for dwarf_version >= 5.
+
+2018-05-16 Mark Wielaard <mark@klomp.org>
+
+ * dwarf2out.c (dwarf_FORM): New function.
+ (set_indirect_string): Use dwarf_FORM.
+ (reset_indirect_string): Likewise.
+ (size_of_die): Likewise.
+ (value_format): Likewise.
+ (output_die): Likewise.
+ (add_skeleton_AT_string): Likewise.
+ (output_macinfo_op): Likewise.
+ (index_string): Likewise.
+ (output_index_string_offset): Likewise.
+ (output_index_string): Likewise.
+ (count_index_strings): Likewise.
+
+2018-05-16 Carl Love <cel@us.ibm.com>
+
+ * config/rs6000/rs6000.md (prefetch): Generate ISA 2.06 instructions
+ dcbt and dcbtstt with TH=16 if operands[2] is 0 and Power 8 or newer.
+
+2018-05-16 Martin Jambor <mjambor@suse.cz>
+
+ * ipa-prop.c (ipa_free_all_edge_args): Remove.
+ * ipa-prop.h (ipa_free_all_edge_args): Likewise.
+
+2018-05-16 Wilco Dijkstra <wdijkstr@arm.com>
+
+ * config/aarch64/aarch64.md (fma<mode>4): Change into expand pattern.
+ (fnma<mode>4): Likewise.
+ (fms<mode>4): Likewise.
+ (fnms<mode>4): Likewise.
+ (aarch64_fma<mode>4): Rename insn, reorder accumulator operand.
+ (aarch64_fnma<mode>4): Likewise.
+ (aarch64_fms<mode>4): Likewise.
+ (aarch64_fnms<mode>4): Likewise.
+ (aarch64_fnmadd<mode>4): Likewise.
+
+2018-05-16 Jason Merrill <jason@redhat.com>
+
+ * tree.c (warn_deprecated_use): Return bool. Simplify logic.
+
+2018-05-16 Richard Biener <rguenther@suse.de>
+
+ * tree-vectorizer.h (struct stmt_info_for_cost): Add where member.
+ (dump_stmt_cost): Declare.
+ (add_stmt_cost): Dump cost we add.
+ (add_stmt_costs): New function.
+ (vect_model_simple_cost, vect_model_store_cost, vect_model_load_cost):
+ No longer exported.
+ (vect_analyze_stmt): Adjust prototype.
+ (vectorizable_condition): Likewise.
+ (vectorizable_live_operation): Likewise.
+ (vectorizable_reduction): Likewise.
+ (vectorizable_induction): Likewise.
+ * tree-vect-loop.c (vect_analyze_loop_operations): Create local
+ cost vector to pass to vectorizable_ and record afterwards.
+ (vect_model_reduction_cost): Take cost vector argument and adjust.
+ (vect_model_induction_cost): Likewise.
+ (vectorizable_reduction): Likewise.
+ (vectorizable_induction): Likewise.
+ (vectorizable_live_operation): Likewise.
+ * tree-vect-slp.c (vect_create_new_slp_node): Initialize
+ SLP_TREE_NUMBER_OF_VEC_STMTS.
+ (vect_analyze_slp_cost_1): Remove.
+ (vect_analyze_slp_cost): Likewise.
+ (vect_slp_analyze_node_operations): Take visited args and
+ a target cost vector. Avoid processing already visited stmt sets.
+ (vect_slp_analyze_operations): Use a local cost vector to gather
+ costs and register those of non-discarded instances.
+ (vect_bb_vectorization_profitable_p): Use add_stmt_costs.
+ (vect_schedule_slp_instance): Remove copying of
+ SLP_TREE_NUMBER_OF_VEC_STMTS. Instead assert that it is not
+ zero.
+ * tree-vect-stmts.c (record_stmt_cost): Remove path directly
+ adding cost. Record cost entry location.
+ (vect_prologue_cost_for_slp_op): Function to compute cost of
+ a constant or invariant generated for SLP vect in the prologue,
+ split out from vect_analyze_slp_cost_1.
+ (vect_model_simple_cost): Make static. Adjust for SLP costing.
+ (vect_model_promotion_demotion_cost): Likewise.
+ (vect_model_store_cost): Likewise, make static.
+ (vect_model_load_cost): Likewise.
+ (vectorizable_bswap): Add cost vector arg and adjust.
+ (vectorizable_call): Likewise.
+ (vectorizable_simd_clone_call): Likewise.
+ (vectorizable_conversion): Likewise.
+ (vectorizable_assignment): Likewise.
+ (vectorizable_shift): Likewise.
+ (vectorizable_operation): Likewise.
+ (vectorizable_store): Likewise.
+ (vectorizable_load): Likewise.
+ (vectorizable_condition): Likewise.
+ (vectorizable_comparison): Likewise.
+ (can_vectorize_live_stmts): Likewise.
+ (vect_analyze_stmt): Likewise.
+ (vect_transform_stmt): Adjust calls to vectorizable_*.
+ * tree-vectorizer.c: Include gimple-pretty-print.h.
+ (dump_stmt_cost): New function.
+
+2018-05-16 Richard Biener <rguenther@suse.de>
+
+ * params.def (PARAM_DSE_MAX_ALIAS_QUERIES_PER_STORE): New param.
+ * doc/invoke.texi (dse-max-alias-queries-per-store): Document.
+ * tree-ssa-dse.c: Include tree-ssa-loop.h.
+ (check_name): New callback.
+ (dse_classify_store): Track cycles via a visited bitmap of PHI
+ defs and simplify handling of in-loop and across loop dead stores
+ and properly fail for loop-variant refs. Handle byte-tracking with
+ multiple defs. Use PARAM_DSE_MAX_ALIAS_QUERIES_PER_STORE for
+ limiting the walk.
+
+2018-05-16 Richard Sandiford <richard.sandiford@linaro.org>
+
+ * tree-vectorizer.h (vect_get_vector_types_for_stmt): Declare.
+ (vect_get_mask_type_for_stmt): Likewise.
+ * tree-vect-slp.c (vect_two_operations_perm_ok_p): New function,
+ split out from...
+ (vect_build_slp_tree_1): ...here. Use vect_get_vector_types_for_stmt
+ to determine the statement's vector type and the vector type that
+ should be used for calculating nunits. Deal with cases in which
+ the type has to be deferred.
+ (vect_slp_analyze_node_operations): Use vect_get_vector_types_for_stmt
+ and vect_get_mask_type_for_stmt to calculate STMT_VINFO_VECTYPE.
+ * tree-vect-loop.c (vect_determine_vf_for_stmt_1)
+ (vect_determine_vf_for_stmt): New functions, split out from...
+ (vect_determine_vectorization_factor): ...here.
+ * tree-vect-stmts.c (vect_get_vector_types_for_stmt)
+ (vect_get_mask_type_for_stmt): New functions, split out from
+ vect_determine_vectorization_factor.
+
+2018-05-16 Richard Biener <rguenther@suse.de>
+
+ * tree-cfg.c (verify_gimple_assign_ternary): Properly
+ verify the [VEC_]COND_EXPR embedded comparison.
+
+2018-05-15 Martin Sebor <msebor@redhat.com>
+
+ PR tree-optimization/85753
+ * gimple-ssa-warn-restrict.c (builtin_memref::builtin_memref): Handle
+ RECORD_TYPE in addition to ARRAY_TYPE.
+
+2018-05-15 Martin Sebor <msebor@redhat.com>
+
+ PR middle-end/85643
+ * calls.c (get_attr_nonstring_decl): Handle MEM_REF.
+
2018-05-15 Richard Biener <rguenther@suse.de>
* tree-ssa-dse.c (dse_classify_store): Remove use_stmt parameter,
projects / gcc.git / blobdiff