+2017-12-20 Richard Sandiford <richard.sandiford@linaro.org>
+ Alan Hayward <alan.hayward@arm.com>
+ David Sherwood <david.sherwood@arm.com>
+
+ * expmed.h (store_bit_field): Take bitsize and bitnum as
+ poly_uint64s rather than unsigned HOST_WIDE_INTs.
+ * expmed.c (simple_mem_bitfield_p): Likewise. Add a parameter
+ that returns the byte size.
+ (store_bit_field_1): Take bitsize and bitnum as
+ poly_uint64s rather than unsigned HOST_WIDE_INTs. Update call
+ to simple_mem_bitfield_p. Split the part that can only handle
+ constant bitsize and bitnum out into...
+ (store_integral_bit_field): ...this new function.
+ (store_bit_field): Take bitsize and bitnum as poly_uint64s rather
+ than unsigned HOST_WIDE_INTs.
+ (extract_bit_field_1): Update call to simple_mem_bitfield_p.
+
+2017-12-20 Richard Sandiford <richard.sandiford@linaro.org>
+ Alan Hayward <alan.hayward@arm.com>
+ David Sherwood <david.sherwood@arm.com>
+
+ * lra-int.h (lra_reg): Change offset from int to poly_int64.
+ (lra_insn_recog_data): Change sp_offset from HOST_WIDE_INT
+ to poly_int64.
+ (lra_eliminate_regs_1, eliminate_regs_in_insn): Change
+ update_sp_offset from a HOST_WIDE_INT to a poly_int64.
+ (lra_update_reg_val_offset, lra_reg_val_equal_p): Take the
+ offset as a poly_int64 rather than an int.
+ * lra-assigns.c (find_hard_regno_for_1): Handle poly_int64 offsets.
+ (setup_live_pseudos_and_spill_after_risky_transforms): Likewise.
+ * lra-constraints.c (equiv_address_substitution): Track offsets
+ as poly_int64s.
+ (emit_inc): Check poly_int_rtx_p instead of CONST_INT_P.
+ (curr_insn_transform): Handle the new form of sp_offset.
+ * lra-eliminations.c (lra_elim_table): Change previous_offset
+ and offset from HOST_WIDE_INT to poly_int64.
+ (print_elim_table, update_reg_eliminate): Update accordingly.
+ (self_elim_offsets): Change from HOST_WIDE_INT to poly_int64_pod.
+ (get_elimination): Update accordingly.
+ (form_sum): Check poly_int_rtx_p instead of CONST_INT_P.
+ (lra_eliminate_regs_1, eliminate_regs_in_insn): Change
+ update_sp_offset from a HOST_WIDE_INT to a poly_int64. Handle
+ poly_int64 offsets generally.
+ (curr_sp_change): Change from HOST_WIDE_INT to poly_int64.
+ (mark_not_eliminable, init_elimination): Update accordingly.
+ (remove_reg_equal_offset_note): Return a bool and pass the new
+ offset back by pointer as a poly_int64.
+ * lra-remat.c (change_sp_offset): Take sp_offset as a poly_int64
+ rather than a HOST_WIDE_INT.
+ (do_remat): Track offsets poly_int64s.
+ * lra.c (lra_update_insn_recog_data, setup_sp_offset): Likewise.
+
+2017-12-20 Richard Sandiford <richard.sandiford@linaro.org>
+ Alan Hayward <alan.hayward@arm.com>
+ David Sherwood <david.sherwood@arm.com>
+
+ * rtl.h (mem_attrs): Add a default constructor. Change size and
+ offset from HOST_WIDE_INT to poly_int64.
+ * emit-rtl.h (set_mem_offset, set_mem_size, adjust_address_1)
+ (adjust_automodify_address_1, set_mem_attributes_minus_bitpos)
+ (widen_memory_access): Take the sizes and offsets as poly_int64s
+ rather than HOST_WIDE_INTs.
+ * alias.c (ao_ref_from_mem): Handle the new form of MEM_OFFSET.
+ (offset_overlap_p): Take poly_int64s rather than HOST_WIDE_INTs
+ and ints.
+ (adjust_offset_for_component_ref): Change the offset from a
+ HOST_WIDE_INT to a poly_int64.
+ (nonoverlapping_memrefs_p): Track polynomial offsets and sizes.
+ * cfgcleanup.c (merge_memattrs): Update after mem_attrs changes.
+ * dce.c (find_call_stack_args): Likewise.
+ * dse.c (record_store): Likewise.
+ * dwarf2out.c (tls_mem_loc_descriptor, dw_sra_loc_expr): Likewise.
+ * print-rtl.c (rtx_writer::print_rtx): Likewise.
+ * read-rtl-function.c (test_loading_mem): Likewise.
+ * rtlanal.c (may_trap_p_1): Likewise.
+ * simplify-rtx.c (delegitimize_mem_from_attrs): Likewise.
+ * var-tracking.c (int_mem_offset, track_expr_p): Likewise.
+ * emit-rtl.c (mem_attrs_eq_p, get_mem_align_offset): Likewise.
+ (mem_attrs::mem_attrs): New function.
+ (set_mem_attributes_minus_bitpos): Change bitpos from a
+ HOST_WIDE_INT to poly_int64.
+ (set_mem_alias_set, set_mem_addr_space, set_mem_align, set_mem_expr)
+ (clear_mem_offset, clear_mem_size, change_address)
+ (get_spill_slot_decl, set_mem_attrs_for_spill): Directly
+ initialize mem_attrs.
+ (set_mem_offset, set_mem_size, adjust_address_1)
+ (adjust_automodify_address_1, offset_address, widen_memory_access):
+ Likewise. Take poly_int64s rather than HOST_WIDE_INT.
+
+2017-12-20 Richard Sandiford <richard.sandiford@linaro.org>
+ Alan Hayward <alan.hayward@arm.com>
+ David Sherwood <david.sherwood@arm.com>
+
+ * rtlanal.c (rtx_addr_can_trap_p_1): Take the offset and size
+ as poly_int64s rather than HOST_WIDE_INTs. Use a size of -1
+ rather than 0 to represent an unknown size. Assert that the size
+ is known when the mode isn't BLKmode.
+ (may_trap_p_1): Use -1 for unknown sizes.
+ (rtx_addr_can_trap_p): Likewise. Pass BLKmode rather than VOIDmode.
+
+2017-12-20 Richard Sandiford <richard.sandiford@linaro.org>
+ Alan Hayward <alan.hayward@arm.com>
+ David Sherwood <david.sherwood@arm.com>
+
+ * dse.c (store_info): Change offset and width from HOST_WIDE_INT
+ to poly_int64. Update commentary for positions_needed.large.
+ (read_info_type): Change offset and width from HOST_WIDE_INT
+ to poly_int64.
+ (set_usage_bits): Likewise.
+ (canon_address): Return the offset as a poly_int64 rather than
+ a HOST_WIDE_INT. Use strip_offset_and_add.
+ (set_all_positions_unneeded, any_positions_needed_p): Use
+ positions_needed.large to track stores with non-constant widths.
+ (all_positions_needed_p): Likewise. Take the offset and width
+ as poly_int64s rather than ints. Assert that rhs is nonnull.
+ (record_store): Cope with non-constant offsets and widths.
+ Nullify the rhs of an earlier store if we can't tell which bytes
+ of it are needed.
+ (find_shift_sequence): Take the access_size and shift as poly_int64s
+ rather than ints.
+ (get_stored_val): Take the read_offset and read_width as poly_int64s
+ rather than HOST_WIDE_INTs.
+ (check_mem_read_rtx, scan_stores, scan_reads, dse_step5): Handle
+ non-constant offsets and widths.
+
+2017-12-20 Richard Sandiford <richard.sandiford@linaro.org>
+ Alan Hayward <alan.hayward@arm.com>
+ David Sherwood <david.sherwood@arm.com>
+
+ * inchash.h (inchash::hash::add_poly_int): New function.
+ * tree-ssa-alias.h (ao_ref::offset, ao_ref::size, ao_ref::max_size):
+ Use poly_int64 rather than HOST_WIDE_INT.
+ (ao_ref::max_size_known_p): New function.
+ * tree-ssa-sccvn.h (vn_reference_op_struct::off): Use poly_int64_pod
+ rather than HOST_WIDE_INT.
+ * tree-ssa-alias.c (ao_ref_base): Apply get_ref_base_and_extent
+ to temporaries until its interface is adjusted to match.
+ (ao_ref_init_from_ptr_and_size): Handle polynomial offsets and sizes.
+ (aliasing_component_refs_p, decl_refs_may_alias_p)
+ (indirect_ref_may_alias_decl_p, indirect_refs_may_alias_p): Take
+ the offsets and max_sizes as poly_int64s instead of HOST_WIDE_INTs.
+ (refs_may_alias_p_1, stmt_kills_ref_p): Adjust for changes to
+ ao_ref fields.
+ * alias.c (ao_ref_from_mem): Likewise.
+ * tree-ssa-dce.c (mark_aliased_reaching_defs_necessary_1): Likewise.
+ * tree-ssa-dse.c (valid_ao_ref_for_dse, normalize_ref)
+ (clear_bytes_written_by, setup_live_bytes_from_ref, compute_trims)
+ (maybe_trim_complex_store, maybe_trim_constructor_store)
+ (live_bytes_read, dse_classify_store): Likewise.
+ * tree-ssa-sccvn.c (vn_reference_compute_hash, vn_reference_eq):
+ (copy_reference_ops_from_ref, ao_ref_init_from_vn_reference)
+ (fully_constant_vn_reference_p, valueize_refs_1): Likewise.
+ (vn_reference_lookup_3): Likewise.
+ * tree-ssa-uninit.c (warn_uninitialized_vars): Likewise.
+
+2017-12-20 Richard Sandiford <richard.sandiford@linaro.org>
+ Alan Hayward <alan.hayward@arm.com>
+ David Sherwood <david.sherwood@arm.com>
+
+ * tree-ssa-alias.c (indirect_ref_may_alias_decl_p)
+ (indirect_refs_may_alias_p): Use ranges_may_overlap_p
+ instead of ranges_overlap_p.
+
+2017-12-20 Richard Sandiford <richard.sandiford@linaro.org>
+ Alan Hayward <alan.hayward@arm.com>
+ David Sherwood <david.sherwood@arm.com>
+
+ * tree-ssa-alias.c (same_addr_size_stores_p): Take the offsets and
+ sizes as poly_int64s rather than HOST_WIDE_INTs.
+
+2017-12-20 Richard Sandiford <richard.sandiford@linaro.org>
+ Alan Hayward <alan.hayward@arm.com>
+ David Sherwood <david.sherwood@arm.com>
+
+ * gimple-fold.h (fold_ctor_reference): Take the offset and size
+ as poly_uint64 rather than unsigned HOST_WIDE_INT.
+ * gimple-fold.c (fold_ctor_reference): Likewise.
+
+2017-12-20 Richard Sandiford <richard.sandiford@linaro.org>
+ Alan Hayward <alan.hayward@arm.com>
+ David Sherwood <david.sherwood@arm.com>
+
+ * target.def (dwarf_poly_indeterminate_value): New hook.
+ * targhooks.h (default_dwarf_poly_indeterminate_value): Declare.
+ * targhooks.c (default_dwarf_poly_indeterminate_value): New function.
+ * doc/tm.texi.in (TARGET_DWARF_POLY_INDETERMINATE_VALUE): Document.
+ * doc/tm.texi: Regenerate.
+ * dwarf2out.h (build_cfa_loc, build_cfa_aligned_loc): Take the
+ offset as a poly_int64.
+ * dwarf2out.c (new_reg_loc_descr): Move later in file. Take the
+ offset as a poly_int64.
+ (loc_descr_plus_const, loc_list_plus_const, build_cfa_aligned_loc):
+ Take the offset as a poly_int64.
+ (build_cfa_loc): Likewise. Use loc_descr_plus_const.
+ (frame_pointer_fb_offset): Change to a poly_int64.
+ (int_loc_descriptor): Take the offset as a poly_int64. Use
+ targetm.dwarf_poly_indeterminate_value for polynomial offsets.
+ (based_loc_descr): Take the offset as a poly_int64.
+ Use strip_offset_and_add to handle (plus X (const)).
+ Use new_reg_loc_descr instead of an open-coded version of the
+ previous implementation.
+ (mem_loc_descriptor): Handle CONST_POLY_INT.
+ (compute_frame_pointer_to_fb_displacement): Take the offset as a
+ poly_int64. Use strip_offset_and_add to handle (plus X (const)).
+
+2017-12-20 Richard Sandiford <richard.sandiford@linaro.org>
+ Alan Hayward <alan.hayward@arm.com>
+ David Sherwood <david.sherwood@arm.com>
+
+ * rtl.h (reg_attrs::offset): Change from HOST_WIDE_INT to poly_int64.
+ (gen_rtx_REG_offset): Take the offset as a poly_int64.
+ * inchash.h (inchash::hash::add_poly_hwi): New function.
+ * gengtype.c (main): Register poly_int64.
+ * emit-rtl.c (reg_attr_hasher::hash): Use inchash. Treat the
+ offset as a poly_int.
+ (reg_attr_hasher::equal): Use must_eq to compare offsets.
+ (get_reg_attrs, update_reg_offset, gen_rtx_REG_offset): Take the
+ offset as a poly_int64.
+ (set_reg_attrs_from_value): Treat the offset as a poly_int64.
+ * print-rtl.c (print_poly_int): New function.
+ (rtx_writer::print_rtx_operand_code_r): Treat REG_OFFSET as
+ a poly_int.
+ * var-tracking.c (track_offset_p, get_tracked_reg_offset): New
+ functions.
+ (var_reg_set, var_reg_delete_and_set, var_reg_delete): Use them.
+ (same_variable_part_p, track_loc_p): Take the offset as a poly_int64.
+ (vt_get_decl_and_offset): Return the offset as a poly_int64.
+ Enforce track_offset_p for parts of a PARALLEL.
+ (vt_add_function_parameter): Use const_offset for the final
+ offset to track. Use get_tracked_reg_offset for the parts
+ of a PARALLEL.
+
+2017-12-20 Richard Sandiford <richard.sandiford@linaro.org>
+ Alan Hayward <alan.hayward@arm.com>
+ David Sherwood <david.sherwood@arm.com>
+
+ * target.def (truly_noop_truncation): Take poly_uint64s instead of
+ unsigned ints. Change default to hook_bool_puint64_puint64_true.
+ * doc/tm.texi: Regenerate.
+ * hooks.h (hook_bool_uint_uint_true): Delete.
+ (hook_bool_puint64_puint64_true): Declare.
+ * hooks.c (hook_bool_uint_uint_true): Delete.
+ (hook_bool_puint64_puint64_true): New function.
+ * config/mips/mips.c (mips_truly_noop_truncation): Take poly_uint64s
+ instead of unsigned ints.
+ * config/spu/spu.c (spu_truly_noop_truncation): Likewise.
+ * config/tilegx/tilegx.c (tilegx_truly_noop_truncation): Likewise.
+
+2017-12-20 Richard Sandiford <richard.sandiford@linaro.org>
+ Alan Hayward <alan.hayward@arm.com>
+ David Sherwood <david.sherwood@arm.com>
+
+ * optabs.h (expand_operand): Add an int_value field.
+ (create_expand_operand): Add an int_value parameter and use it
+ to initialize the new expand_operand field.
+ (create_integer_operand): Replace with a declaration of a function
+ that accepts poly_int64s. Move the implementation to...
+ * optabs.c (create_integer_operand): ...here.
+ (maybe_legitimize_operand): For EXPAND_INTEGER, check whether
+ the mode preserves the value of int_value, instead of calling
+ const_int_operand on the rtx. Use gen_int_mode to generate
+ the new rtx.
+
+2017-12-20 Richard Sandiford <richard.sandiford@linaro.org>
+ Alan Hayward <alan.hayward@arm.com>
+ David Sherwood <david.sherwood@arm.com>
+
+ * dumpfile.h (dump_dec): Declare.
+ * dumpfile.c (dump_dec): New function.
+ * pretty-print.h (pp_wide_integer): Turn into a function and
+ declare a poly_int version.
+ * pretty-print.c (pp_wide_integer): New function for poly_ints.
+
+2017-12-20 Richard Sandiford <richard.sandiford@linaro.org>
+ Alan Hayward <alan.hayward@arm.com>
+ David Sherwood <david.sherwood@arm.com>
+
+ * doc/generic.texi (POLY_INT_CST): Document.
+ * tree.def (POLY_INT_CST): New tree code.
+ * treestruct.def (TS_POLY_INT_CST): New tree layout.
+ * tree-core.h (tree_poly_int_cst): New struct.
+ (tree_node): Add a poly_int_cst field.
+ * tree.h (POLY_INT_CST_P, POLY_INT_CST_COEFF): New macros.
+ (wide_int_to_tree, force_fit_type): Take a poly_wide_int_ref
+ instead of a wide_int_ref.
+ (build_int_cst, build_int_cst_type): Take a poly_int64 instead
+ of a HOST_WIDE_INT.
+ (build_int_cstu, build_array_type_nelts): Take a poly_uint64
+ instead of an unsigned HOST_WIDE_INT.
+ (build_poly_int_cst, tree_fits_poly_int64_p, tree_fits_poly_uint64_p)
+ (ptrdiff_tree_p): Declare.
+ (tree_to_poly_int64, tree_to_poly_uint64): Likewise. Provide
+ extern inline implementations if the target doesn't use POLY_INT_CST.
+ (poly_int_tree_p): New function.
+ (wi::unextended_tree): New class.
+ (wi::int_traits <unextended_tree>): New override.
+ (wi::extended_tree): Add a default constructor.
+ (wi::extended_tree::get_tree): New function.
+ (wi::widest_extended_tree, wi::offset_extended_tree): New typedefs.
+ (wi::tree_to_widest_ref, wi::tree_to_offset_ref): Use them.
+ (wi::tree_to_poly_widest_ref, wi::tree_to_poly_offset_ref)
+ (wi::tree_to_poly_wide_ref): New typedefs.
+ (wi::ints_for): Provide overloads for extended_tree and
+ unextended_tree.
+ (poly_int_cst_value, wi::to_poly_widest, wi::to_poly_offset)
+ (wi::to_wide): New functions.
+ (wi::fits_to_boolean_p, wi::fits_to_tree_p): Handle poly_ints.
+ * tree.c (poly_int_cst_hasher): New struct.
+ (poly_int_cst_hash_table): New variable.
+ (tree_node_structure_for_code, tree_code_size, simple_cst_equal)
+ (valid_constant_size_p, add_expr, drop_tree_overflow): Handle
+ POLY_INT_CST.
+ (initialize_tree_contains_struct): Handle TS_POLY_INT_CST.
+ (init_ttree): Initialize poly_int_cst_hash_table.
+ (build_int_cst, build_int_cst_type, build_invariant_address): Take
+ a poly_int64 instead of a HOST_WIDE_INT.
+ (build_int_cstu, build_array_type_nelts): Take a poly_uint64
+ instead of an unsigned HOST_WIDE_INT.
+ (wide_int_to_tree): Rename to...
+ (wide_int_to_tree_1): ...this.
+ (build_new_poly_int_cst, build_poly_int_cst): New functions.
+ (force_fit_type): Take a poly_wide_int_ref instead of a wide_int_ref.
+ (wide_int_to_tree): New function that takes a poly_wide_int_ref.
+ (ptrdiff_tree_p, tree_to_poly_int64, tree_to_poly_uint64)
+ (tree_fits_poly_int64_p, tree_fits_poly_uint64_p): New functions.
+ * lto-streamer-out.c (DFS::DFS_write_tree_body, hash_tree): Handle
+ TS_POLY_INT_CST.
+ * tree-streamer-in.c (lto_input_ts_poly_tree_pointers): Likewise.
+ (streamer_read_tree_body): Likewise.
+ * tree-streamer-out.c (write_ts_poly_tree_pointers): Likewise.
+ (streamer_write_tree_body): Likewise.
+ * tree-streamer.c (streamer_check_handled_ts_structures): Likewise.
+ * asan.c (asan_protect_global): Require the size to be an INTEGER_CST.
+ * cfgexpand.c (expand_debug_expr): Handle POLY_INT_CST.
+ * expr.c (expand_expr_real_1, const_vector_from_tree): Likewise.
+ * gimple-expr.h (is_gimple_constant): Likewise.
+ * gimplify.c (maybe_with_size_expr): Likewise.
+ * print-tree.c (print_node): Likewise.
+ * tree-data-ref.c (data_ref_compare_tree): Likewise.
+ * tree-pretty-print.c (dump_generic_node): Likewise.
+ * tree-ssa-address.c (addr_for_mem_ref): Likewise.
+ * tree-vect-data-refs.c (dr_group_sort_cmp): Likewise.
+ * tree-vrp.c (compare_values_warnv): Likewise.
+ * tree-ssa-loop-ivopts.c (determine_base_object, constant_multiple_of)
+ (get_loop_invariant_expr, add_candidate_1, get_computation_aff_1)
+ (force_expr_to_var_cost): Likewise.
+ * tree-ssa-loop.c (for_each_index): Likewise.
+ * fold-const.h (build_invariant_address, size_int_kind): Take a
+ poly_int64 instead of a HOST_WIDE_INT.
+ * fold-const.c (fold_negate_expr_1, const_binop, const_unop)
+ (fold_convert_const, multiple_of_p, fold_negate_const): Handle
+ POLY_INT_CST.
+ (size_binop_loc): Likewise. Allow int_const_binop_1 to fail.
+ (int_const_binop_2): New function, split out from...
+ (int_const_binop_1): ...here. Handle POLY_INT_CST.
+ (size_int_kind): Take a poly_int64 instead of a HOST_WIDE_INT.
+ * expmed.c (make_tree): Handle CONST_POLY_INT_P.
+ * gimple-ssa-strength-reduction.c (slsr_process_add)
+ (slsr_process_mul): Check for INTEGER_CSTs before using them
+ as candidates.
+ * stor-layout.c (bits_from_bytes): New function.
+ (bit_from_pos): Use it.
+ (layout_type): Likewise. For vectors, multiply the TYPE_SIZE_UNIT
+ by BITS_PER_UNIT to get the TYPE_SIZE.
+ * tree-cfg.c (verify_expr, verify_types_in_gimple_reference): Allow
+ MEM_REF and TARGET_MEM_REF offsets to be a POLY_INT_CST.
+
+2017-12-20 Richard Sandiford <richard.sandiford@linaro.org>
+ Alan Hayward <alan.hayward@arm.com>
+ David Sherwood <david.sherwood@arm.com>
+
+ * doc/rtl.texi (const_poly_int): Document. Also document the
+ rtl sharing behavior.
+ * gengenrtl.c (excluded_rtx): Return true for CONST_POLY_INT.
+ * rtl.h (const_poly_int_def): New struct.
+ (rtx_def::u): Add a cpi field.
+ (CASE_CONST_UNIQUE, CASE_CONST_ANY): Add CONST_POLY_INT.
+ (CONST_POLY_INT_P, CONST_POLY_INT_COEFFS): New macros.
+ (wi::rtx_to_poly_wide_ref): New typedef
+ (const_poly_int_value, wi::to_poly_wide, rtx_to_poly_int64)
+ (poly_int_rtx_p): New functions.
+ (trunc_int_for_mode): Declare a poly_int64 version.
+ (plus_constant): Take a poly_int64 instead of a HOST_WIDE_INT.
+ (immed_wide_int_const): Take a poly_wide_int_ref rather than
+ a wide_int_ref.
+ (strip_offset): Declare.
+ (strip_offset_and_add): New function.
+ * rtl.def (CONST_POLY_INT): New rtx code.
+ * rtl.c (rtx_size): Handle CONST_POLY_INT.
+ (shared_const_p): Use poly_int_rtx_p.
+ * emit-rtl.h (gen_int_mode): Take a poly_int64 instead of a
+ HOST_WIDE_INT.
+ (gen_int_shift_amount): Likewise.
+ * emit-rtl.c (const_poly_int_hasher): New class.
+ (const_poly_int_htab): New variable.
+ (init_emit_once): Initialize it when NUM_POLY_INT_COEFFS > 1.
+ (const_poly_int_hasher::hash): New function.
+ (const_poly_int_hasher::equal): Likewise.
+ (gen_int_mode): Take a poly_int64 instead of a HOST_WIDE_INT.
+ (immed_wide_int_const): Rename to...
+ (immed_wide_int_const_1): ...this and make static.
+ (immed_wide_int_const): New function, taking a poly_wide_int_ref
+ instead of a wide_int_ref.
+ (gen_int_shift_amount): Take a poly_int64 instead of a HOST_WIDE_INT.
+ (gen_lowpart_common): Handle CONST_POLY_INT.
+ * cse.c (hash_rtx_cb, equiv_constant): Likewise.
+ * cselib.c (cselib_hash_rtx): Likewise.
+ * dwarf2out.c (const_ok_for_output_1): Likewise.
+ * expr.c (convert_modes): Likewise.
+ * print-rtl.c (rtx_writer::print_rtx, print_value): Likewise.
+ * rtlhash.c (add_rtx): Likewise.
+ * explow.c (trunc_int_for_mode): Add a poly_int64 version.
+ (plus_constant): Take a poly_int64 instead of a HOST_WIDE_INT.
+ Handle existing CONST_POLY_INT rtxes.
+ * expmed.h (expand_shift): Take a poly_int64 instead of a
+ HOST_WIDE_INT.
+ * expmed.c (expand_shift): Likewise.
+ * rtlanal.c (strip_offset): New function.
+ (commutative_operand_precedence): Give CONST_POLY_INT the same
+ precedence as CONST_DOUBLE and put CONST_WIDE_INT between that
+ and CONST_INT.
+ * rtl-tests.c (const_poly_int_tests): New struct.
+ (rtl_tests_c_tests): Use it.
+ * simplify-rtx.c (simplify_const_unary_operation): Handle
+ CONST_POLY_INT.
+ (simplify_const_binary_operation): Likewise.
+ (simplify_binary_operation_1): Fold additions of symbolic constants
+ and CONST_POLY_INTs.
+ (simplify_subreg): Handle extensions and truncations of
+ CONST_POLY_INTs.
+ (simplify_const_poly_int_tests): New struct.
+ (simplify_rtx_c_tests): Use it.
+ * wide-int.h (storage_ref): Add default constructor.
+ (wide_int_ref_storage): Likewise.
+ (trailing_wide_ints): Use GTY((user)).
+ (trailing_wide_ints::operator[]): Add a const version.
+ (trailing_wide_ints::get_precision): New function.
+ (trailing_wide_ints::extra_size): Likewise.
+
+2017-12-20 Richard Sandiford <richard.sandiford@linaro.org>
+ Alan Hayward <alan.hayward@arm.com>
+ David Sherwood <david.sherwood@arm.com>
+
+ * emit-rtl.h (gen_int_shift_amount): Declare.
+ * emit-rtl.c (gen_int_shift_amount): New function.
+ * asan.c (asan_emit_stack_protection): Use gen_int_shift_amount
+ instead of GEN_INT.
+ * calls.c (shift_return_value): Likewise.
+ * cse.c (fold_rtx): Likewise.
+ * dse.c (find_shift_sequence): Likewise.
+ * expmed.c (init_expmed_one_mode, store_bit_field_1, expand_shift_1)
+ (expand_shift, expand_smod_pow2): Likewise.
+ * lower-subreg.c (shift_cost): Likewise.
+ * optabs.c (expand_superword_shift, expand_doubleword_mult)
+ (expand_unop, expand_binop, shift_amt_for_vec_perm_mask)
+ (expand_vec_perm_var): Likewise.
+ * simplify-rtx.c (simplify_unary_operation_1): Likewise.
+ (simplify_binary_operation_1): Likewise.
+ * combine.c (try_combine, find_split_point, force_int_to_mode)
+ (simplify_shift_const_1, simplify_shift_const): Likewise.
+ (change_zero_ext): Likewise. Use simplify_gen_binary.
+
+2017-12-20 Richard Sandiford <richard.sandiford@linaro.org>
+
+ * poly-int.h (multiple_p): Fix handling of two non-poly_ints.
+
+2017-12-20 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * doc/invoke.texi (ARM Options): Document accepted extension options
+ for -march=armv8.3-a.
+
+2017-12-20 Richard Earnshaw <rearnsha@arm.com>
+
+ PR target/83105
+ * config.gcc (arm*-*-linux*): When configured with --with-float=hard
+ or --with-float=softfp, set the default CPU to arm10e.
+
+2017-12-20 Eric Botcazou <ebotcazou@adacore.com>
+
+ * config/visium/constraints.md (J, K, L): Use IN_RANGE macro.
+ * config/visium/predicates.md (const_shift_operand): Likewise.
+ * config/visium/visium.c (visium_legitimize_address): Fix oversight.
+ (visium_legitimize_reload_address): Likewise.
+
+2017-12-20 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ PR target/82975
+ * config/arm/arm.h (TEST_REGNO): Adjust comment as expected in r255830.
+
+2017-12-20 Jakub Jelinek <jakub@redhat.com>
+
+ PR c++/83490
+ * calls.c (compute_argument_addresses): Ignore TYPE_EMPTY_P arguments.
+
+2017-12-20 Julia Koval <julia.koval@intel.com>
+
+ * common/config/i386/i386-common.c (OPTION_MASK_ISA_VPCLMULQDQ_SET,
+ OPTION_MASK_ISA_VPCLMULQDQ_UNSET): New.
+ (ix86_handle_option): Handle -mvpclmulqdq, move cx6 to flags2.
+ * config.gcc: Include vpclmulqdqintrin.h.
+ * config/i386/cpuid.h: Handle bit_VPCLMULQDQ.
+ * config/i386/driver-i386.c (host_detect_local_cpu): Handle
+ -mvpclmulqdq.
+ * config/i386/i386-builtin.def (__builtin_ia32_vpclmulqdq_v2di,
+ __builtin_ia32_vpclmulqdq_v4di, __builtin_ia32_vpclmulqdq_v8di): New.
+ * config/i386/i386-c.c (__VPCLMULQDQ__): New.
+ * config/i386/i386.c (isa2_opts): Add -mcx16.
+ (isa_opts): Add -mpclmulqdq, remove -mcx16.
+ (ix86_option_override_internal): Move mcx16 to flags2.
+ (ix86_valid_target_attribute_inner_p): Add vpclmulqdq.
+ (ix86_expand_builtin): Handle OPTION_MASK_ISA_VPCLMULQDQ.
+ * config/i386/i386.h (TARGET_VPCLMULQDQ, TARGET_VPCLMULQDQ_P): New.
+ * config/i386/i386.opt: Add mvpclmulqdq, move mcx16 to flags2.
+ * config/i386/immintrin.h: Include vpclmulqdqintrin.h.
+ * config/i386/sse.md (vpclmulqdq_<mode>): New pattern.
+ * config/i386/vpclmulqdqintrin.h (_mm512_clmulepi64_epi128,
+ _mm_clmulepi64_epi128, _mm256_clmulepi64_epi128): New intrinsics.
+ * doc/invoke.texi: Add -mvpclmulqdq.
+
+2017-12-20 Tom de Vries <tom@codesourcery.com>
+
+ PR middle-end/83423
+ * config/i386/i386.c (ix86_static_chain): Move DECL_STATIC_CHAIN test ...
+ * calls.c (rtx_for_static_chain): ... here. New function.
+ * calls.h (rtx_for_static_chain): Declare.
+ * builtins.c (expand_builtin_setjmp_receiver): Use rtx_for_static_chain
+ instead of targetm.calls.static_chain.
+ * df-scan.c (df_get_entry_block_def_set): Same.
+
+2017-12-19 Tom de Vries <tom@codesourcery.com>
+
+ PR tree-optimization/83493
+ * graphite-isl-ast-to-gimple.c (translate_isl_ast_node_for): Unshare ub
+ and lb.
+
+2017-12-19 Jakub Jelinek <jakub@redhat.com>
+
+ * gimple-ssa-sprintf.c (format_directive): Use inform_n instead of
+ inform with hardcoded english plural handling.
+
+2017-12-18 Jeff Law <law@redhat.com>
+
+ PR tree-optimization/83477
+ * tree-ssa-threadedge.c (record_temporary_equivalences_from_phis): For
+ a non-virtual PHI, always push a new range.
+
+2017-12-19 Martin Sebor <msebor@redhat.com>
+
+ PR middle-end/77608
+ * builtins.c (compute_objsize): Handle non-constant offsets.
+
+2017-12-19 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/83444
+ * tree-ssa-strlen.c (strlen_check_and_optimize_stmt): For the
+ character load case, if get_stridx on MEM_REF's operand doesn't
+ look usable, retry with get_addr_stridx.
+
+2017-12-19 Alexandre Oliva <aoliva@redhat.com>
+
+ PR debug/83422
+ * var-tracking.c (vt_debug_insns_local): Do not drop markers.
+ (variable_tracking_main_1): Keep markers even when VTA fails.
+
+ PR bootstrap/83396
+ * cfgexpand.c (expand_gimple_basic_block): Expand label first,
+ even if there are markers before it.
+ * cfgrtl.c (rtl_verify_bb_layout): Reject DEBUG_INSNs outside BBs.
+
+2017-12-19 Jakub Jelinek <jakub@redhat.com>
+
+ * read-rtl.c (parse_reg_note_name): Replace Yoda conditions with
+ typical order conditions.
+ * sel-sched.c (extract_new_fences_from): Likewise.
+ * config/visium/constraints.md (J, K, L): Likewise.
+ * config/visium/predicates.md (const_shift_operand): Likewise.
+ * config/visium/visium.c (visium_legitimize_address,
+ visium_legitimize_reload_address): Likewise.
+ * config/m68k/m68k.c (output_reg_adjust, emit_reg_adjust): Likewise.
+ * config/arm/arm.c (arm_block_move_unaligned_straight): Likewise.
+ * config/avr/constraints.md (Y01, Ym1, Y02, Ym2): Likewise.
+ * config/avr/avr-log.c (avr_vdump, avr_log_set_avr_log,
+ SET_DUMP_DETAIL): Likewise.
+ * config/avr/predicates.md (const_8_16_24_operand): Likewise.
+ * config/avr/avr.c (STR_PREFIX_P, avr_popcount_each_byte,
+ avr_is_casesi_sequence, avr_casei_sequence_check_operands,
+ avr_set_core_architecture, avr_set_current_function,
+ avr_legitimize_reload_address, avr_asm_len, avr_print_operand,
+ output_movqi, output_movsisf, avr_out_plus, avr_out_bitop,
+ avr_out_fract, avr_adjust_insn_length, avr_encode_section_info,
+ avr_2word_insn_p, output_reload_in_const, avr_has_nibble_0xf,
+ avr_map_decompose, avr_fold_builtin): Likewise.
+ * config/avr/driver-avr.c (avr_devicespecs_file): Likewise.
+ * config/avr/gen-avr-mmcu-specs.c (str_prefix_p, print_mcu): Likewise.
+ * config/i386/i386.c (ix86_parse_stringop_strategy_string): Likewise.
+ * config/m32c/m32c-pragma.c (m32c_pragma_memregs): Likewise.
+ * config/m32c/m32c.c (m32c_conditional_register_usage,
+ m32c_address_cost): Likewise.
+ * config/m32c/predicates.md (shiftcount_operand,
+ longshiftcount_operand): Likewise.
+ * config/iq2000/iq2000.c (iq2000_expand_prologue): Likewise.
+ * config/nios2/nios2.c (nios2_handle_custom_fpu_insn_option,
+ can_use_cdx_ldstw): Likewise.
+ * config/nios2/nios2.h (CDX_REG_P): Likewise.
+ * config/cr16/cr16.h (RETURN_ADDR_RTX, REGNO_MODE_OK_FOR_BASE_P):
+ Likewise.
+ * config/cr16/cr16.md (*mov<mode>_double): Likewise.
+ * config/cr16/cr16.c (cr16_create_dwarf_for_multi_push): Likewise.
+ * config/h8300/h8300.c (h8300_rtx_costs, get_shift_alg): Likewise.
+ * config/vax/constraints.md (U06, U08, U16, CN6, S08, S16): Likewise.
+ * config/vax/vax.c (adjacent_operands_p): Likewise.
+ * config/ft32/constraints.md (L, b, KA): Likewise.
+ * config/ft32/ft32.c (ft32_load_immediate, ft32_expand_prologue):
+ Likewise.
+ * cfgexpand.c (expand_stack_alignment): Likewise.
+ * gcse.c (insert_expr_in_table): Likewise.
+ * print-rtl.c (rtx_writer::print_rtx_operand_codes_E_and_V): Likewise.
+ * cgraphunit.c (cgraph_node::expand): Likewise.
+ * ira-build.c (setup_min_max_allocno_live_range_point): Likewise.
+ * emit-rtl.c (add_insn): Likewise.
+ * input.c (dump_location_info): Likewise.
+ * passes.c (NEXT_PASS): Likewise.
+ * read-rtl-function.c (parse_note_insn_name,
+ function_reader::read_rtx_operand_r, function_reader::parse_mem_expr):
+ Likewise.
+ * sched-rgn.c (sched_rgn_init): Likewise.
+ * diagnostic-show-locus.c (layout::show_ruler): Likewise.
+ * combine.c (find_split_point, simplify_if_then_else, force_to_mode,
+ if_then_else_cond, simplify_shift_const_1, simplify_comparison): Likewise.
+ * explow.c (eliminate_constant_term): Likewise.
+ * final.c (leaf_renumber_regs_insn): Likewise.
+ * cfgrtl.c (print_rtl_with_bb): Likewise.
+ * genhooks.c (emit_init_macros): Likewise.
+ * poly-int.h (maybe_ne, maybe_le, maybe_lt): Likewise.
+ * tree-data-ref.c (conflict_fn): Likewise.
+ * selftest.c (assert_streq): Likewise.
+ * expr.c (store_constructor_field, expand_expr_real_1): Likewise.
+ * fold-const.c (fold_range_test, extract_muldiv_1, fold_truth_andor,
+ fold_binary_loc, multiple_of_p): Likewise.
+ * reload.c (push_reload, find_equiv_reg): Likewise.
+ * et-forest.c (et_nca, et_below): Likewise.
+ * dbxout.c (dbxout_symbol_location): Likewise.
+ * reorg.c (relax_delay_slots): Likewise.
+ * dojump.c (do_compare_rtx_and_jump): Likewise.
+ * gengtype-parse.c (type): Likewise.
+ * simplify-rtx.c (simplify_gen_ternary, simplify_gen_relational,
+ simplify_const_relational_operation): Likewise.
+ * reload1.c (do_output_reload): Likewise.
+ * dumpfile.c (get_dump_file_info_by_switch): Likewise.
+ * gengtype.c (type_for_name): Likewise.
+ * gimple-ssa-sprintf.c (format_directive): Likewise.
+
+2017-12-19 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ PR target/82975
+ * config/arm/arm.h (TEST_REGNO): Check reg_renumber is set before
+ accessing it. Adjust comment.
+
+2017-12-19 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/81914
+ * predict.c (zero_one_minusone): New function.
+ (apply_return_prediction): Avoid return prediction for functions
+ returning only -1, 0 and 1 values, unless they only return -1 and 0
+ or 0 and 1.
+
+2017-12-19 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * config/arc/arc.c (legitimate_scaled_address_p): Clean
+ fall-through warning.
+ (arc_compute_frame_size): Remove unused variables.
+ (arc_print_operand): Fix fprintif format.
+ (arc_can_follow_jump): Clean fall-through warning.
+
+2017-12-19 Marek Polacek <polacek@redhat.com>
+
+ PR c++/83489
+ * config/i386/i386.c (init_cumulative_args): Don't check TYPE_EMPTY_P
+ on an error node.
+
+2017-12-19 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * config/arc/arc.c (overriderregs): New variable.
+ (arc_override_options): Track fixed/call saved/call options.
+ (arc_conditional_register_usage): Check against overrideregs
+ variable whenever we change register properties.
+
2017-12-19 Nathan Sidwell <nathan@acm.org>
* opts.c (finish_options): Don't prefix dump_base_name if it
projects / gcc.git / blobdiff