[AArch64] Fix ICES with -mgeneral-regs-only / -march=...+nofp

[gcc.git] / gcc / config / aarch64 / aarch64.md

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index d3f5d5b20632b412d028416591ca7c449d885e08..934c8faf6d6ecd90a21fbc3243b8b79ab328177c 100644 (file)
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -979,18 +979,18 @@
   [(set (match_operand:GPF 0 "nonimmediate_operand" "")
        (match_operand:GPF 1 "general_operand" ""))]
   ""
-  "
+  {
     if (!TARGET_FLOAT)
-     {
-       sorry (\"%qs and floating point code\", \"-mgeneral-regs-only\");
+      {
+       aarch64_err_no_fpadvsimd (<MODE>mode, "code");
        FAIL;
-     }
+      }
 
     if (GET_CODE (operands[0]) == MEM
         && ! (GET_CODE (operands[1]) == CONST_DOUBLE
              && aarch64_float_const_zero_rtx_p (operands[1])))
       operands[1] = force_reg (<MODE>mode, operands[1]);
-  "
+  }
 )
 
 (define_insn "*movsf_aarch64"
@@ -1035,18 +1035,18 @@
   [(set (match_operand:TF 0 "nonimmediate_operand" "")
        (match_operand:TF 1 "general_operand" ""))]
   ""
-  "
+  {
     if (!TARGET_FLOAT)
-     {
-       sorry (\"%qs and floating point code\", \"-mgeneral-regs-only\");
+      {
+       aarch64_err_no_fpadvsimd (TFmode, "code");
        FAIL;
-     }
+      }
 
     if (GET_CODE (operands[0]) == MEM
         && ! (GET_CODE (operands[1]) == CONST_DOUBLE
              && aarch64_float_const_zero_rtx_p (operands[1])))
       operands[1] = force_reg (TFmode, operands[1]);
-  "
+  }
 )
 
 (define_insn "*movtf_aarch64"