AArch64 - use CSDB based sequences if speculation tracking is enabled

[gcc.git] / gcc / config / aarch64 / iterators.md

diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index c5ef2eecf20c4167c071f1b964e45092222b147c..450edea8ca090f78e054eedc94b59abdebb68b55 100644 (file)
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -35,6 +35,9 @@
 ;; Iterator for all integer modes (up to 64-bit)
 (define_mode_iterator ALLI [QI HI SI DI])
 
+;; Iterator for all integer modes (up to 128-bit)
+(define_mode_iterator ALLI_TI [QI HI SI DI TI])
+
 ;; Iterator for all integer modes that can be extended (up to 64-bit)
 (define_mode_iterator ALLX [QI HI SI])
 
@@ -471,6 +474,10 @@
     UNSPEC_COND_DIV    ; Used in aarch64-sve.md.
     UNSPEC_COND_MAX    ; Used in aarch64-sve.md.
     UNSPEC_COND_MIN    ; Used in aarch64-sve.md.
+    UNSPEC_COND_FMLA   ; Used in aarch64-sve.md.
+    UNSPEC_COND_FMLS   ; Used in aarch64-sve.md.
+    UNSPEC_COND_FNMLA  ; Used in aarch64-sve.md.
+    UNSPEC_COND_FNMLS  ; Used in aarch64-sve.md.
     UNSPEC_COND_LT     ; Used in aarch64-sve.md.
     UNSPEC_COND_LE     ; Used in aarch64-sve.md.
     UNSPEC_COND_EQ     ; Used in aarch64-sve.md.
@@ -1207,11 +1214,11 @@
 ;; SVE floating-point unary operations.
 (define_code_iterator SVE_FP_UNARY [neg abs sqrt])
 
+;; SVE integer binary operations.
 (define_code_iterator SVE_INT_BINARY [plus minus mult smax umax smin umin
                                      and ior xor])
 
-(define_code_iterator SVE_INT_BINARY_REV [minus])
-
+;; SVE integer binary division operations.
 (define_code_iterator SVE_INT_BINARY_SD [div udiv])
 
 ;; SVE integer comparisons.
@@ -1402,6 +1409,19 @@
                              (not "not")
                              (popcount "cnt")])
 
+(define_code_attr sve_int_op_rev [(plus "add")
+                                 (minus "subr")
+                                 (mult "mul")
+                                 (div "sdivr")
+                                 (udiv "udivr")
+                                 (smin "smin")
+                                 (smax "smax")
+                                 (umin "umin")
+                                 (umax "umax")
+                                 (and "and")
+                                 (ior "orr")
+                                 (xor "eor")])
+
 ;; The floating-point SVE instruction that implements an rtx code.
 (define_code_attr sve_fp_op [(plus "fadd")
                             (neg "fneg")
@@ -1448,6 +1468,10 @@
                              UNSPEC_SHSUB UNSPEC_UHSUB
                              UNSPEC_SRHSUB UNSPEC_URHSUB])
 
+(define_int_iterator HADD [UNSPEC_SHADD UNSPEC_UHADD])
+
+(define_int_iterator RHADD [UNSPEC_SRHADD UNSPEC_URHADD])
+
 (define_int_iterator DOTPROD [UNSPEC_SDOT UNSPEC_UDOT])
 
 (define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN
@@ -1550,7 +1574,10 @@
                                         UNSPEC_COND_MUL UNSPEC_COND_DIV
                                         UNSPEC_COND_MAX UNSPEC_COND_MIN])
 
-(define_int_iterator SVE_COND_FP_BINARY_REV [UNSPEC_COND_SUB UNSPEC_COND_DIV])
+(define_int_iterator SVE_COND_FP_TERNARY [UNSPEC_COND_FMLA
+                                         UNSPEC_COND_FMLS
+                                         UNSPEC_COND_FNMLA
+                                         UNSPEC_COND_FNMLS])
 
 (define_int_iterator SVE_COND_FP_CMP [UNSPEC_COND_LT UNSPEC_COND_LE
                                      UNSPEC_COND_EQ UNSPEC_COND_NE
@@ -1584,7 +1611,11 @@
                        (UNSPEC_COND_MUL "mul")
                        (UNSPEC_COND_DIV "div")
                        (UNSPEC_COND_MAX "smax")
-                       (UNSPEC_COND_MIN "smin")])
+                       (UNSPEC_COND_MIN "smin")
+                       (UNSPEC_COND_FMLA "fma")
+                       (UNSPEC_COND_FMLS "fnma")
+                       (UNSPEC_COND_FNMLA "fnms")
+                       (UNSPEC_COND_FNMLS "fms")])
 
 (define_int_attr  maxmin_uns [(UNSPEC_UMAXV "umax")
                              (UNSPEC_UMINV "umin")
@@ -1672,8 +1703,10 @@
 
 (define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
                    (UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u")
-                    (UNSPEC_SQSHRN "")  (UNSPEC_UQSHRN "")
-                    (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "")])
+                   (UNSPEC_SQSHRN "")  (UNSPEC_UQSHRN "")
+                   (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "")
+                   (UNSPEC_SHADD "") (UNSPEC_UHADD "u")
+                   (UNSPEC_SRHADD "") (UNSPEC_URHADD "u")])
 
 (define_int_attr addsub [(UNSPEC_SHADD "add")
                         (UNSPEC_UHADD "add")
@@ -1802,6 +1835,23 @@
                            (UNSPEC_COND_MAX "fmaxnm")
                            (UNSPEC_COND_MIN "fminnm")])
 
+(define_int_attr sve_fp_op_rev [(UNSPEC_COND_ADD "fadd")
+                               (UNSPEC_COND_SUB "fsubr")
+                               (UNSPEC_COND_MUL "fmul")
+                               (UNSPEC_COND_DIV "fdivr")
+                               (UNSPEC_COND_MAX "fmaxnm")
+                               (UNSPEC_COND_MIN "fminnm")])
+
+(define_int_attr sve_fmla_op [(UNSPEC_COND_FMLA "fmla")
+                             (UNSPEC_COND_FMLS "fmls")
+                             (UNSPEC_COND_FNMLA "fnmla")
+                             (UNSPEC_COND_FNMLS "fnmls")])
+
+(define_int_attr sve_fmad_op [(UNSPEC_COND_FMLA "fmad")
+                             (UNSPEC_COND_FMLS "fmsb")
+                             (UNSPEC_COND_FNMLA "fnmad")
+                             (UNSPEC_COND_FNMLS "fnmsb")])
+
 (define_int_attr commutative [(UNSPEC_COND_ADD "true")
                              (UNSPEC_COND_SUB "false")
                              (UNSPEC_COND_MUL "true")