/* Subroutines used for code generation on the DEC Alpha.
Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
- 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
+ 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
This file is part of GCC.
/* Specify which cpu to schedule for. */
enum processor_type alpha_cpu;
-static const char * const alpha_cpu_name[] =
+static const char * const alpha_cpu_name[] =
{
"ev4", "ev5", "ev6"
};
{ "21264a", PROCESSOR_EV6, EV6_MASK|MASK_CIX },
{ 0, 0, 0 }
};
-
+
/* Unicos/Mk doesn't have shared libraries. */
if (TARGET_ABI_UNICOSMK && flag_pic)
{
flag_pic = 0;
}
- /* On Unicos/Mk, the native compiler consistently generates /d suffices for
+ /* On Unicos/Mk, the native compiler consistently generates /d suffices for
floating-point instructions. Make that the default for this target. */
if (TARGET_ABI_UNICOSMK)
alpha_fprm = ALPHA_FPRM_DYN;
alpha_tp = ALPHA_TP_PROG;
alpha_fptm = ALPHA_FPTM_N;
- /* We cannot use su and sui qualifiers for conversion instructions on
+ /* We cannot use su and sui qualifiers for conversion instructions on
Unicos/Mk. I'm not sure if this is due to assembler or hardware
limitations. Right now, we issue a warning if -mieee is specified
and then ignore it; eventually, we should either get it right or
&& ISDIGIT ((unsigned char)alpha_mlat_string[1])
&& alpha_mlat_string[2] == '\0')
{
- static int const cache_latency[][4] =
+ static int const cache_latency[][4] =
{
{ 3, 30, -1 }, /* ev4 -- Bcache is a guess */
{ 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
return 1;
}
-/* Return true if OP is valid for a particular TLS relocation.
+/* Return true if OP is valid for a particular TLS relocation.
We are already guaranteed that OP is a CONST. */
int
}
}
+/* The scalar modes supported differs from the default check-what-c-supports
+ version in that sometimes TFmode is available even when long double
+ indicates only DFmode. On unicosmk, we have the situation that HImode
+ doesn't map to any C type, but of course we still support that. */
+
+static bool
+alpha_scalar_mode_supported_p (enum machine_mode mode)
+{
+ switch (mode)
+ {
+ case QImode:
+ case HImode:
+ case SImode:
+ case DImode:
+ case TImode: /* via optabs.c */
+ return true;
+
+ case SFmode:
+ case DFmode:
+ return true;
+
+ case TFmode:
+ return TARGET_HAS_XFLOATING_LIBS;
+
+ default:
+ return false;
+ }
+}
+
+/* Alpha implements a couple of integer vector mode operations when
+ TARGET_MAX is enabled. We do not check TARGET_MAX here, however,
+ which allows the vectorizer to operate on e.g. move instructions,
+ or when expand_vector_operations can do something useful. */
+
+static bool
+alpha_vector_mode_supported_p (enum machine_mode mode)
+{
+ return mode == V8QImode || mode == V4HImode || mode == V2SImode;
+}
+
/* Return 1 if this function can directly return via $26. */
int
tga = get_tls_get_addr ();
dest = gen_reg_rtx (Pmode);
seq = GEN_INT (alpha_next_sequence_number++);
-
+
emit_insn (gen_movdi_er_tlsgd (r16, pic_offset_table_rtx, x, seq));
insn = gen_call_value_osf_tlsgd (r0, tga, seq);
insn = emit_call_insn (insn);
}
}
+/* Primarily this is required for TLS symbols, but given that our move
+ patterns *ought* to be able to handle any symbol at any time, we
+ should never be spilling symbolic operands to the constant pool, ever. */
+
+static bool
+alpha_cannot_force_const_mem (rtx x)
+{
+ enum rtx_code code = GET_CODE (x);
+ return code == SYMBOL_REF || code == LABEL_REF || code == CONST;
+}
+
/* We do not allow indirect calls to be optimized into sibling calls, nor
can we allow a call to a function with a different GP to be optimized
into a sibcall. */
return decl_has_samegp (decl);
}
-/* For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a
- small symbolic operand until after reload. At which point we need
- to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref))
- so that sched2 has the proper dependency information. */
-/*
- {"some_small_symbolic_operand", {SET, PARALLEL, PREFETCH, UNSPEC, \
- UNSPEC_VOLATILE}},
-*/
-
-static int
-some_small_symbolic_operand_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
+int
+some_small_symbolic_operand_int (rtx *px, void *data ATTRIBUTE_UNUSED)
{
rtx x = *px;
return small_symbolic_operand (x, Pmode) != 0;
}
-int
-some_small_symbolic_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
- return for_each_rtx (&x, some_small_symbolic_operand_1, NULL);
-}
-
static int
split_small_symbolic_operand_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
{
return false;
}
-
+
/* Try a machine-dependent way of reloading an illegitimate address
operand. If we find one, push the reload and return the new rtx. */
-
+
rtx
alpha_legitimize_reload_address (rtx x,
enum machine_mode mode ATTRIBUTE_UNUSED,
else
*total = COSTS_N_INSNS (2);
return true;
-
+
case CONST:
case SYMBOL_REF:
case LABEL_REF:
/* Otherwise we do a load from the GOT. */
*total = COSTS_N_INSNS (optimize_size ? 1 : alpha_memory_latency);
return true;
-
+
case PLUS:
case MINUS:
if (float_mode_p)
*pbitnum = GEN_INT ((offset & 3) * 8);
}
-/* Similar, but just get the address. Handle the two reload cases.
+/* Similar, but just get the address. Handle the two reload cases.
Add EXTRA_OFFSET to the address we return. */
rtx
}
/* On the Alpha, all (non-symbolic) constants except zero go into
- a floating-point register via memory. Note that we cannot
+ a floating-point register via memory. Note that we cannot
return anything that is not a subset of CLASS, and that some
symbolic constants cannot be dropped to memory. */
/* Loading and storing HImode or QImode values to and from memory
usually requires a scratch register. The exceptions are loading
QImode and HImode from an aligned address to a general register
- unless byte instructions are permitted.
+ unless byte instructions are permitted.
We also cannot load an unaligned address or a paradoxical SUBREG
- into an FP register.
+ into an FP register.
We also cannot do integral arithmetic into FP regs, as might result
from register elimination into a DImode fp register. */
if (GET_CODE (ref) != MEM)
return;
- /* This is only called from alpha.md, after having had something
+ /* This is only called from alpha.md, after having had something
generated from one of the insn patterns. So if everything is
zero, the pattern is already up-to-date. */
if (!MEM_VOLATILE_P (ref)
{
/* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
but that meant that we can't handle INT_MIN on 32-bit machines
- (like NT/Alpha), because we recurse indefinitely through
+ (like NT/Alpha), because we recurse indefinitely through
emit_move_insn to gen_movdi. So instead, since we know exactly
what we want, create it explicitly. */
bool
alpha_expand_mov (enum machine_mode mode, rtx *operands)
{
+ /* Honor misaligned loads, for those we promised to do so. */
+ if (GET_CODE (operands[1]) == MEM
+ && alpha_vector_mode_supported_p (mode)
+ && MEM_ALIGN (operands[1]) < GET_MODE_ALIGNMENT (mode))
+ {
+ rtx tmp;
+ if (register_operand (operands[0], mode))
+ tmp = operands[0];
+ else
+ tmp = gen_reg_rtx (mode);
+ alpha_expand_unaligned_load (tmp, operands[1], 8, 0, 0);
+ if (tmp == operands[0])
+ return true;
+ operands[1] = tmp;
+ }
+
/* If the output is not a register, the input must be. */
if (GET_CODE (operands[0]) == MEM
&& ! reg_or_0_operand (operands[1], mode))
operands[1] = force_reg (mode, operands[1]);
+ /* Honor misaligned stores, for those we promised to do so. */
+ if (GET_CODE (operands[0]) == MEM
+ && alpha_vector_mode_supported_p (mode)
+ && MEM_ALIGN (operands[0]) < GET_MODE_ALIGNMENT (mode))
+ {
+ alpha_expand_unaligned_store (operands[0], operands[1], 8, 0);
+ return true;
+ }
+
/* Allow legitimize_address to perform some simplifications. */
if (mode == Pmode && symbolic_operand (operands[1], mode))
{
/* When we are not as concerned about non-finite values, and we
are comparing against zero, we can branch directly. */
if (op1 == CONST0_RTX (DFmode))
- cmp_code = NIL, branch_code = code;
+ cmp_code = UNKNOWN, branch_code = code;
else if (op0 == CONST0_RTX (DFmode))
{
/* Undo the swap we probably did just above. */
tem = op0, op0 = op1, op1 = tem;
branch_code = swap_condition (cmp_code);
- cmp_code = NIL;
+ cmp_code = UNKNOWN;
}
}
else
{
/* ??? We mark the branch mode to be CCmode to prevent the
- compare and branch from being combined, since the compare
+ compare and branch from being combined, since the compare
insn follows IEEE rules that the branch does not. */
branch_mode = CCmode;
}
{
/* Whee. Compare and branch against 0 directly. */
if (op1 == const0_rtx)
- cmp_code = NIL, branch_code = code;
+ cmp_code = UNKNOWN, branch_code = code;
/* If the constants doesn't fit into an immediate, but can
be generated by lda/ldah, we adjust the argument and
/* Emit an initial compare instruction, if necessary. */
tem = op0;
- if (cmp_code != NIL)
+ if (cmp_code != UNKNOWN)
{
tem = gen_reg_rtx (cmp_mode);
emit_move_insn (tem, gen_rtx_fmt_ee (cmp_code, cmp_mode, op0, op1));
/* The general case: fold the comparison code to the types of compares
that we have, choosing the branch as necessary. */
- cmp_code = NIL;
+ cmp_code = UNKNOWN;
switch (code)
{
case EQ: case LE: case LT: case LEU: case LTU:
}
/* Emit an initial compare instruction, if necessary. */
- if (cmp_code != NIL)
+ if (cmp_code != UNKNOWN)
{
enum machine_mode mode = fp_p ? DFmode : DImode;
rtx libcall;
};
-static GTY(()) struct xfloating_op xfloating_ops[] =
+static GTY(()) struct xfloating_op xfloating_ops[] =
{
{ PLUS, "_OtsAddX", "OTS$ADD_X", 0 },
{ MINUS, "_OtsSubX", "OTS$SUB_X", 0 },
Note that these functions do not follow normal calling conventions:
TFmode arguments are passed in two integer registers (as opposed to
- indirect); TFmode return values appear in R16+R17.
+ indirect); TFmode return values appear in R16+R17.
FUNC is the function to call.
TARGET is where the output belongs.
out_operands[0] = operands[1];
out_operands[1] = operands[2];
out_operands[2] = GEN_INT (mode);
- alpha_emit_xfloating_libcall (func, operands[0], out_operands, 3,
+ alpha_emit_xfloating_libcall (func, operands[0], out_operands, 3,
gen_rtx_fmt_ee (code, TFmode, operands[1],
operands[2]));
}
abort ();
}
-/* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
- op2 is a register containing the sign bit, operation is the
+/* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
+ op2 is a register containing the sign bit, operation is the
logical operation to be performed. */
void
mema = force_reg (Pmode, mema);
/* AND addresses cannot be in any alias set, since they may implicitly
- alias surrounding code. Ideally we'd have some alias set that
+ alias surrounding code. Ideally we'd have some alias set that
covered all types except those with alignment 8 or higher. */
tmp = change_address (mem, DImode,
- gen_rtx_AND (DImode,
+ gen_rtx_AND (DImode,
plus_constant (mema, ofs),
GEN_INT (-8)));
set_mem_alias_set (tmp, 0);
emit_move_insn (meml, tmp);
tmp = change_address (mem, DImode,
- gen_rtx_AND (DImode,
+ gen_rtx_AND (DImode,
plus_constant (mema, ofs + size - 1),
GEN_INT (-8)));
set_mem_alias_set (tmp, 0);
addr for the target, because addr is marked as a pointer and combine
knows that pointers are always sign-extended 32 bit values. */
addr = expand_binop (DImode, ior_optab, extl, exth, tgt, 1, OPTAB_WIDEN);
- addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (48),
+ addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (48),
addr, 1, OPTAB_WIDEN);
}
else
HOST_WIDE_INT size, HOST_WIDE_INT ofs)
{
rtx dstl, dsth, addr, insl, insh, meml, memh, dsta;
-
+
dstl = gen_reg_rtx (DImode);
dsth = gen_reg_rtx (DImode);
insl = gen_reg_rtx (DImode);
dsta = force_reg (Pmode, dsta);
/* AND addresses cannot be in any alias set, since they may implicitly
- alias surrounding code. Ideally we'd have some alias set that
+ alias surrounding code. Ideally we'd have some alias set that
covered all types except those with alignment 8 or higher. */
meml = change_address (dst, DImode,
- gen_rtx_AND (DImode,
+ gen_rtx_AND (DImode,
plus_constant (dsta, ofs),
GEN_INT (-8)));
set_mem_alias_set (meml, 0);
memh = change_address (dst, DImode,
- gen_rtx_AND (DImode,
+ gen_rtx_AND (DImode,
plus_constant (dsta, ofs + size - 1),
GEN_INT (-8)));
set_mem_alias_set (memh, 0);
{
addr = copy_addr_to_reg (plus_constant (dsta, ofs));
- if (src != const0_rtx)
+ if (src != CONST0_RTX (GET_MODE (src)))
{
emit_insn (gen_insxh (insh, gen_lowpart (DImode, src),
GEN_INT (size*8), addr));
}
}
- if (src != const0_rtx)
+ if (src != CONST0_RTX (GET_MODE (src)))
{
dsth = expand_binop (DImode, ior_optab, insh, dsth, dsth, 0, OPTAB_WIDEN);
dstl = expand_binop (DImode, ior_optab, insl, dstl, dstl, 0, OPTAB_WIDEN);
}
-
+
if (WORDS_BIG_ENDIAN)
{
emit_move_insn (meml, dstl);
if (ofs != 0)
smem = adjust_address (smem, GET_MODE (smem), ofs);
-
+
/* Load up all of the source data. */
for (i = 0; i < words; ++i)
{
emit_move_insn (data_regs[words], tmp);
/* Extract the half-word fragments. Unfortunately DEC decided to make
- extxh with offset zero a noop instead of zeroing the register, so
+ extxh with offset zero a noop instead of zeroing the register, so
we must take care of that edge condition ourselves with cmov. */
sreg = copy_addr_to_reg (smema);
- areg = expand_binop (DImode, and_optab, sreg, GEN_INT (7), NULL,
+ areg = expand_binop (DImode, and_optab, sreg, GEN_INT (7), NULL,
1, OPTAB_WIDEN);
if (WORDS_BIG_ENDIAN)
emit_move_insn (sreg, plus_constant (sreg, 7));
ins_tmps[i] = gen_reg_rtx(DImode);
st_tmp_1 = gen_reg_rtx(DImode);
st_tmp_2 = gen_reg_rtx(DImode);
-
+
if (ofs != 0)
dmem = adjust_address (dmem, GET_MODE (dmem), ofs);
rtx data_regs[2 * MAX_MOVE_WORDS + 16];
rtx tmp;
unsigned int i, words, ofs, nregs = 0;
-
+
if (orig_bytes <= 0)
return 1;
else if (orig_bytes > MAX_MOVE_WORDS * UNITS_PER_WORD)
src_align = 16;
}
}
-
+
tmp = XEXP (orig_dst, 0);
if (GET_CODE (tmp) == REG)
dst_align = MAX (dst_align, REGNO_POINTER_ALIGN (REGNO (tmp)));
else
alpha_expand_unaligned_store_words (data_regs + i, orig_dst,
words, ofs);
-
+
i += words;
ofs += words * 8;
}
rtx orig_dst = operands[0];
rtx tmp;
int i, words, ofs = 0;
-
+
if (orig_bytes <= 0)
return 1;
if (orig_bytes > MAX_MOVE_WORDS * UNITS_PER_WORD)
static struct machine_function *
alpha_init_machine_status (void)
{
- return ((struct machine_function *)
+ return ((struct machine_function *)
ggc_alloc_cleared (sizeof (struct machine_function)));
}
{
case ALPHA_FPRM_NORM:
return NULL;
- case ALPHA_FPRM_MINF:
+ case ALPHA_FPRM_MINF:
return "m";
case ALPHA_FPRM_CHOP:
return "c";
if (GET_CODE (x) != CONST_INT
|| (unsigned HOST_WIDE_INT) INTVAL (x) >= (WORDS_BIG_ENDIAN
? 56
- : 64)
+ : 64)
|| (INTVAL (x) & 7) != 0)
output_operand_lossage ("invalid %%s value");
if (offset)
fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
-
+
addr = XEXP (addr, 0);
if (GET_CODE (addr) == REG)
basereg = REGNO (addr);
code. CXT is an RTX for the static chain value for the function.
The three offset parameters are for the individual template's
- layout. A JMPOFS < 0 indicates that the trampoline does not
+ layout. A JMPOFS < 0 indicates that the trampoline does not
contain instructions at all.
We assume here that a function will be called many more times than
temp = expand_binop (DImode, sub_optab, fnaddr, temp, temp, 1,
OPTAB_WIDEN);
temp = expand_shift (RSHIFT_EXPR, Pmode, temp,
- build_int_cst (NULL_TREE, 2, 0), NULL_RTX, 1);
+ build_int_cst (NULL_TREE, 2), NULL_RTX, 1);
temp = expand_and (SImode, gen_lowpart (SImode, temp),
GEN_INT (0x3fff), 0);
break;
default:
- /* ??? We get called on all sorts of random stuff from
+ /* ??? We get called on all sorts of random stuff from
aggregate_value_p. We can't abort, but it's not clear
what's safe to return. Pretend it's a struct I guess. */
return true;
return gen_rtx_REG (mode, regnum);
}
-/* TCmode complex values are passed by invisible reference. We
+/* TCmode complex values are passed by invisible reference. We
should not split these values. */
static bool
in order to account for the integer arg registers which are counted
in argsize above, but which are not actually stored on the stack.
Must further be careful here about structures straddling the last
- integer argument register; that futzes with pretend_args_size,
+ integer argument register; that futzes with pretend_args_size,
which changes the meaning of AP. */
if (NUM_ARGS <= 6)
t = make_tree (ptr_type_node, virtual_incoming_args_rtx);
t = build (PLUS_EXPR, ptr_type_node, t,
- build_int_cst (NULL_TREE, offset, 0));
+ build_int_cst (NULL_TREE, offset));
t = build (MODIFY_EXPR, TREE_TYPE (base_field), base_field, t);
TREE_SIDE_EFFECTS (t) = 1;
expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
- t = build_int_cst (NULL_TREE, NUM_ARGS * UNITS_PER_WORD, 0);
+ t = build_int_cst (NULL_TREE, NUM_ARGS * UNITS_PER_WORD);
t = build (MODIFY_EXPR, TREE_TYPE (offset_field), offset_field, t);
TREE_SIDE_EFFECTS (t) = 1;
expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
reserved for the registers. */
if (targetm.calls.must_pass_in_stack (TYPE_MODE (type), type))
{
- t = build_int_cst (TREE_TYPE (offset), 6*8, 0);
+ t = build_int_cst (TREE_TYPE (offset), 6*8);
t = build (MODIFY_EXPR, TREE_TYPE (offset), offset,
build (MAX_EXPR, TREE_TYPE (offset), offset, t));
gimplify_and_add (t, pre_p);
{
tree fpaddend, cond, fourtyeight;
- fourtyeight = build_int_cst (TREE_TYPE (addend), 6*8, 0);
+ fourtyeight = build_int_cst (TREE_TYPE (addend), 6*8);
fpaddend = fold (build (MINUS_EXPR, TREE_TYPE (addend),
addend, fourtyeight));
cond = fold (build (LT_EXPR, boolean_type_node, addend, fourtyeight));
break;
imask |= 1UL << regno;
}
-
- /* Glibc likes to use $31 as an unwind stopper for crt0. To
- avoid hackery in unwind-dw2.c, we need to actively store a
- zero in the prologue of _Unwind_RaiseException et al. */
- imask |= 1UL << 31;
}
-
+
/* If any register spilled, then spill the return address also. */
/* ??? This is required by the Digital stack unwind specification
and isn't needed if we're doing Dwarf2 unwinding. */
if (current_function_has_nonlocal_goto)
return 1;
- /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
+ /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
Even if we are a static function, we still need to do this in case
our address is taken and passed to something like qsort. */
#define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
+/* Generates a store with the proper unwind info attached. VALUE is
+ stored at BASE_REG+BASE_OFS. If FRAME_BIAS is nonzero, then BASE_REG
+ contains SP+FRAME_BIAS, and that is the unwind info that should be
+ generated. If FRAME_REG != VALUE, then VALUE is being stored on
+ behalf of FRAME_REG, and FRAME_REG should be present in the unwind. */
+
+static void
+emit_frame_store_1 (rtx value, rtx base_reg, HOST_WIDE_INT frame_bias,
+ HOST_WIDE_INT base_ofs, rtx frame_reg)
+{
+ rtx addr, mem, insn;
+
+ addr = plus_constant (base_reg, base_ofs);
+ mem = gen_rtx_MEM (DImode, addr);
+ set_mem_alias_set (mem, alpha_sr_alias_set);
+
+ insn = emit_move_insn (mem, value);
+ RTX_FRAME_RELATED_P (insn) = 1;
+
+ if (frame_bias || value != frame_reg)
+ {
+ if (frame_bias)
+ {
+ addr = plus_constant (stack_pointer_rtx, frame_bias + base_ofs);
+ mem = gen_rtx_MEM (DImode, addr);
+ }
+
+ REG_NOTES (insn)
+ = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
+ gen_rtx_SET (VOIDmode, mem, frame_reg),
+ REG_NOTES (insn));
+ }
+}
+
+static void
+emit_frame_store (unsigned int regno, rtx base_reg,
+ HOST_WIDE_INT frame_bias, HOST_WIDE_INT base_ofs)
+{
+ rtx reg = gen_rtx_REG (DImode, regno);
+ emit_frame_store_1 (reg, base_reg, frame_bias, base_ofs, reg);
+}
+
/* Write function prologue. */
/* On vms we have two kinds of functions:
HOST_WIDE_INT frame_size;
/* Offset from base reg to register save area. */
HOST_WIDE_INT reg_offset;
- rtx sa_reg, mem;
+ rtx sa_reg;
int i;
sa_size = alpha_sa_size ();
frame_size = get_frame_size ();
if (TARGET_ABI_OPEN_VMS)
- frame_size = ALPHA_ROUND (sa_size
+ frame_size = ALPHA_ROUND (sa_size
+ (alpha_procedure_type == PT_STACK ? 8 : 0)
+ frame_size
+ current_function_pretend_args_size);
4096 bytes (we can probably get away without the latter test) and
every 8192 bytes in between. If the frame size is > 32768, we
do this in a loop. Otherwise, we generate the explicit probe
- instructions.
+ instructions.
Note that we are only allowed to adjust sp once in the prologue. */
/* For NT stack unwind (done by 'reverse execution'), it's
not OK to take the result of a loop, even though the value
is already in ptr, so we reload it via a single operation
- and subtract it to sp.
+ and subtract it to sp.
Yes, that's correct -- we have to reload the whole constant
into a temporary via ldah+lda then subtract from sp. */
if (!TARGET_ABI_UNICOSMK)
{
+ HOST_WIDE_INT sa_bias = 0;
+
/* Cope with very large offsets to the register save area. */
sa_reg = stack_pointer_rtx;
if (reg_offset + sa_size > 0x8000)
{
int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000;
- HOST_WIDE_INT bias;
+ rtx sa_bias_rtx;
if (low + sa_size <= 0x8000)
- bias = reg_offset - low, reg_offset = low;
- else
- bias = reg_offset, reg_offset = 0;
+ sa_bias = reg_offset - low, reg_offset = low;
+ else
+ sa_bias = reg_offset, reg_offset = 0;
sa_reg = gen_rtx_REG (DImode, 24);
- FRP (emit_insn (gen_adddi3 (sa_reg, stack_pointer_rtx,
- GEN_INT (bias))));
+ sa_bias_rtx = GEN_INT (sa_bias);
+
+ if (add_operand (sa_bias_rtx, DImode))
+ emit_insn (gen_adddi3 (sa_reg, stack_pointer_rtx, sa_bias_rtx));
+ else
+ {
+ emit_move_insn (sa_reg, sa_bias_rtx);
+ emit_insn (gen_adddi3 (sa_reg, stack_pointer_rtx, sa_reg));
+ }
}
-
+
/* Save regs in stack order. Beginning with VMS PV. */
if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
- {
- mem = gen_rtx_MEM (DImode, stack_pointer_rtx);
- set_mem_alias_set (mem, alpha_sr_alias_set);
- FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_PV)));
- }
+ emit_frame_store (REG_PV, stack_pointer_rtx, 0, 0);
/* Save register RA next. */
if (imask & (1UL << REG_RA))
{
- mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
- set_mem_alias_set (mem, alpha_sr_alias_set);
- FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_RA)));
+ emit_frame_store (REG_RA, sa_reg, sa_bias, reg_offset);
imask &= ~(1UL << REG_RA);
reg_offset += 8;
}
for (i = 0; i < 31; i++)
if (imask & (1UL << i))
{
- mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
- set_mem_alias_set (mem, alpha_sr_alias_set);
- FRP (emit_move_insn (mem, gen_rtx_REG (DImode, i)));
+ emit_frame_store (i, sa_reg, sa_bias, reg_offset);
reg_offset += 8;
}
- /* Store a zero if requested for unwinding. */
- if (imask & (1UL << 31))
- {
- rtx insn, t;
-
- mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
- set_mem_alias_set (mem, alpha_sr_alias_set);
- insn = emit_move_insn (mem, const0_rtx);
-
- RTX_FRAME_RELATED_P (insn) = 1;
- t = gen_rtx_REG (Pmode, 31);
- t = gen_rtx_SET (VOIDmode, mem, t);
- t = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, t, REG_NOTES (insn));
- REG_NOTES (insn) = t;
-
- reg_offset += 8;
- }
-
for (i = 0; i < 31; i++)
if (fmask & (1UL << i))
{
- mem = gen_rtx_MEM (DFmode, plus_constant (sa_reg, reg_offset));
- set_mem_alias_set (mem, alpha_sr_alias_set);
- FRP (emit_move_insn (mem, gen_rtx_REG (DFmode, i+32)));
+ emit_frame_store (i+32, sa_reg, sa_bias, reg_offset);
reg_offset += 8;
}
}
for (i = 9; i < 15; i++)
if (imask & (1UL << i))
{
- mem = gen_rtx_MEM (DImode, plus_constant(hard_frame_pointer_rtx,
- reg_offset));
- set_mem_alias_set (mem, alpha_sr_alias_set);
- FRP (emit_move_insn (mem, gen_rtx_REG (DImode, i)));
+ emit_frame_store (i, hard_frame_pointer_rtx, 0, reg_offset);
reg_offset -= 8;
}
for (i = 2; i < 10; i++)
if (fmask & (1UL << i))
{
- mem = gen_rtx_MEM (DFmode, plus_constant (hard_frame_pointer_rtx,
- reg_offset));
- set_mem_alias_set (mem, alpha_sr_alias_set);
- FRP (emit_move_insn (mem, gen_rtx_REG (DFmode, i+32)));
+ emit_frame_store (i+32, hard_frame_pointer_rtx, 0, reg_offset);
reg_offset -= 8;
}
}
if (current_function_outgoing_args_size != 0)
{
rtx seq
- = emit_move_insn (stack_pointer_rtx,
+ = emit_move_insn (stack_pointer_rtx,
plus_constant
(hard_frame_pointer_rtx,
- (ALPHA_ROUND
(current_function_outgoing_args_size))));
-
+
/* Only set FRAME_RELATED_P on the stack adjustment we just emitted
if ! frame_pointer_needed. Setting the bit will change the CFA
computation rule to use sp again, which would be wrong if we had
(clobber:BLK (scratch)), but this doesn't work for fp insns. So we
have to prevent all such scheduling with a blockage.
- Linux, on the other hand, never bothered to implement OSF/1's
+ Linux, on the other hand, never bothered to implement OSF/1's
exception handling, and so doesn't care about such things. Anyone
planning to use dwarf2 frame-unwind info can also omit the blockage. */
frame_size = get_frame_size ();
if (TARGET_ABI_OPEN_VMS)
- frame_size = ALPHA_ROUND (sa_size
+ frame_size = ALPHA_ROUND (sa_size
+ (alpha_procedure_type == PT_STACK ? 8 : 0)
+ frame_size
+ current_function_pretend_args_size);
/* Write function epilogue. */
-/* ??? At some point we will want to support full unwind, and so will
+/* ??? At some point we will want to support full unwind, and so will
need to mark the epilogue as well. At the moment, we just confuse
dwarf2out. */
#undef FRP
frame_size = get_frame_size ();
if (TARGET_ABI_OPEN_VMS)
- frame_size = ALPHA_ROUND (sa_size
+ frame_size = ALPHA_ROUND (sa_size
+ (alpha_procedure_type == PT_STACK ? 8 : 0)
+ frame_size
+ current_function_pretend_args_size);
if (low + sa_size <= 0x8000)
bias = reg_offset - low, reg_offset = low;
- else
+ else
bias = reg_offset, reg_offset = 0;
sa_reg = gen_rtx_REG (DImode, 22);
FRP (emit_move_insn (sa_reg, sa_reg_exp));
}
-
+
/* Restore registers in order, excepting a true frame pointer. */
mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
reg_offset += 8;
}
- if (imask & (1UL << 31))
- reg_offset += 8;
-
for (i = 0; i < 31; ++i)
if (fmask & (1UL << i))
{
FRP (emit_move_insn (stack_pointer_rtx,
gen_rtx_PLUS (DImode, sp_adj1, sp_adj2)));
}
- else
+ else
{
if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_REGISTER)
{
case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND:
case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT:
case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS:
- case SQRT: case FFS:
+ case SQRT: case FFS:
summarize_insn (XEXP (x, 0), sum, 0);
break;
shadow.used.fp = 0;
shadow.used.mem = 0;
shadow.defd = shadow.used;
-
+
for (i = get_insns (); i ; i = NEXT_INSN (i))
{
if (GET_CODE (i) == NOTE)
}
}
-/* IN_USE is a mask of the slots currently filled within the insn group.
+/* IN_USE is a mask of the slots currently filled within the insn group.
The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
- the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
+ the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
LEN is, of course, the length of the group in bytes. */
abort();
}
len += 4;
-
+
/* Haifa doesn't do well scheduling branches. */
if (GET_CODE (insn) == JUMP_INSN)
goto next_and_done;
return insn;
}
-/* IN_USE is a mask of the slots currently filled within the insn group.
+/* IN_USE is a mask of the slots currently filled within the insn group.
The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
- the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
+ the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
LEN is, of course, the length of the group in bytes. */
len = get_attr_length (insn);
goto next_and_done;
- /* ??? Most of the places below, we would like to abort, as
- it would indicate an error either in Haifa, or in the
- scheduling description. Unfortunately, Haifa never
+ /* ??? Most of the places below, we would like to abort, as
+ it would indicate an error either in Haifa, or in the
+ scheduling description. Unfortunately, Haifa never
schedules the last instruction of the BB, so we don't
have an accurate TI bit to go off. */
case EV5_E01:
abort();
}
len += 4;
-
+
/* Haifa doesn't do well scheduling branches. */
/* ??? If this is predicted not-taken, slotting continues, except
that no more IBR, FBR, or JSR insns may be slotted. */
else
where = i;
- do
+ do
emit_insn_before ((*next_nop)(&prev_in_use), where);
while (--nop_count);
ofs = 0;
if (TARGET_SUPPORT_ARCH | TARGET_BWX | TARGET_MAX | TARGET_FIX | TARGET_CIX)
fprintf (asm_out_file,
"\t.arch %s\n",
- TARGET_CPU_EV6 ? "ev6"
+ TARGET_CPU_EV6 ? "ev6"
: (TARGET_CPU_EV5
? (TARGET_MAX ? "pca56" : TARGET_BWX ? "ev56" : "ev5")
: "ev4"));
if (!alpha_funcs_tree)
alpha_funcs_tree = splay_tree_new_ggc ((splay_tree_compare_fn)
splay_tree_compare_pointers);
-
+
cfaf = (struct alpha_funcs *) ggc_alloc (sizeof (struct alpha_funcs));
cfaf->links = 0;
al->rkind = KIND_CODEADDR;
else
al->rkind = KIND_LINKAGE;
-
+
if (lflag)
return gen_rtx_MEM (Pmode, plus_constant (al->linkage, 8));
else
the section; 0 if the default should be used. */
static void
-vms_asm_named_section (const char *name, unsigned int flags)
+vms_asm_named_section (const char *name, unsigned int flags,
+ tree decl ATTRIBUTE_UNUSED)
{
fputc ('\n', asm_out_file);
fprintf (asm_out_file, ".section\t%s", name);
/* Record an element in the table of global constructors. SYMBOL is
a SYMBOL_REF of the function to be called; PRIORITY is a number
- between 0 and MAX_INIT_PRIORITY.
+ between 0 and MAX_INIT_PRIORITY.
Differs from default_ctors_section_asm_out_constructor in that the
width of the .ctors entry is always 64 bits, rather than the 32 bits
unicosmk_initial_elimination_offset (int from, int to)
{
int fixed_size;
-
+
fixed_size = alpha_sa_size();
if (fixed_size != 0)
fixed_size += 48;
if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
- return -fixed_size;
+ return -fixed_size;
else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
return 0;
else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
+ ALPHA_ROUND (get_frame_size()));
else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
return (ALPHA_ROUND (fixed_size)
- + ALPHA_ROUND (get_frame_size()
+ + ALPHA_ROUND (get_frame_size()
+ current_function_outgoing_args_size));
else
abort ();
unsigned len = strlen (name);
char *clean_name = alloca (len + 2);
char *ptr = clean_name;
-
+
/* CAM only accepts module names that start with a letter or '$'. We
prefix the module name with a '$' if necessary. */
const char *name;
int len;
- if (!decl)
+ if (!decl)
abort ();
name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
{
char *string;
- /* It is essential that we prefix the section name here because
- otherwise the section names generated for constructors and
+ /* It is essential that we prefix the section name here because
+ otherwise the section names generated for constructors and
destructors confuse collect2. */
string = alloca (len + 6);
the section; 0 if the default should be used. */
static void
-unicosmk_asm_named_section (const char *name, unsigned int flags)
+unicosmk_asm_named_section (const char *name, unsigned int flags,
+ tree decl ATTRIBUTE_UNUSED)
{
const char *kind;
/* Output an alignment directive. We have to use the macro 'gcc@code@align'
in code sections because .align fill unused space with zeroes. */
-
+
void
unicosmk_output_align (FILE *file, int align)
{
unicosmk_defer_case_vector (rtx lab, rtx vec)
{
struct machine_function *machine = cfun->machine;
-
+
vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
machine->addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec,
- machine->addr_list);
+ machine->addr_list);
}
/* Output a case vector. */
static const char *
unicosmk_ssib_name (void)
{
- /* This is ok since CAM won't be able to deal with names longer than that
+ /* This is ok since CAM won't be able to deal with names longer than that
anyway. */
static char name[256];
return name;
}
-/* Set up the dynamic subprogram information block (DSIB) and update the
- frame pointer register ($15) for subroutines which have a frame. If the
+/* Set up the dynamic subprogram information block (DSIB) and update the
+ frame pointer register ($15) for subroutines which have a frame. If the
subroutine doesn't have a frame, simply increment $15. */
static void
unicosmk_text_section (void)
{
static int count = 0;
- sprintf (unicosmk_section_buf, "\t.endp\n\n\t.psect\tgcc@text___%d,code",
+ sprintf (unicosmk_section_buf, "\t.endp\n\n\t.psect\tgcc@text___%d,code",
count++);
return unicosmk_section_buf;
}
unicosmk_data_section (void)
{
static int count = 1;
- sprintf (unicosmk_section_buf, "\t.endp\n\n\t.psect\tgcc@data___%d,data",
+ sprintf (unicosmk_section_buf, "\t.endp\n\n\t.psect\tgcc@data___%d,data",
count++);
return unicosmk_section_buf;
}
len = strlen (user_label_prefix);
for (p = unicosmk_extern_head; p != 0; p = p->next)
{
- /* We have to strip the encoding and possibly remove user_label_prefix
+ /* We have to strip the encoding and possibly remove user_label_prefix
from the identifier in order to handle -fleading-underscore and
explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
real_name = default_strip_name_encoding (p->name);
if (len && p->name[0] == '*'
&& !memcmp (real_name, user_label_prefix, len))
real_name += len;
-
+
name_tree = get_identifier (real_name);
if (! TREE_ASM_WRITTEN (name_tree))
{
}
}
}
-
+
/* Record an extern. */
void
const char *name;
};
-/* List of identifiers which have been replaced by DEX expressions. The DEX
+/* List of identifiers which have been replaced by DEX expressions. The DEX
number is determined by the position in the list. */
-static struct unicosmk_dex *unicosmk_dex_list = NULL;
+static struct unicosmk_dex *unicosmk_dex_list = NULL;
/* The number of elements in the DEX list. */
struct unicosmk_dex *dex;
const char *name;
int i;
-
+
if (GET_CODE (x) != SYMBOL_REF)
return 0;
return i;
--i;
}
-
+
dex = (struct unicosmk_dex *) xmalloc (sizeof (struct unicosmk_dex));
dex->name = name;
dex->next = unicosmk_dex_list;
putc ('\n', file);
--i;
}
-
+
fprintf (file, "\t.dexend\n");
}
/* Output text that to appear at the beginning of an assembler file. */
-static void
+static void
unicosmk_file_start (void)
{
int i;
unicosmk_output_externs (asm_out_file);
- /* Output dex definitions used for functions whose names conflict with
+ /* Output dex definitions used for functions whose names conflict with
register names. */
unicosmk_output_dex (asm_out_file);
#define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall
#undef TARGET_CANNOT_COPY_INSN_P
#define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p
+#undef TARGET_CANNOT_FORCE_CONST_MEM
+#define TARGET_CANNOT_FORCE_CONST_MEM alpha_cannot_force_const_mem
#if TARGET_ABI_OSF
#undef TARGET_ASM_OUTPUT_MI_THUNK
#undef TARGET_GIMPLIFY_VA_ARG_EXPR
#define TARGET_GIMPLIFY_VA_ARG_EXPR alpha_gimplify_va_arg
+#undef TARGET_SCALAR_MODE_SUPPORTED_P
+#define TARGET_SCALAR_MODE_SUPPORTED_P alpha_scalar_mode_supported_p
+#undef TARGET_VECTOR_MODE_SUPPORTED_P
+#define TARGET_VECTOR_MODE_SUPPORTED_P alpha_vector_mode_supported_p
+
#undef TARGET_BUILD_BUILTIN_VA_LIST
#define TARGET_BUILD_BUILTIN_VA_LIST alpha_build_builtin_va_list
+#undef TARGET_VECTORIZE_MISALIGNED_MEM_OK
+#define TARGET_VECTORIZE_MISALIGNED_MEM_OK alpha_vector_mode_supported_p
+
struct gcc_target targetm = TARGET_INITIALIZER;
\f
#include "gt-alpha.h"
-
projects / gcc.git / blobdiff