/* Definitions of target machine for GNU compiler, for DEC Alpha.
Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
- 2000, 2001, 2002, 2004 Free Software Foundation, Inc.
+ 2000, 2001, 2002, 2004, 2005 Free Software Foundation, Inc.
Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
This file is part of GCC.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
+the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+Boston, MA 02110-1301, USA. */
/* Target CPU builtins. */
#define TARGET_CPU_CPP_BUILTINS() \
builtin_define ("__alpha_max__"); \
builtin_assert ("cpu=max"); \
} \
- if (TARGET_CPU_EV6) \
+ if (alpha_cpu == PROCESSOR_EV6) \
{ \
builtin_define ("__alpha_ev6__"); \
builtin_assert ("cpu=ev6"); \
} \
- else if (TARGET_CPU_EV5) \
+ else if (alpha_cpu == PROCESSOR_EV5) \
{ \
builtin_define ("__alpha_ev5__"); \
builtin_assert ("cpu=ev5"); \
};
extern enum processor_type alpha_cpu;
+extern enum processor_type alpha_tune;
enum alpha_trap_precision
{
extern enum alpha_trap_precision alpha_tp;
extern enum alpha_fp_rounding_mode alpha_fprm;
extern enum alpha_fp_trap_mode alpha_fptm;
-extern int alpha_tls_size;
-/* This means that floating-point support exists in the target implementation
- of the Alpha architecture. This is usually the default. */
-#define MASK_FP (1 << 0)
-#define TARGET_FP (target_flags & MASK_FP)
-
-/* This means that floating-point registers are allowed to be used. Note
- that Alpha implementations without FP operations are required to
- provide the FP registers. */
-
-#define MASK_FPREGS (1 << 1)
-#define TARGET_FPREGS (target_flags & MASK_FPREGS)
-
-/* This means that gas is used to process the assembler file. */
-
-#define MASK_GAS (1 << 2)
-#define TARGET_GAS (target_flags & MASK_GAS)
-
-/* This means that we should mark procedures as IEEE conformant. */
-
-#define MASK_IEEE_CONFORMANT (1 << 3)
-#define TARGET_IEEE_CONFORMANT (target_flags & MASK_IEEE_CONFORMANT)
-
-/* This means we should be IEEE-compliant except for inexact. */
-
-#define MASK_IEEE (1 << 4)
-#define TARGET_IEEE (target_flags & MASK_IEEE)
-
-/* This means we should be fully IEEE-compliant. */
-
-#define MASK_IEEE_WITH_INEXACT (1 << 5)
-#define TARGET_IEEE_WITH_INEXACT (target_flags & MASK_IEEE_WITH_INEXACT)
-
-/* This means we must construct all constants rather than emitting
- them as literal data. */
-
-#define MASK_BUILD_CONSTANTS (1 << 6)
-#define TARGET_BUILD_CONSTANTS (target_flags & MASK_BUILD_CONSTANTS)
-
-/* This means we handle floating points in VAX F- (float)
- or G- (double) Format. */
-
-#define MASK_FLOAT_VAX (1 << 7)
-#define TARGET_FLOAT_VAX (target_flags & MASK_FLOAT_VAX)
-
-/* This means that the processor has byte and half word loads and stores
- (the BWX extension). */
-
-#define MASK_BWX (1 << 8)
-#define TARGET_BWX (target_flags & MASK_BWX)
-
-/* This means that the processor has the MAX extension. */
-#define MASK_MAX (1 << 9)
-#define TARGET_MAX (target_flags & MASK_MAX)
-
-/* This means that the processor has the FIX extension. */
-#define MASK_FIX (1 << 10)
-#define TARGET_FIX (target_flags & MASK_FIX)
-
-/* This means that the processor has the CIX extension. */
-#define MASK_CIX (1 << 11)
-#define TARGET_CIX (target_flags & MASK_CIX)
-
-/* This means use !literal style explicit relocations. */
-#define MASK_EXPLICIT_RELOCS (1 << 12)
-#define TARGET_EXPLICIT_RELOCS (target_flags & MASK_EXPLICIT_RELOCS)
-
-/* This means use 16-bit relocations to .sdata/.sbss. */
-#define MASK_SMALL_DATA (1 << 13)
-#define TARGET_SMALL_DATA (target_flags & MASK_SMALL_DATA)
-
-/* This means emit thread pointer loads for kernel not user. */
-#define MASK_TLS_KERNEL (1 << 14)
-#define TARGET_TLS_KERNEL (target_flags & MASK_TLS_KERNEL)
-
-/* This means use direct branches to local functions. */
-#define MASK_SMALL_TEXT (1 << 15)
-#define TARGET_SMALL_TEXT (target_flags & MASK_SMALL_TEXT)
-
-/* This means use IEEE quad-format for long double. Assumes the
- presence of the GEM support library routines. */
-#define MASK_LONG_DOUBLE_128 (1 << 16)
-#define TARGET_LONG_DOUBLE_128 (target_flags & MASK_LONG_DOUBLE_128)
-
-/* This means that the processor is an EV5, EV56, or PCA56.
- Unlike alpha_cpu this is not affected by -mtune= setting. */
-#define MASK_CPU_EV5 (1 << 28)
-#define TARGET_CPU_EV5 (target_flags & MASK_CPU_EV5)
-
-/* Likewise for EV6. */
-#define MASK_CPU_EV6 (1 << 29)
-#define TARGET_CPU_EV6 (target_flags & MASK_CPU_EV6)
-
-/* This means we support the .arch directive in the assembler. Only
- defined in TARGET_CPU_DEFAULT. */
-#define MASK_SUPPORT_ARCH (1 << 30)
-#define TARGET_SUPPORT_ARCH (target_flags & MASK_SUPPORT_ARCH)
+/* Invert the easy way to make options work. */
+#define TARGET_FP (!TARGET_SOFT_FP)
/* These are for target os support and cannot be changed at runtime. */
#define TARGET_ABI_WINDOWS_NT 0
#define HAVE_AS_TLS 0
#endif
-/* Macro to define tables used to set the flags.
- This is a list in braces of pairs in braces,
- each pair being { "NAME", VALUE }
- where VALUE is the bits to set or minus the bits to clear.
- An empty string NAME is used to identify the default VALUE. */
-
-#define TARGET_SWITCHES \
- { {"no-soft-float", MASK_FP, N_("Use hardware fp")}, \
- {"soft-float", - MASK_FP, N_("Do not use hardware fp")}, \
- {"fp-regs", MASK_FPREGS, N_("Use fp registers")}, \
- {"no-fp-regs", - (MASK_FP|MASK_FPREGS), \
- N_("Do not use fp registers")}, \
- {"alpha-as", -MASK_GAS, N_("Do not assume GAS")}, \
- {"gas", MASK_GAS, N_("Assume GAS")}, \
- {"ieee-conformant", MASK_IEEE_CONFORMANT, \
- N_("Request IEEE-conformant math library routines (OSF/1)")}, \
- {"ieee", MASK_IEEE|MASK_IEEE_CONFORMANT, \
- N_("Emit IEEE-conformant code, without inexact exceptions")}, \
- {"ieee-with-inexact", MASK_IEEE_WITH_INEXACT|MASK_IEEE_CONFORMANT, \
- N_("Emit IEEE-conformant code, with inexact exceptions")}, \
- {"build-constants", MASK_BUILD_CONSTANTS, \
- N_("Do not emit complex integer constants to read-only memory")}, \
- {"float-vax", MASK_FLOAT_VAX, N_("Use VAX fp")}, \
- {"float-ieee", -MASK_FLOAT_VAX, N_("Do not use VAX fp")}, \
- {"bwx", MASK_BWX, N_("Emit code for the byte/word ISA extension")}, \
- {"no-bwx", -MASK_BWX, ""}, \
- {"max", MASK_MAX, \
- N_("Emit code for the motion video ISA extension")}, \
- {"no-max", -MASK_MAX, ""}, \
- {"fix", MASK_FIX, \
- N_("Emit code for the fp move and sqrt ISA extension")}, \
- {"no-fix", -MASK_FIX, ""}, \
- {"cix", MASK_CIX, N_("Emit code for the counting ISA extension")}, \
- {"no-cix", -MASK_CIX, ""}, \
- {"explicit-relocs", MASK_EXPLICIT_RELOCS, \
- N_("Emit code using explicit relocation directives")}, \
- {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, ""}, \
- {"small-data", MASK_SMALL_DATA, \
- N_("Emit 16-bit relocations to the small data areas")}, \
- {"large-data", -MASK_SMALL_DATA, \
- N_("Emit 32-bit relocations to the small data areas")}, \
- {"small-text", MASK_SMALL_TEXT, \
- N_("Emit direct branches to local functions")}, \
- {"large-text", -MASK_SMALL_TEXT, ""}, \
- {"tls-kernel", MASK_TLS_KERNEL, \
- N_("Emit rdval instead of rduniq for thread pointer")}, \
- {"long-double-128", MASK_LONG_DOUBLE_128, \
- N_("Use 128-bit long double")}, \
- {"long-double-64", -MASK_LONG_DOUBLE_128, \
- N_("Use 64-bit long double")}, \
- {"", TARGET_DEFAULT | TARGET_CPU_DEFAULT \
- | TARGET_DEFAULT_EXPLICIT_RELOCS, ""} }
-
-#define TARGET_DEFAULT MASK_FP|MASK_FPREGS
+#define TARGET_DEFAULT MASK_FPREGS
#ifndef TARGET_CPU_DEFAULT
#define TARGET_CPU_DEFAULT 0
#ifndef TARGET_DEFAULT_EXPLICIT_RELOCS
#ifdef HAVE_AS_EXPLICIT_RELOCS
#define TARGET_DEFAULT_EXPLICIT_RELOCS MASK_EXPLICIT_RELOCS
+#define TARGET_SUPPORT_ARCH 1
#else
#define TARGET_DEFAULT_EXPLICIT_RELOCS 0
#endif
#endif
-extern const char *alpha_cpu_string; /* For -mcpu= */
-extern const char *alpha_tune_string; /* For -mtune= */
-extern const char *alpha_fprm_string; /* For -mfp-rounding-mode=[n|m|c|d] */
-extern const char *alpha_fptm_string; /* For -mfp-trap-mode=[n|u|su|sui] */
-extern const char *alpha_tp_string; /* For -mtrap-precision=[p|f|i] */
-extern const char *alpha_mlat_string; /* For -mmemory-latency= */
-extern const char *alpha_tls_size_string; /* For -mtls-size= */
-
-#define TARGET_OPTIONS \
-{ \
- {"cpu=", &alpha_cpu_string, \
- N_("Use features of and schedule given CPU"), 0}, \
- {"tune=", &alpha_tune_string, \
- N_("Schedule given CPU"), 0}, \
- {"fp-rounding-mode=", &alpha_fprm_string, \
- N_("Control the generated fp rounding mode"), 0}, \
- {"fp-trap-mode=", &alpha_fptm_string, \
- N_("Control the IEEE trap mode"), 0}, \
- {"trap-precision=", &alpha_tp_string, \
- N_("Control the precision given to fp exceptions"), 0}, \
- {"memory-latency=", &alpha_mlat_string, \
- N_("Tune expected memory latency"), 0}, \
- {"tls-size=", &alpha_tls_size_string, \
- N_("Specify bit size of immediate TLS offsets"), 0}, \
-}
+#ifndef TARGET_SUPPORT_ARCH
+#define TARGET_SUPPORT_ARCH 0
+#endif
/* Support for a compile-time default CPU, et cetera. The rules are:
--with-cpu is ignored if -mcpu is specified.
#define WCHAR_TYPE_SIZE 32
/* Define this macro if it is advisable to hold scalars in registers
- in a wider mode than that declared by the program. In such cases,
+ in a wider mode than that declared by the program. In such cases,
the value is constrained to be within the bounds of the declared
type, but kept valid in the wider mode. The signedness of the
extension may differ from that of the type.
- For Alpha, we always store objects in a full register. 32-bit objects
- are always sign-extended, but smaller objects retain their signedness. */
+ For Alpha, we always store objects in a full register. 32-bit integers
+ are always sign-extended, but smaller objects retain their signedness.
-#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
- if (GET_MODE_CLASS (MODE) == MODE_INT \
- && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
- { \
- if ((MODE) == SImode) \
- (UNSIGNEDP) = 0; \
- (MODE) = DImode; \
+ Note that small vector types can get mapped onto integer modes at the
+ whim of not appearing in alpha-modes.def. We never promoted these
+ values before; don't do so now that we've trimmed the set of modes to
+ those actually implemented in the backend. */
+
+#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
+ if (GET_MODE_CLASS (MODE) == MODE_INT \
+ && (TYPE == NULL || TREE_CODE (TYPE) != VECTOR_TYPE) \
+ && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
+ { \
+ if ((MODE) == SImode) \
+ (UNSIGNEDP) = 0; \
+ (MODE) = DImode; \
}
/* Define this if most significant bit is lowest numbered
On the Alpha, they trap. */
#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
-\f
+
/* Standard register usage. */
/* Number of actual hardware registers.
We define all 32 integer registers, even though $31 is always zero,
and all 32 floating-point registers, even though $f31 is also
always zero. We do not bother defining the FP status register and
- there are no other registers.
+ there are no other registers.
Since $31 is always zero, we will use register number 31 as the
argument pointer. It will never appear in the generated code
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
((REGNO) >= 32 && (REGNO) <= 62 \
? (MODE) == SFmode || (MODE) == DFmode || (MODE) == DImode \
+ || (MODE) == SCmode || (MODE) == DCmode \
: 1)
-/* Value is 1 if MODE is a supported vector mode. */
-
-#define VECTOR_MODE_SUPPORTED_P(MODE) \
- (TARGET_MAX \
- && ((MODE) == V8QImode || (MODE) == V4HImode || (MODE) == V2SImode))
-
/* A C expression that is nonzero if a value of mode
MODE1 is accessible in mode MODE2 without copying.
/* Base register for access to local variables of function. */
#define FRAME_POINTER_REGNUM 63
-/* Register in which static-chain is passed to a function.
+/* Register in which static-chain is passed to a function.
For the Alpha, this is based on an example; the calling sequence
doesn't seem to specify this. */
For any two classes, it is very desirable that there be another
class that represents their union. */
-
+
enum reg_class {
NO_REGS, R0_REG, R24_REG, R25_REG, R27_REG,
GENERAL_REGS, FLOAT_REGS, ALL_REGS,
`R' is a SYMBOL_REF that has SYMBOL_REF_FLAG set or is the current
function.
- 'S' is a 6-bit constant (valid for a shift insn).
+ 'S' is a 6-bit constant (valid for a shift insn).
'T' is a HIGH.
? reg_classes_intersect_p (FLOAT_REGS, CLASS) : 0)
/* Define the cost of moving between registers of various classes. Moving
- between FLOAT_REGS and anything else except float regs is expensive.
+ between FLOAT_REGS and anything else except float regs is expensive.
In fact, we make it quite expensive because we really don't want to
do these moves unless it is clearly worth it. Optimizations may
reduce the impact of not being able to allocate a pseudo to a
hard register. */
-#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
- (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) \
- ? 2 \
- : TARGET_FIX ? 3 : 4+2*alpha_memory_latency)
+#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
+ (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) ? 2 \
+ : TARGET_FIX ? ((CLASS1) == FLOAT_REGS ? 6 : 8) \
+ : 4+2*alpha_memory_latency)
/* A C expressions returning the cost of moving data of MODE from a register to
or from memory.
makes the stack pointer a smaller address. */
#define STACK_GROWS_DOWNWARD
-/* Define this if the nominal address of the stack frame
+/* Define this to non-zero if the nominal address of the stack frame
is at the high-address end of the local variables;
that is, each additional local variable allocated
goes at a more negative offset in the frame. */
-/* #define FRAME_GROWS_DOWNWARD */
+/* #define FRAME_GROWS_DOWNWARD 0 */
/* Offset within stack frame to start allocating local variables at.
If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
function_arg((CUM), (MODE), (TYPE), (NAMED))
-/* For an arg passed partly in registers and partly in memory,
- this is the number of registers used.
- For args passed entirely in registers or entirely in memory, zero. */
-
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
-((CUM) < 6 && 6 < (CUM) + ALPHA_ARG_SIZE (MODE, TYPE, NAMED) \
- ? 6 - (CUM) : 0)
-
/* Try to output insns to set TARGET equal to the constant C if it can be
done in less than N insns. Do all computations in MODE. Returns the place
where the output has been placed if it can be done and the insns have been
#define ASM_DECLARE_FUNCTION_SIZE(FILE,NAME,DECL) \
alpha_end_function(FILE,NAME,DECL)
-
+
/* Output any profiling code before the prologue. */
#define PROFILE_BEFORE_PROLOGUE 1
of a trampoline, leaving space for the variable parts.
The trampoline should set the static chain pointer to value placed
- into the trampoline and should branch to the specified routine.
+ into the trampoline and should branch to the specified routine.
Note that $27 has been set to the address of the trampoline, so we can
use it for addressability of the two data items. */
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 26)
#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (26)
#define DWARF_ALT_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (64)
+#define DWARF_ZERO_REG 31
/* Describe how we implement __builtin_eh_return. */
#define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 16 : INVALID_REGNUM)
/* Include all constant integers and constant doubles, but not
floating-point, except for floating-point zero. */
-#define LEGITIMATE_CONSTANT_P(X) \
- (GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \
- || (X) == CONST0_RTX (GET_MODE (X)))
+#define LEGITIMATE_CONSTANT_P alpha_legitimate_constant_p
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
and check its validity for a certain class.
/* Try a machine-dependent way of reloading an illegitimate address
operand. If we find one, push the reload and jump to WIN. This
macro is used in only one place: `find_reloads_address' in reload.c. */
-
+
#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_L,WIN) \
do { \
rtx new_x = alpha_legitimize_reload_address (X, MODE, OPNUM, TYPE, IND_L); \
/* Nonzero if access to memory by bytes is no faster than for words.
Also nonzero if doing byte operations (specifically shifts) in registers
- is undesirable.
+ is undesirable.
On the Alpha, we want to not use the byte operation and instead use
masking operations to access fields; these will save instructions. */
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
be the code that says which one of the two operations is implicitly
- done, NIL if none. */
+ done, UNKNOWN if none. */
#define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
/* Define if loading short immediate values into registers sign extends. */
/* This is how to output an element of a case-vector that is absolute.
(Alpha does not use such vectors, but we must define this macro anyway.) */
-#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) abort ()
+#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) gcc_unreachable ()
/* This is how to output an element of a case-vector that is relative. */
((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) + alpha_auto_offset)
#define DEBUGGER_ARG_OFFSET(OFFSET, X) (OFFSET + alpha_arg_offset)
+/* mips-tfile doesn't understand .stabd directives. */
+#define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
+ dbxout_begin_stabn_sline (LINE); \
+ dbxout_stab_value_internal_label ("LM", &COUNTER); \
+} while (0)
-#define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) \
- alpha_output_lineno (STREAM, LINE)
+/* We want to use MIPS-style .loc directives for SDB line numbers. */
+extern int num_source_filenames;
+#define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
+ fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
#define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
alpha_output_filename (STREAM, NAME)
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