;; Machine description for DEC Alpha for GNU C compiler
;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-;; 2000, 2001, 2002 Free Software Foundation, Inc.
+;; 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
;;
;; This file is part of GNU CC.
(UNSPEC_AMASK 24)
(UNSPEC_IMPLVER 25)
(UNSPEC_PERR 26)
+ (UNSPEC_CTLZ 27)
+ (UNSPEC_CTPOP 28)
])
;; UNSPEC_VOLATILE:
;; separately.
(define_attr "type"
- "ild,fld,ldsym,ist,fst,ibr,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,\
+ "ild,fld,ldsym,ist,fst,ibr,callpal,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,\
fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
(const_string "iadd"))
;; The ROUND_SUFFIX attribute marks which instructions require a
;; rounding-mode suffix. The value NONE indicates no suffix,
-;; the value NORMAL indicates a suffix controled by alpha_fprm.
+;; the value NORMAL indicates a suffix controlled by alpha_fprm.
(define_attr "round_suffix" "none,normal,c"
(const_string "none"))
;; V_SV_SVI accepts /v, /sv and /svi (cvttq only)
;; U_SU_SUI accepts /u, /su and /sui (most fp instructions)
;;
-;; The actual suffix emitted is controled by alpha_fptm.
+;; The actual suffix emitted is controlled by alpha_fptm.
(define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
(const_string "none"))
(define_attr "length" ""
(const_int 4))
+
+;; The USEGP attribute marks instructions that have relocations that use
+;; the GP.
+
+(define_attr "usegp" "no,yes"
+ (cond [(eq_attr "type" "ldsym,jsr")
+ (const_string "yes")
+ (eq_attr "type" "ild,fld,ist,fst")
+ (symbol_ref "alpha_find_lo_sum_using_gp(insn)")
+ ]
+ (const_string "no")))
+
\f
;; Include scheduling descriptions.
(match_operand:SI 1 "nonimmediate_operand" "r,m,*f,m")))]
"! TARGET_FIX"
"@
- addl %1,$31,%0
+ addl $31,%1,%0
ldl %0,%1
cvtlq %1,%0
lds %0,%1\;cvtlq %0,%0"
(match_operand:SI 1 "nonimmediate_operand" "r,m,*f,*f,m")))]
"TARGET_FIX"
"@
- addl %1,$31,%0
+ addl $31,%1,%0
ldl %0,%1
ftois %1,%0
cvtlq %1,%0
[(set (match_operand:DI 0 "register_operand" "=r")
(plus:DI (match_operand:DI 1 "register_operand" "r")
(high:DI (match_operand:DI 2 "local_symbolic_operand" ""))))]
- "TARGET_EXPLICIT_RELOCS"
- "ldah %0,%2(%1)\t\t!gprelhigh")
+ "TARGET_EXPLICIT_RELOCS && reload_completed"
+ "ldah %0,%2(%1)\t\t!gprelhigh"
+ [(set_attr "usegp" "yes")])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
"mulqv %r1,%2,%0"
[(set_attr "type" "imul")])
-(define_insn "umuldi3_highpart"
+(define_expand "umuldi3_highpart"
+ [(set (match_operand:DI 0 "register_operand" "")
+ (truncate:DI
+ (lshiftrt:TI
+ (mult:TI (zero_extend:TI
+ (match_operand:DI 1 "register_operand" ""))
+ (match_operand:DI 2 "reg_or_8bit_operand" ""))
+ (const_int 64))))]
+ ""
+{
+ if (REG_P (operands[2]))
+ operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]);
+})
+
+(define_insn "*umuldi3_highpart_reg"
[(set (match_operand:DI 0 "register_operand" "=r")
(truncate:DI
(lshiftrt:TI
(mult:TI (zero_extend:TI
- (match_operand:DI 1 "reg_or_0_operand" "%rJ"))
+ (match_operand:DI 1 "register_operand" "r"))
(zero_extend:TI
- (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
+ (match_operand:DI 2 "register_operand" "r")))
(const_int 64))))]
""
- "umulh %r1,%2,%0"
+ "umulh %1,%2,%0"
[(set_attr "type" "imul")
(set_attr "opsize" "udi")])
"eqv %r1,%2,%0"
[(set_attr "type" "ilog")])
\f
-;; Handle the FFS insn iff we support CIX.
+;; Handle FFS and related insns iff we support CIX.
(define_expand "ffsdi2"
[(set (match_dup 2)
; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just
; reuse the existing type name.
[(set_attr "type" "mvi")])
+
+(define_insn "clzdi2"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (clz:DI (match_operand:DI 1 "register_operand" "r")))]
+ "TARGET_CIX"
+ "ctlz %1,%0"
+ [(set_attr "type" "mvi")])
+
+(define_insn "ctzdi2"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (ctz:DI (match_operand:DI 1 "register_operand" "r")))]
+ "TARGET_CIX"
+ "cttz %1,%0"
+ [(set_attr "type" "mvi")])
+
+(define_insn "popcountdi2"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (popcount:DI (match_operand:DI 1 "register_operand" "r")))]
+ "TARGET_CIX"
+ "ctpop %1,%0"
+ [(set_attr "type" "mvi")])
\f
;; Next come the shifts and the various extract and insert operations.
"ext%M2l %r1,%3,%0"
[(set_attr "type" "shift")])
-;; Combine has some strange notion of preserving existing undefined behaviour
+;; Combine has some strange notion of preserving existing undefined behavior
;; in shifts larger than a word size. So capture these patterns that it
;; should have turned into zero_extracts.
(define_expand "abstf2"
[(parallel [(set (match_operand:TF 0 "register_operand" "")
- (neg:TF (match_operand:TF 1 "reg_or_0_operand" "")))
+ (abs:TF (match_operand:TF 1 "reg_or_0_operand" "")))
(use (match_dup 2))])]
"TARGET_HAS_XFLOATING_LIBS"
{
[(set (match_operand:DF 0 "register_operand" "=f")
(sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
"TARGET_FP && TARGET_FIX"
- "sqrt%-%/ %1,%0"
+ "sqrt%-%/ %R1,%0"
[(set_attr "type" "fsqrt")
(set_attr "trap" "yes")
(set_attr "round_suffix" "normal")
(match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
"TARGET_MAX"
"maxuw4 %r1,%2,%0"
- [(set_attr "type" "shift")])
+ [(set_attr "type" "mvi")])
(define_expand "smaxdi3"
[(set (match_dup 3)
emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
if (GET_CODE (operands[0]) == SYMBOL_REF)
{
- rtx linkage = alpha_need_linkage (XSTR (operands[0], 0), 0);
+ alpha_need_linkage (XSTR (operands[0], 0), 0);
- emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
- operands[2]
- = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
+ operands[2] = const0_rtx;
}
else
{
emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
if (GET_CODE (operands[1]) == SYMBOL_REF)
{
- rtx linkage = alpha_need_linkage (XSTR (operands[1], 0), 0);
+ alpha_need_linkage (XSTR (operands[1], 0), 0);
- emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
- operands[3]
- = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
+ operands[3] = const0_rtx;
}
else
{
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
"@
jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
- bsr $26,$%0..ng
+ bsr $26,%0\t\t!samegp
ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
[(set_attr "type" "jsr")
(set_attr "length" "12,*,16")])
(use (reg:DI 29))
(clobber (reg:DI 26))])]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
- && ! current_file_function_operand (operands[0], Pmode)
+ && ! samegp_function_operand (operands[0], Pmode)
&& peep2_regno_dead_p (1, 29)"
[(parallel [(call (mem:DI (match_dup 2))
(match_dup 1))
(use (reg:DI 29))
(clobber (reg:DI 26))])]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
- && ! current_file_function_operand (operands[0], Pmode)
+ && ! samegp_function_operand (operands[0], Pmode)
&& ! peep2_regno_dead_p (1, 29)"
[(parallel [(call (mem:DI (match_dup 2))
(match_dup 1))
"jsr $26,(%0),%2%J3"
[(set_attr "type" "jsr")])
+;; We output a nop after noreturn calls at the very end of the function to
+;; ensure that the return address always remains in the caller's code range,
+;; as not doing so might confuse unwinding engines.
+;;
+;; The potential change in insn length is not reflected in the length
+;; attributes at this stage. Since the extra space is only actually added at
+;; the very end of the compilation process (via final/print_operand), it
+;; really seems harmless and not worth the trouble of some extra computation
+;; cost and complexity.
+
(define_insn "*call_osf_1_noreturn"
[(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
(match_operand 1 "" ""))
"! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
&& find_reg_note (insn, REG_NORETURN, NULL_RTX)"
"@
- jsr $26,($27),0
- bsr $26,$%0..ng
- jsr $26,%0"
+ jsr $26,($27),0%+
+ bsr $26,$%0..ng%+
+ jsr $26,%0%+"
[(set_attr "type" "jsr")
(set_attr "length" "*,*,8")])
(unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
"@
- br $31,$%0..ng
+ br $31,%0\t\t!samegp
ldq $27,%0($29)\t\t!literal!%#\;jmp $31,($27),%0\t\t!lituse_jsr!%#"
[(set_attr "type" "jsr")
(set_attr "length" "*,8")])
[(set_attr "type" "jsr")
(set_attr "length" "*,*,12")])
+; GAS relies on the order and position of instructions output below in order
+; to generate relocs for VMS link to potentially optimize the call.
+; Please do not molest.
(define_insn "*call_vms_1"
[(call (mem:DI (match_operand:DI 0 "call_operand" "r,s"))
(match_operand 1 "" ""))
- (use (match_operand:DI 2 "nonimmediate_operand" "r,m"))
+ (use (match_operand:DI 2 "nonmemory_operand" "r,n"))
(use (reg:DI 25))
(use (reg:DI 26))
(clobber (reg:DI 27))]
"TARGET_ABI_OPEN_VMS"
- "@
- mov %2,$27\;jsr $26,0\;ldq $27,0($29)
- ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"
+{
+ switch (which_alternative)
+ {
+ case 0:
+ return "mov %2,$27\;jsr $26,0\;ldq $27,0($29)";
+ case 1:
+ operands [2] = alpha_use_linkage (operands [0], cfun->decl, 1, 0);
+ operands [3] = alpha_use_linkage (operands [0], cfun->decl, 0, 0);
+ return "ldq $26,%3\;ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)";
+ default:
+ abort();
+ }
+}
[(set_attr "type" "jsr")
(set_attr "length" "12,16")])
[(unspec_volatile [(const_int 0)] UNSPECV_IMB)]
""
"call_pal 0x86"
- [(set_attr "type" "ibr")])
+ [(set_attr "type" "callpal")])
;; BUGCHK is documented common to OSF/1 and VMS PALcode.
;; NT does not document anything at 0x81 -- presumably it would generate
[(trap_if (const_int 1) (const_int 0))]
"!TARGET_ABI_WINDOWS_NT"
"call_pal 0x81"
- [(set_attr "type" "ibr")])
+ [(set_attr "type" "callpal")])
;; For userland, we load the thread pointer from the TCB.
;; For the kernel, we load the per-cpu private value.
else
return "call_pal 0x9e";
}
- [(set_attr "type" "ibr")])
+ [(set_attr "type" "callpal")])
;; For completeness, and possibly a __builtin function, here's how to
;; set the thread pointer. Since we don't describe enough of this
else
return "call_pal 0x9f";
}
- [(set_attr "type" "ibr")])
+ [(set_attr "type" "callpal")])
\f
;; Finally, we have the basic data motion insns. The byte and word insns
;; are done via define_expand. Start with the floating-point insns, since
;; Split the load of an address into a four-insn sequence on Unicos/Mk.
;; Always generate a REG_EQUAL note for the last instruction to facilitate
-;; optimisations. If the symbolic operand is a label_ref, generate REG_LABEL
+;; optimizations. If the symbolic operand is a label_ref, generate REG_LABEL
;; notes and update LABEL_NUSES because this is not done automatically.
;; Labels may be incorrectly deleted if we don't do this.
;;
return "lda %0,%2(%1)\t\t!gprel";
else
return "lda %0,%2(%1)\t\t!gprellow";
-})
+}
+ [(set_attr "usegp" "yes")])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
[(match_dup 0)]
"operands[0] = split_small_symbolic_operand (operands[0]);")
+;; Accepts any symbolic, not just global, since function calls that
+;; don't go via bsr still use !literal in hopes of linker relaxation.
(define_insn "movdi_er_high_g"
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "register_operand" "r")
- (match_operand:DI 2 "global_symbolic_operand" "")
+ (match_operand:DI 2 "symbolic_operand" "")
(match_operand 3 "const_int_operand" "")]
UNSPEC_LITERAL))]
"TARGET_EXPLICIT_RELOCS"
UNSPEC_DTPREL))]
"HAVE_AS_TLS"
"ldq %0,%2(%1)\t\t!gotdtprel"
- [(set_attr "type" "ild")])
+ [(set_attr "type" "ild")
+ (set_attr "usegp" "yes")])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
UNSPEC_TPREL))]
"HAVE_AS_TLS"
"ldq %0,%2(%1)\t\t!gottprel"
- [(set_attr "type" "ild")])
+ [(set_attr "type" "ild")
+ (set_attr "usegp" "yes")])
(define_split
[(set (match_operand:DI 0 "register_operand" "")
fmov %R1,%0
ldt %0,%1
stt %R1,%0"
- [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
+ [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")
+ (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*")])
;; The 'U' constraint matches symbolic operands on Unicos/Mk. Those should
;; have been split up by the rules above but we shouldn't reject the
stt %R1,%0
ftoit %1,%0
itoft %1,%0"
- [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
+ [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")
+ (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*,*")])
(define_insn "*movdi_fix"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f")
FAIL;
})
+(define_expand "movstrdi"
+ [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
+ (match_operand:BLK 1 "memory_operand" ""))
+ (use (match_operand:DI 2 "immediate_operand" ""))
+ (use (match_operand:DI 3 "immediate_operand" ""))
+ (use (match_dup 4))
+ (clobber (reg:DI 25))
+ (clobber (reg:DI 16))
+ (clobber (reg:DI 17))
+ (clobber (reg:DI 18))
+ (clobber (reg:DI 19))
+ (clobber (reg:DI 20))
+ (clobber (reg:DI 26))
+ (clobber (reg:DI 27))])]
+ "TARGET_ABI_OPEN_VMS"
+{
+ operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$MOVE");
+ alpha_need_linkage (XSTR (operands[4], 0), 0);
+})
+
+(define_insn "*movstrdi_1"
+ [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
+ (match_operand:BLK 1 "memory_operand" "m,m"))
+ (use (match_operand:DI 2 "nonmemory_operand" "r,i"))
+ (use (match_operand:DI 3 "immediate_operand" ""))
+ (use (match_operand:DI 4 "call_operand" "i,i"))
+ (clobber (reg:DI 25))
+ (clobber (reg:DI 16))
+ (clobber (reg:DI 17))
+ (clobber (reg:DI 18))
+ (clobber (reg:DI 19))
+ (clobber (reg:DI 20))
+ (clobber (reg:DI 26))
+ (clobber (reg:DI 27))]
+ "TARGET_ABI_OPEN_VMS"
+{
+ operands [5] = alpha_use_linkage (operands [4], cfun->decl, 0, 1);
+ switch (which_alternative)
+ {
+ case 0:
+ return "lda $16,%0\;bis $31,%2,$17\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
+ case 1:
+ return "lda $16,%0\;lda $17,%2($31)\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
+ default:
+ abort();
+ }
+}
+ [(set_attr "type" "multi")
+ (set_attr "length" "28")])
+
(define_expand "clrstrqi"
[(parallel [(set (match_operand:BLK 0 "memory_operand" "")
(const_int 0))
else
FAIL;
})
+
+(define_expand "clrstrdi"
+ [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
+ (const_int 0))
+ (use (match_operand:DI 1 "immediate_operand" ""))
+ (use (match_operand:DI 2 "immediate_operand" ""))
+ (use (match_dup 3))
+ (clobber (reg:DI 25))
+ (clobber (reg:DI 16))
+ (clobber (reg:DI 17))
+ (clobber (reg:DI 26))
+ (clobber (reg:DI 27))])]
+ "TARGET_ABI_OPEN_VMS"
+{
+ operands[3] = gen_rtx_SYMBOL_REF (Pmode, "OTS$ZERO");
+ alpha_need_linkage (XSTR (operands[3], 0), 0);
+})
+
+(define_insn "*clrstrdi_1"
+ [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
+ (const_int 0))
+ (use (match_operand:DI 1 "nonmemory_operand" "r,i"))
+ (use (match_operand:DI 2 "immediate_operand" ""))
+ (use (match_operand:DI 3 "call_operand" "i,i"))
+ (clobber (reg:DI 25))
+ (clobber (reg:DI 16))
+ (clobber (reg:DI 17))
+ (clobber (reg:DI 26))
+ (clobber (reg:DI 27))]
+ "TARGET_ABI_OPEN_VMS"
+{
+ operands [4] = alpha_use_linkage (operands [3], cfun->decl, 0, 1);
+ switch (which_alternative)
+ {
+ case 0:
+ return "lda $16,%0\;bis $31,%1,$17\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
+ case 1:
+ return "lda $16,%0\;lda $17,%1($31)\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
+ default:
+ abort();
+ }
+}
+ [(set_attr "type" "multi")
+ (set_attr "length" "24")])
+
\f
;; Subroutine of stack space allocation. Perform a stack probe.
(define_expand "probe_stack"
""
{
operands[2] = gen_label_rtx ();
- ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
+ (*targetm.asm_out.internal_label) (asm_out_file, "L",
CODE_LABEL_NUMBER (operands[2]));
return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2";
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
&& prev_nonnote_insn (insn) == operands[0]"
[(const_int 0)]
- "DONE;")
+ "
+{
+ emit_note (NOTE_INSN_DELETED);
+ DONE;
+}")
(define_insn "*builtin_setjmp_receiver_1"
[(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
and leave the LRU eviction counter pointing to that block. */
static const char * const alt[2][2] = {
{
- "lds $f31,%a0", /* read, evict next */
+ "ldq $31,%a0", /* read, evict next */
"ldl $31,%a0", /* read, evict last */
},
{
"ldt $f31,%a0", /* write, evict next */
- "ldq $31,%a0", /* write, evict last */
+ "lds $f31,%a0", /* write, evict last */
}
};
;; actually differentiate between ILOG and ICMP in the schedule.
[(set_attr "type" "icmp")])
+(define_expand "builtin_extbl"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_extxl_be;
+ else
+ gen = gen_extxl_le;
+ emit_insn ((*gen) (operands[0], operands[1], GEN_INT (8), operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_extwl"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_extxl_be;
+ else
+ gen = gen_extxl_le;
+ emit_insn ((*gen) (operands[0], operands[1], GEN_INT (16), operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_extll"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_extxl_be;
+ else
+ gen = gen_extxl_le;
+ emit_insn ((*gen) (operands[0], operands[1], GEN_INT (32), operands[2]));
+ DONE;
+})
+
(define_expand "builtin_extql"
[(match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "reg_or_0_operand" "")
DONE;
})
+(define_expand "builtin_extwh"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx));
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_extwh_be;
+ else
+ gen = gen_extwh_le;
+ emit_insn ((*gen) (operands[0], operands[1], operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_extlh"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx));
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_extlh_be;
+ else
+ gen = gen_extlh_le;
+ emit_insn ((*gen) (operands[0], operands[1], operands[2]));
+ DONE;
+})
+
(define_expand "builtin_extqh"
[(match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "reg_or_0_operand" "")
DONE;
})
+(define_expand "builtin_insbl"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx));
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_insbl_be;
+ else
+ gen = gen_insbl_le;
+ operands[1] = gen_lowpart (QImode, operands[1]);
+ emit_insn ((*gen) (operands[0], operands[1], operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_inswl"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx));
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_inswl_be;
+ else
+ gen = gen_inswl_le;
+ operands[1] = gen_lowpart (HImode, operands[1]);
+ emit_insn ((*gen) (operands[0], operands[1], operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_insll"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx));
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_insll_be;
+ else
+ gen = gen_insll_le;
+ operands[1] = gen_lowpart (SImode, operands[1]);
+ emit_insn ((*gen) (operands[0], operands[1], operands[2]));
+ emit_insn ((*gen) (operands[0], operands[1], operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_insql"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx));
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_insql_be;
+ else
+ gen = gen_insql_le;
+ emit_insn ((*gen) (operands[0], operands[1], operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_inswh"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "register_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_inslh"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "register_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_insqh"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "register_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_mskbl"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
+ rtx mask;
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_mskxl_be;
+ else
+ gen = gen_mskxl_le;
+ mask = GEN_INT (0xff);
+ emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_mskwl"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
+ rtx mask;
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_mskxl_be;
+ else
+ gen = gen_mskxl_le;
+ mask = GEN_INT (0xffff);
+ emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_mskll"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
+ rtx mask;
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_mskxl_be;
+ else
+ gen = gen_mskxl_le;
+ mask = immed_double_const (0xffffffff, 0, DImode);
+ emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_mskql"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "reg_or_0_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
+ rtx mask;
+ if (WORDS_BIG_ENDIAN)
+ gen = gen_mskxl_be;
+ else
+ gen = gen_mskxl_le;
+ mask = constm1_rtx;
+ emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_mskwh"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "register_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_msklh"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "register_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2]));
+ DONE;
+})
+
+(define_expand "builtin_mskqh"
+ [(match_operand:DI 0 "register_operand" "")
+ (match_operand:DI 1 "register_operand" "")
+ (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ ""
+{
+ emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2]));
+ DONE;
+})
+
(define_expand "builtin_zap"
[(set (match_operand:DI 0 "register_operand" "")
(and:DI (unspec:DI
{
rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
- if (operands[1] == const0_rtx)
+ if (mask == const0_rtx)
{
emit_move_insn (operands[0], const0_rtx);
DONE;
}
- if (operands[1] == constm1_rtx)
+ if (mask == constm1_rtx)
{
emit_move_insn (operands[0], operands[1]);
DONE;
(define_expand "builtin_zapnot"
[(set (match_operand:DI 0 "register_operand" "")
(and:DI (unspec:DI
- [(not:QI (match_operand:QI 2 "reg_or_const_int_operand" ""))]
+ [(not:QI (match_operand:DI 2 "reg_or_const_int_operand" ""))]
UNSPEC_ZAP)
(match_operand:DI 1 "reg_or_const_int_operand" "")))]
""
{
rtx mask = alpha_expand_zap_mask (~ INTVAL (operands[2]));
- if (operands[1] == const0_rtx)
+ if (mask == const0_rtx)
{
emit_move_insn (operands[0], const0_rtx);
DONE;
}
- if (operands[1] == constm1_rtx)
+ if (mask == constm1_rtx)
{
emit_move_insn (operands[0], operands[1]);
DONE;
})
(define_insn "*pkwb"
- [(set (match_operand:V8QI 0 "register_operand" "")
+ [(set (match_operand:V8QI 0 "register_operand" "=r")
(vec_concat:V8QI
- (truncate:V4QI (match_operand:V4HI 1 "register_operand" ""))
+ (truncate:V4QI (match_operand:V4HI 1 "register_operand" "r"))
(match_operand:V4QI 2 "const0_operand" "")))]
"TARGET_MAX"
"pkwb %r1,%0"
"TARGET_MAX"
"unpkbw %r1,%0"
[(set_attr "type" "mvi")])
+
+(define_expand "builtin_cttz"
+ [(set (match_operand:DI 0 "register_operand" "")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "")]
+ UNSPEC_CTTZ))]
+ "TARGET_CIX"
+ "")
+
+(define_insn "builtin_ctlz"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+ UNSPEC_CTLZ))]
+ "TARGET_CIX"
+ "ctlz %1,%0"
+ [(set_attr "type" "mvi")])
+
+(define_insn "builtin_ctpop"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+ UNSPEC_CTPOP))]
+ "TARGET_CIX"
+ "ctpop %1,%0"
+ [(set_attr "type" "mvi")])
\f
;; The call patterns are at the end of the file because their
;; wildcard operand0 interferes with nice recognition.
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
"@
jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
- bsr $26,$%1..ng
+ bsr $26,%1\t\t!samegp
ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
[(set_attr "type" "jsr")
(set_attr "length" "12,*,16")])
(use (reg:DI 29))
(clobber (reg:DI 26))])]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
- && ! current_file_function_operand (operands[1], Pmode)
+ && ! samegp_function_operand (operands[1], Pmode)
&& peep2_regno_dead_p (1, 29)"
[(parallel [(set (match_dup 0)
(call (mem:DI (match_dup 3))
(use (reg:DI 29))
(clobber (reg:DI 26))])]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
- && ! current_file_function_operand (operands[1], Pmode)
+ && ! samegp_function_operand (operands[1], Pmode)
&& ! peep2_regno_dead_p (1, 29)"
[(parallel [(set (match_dup 0)
(call (mem:DI (match_dup 3))
"! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
&& find_reg_note (insn, REG_NORETURN, NULL_RTX)"
"@
- jsr $26,($27),0
- bsr $26,$%1..ng
- jsr $26,%1"
+ jsr $26,($27),0%+
+ bsr $26,$%1..ng%+
+ jsr $26,%1%+"
[(set_attr "type" "jsr")
(set_attr "length" "*,*,8")])
(unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
"@
- br $31,$%1..ng
+ br $31,%1\t\t!samegp
ldq $27,%1($29)\t\t!literal!%#\;jmp $31,($27),%1\t\t!lituse_jsr!%#"
[(set_attr "type" "jsr")
(set_attr "length" "*,8")])
[(set_attr "type" "jsr")
(set_attr "length" "*,*,12")])
+; GAS relies on the order and position of instructions output below in order
+; to generate relocs for VMS link to potentially optimize the call.
+; Please do not molest.
(define_insn "*call_value_vms_1"
[(set (match_operand 0 "" "")
(call (mem:DI (match_operand:DI 1 "call_operand" "r,s"))
(match_operand 2 "" "")))
- (use (match_operand:DI 3 "nonimmediate_operand" "r,m"))
+ (use (match_operand:DI 3 "nonmemory_operand" "r,n"))
(use (reg:DI 25))
(use (reg:DI 26))
(clobber (reg:DI 27))]
"TARGET_ABI_OPEN_VMS"
- "@
- mov %3,$27\;jsr $26,0\;ldq $27,0($29)
- ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"
+{
+ switch (which_alternative)
+ {
+ case 0:
+ return "mov %3,$27\;jsr $26,0\;ldq $27,0($29)";
+ case 1:
+ operands [3] = alpha_use_linkage (operands [1], cfun->decl, 1, 0);
+ operands [4] = alpha_use_linkage (operands [1], cfun->decl, 0, 0);
+ return "ldq $26,%4\;ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)";
+ default:
+ abort();
+ }
+}
[(set_attr "type" "jsr")
(set_attr "length" "12,16")])
projects / gcc.git / blobdiff