/* Output routines for GCC for ARM.
- Copyright (C) 1991, 93, 94, 95, 96, 97, 98, 1999 Free Software Foundation, Inc.
+ Copyright (C) 1991, 93, 94, 95, 96, 97, 98, 99, 2000 Free Software Foundation, Inc.
Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
and Martin Simmons (@harleqn.co.uk).
More major hacks by Richard Earnshaw (rearnsha@arm.com).
#include "flags.h"
#include "reload.h"
#include "tree.h"
+#include "function.h"
#include "expr.h"
#include "toplev.h"
+#include "recog.h"
+#include "ggc.h"
+#include "tm_p.h"
+
+#ifndef Mmode
+#define Mmode enum machine_mode
+#endif
+
+/* Some function declarations. */
+static HOST_WIDE_INT int_log2 PARAMS ((HOST_WIDE_INT));
+static char * output_multi_immediate PARAMS ((rtx *, char *, char *, int, HOST_WIDE_INT));
+static int arm_gen_constant PARAMS ((enum rtx_code, Mmode, HOST_WIDE_INT, rtx, rtx, int, int));
+static int arm_naked_function_p PARAMS ((tree));
+static void init_fpa_table PARAMS ((void));
+static enum machine_mode select_dominance_cc_mode PARAMS ((rtx, rtx, HOST_WIDE_INT));
+static HOST_WIDE_INT add_minipool_constant PARAMS ((rtx, Mmode));
+static void dump_minipool PARAMS ((rtx));
+static rtx find_barrier PARAMS ((rtx, int));
+static void push_minipool_fix PARAMS ((rtx, int, rtx *, Mmode, rtx));
+static void push_minipool_barrier PARAMS ((rtx, int));
+static void note_invalid_constants PARAMS ((rtx, int));
+static char * fp_const_from_val PARAMS ((REAL_VALUE_TYPE *));
+static int eliminate_lr2ip PARAMS ((rtx *));
+static char * shift_op PARAMS ((rtx, HOST_WIDE_INT *));
+static int pattern_really_clobbers_lr PARAMS ((rtx));
+static int function_really_clobbers_lr PARAMS ((rtx));
+static rtx emit_multi_reg_push PARAMS ((int));
+static rtx emit_sfm PARAMS ((int, int));
+static enum arm_cond_code get_arm_condition_code PARAMS ((rtx));
+static int const_ok_for_op PARAMS ((HOST_WIDE_INT, enum rtx_code));
+static void arm_add_gc_roots PARAMS ((void));
/* The maximum number of insns skipped which will be conditionalised if
possible. */
static int max_insns_skipped = 5;
extern FILE * asm_out_file;
-/* Some function declarations. */
-static HOST_WIDE_INT int_log2 PROTO ((HOST_WIDE_INT));
-static char *output_multi_immediate PROTO ((rtx *, char *, char *, int,
- HOST_WIDE_INT));
-static int arm_gen_constant PROTO ((enum rtx_code, enum machine_mode,
- HOST_WIDE_INT, rtx, rtx, int, int));
-static int arm_naked_function_p PROTO ((tree));
-static void init_fpa_table PROTO ((void));
-static enum machine_mode select_dominance_cc_mode PROTO ((enum rtx_code, rtx,
- rtx, HOST_WIDE_INT));
-static HOST_WIDE_INT add_constant PROTO ((rtx, enum machine_mode, int *));
-static void dump_table PROTO ((rtx));
-static int fixit PROTO ((rtx, enum machine_mode, int));
-static rtx find_barrier PROTO ((rtx, int));
-static int broken_move PROTO ((rtx));
-static char *fp_const_from_val PROTO ((REAL_VALUE_TYPE *));
-static int eliminate_lr2ip PROTO ((rtx *));
-static char *shift_op PROTO ((rtx, HOST_WIDE_INT *));
-static int pattern_really_clobbers_lr PROTO ((rtx));
-static int function_really_clobbers_lr PROTO ((rtx));
-static void emit_multi_reg_push PROTO ((int));
-static void emit_sfm PROTO ((int, int));
-static enum arm_cond_code get_arm_condition_code PROTO ((rtx));
-
-/* Define the information needed to generate branch insns. This is
- stored from the compare operation. */
+/* True if we are currently building a constant table. */
+int making_const_table;
+/* Define the information needed to generate branch insns. This is
+ stored from the compare operation. */
rtx arm_compare_op0, arm_compare_op1;
-int arm_compare_fp;
-/* What type of floating point are we tuning for? */
+/* What type of floating point are we tuning for? */
enum floating_point_type arm_fpu;
-/* What type of floating point instructions are available? */
+/* What type of floating point instructions are available? */
enum floating_point_type arm_fpu_arch;
-/* What program mode is the cpu running in? 26-bit mode or 32-bit mode */
+/* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */
enum prog_mode_type arm_prgmode;
-/* Set by the -mfp=... option */
-char * target_fp_name = NULL;
+/* Set by the -mfp=... option. */
+const char * target_fp_name = NULL;
/* Used to parse -mstructure_size_boundary command line option. */
-char * structure_size_string = NULL;
-int arm_structure_size_boundary = 32; /* Used to be 8 */
+const char * structure_size_string = NULL;
+int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
+
+/* Bit values used to identify processor capabilities. */
+#define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
+#define FL_FAST_MULT (1 << 1) /* Fast multiply */
+#define FL_MODE26 (1 << 2) /* 26-bit mode support */
+#define FL_MODE32 (1 << 3) /* 32-bit mode support */
+#define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
+#define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
+#define FL_THUMB (1 << 6) /* Thumb aware */
+#define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
+#define FL_STRONG (1 << 8) /* StrongARM */
+
+/* The bits in this mask specify which instructions we are allowed to
+ generate. */
+static int insn_flags = 0;
+/* The bits in this mask specify which instruction scheduling options should
+ be used. Note - there is an overlap with the FL_FAST_MULT. For some
+ hardware we want to be able to generate the multiply instructions, but to
+ tune as if they were not present in the architecture. */
+static int tune_flags = 0;
+
+/* The following are used in the arm.md file as equivalents to bits
+ in the above two flag variables. */
/* Nonzero if this is an "M" variant of the processor. */
int arm_fast_multiply = 0;
-/* Nonzero if this chip supports the ARM Architecture 4 extensions */
+/* Nonzero if this chip supports the ARM Architecture 4 extensions. */
int arm_arch4 = 0;
-/* Nonzero if this chip can benefit from laod scheduling. */
+/* Nonzero if this chip supports the ARM Architecture 5 extensions. */
+int arm_arch5 = 0;
+
+/* Nonzero if this chip can benefit from load scheduling. */
int arm_ld_sched = 0;
/* Nonzero if this chip is a StrongARM. */
int current_function_anonymous_args;
/* The register number to be used for the PIC offset register. */
+const char * arm_pic_register_string = NULL;
int arm_pic_register = 9;
-/* Location counter of .text segment. */
-int arm_text_location = 0;
-
/* Set to one if we think that lr is only saved because of subroutine calls,
- but all of these can be `put after' return insns */
+ but all of these can be `put after' return insns. */
int lr_save_eliminated;
/* Set to 1 when a return insn is output, this means that the epilogue
- is not needed. */
-
+ is not needed. */
static int return_used_this_function;
+/* Set to 1 after arm_reorg has started. Reset to start at the start of
+ the next function. */
+static int after_arm_reorg = 0;
+
+/* The maximum number of insns to be used when loading a constant. */
static int arm_constant_limit = 3;
/* For an explanation of these variables, see final_prescan_insn below. */
#define streq(string1, string2) (strcmp (string1, string2) == 0)
\f
-/* Initialization code */
-
-#define FL_CO_PROC 0x01 /* Has external co-processor bus */
-#define FL_FAST_MULT 0x02 /* Fast multiply */
-#define FL_MODE26 0x04 /* 26-bit mode support */
-#define FL_MODE32 0x08 /* 32-bit mode support */
-#define FL_ARCH4 0x10 /* Architecture rel 4 */
-#define FL_THUMB 0x20 /* Thumb aware */
-#define FL_LDSCHED 0x40 /* Load scheduling necessary */
-#define FL_STRONG 0x80 /* StrongARM */
+/* Initialization code. */
struct processors
{
{"arm600", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
{"arm610", FL_MODE26 | FL_MODE32 },
{"arm620", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
- {"arm7", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
- {"arm7m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, /* arm7m doesn't exist on its own, */
- {"arm7d", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, /* but only with D, (and I), */
- {"arm7dm", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, /* but those don't alter the code, */
- {"arm7di", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, /* so arm7m is sometimes used. */
+ {"arm7", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
+ /* arm7m doesn't exist on its own, but only with D, (and I), but
+ those don't alter the code, so arm7m is sometimes used. */
+ {"arm7m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
+ {"arm7d", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
+ {"arm7dm", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
+ {"arm7di", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
{"arm7dmi", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
{"arm70", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
{"arm700", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
{"arm700i", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
{"arm710", FL_MODE26 | FL_MODE32 },
+ {"arm720", FL_MODE26 | FL_MODE32 },
{"arm710c", FL_MODE26 | FL_MODE32 },
{"arm7100", FL_MODE26 | FL_MODE32 },
{"arm7500", FL_MODE26 | FL_MODE32 },
- {"arm7500fe", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, /* Doesn't really have an external co-proc, but does have embedded fpu. */
+ /* Doesn't have an external co-proc, but does have embedded fpu. */
+ {"arm7500fe", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
{"arm7tdmi", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
{"arm8", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
{"arm810", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
{"arm9", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
+ {"arm920", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
+ {"arm920t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
{"arm9tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
{"strongarm", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
{"strongarm110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
{
/* ARM Architectures */
- {"armv2", FL_CO_PROC | FL_MODE26 },
- {"armv2a", FL_CO_PROC | FL_MODE26 },
- {"armv3", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
- {"armv3m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
- {"armv4", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 },
+ { "armv2", FL_CO_PROC | FL_MODE26 },
+ { "armv2a", FL_CO_PROC | FL_MODE26 },
+ { "armv3", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
+ { "armv3m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
+ { "armv4", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 },
/* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
implementations that support it, so we will leave it out for now. */
- {"armv4t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
- {NULL, 0}
+ { "armv4t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
+ { "armv5", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 },
+ { NULL, 0 }
};
/* This is a magic stucture. The 'string' field is magically filled in
{ NULL, "-mtune=", all_cores }
};
+/* Return the number of bits set in value' */
+static unsigned int
+bit_count (value)
+ signed int value;
+{
+ unsigned int count = 0;
+
+ while (value)
+ {
+ value &= ~(value & - value);
+ ++ count;
+ }
+
+ return count;
+}
+
/* Fix up any incompatible options that the user has specified.
This has now turned into a maze. */
void
arm_override_options ()
{
- unsigned int flags = 0;
unsigned i;
- struct arm_cpu_select * ptr;
/* Set up the flags based on the cpu/architecture selected by the user. */
for (i = sizeof (arm_select) / sizeof (arm_select[0]); i--;)
if (ptr->string != NULL && ptr->string[0] != '\0')
{
- struct processors * sel;
+ const struct processors * sel;
for (sel = ptr->processors; sel->name != NULL; sel ++)
if (streq (ptr->string, sel->name))
{
- if (flags != 0)
+ if (i == 2)
+ tune_flags = sel->flags;
+ else
{
- /* We scan the arm_select array in the order:
- tune -> arch -> cpu
- So if we have been asked to tune for, say, an ARM8,
- but we are told that the cpu is only an ARM6, then
- we have problems. We detect this by seeing if the
- flags bits accumulated so far can be supported by the
- cpu/architecture type now being parsed. If they can,
- then OR in any new bits. If they cannot then report
- an error. */
- if ((flags & sel->flags) != flags)
- error ("switch %s%s overridden by another switch",
- ptr->string, sel->name );
+ /* If we have been given an architecture and a processor
+ make sure that they are compatible. We only generate
+ a warning though, and we prefer the CPU over the
+ architecture. */
+ if (insn_flags != 0 && (insn_flags ^ sel->flags))
+ warning ("switch -mcpu=%s conflicts with -march= switch",
+ ptr->string);
+
+ insn_flags = sel->flags;
}
-
- flags = sel->flags;
break;
}
error ("bad value (%s) for %s switch", ptr->string, ptr->name);
}
}
-
+
/* If the user did not specify a processor, choose one for them. */
- if (flags == 0)
+ if (insn_flags == 0)
{
struct processors * sel;
- int sought = 0;
+ unsigned int sought;
+ static struct cpu_default
+ {
+ int cpu;
+ char * name;
+ }
+ cpu_defaults[] =
+ {
+ { TARGET_CPU_arm2, "arm2" },
+ { TARGET_CPU_arm6, "arm6" },
+ { TARGET_CPU_arm610, "arm610" },
+ { TARGET_CPU_arm710, "arm710" },
+ { TARGET_CPU_arm7m, "arm7m" },
+ { TARGET_CPU_arm7500fe, "arm7500fe" },
+ { TARGET_CPU_arm7tdmi, "arm7tdmi" },
+ { TARGET_CPU_arm8, "arm8" },
+ { TARGET_CPU_arm810, "arm810" },
+ { TARGET_CPU_arm9, "arm9" },
+ { TARGET_CPU_strongarm, "strongarm" },
+ { TARGET_CPU_generic, "arm" },
+ { 0, 0 }
+ };
+ struct cpu_default * def;
+
+ /* Find the default. */
+ for (def = cpu_defaults; def->name; def ++)
+ if (def->cpu == TARGET_CPU_DEFAULT)
+ break;
+
+ /* Make sure we found the default CPU. */
+ if (def->name == NULL)
+ abort ();
- if (TARGET_THUMB_INTERWORK)
- {
- sought |= FL_THUMB;
+ /* Find the default CPU's flags. */
+ for (sel = all_cores; sel->name != NULL; sel ++)
+ if (streq (def->name, sel->name))
+ break;
+
+ if (sel->name == NULL)
+ abort ();
- /* Force apcs-32 to be used for Thumb targets. */
+ insn_flags = sel->flags;
+
+ /* Now check to see if the user has specified some command line
+ switch that require certain abilities from the cpu. */
+ sought = 0;
+
+ if (TARGET_INTERWORK)
+ {
+ sought |= (FL_THUMB | FL_MODE32);
+
+ /* Force apcs-32 to be used for interworking. */
target_flags |= ARM_FLAG_APCS_32;
+
+ /* There are no ARM processor that supports both APCS-26 and
+ interworking. Therefore we force FL_MODE26 to be removed
+ from insn_flags here (if it was set), so that the search
+ below will always be able to find a compatible processor. */
+ insn_flags &= ~ FL_MODE26;
}
- if (TARGET_APCS_32)
- sought |= FL_MODE32;
- else
+ if (! TARGET_APCS_32)
sought |= FL_MODE26;
- if (sought != 0)
+ if (sought != 0 && ((sought & insn_flags) != sought))
{
- for (sel = all_cores; sel->name != NULL; sel++)
- if ((sel->flags & sought) == sought)
- {
- flags = sel->flags;
- break;
- }
-
- if (sel->name == NULL)
- fatal ("Unable to select a cpu that matches command line specification");
- }
- else
- {
- /* The user did not specify any command line switches that require
- a certain kind of CPU. Use TARGET_CPU_DEFAULT instead. */
-
- static struct cpu_default
- {
- int cpu;
- char * name;
- }
- cpu_defaults[] =
- {
- { TARGET_CPU_arm2, "arm2" },
- { TARGET_CPU_arm6, "arm6" },
- { TARGET_CPU_arm610, "arm610" },
- { TARGET_CPU_arm7m, "arm7m" },
- { TARGET_CPU_arm7500fe, "arm7500fe" },
- { TARGET_CPU_arm7tdmi, "arm7tdmi" },
- { TARGET_CPU_arm8, "arm8" },
- { TARGET_CPU_arm810, "arm810" },
- { TARGET_CPU_arm9, "arm9" },
- { TARGET_CPU_strongarm, "strongarm" },
- { TARGET_CPU_generic, "arm" },
- { 0, 0 }
- };
- struct cpu_default * def;
-
- /* Find the default. */
- for (def = cpu_defaults; def->name; def ++)
- if (def->cpu == TARGET_CPU_DEFAULT)
- break;
-
- if (def->name == NULL)
- abort ();
-
- /* Find the default CPU's flags. */
+ /* Try to locate a CPU type that supports all of the abilities
+ of the default CPU, plus the extra abilities requested by
+ the user. */
for (sel = all_cores; sel->name != NULL; sel ++)
- if (streq (def->name, sel->name))
+ if ((sel->flags & sought) == (sought | insn_flags))
break;
if (sel->name == NULL)
- abort ();
+ {
+ unsigned int current_bit_count = 0;
+ struct processors * best_fit = NULL;
+
+ /* Ideally we would like to issue an error message here
+ saying that it was not possible to find a CPU compatible
+ with the default CPU, but which also supports the command
+ line options specified by the programmer, and so they
+ ought to use the -mcpu=<name> command line option to
+ override the default CPU type.
+
+ Unfortunately this does not work with multilibing. We
+ need to be able to support multilibs for -mapcs-26 and for
+ -mthumb-interwork and there is no CPU that can support both
+ options. Instead if we cannot find a cpu that has both the
+ characteristics of the default cpu and the given command line
+ options we scan the array again looking for a best match. */
+ for (sel = all_cores; sel->name != NULL; sel ++)
+ if ((sel->flags & sought) == sought)
+ {
+ unsigned int count;
- flags = sel->flags;
- }
- }
+ count = bit_count (sel->flags & insn_flags);
- /* Cope with some redundant flags. */
- if (TARGET_6)
- {
- warning ("Option '-m6' deprecated. Use: '-mapcs-32' or -mcpu=<proc>");
- target_flags |= ARM_FLAG_APCS_32;
+ if (count >= current_bit_count)
+ {
+ best_fit = sel;
+ current_bit_count = count;
+ }
+ }
+
+ if (best_fit == NULL)
+ abort ();
+ else
+ sel = best_fit;
+ }
+
+ insn_flags = sel->flags;
+ }
}
- if (TARGET_3)
- {
- warning ("Option '-m3' deprecated. Use: '-mapcs-26' or -mcpu=<proc>");
- target_flags &= ~ARM_FLAG_APCS_32;
- }
-
+ /* If tuning has not been specified, tune for whichever processor or
+ architecture has been selected. */
+ if (tune_flags == 0)
+ tune_flags = insn_flags;
+
/* Make sure that the processor choice does not conflict with any of the
other command line choices. */
- if (TARGET_APCS_32 && !(flags & FL_MODE32))
+ if (TARGET_APCS_32 && !(insn_flags & FL_MODE32))
{
- warning ("target CPU does not support APCS-32" );
+ /* If APCS-32 was not the default then it must have been set by the
+ user, so issue a warning message. If the user has specified
+ "-mapcs-32 -mcpu=arm2" then we loose here. */
+ if ((TARGET_DEFAULT & ARM_FLAG_APCS_32) == 0)
+ warning ("target CPU does not support APCS-32" );
target_flags &= ~ ARM_FLAG_APCS_32;
}
- else if (! TARGET_APCS_32 && !(flags & FL_MODE26))
+ else if (! TARGET_APCS_32 && !(insn_flags & FL_MODE26))
{
warning ("target CPU does not support APCS-26" );
target_flags |= ARM_FLAG_APCS_32;
}
- if (TARGET_THUMB_INTERWORK && !(flags & FL_THUMB))
+ if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
{
warning ("target CPU does not support interworking" );
- target_flags &= ~ARM_FLAG_THUMB;
+ target_flags &= ~ARM_FLAG_INTERWORK;
}
/* If interworking is enabled then APCS-32 must be selected as well. */
- if (TARGET_THUMB_INTERWORK)
+ if (TARGET_INTERWORK)
{
if (! TARGET_APCS_32)
warning ("interworking forces APCS-32 to be used" );
warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
target_flags |= ARM_FLAG_APCS_FRAME;
}
-
- if (write_symbols != NO_DEBUG && flag_omit_frame_pointer)
- warning ("-g with -fomit-frame-pointer may not give sensible debugging");
-
+
if (TARGET_POKE_FUNCTION_NAME)
target_flags |= ARM_FLAG_APCS_FRAME;
-
+
if (TARGET_APCS_REENT && flag_pic)
fatal ("-fpic and -mapcs-reent are incompatible");
-
+
if (TARGET_APCS_REENT)
warning ("APCS reentrant code not supported. Ignored");
-
+
+ if (write_symbols != NO_DEBUG && flag_omit_frame_pointer)
+ warning ("-g with -fomit-frame-pointer may not give sensible debugging");
+
/* If stack checking is disabled, we can use r10 as the PIC register,
which keeps r9 available. */
if (flag_pic && ! TARGET_APCS_STACK)
arm_pic_register = 10;
-
- /* Well, I'm about to have a go, but pic is NOT going to be compatible
- with APCS reentrancy, since that requires too much support in the
- assembler and linker, and the ARMASM assembler seems to lack some
- required directives. */
- if (flag_pic)
- warning ("Position independent code not supported");
-
+
if (TARGET_APCS_FLOAT)
warning ("Passing floating point arguments in fp regs not yet supported");
-
- /* Initialise booleans used elsewhere in this file, and in arm.md */
- arm_fast_multiply = (flags & FL_FAST_MULT) != 0;
- arm_arch4 = (flags & FL_ARCH4) != 0;
- arm_ld_sched = (flags & FL_LDSCHED) != 0;
- arm_is_strong = (flags & FL_STRONG);
- /* The arm.md file needs to know if theprocessor is an ARM6 or an ARM7 */
- arm_is_6_or_7 = ((flags & (FL_MODE26 | FL_MODE32)) && !(flags & FL_ARCH4));
+ /* Initialise boolean versions of the flags, for use in the arm.md file. */
+ arm_fast_multiply = (insn_flags & FL_FAST_MULT) != 0;
+ arm_arch4 = (insn_flags & FL_ARCH4) != 0;
+ arm_arch5 = (insn_flags & FL_ARCH5) != 0;
+
+ arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
+ arm_is_strong = (tune_flags & FL_STRONG) != 0;
+ arm_is_6_or_7 = ((tune_flags & (FL_MODE26 | FL_MODE32))
+ && !(tune_flags & FL_ARCH4)) != 0;
/* Default value for floating point code... if no co-processor
bus, then schedule for emulated floating point. Otherwise,
assume the user has an FPA.
Note: this does not prevent use of floating point instructions,
-msoft-float does that. */
- if ((flags & FL_CO_PROC) == 0)
- arm_fpu = FP_SOFT3;
- else
- arm_fpu = FP_HARD;
+ arm_fpu = (tune_flags & FL_CO_PROC) ? FP_HARD : FP_SOFT3;
if (target_fp_name)
{
if (TARGET_FPE && arm_fpu != FP_HARD)
arm_fpu = FP_SOFT2;
-
+
/* For arm2/3 there is no need to do any scheduling if there is only
a floating point emulator, or we are doing software floating-point. */
- if ((TARGET_SOFT_FLOAT || arm_fpu != FP_HARD) && (flags & FL_MODE32) == 0)
+ if ((TARGET_SOFT_FLOAT || arm_fpu != FP_HARD)
+ && (tune_flags & FL_MODE32) == 0)
flag_schedule_insns = flag_schedule_insns_after_reload = 0;
-
+
arm_prog_mode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26;
if (structure_size_string != NULL)
else
warning ("Structure size boundary can only be set to 8 or 32");
}
+
+ if (arm_pic_register_string != NULL)
+ {
+ int pic_register;
+
+ if (! flag_pic)
+ warning ("-mpic-register= is useless without -fpic");
+
+ pic_register = decode_reg_name (arm_pic_register_string);
+
+ /* Prevent the user from choosing an obviously stupid PIC register. */
+ if (pic_register < 0 || call_used_regs[pic_register]
+ || pic_register == HARD_FRAME_POINTER_REGNUM
+ || pic_register == STACK_POINTER_REGNUM
+ || pic_register >= PC_REGNUM)
+ error ("Unable to use '%s' for PIC register", arm_pic_register_string);
+ else
+ arm_pic_register = pic_register;
+ }
/* If optimizing for space, don't synthesize constants.
For processors with load scheduling, it never costs more than 2 cycles
to load a constant, and the load scheduler may well reduce that to 1. */
- if (optimize_size || (flags & FL_LDSCHED))
+ if (optimize_size || (tune_flags & FL_LDSCHED))
arm_constant_limit = 1;
-
+
/* If optimizing for size, bump the number of instructions that we
are prepared to conditionally execute (even on a StrongARM).
Otherwise for the StrongARM, which has early execution of branches,
max_insns_skipped = 6;
else if (arm_is_strong)
max_insns_skipped = 3;
+
+ /* Register global variables with the garbage collector. */
+ arm_add_gc_roots ();
+}
+
+static void
+arm_add_gc_roots ()
+{
+ ggc_add_rtx_root (&arm_compare_op0, 1);
+ ggc_add_rtx_root (&arm_compare_op1, 1);
+ ggc_add_rtx_root (&arm_target_insn, 1); /* Not sure this is really a root */
+ /* XXX: What about the minipool tables? */
}
-\f
-/* Return 1 if it is possible to return using a single instruction */
+\f
+/* Return 1 if it is possible to return using a single instruction. */
int
use_return_insn (iscond)
int iscond;
if (iscond && arm_is_strong && frame_pointer_needed)
return 0;
if ((iscond && arm_is_strong)
- || TARGET_THUMB_INTERWORK)
- for (regno = 0; regno < 16; regno++)
- if (regs_ever_live[regno] && ! call_used_regs[regno])
+ || TARGET_INTERWORK)
+ {
+ for (regno = 0; regno < 16; regno++)
+ if (regs_ever_live[regno] && ! call_used_regs[regno])
+ return 0;
+
+ if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
return 0;
+ }
/* Can't be done if any of the FPU regs are pushed, since this also
- requires an insn */
+ requires an insn. */
for (regno = 16; regno < 24; regno++)
if (regs_ever_live[regno] && ! call_used_regs[regno])
return 0;
/* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
be all zero, or all one. */
- if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
- && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
+ if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffffUL) != 0
+ && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffffUL)
!= ((~(unsigned HOST_WIDE_INT) 0)
- & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
+ & ~(unsigned HOST_WIDE_INT) 0xffffffffUL)))
return FALSE;
/* Fast return for 0 and powers of 2 */
do
{
- if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0)
+ if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffffUL) == 0)
return TRUE;
mask =
- (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff)
- >> (32 - 2)) | ~((unsigned HOST_WIDE_INT) 0xffffffff);
+ (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffffUL)
+ >> (32 - 2)) | ~((unsigned HOST_WIDE_INT) 0xffffffffUL);
} while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
return FALSE;
}
-/* Return true if I is a valid constant for the operation CODE. */
-int
-const_ok_for_op (i, code, mode)
+/* Return true if I is a valid constant for the operation CODE. */
+static int
+const_ok_for_op (i, code)
HOST_WIDE_INT i;
enum rtx_code code;
- enum machine_mode mode;
{
if (const_ok_for_arm (i))
return 1;
|| (GET_CODE (target) == REG && GET_CODE (source) == REG
&& REGNO (target) != REGNO (source)))
{
- if (arm_gen_constant (code, mode, val, target, source, 1, 0)
- > arm_constant_limit + (code != SET))
+ /* After arm_reorg has been called, we can't fix up expensive
+ constants by pushing them into memory so we must synthesise
+ them in-line, regardless of the cost. This is only likely to
+ be more costly on chips that have load delay slots and we are
+ compiling without running the scheduler (so no splitting
+ occurred before the final instruction emission).
+
+ Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
+ */
+ if (! after_arm_reorg
+ && (arm_gen_constant (code, mode, val, target, source, 1, 0)
+ > arm_constant_limit + (code != SET)))
{
if (code == SET)
{
int set_zero_bit_copies = 0;
int insns = 0;
unsigned HOST_WIDE_INT temp1, temp2;
- unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
+ unsigned HOST_WIDE_INT remainder = val & 0xffffffffUL;
/* find out which operations are safe for a given CODE. Also do a quick
check for degenerate cases; these can occur when DImode operations
break;
case IOR:
- if (remainder == 0xffffffff)
+ if (remainder == 0xffffffffUL)
{
if (generate)
emit_insn (gen_rtx_SET (VOIDmode, target,
emit_insn (gen_rtx_SET (VOIDmode, target, const0_rtx));
return 1;
}
- if (remainder == 0xffffffff)
+ if (remainder == 0xffffffffUL)
{
if (reload_completed && rtx_equal_p (target, source))
return 0;
emit_insn (gen_rtx_SET (VOIDmode, target, source));
return 1;
}
- if (remainder == 0xffffffff)
+ if (remainder == 0xffffffffUL)
{
if (generate)
emit_insn (gen_rtx_SET (VOIDmode, target,
abort ();
}
- /* If we can do it in one insn get out quickly */
+ /* If we can do it in one insn get out quickly. */
if (const_ok_for_arm (val)
|| (can_negate_initial && const_ok_for_arm (-val))
|| (can_invert && const_ok_for_arm (~val)))
return 1;
}
-
/* Calculate a few attributes that may be useful for specific
- optimizations. */
-
+ optimizations. */
for (i = 31; i >= 0; i--)
{
if ((remainder & (1 << i)) == 0)
word. We only look for the simplest cases, to do more would cost
too much. Be careful, however, not to generate this when the
alternative would take fewer insns. */
- if (val & 0xffff0000)
+ if (val & 0xffff0000UL)
{
- temp1 = remainder & 0xffff0000;
+ temp1 = remainder & 0xffff0000UL;
temp2 = remainder & 0x0000ffff;
- /* Overlaps outside this range are best done using other methods. */
+ /* Overlaps outside this range are best done using other methods. */
for (i = 9; i < 24; i++)
{
- if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
+ if ((((temp2 | (temp2 << i)) & 0xffffffffUL) == remainder)
&& ! const_ok_for_arm (temp2))
{
rtx new_src = (subtargets
}
}
- /* Don't duplicate cases already considered. */
+ /* Don't duplicate cases already considered. */
for (i = 17; i < 24; i++)
{
if (((temp1 | (temp1 >> i)) == remainder)
/* See if two shifts will do 2 or more insn's worth of work. */
if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
{
- HOST_WIDE_INT shift_mask = ((0xffffffff
+ HOST_WIDE_INT shift_mask = ((0xffffffffUL
<< (32 - clear_sign_bit_copies))
- & 0xffffffff);
+ & 0xffffffffUL);
- if ((remainder | shift_mask) != 0xffffffff)
+ if ((remainder | shift_mask) != 0xffffffffUL)
{
if (generate)
{
{
HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
- if ((remainder | shift_mask) != 0xffffffff)
+ if ((remainder | shift_mask) != 0xffffffffUL)
{
if (generate)
{
num_bits_set++;
if (code == AND || (can_invert && num_bits_set > 16))
- remainder = (~remainder) & 0xffffffff;
+ remainder = (~remainder) & 0xffffffffUL;
else if (code == PLUS && num_bits_set > 16)
- remainder = (-remainder) & 0xffffffff;
+ remainder = (-remainder) & 0xffffffffUL;
else
{
can_invert = 0;
We start by looking for the largest block of zeros that are aligned on
a 2-bit boundary, we then fill up the temps, wrapping around to the
top of the word when we drop off the bottom.
- In the worst case this code should produce no more than four insns. */
+ In the worst case this code should produce no more than four insns. */
{
int best_start = 0;
int best_consecutive_zeros = 0;
/* Now start emitting the insns, starting with the one with the highest
bit set: we do this so that the smallest number will be emitted last;
- this is more likely to be combinable with addressing insns. */
+ this is more likely to be combinable with addressing insns. */
i = best_start;
do
{
enum rtx_code
arm_canonicalize_comparison (code, op1)
enum rtx_code code;
- rtx *op1;
+ rtx * op1;
{
unsigned HOST_WIDE_INT i = INTVAL (*op1);
tree type;
{
if (! AGGREGATE_TYPE_P (type))
- {
- /* All simple types are returned in registers. */
- return 0;
- }
- else if (int_size_in_bytes (type) > 4)
- {
- /* All structures/unions bigger than one word are returned in memory. */
- return 1;
- }
- else if (TREE_CODE (type) == RECORD_TYPE)
+ /* All simple types are returned in registers. */
+ return 0;
+
+ if (int_size_in_bytes (type) > 4)
+ /* All structures/unions bigger than one word are returned in memory. */
+ return 1;
+
+ if (TREE_CODE (type) == RECORD_TYPE)
{
tree field;
- /* For a struct the APCS says that we must return in a register if
- every addressable element has an offset of zero. For practical
- purposes this means that the structure can have at most one non
- bit-field element and that this element must be the first one in
- the structure. */
-
+ /* For a struct the APCS says that we only return in a register
+ if the type is 'integer like' and every addressable element
+ has an offset of zero. For practical purposes this means
+ that the structure can have at most one non bit-field element
+ and that this element must be the first one in the structure. */
+
/* Find the first field, ignoring non FIELD_DECL things which will
have been created by C++. */
for (field = TYPE_FIELDS (type);
continue;
if (field == NULL)
- return 0; /* An empty structure. Allowed by an extension to ANSI C. */
+ return 0; /* An empty structure. Allowed by an extension to ANSI C. */
- /* Now check the remaining fields, if any. */
+ /* Check that the first field is valid for returning in a register... */
+ if (FLOAT_TYPE_P (TREE_TYPE (field)))
+ return 1;
+
+ if (RETURN_IN_MEMORY (TREE_TYPE (field)))
+ return 1;
+
+ /* Now check the remaining fields, if any. Only bitfields are allowed,
+ since they are not addressable. */
for (field = TREE_CHAIN (field);
field;
field = TREE_CHAIN (field))
return 0;
}
- else if (TREE_CODE (type) == UNION_TYPE)
+
+ if (TREE_CODE (type) == UNION_TYPE)
{
tree field;
if (TREE_CODE (field) != FIELD_DECL)
continue;
+ if (FLOAT_TYPE_P (TREE_TYPE (field)))
+ return 1;
+
if (RETURN_IN_MEMORY (TREE_TYPE (field)))
return 1;
}
return 0;
}
- /* XXX Not sure what should be done for other aggregates, so put them in
- memory. */
+ /* Put other aggregates in memory. */
return 1;
}
+/* Initialize a variable CUM of type CUMULATIVE_ARGS
+ for a call to a function whose data type is FNTYPE.
+ For a library call, FNTYPE is NULL. */
+void
+arm_init_cumulative_args (pcum, fntype, libname, indirect)
+ CUMULATIVE_ARGS * pcum;
+ tree fntype;
+ rtx libname ATTRIBUTE_UNUSED;
+ int indirect ATTRIBUTE_UNUSED;
+{
+ /* On the ARM, the offset starts at 0. */
+ pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype))) ? 1 : 0);
+
+ pcum->call_cookie = CALL_NORMAL;
+
+ if (TARGET_LONG_CALLS)
+ pcum->call_cookie = CALL_LONG;
+
+ /* Check for long call/short call attributes. The attributes
+ override any command line option. */
+ if (fntype)
+ {
+ if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
+ pcum->call_cookie = CALL_SHORT;
+ else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
+ pcum->call_cookie = CALL_LONG;
+ }
+}
+
+/* Determine where to put an argument to a function.
+ Value is zero to push the argument on the stack,
+ or a hard register in which to store the argument.
+
+ MODE is the argument's machine mode.
+ TYPE is the data type of the argument (as a tree).
+ This is null for libcalls where that information may
+ not be available.
+ CUM is a variable of type CUMULATIVE_ARGS which gives info about
+ the preceding args and about the function being called.
+ NAMED is nonzero if this argument is a named parameter
+ (otherwise it is an extra parameter matching an ellipsis). */
+rtx
+arm_function_arg (pcum, mode, type, named)
+ CUMULATIVE_ARGS * pcum;
+ enum machine_mode mode;
+ tree type ATTRIBUTE_UNUSED;
+ int named;
+{
+ if (mode == VOIDmode)
+ /* Compute operand 2 of the call insn. */
+ return GEN_INT (pcum->call_cookie);
+
+ if (! named || pcum->nregs >= NUM_ARG_REGS)
+ return NULL_RTX;
+
+ return gen_rtx_REG (mode, pcum->nregs);
+}
+\f
+/* Encode the current state of the #pragma [no_]long_calls. */
+typedef enum
+{
+ OFF, /* No #pramgma [no_]long_calls is in effect. */
+ LONG, /* #pragma long_calls is in effect. */
+ SHORT /* #pragma no_long_calls is in effect. */
+} arm_pragma_enum;
+
+static arm_pragma_enum arm_pragma_long_calls = OFF;
+
+/* Handle pragmas for compatibility with Intel's compilers.
+ FIXME: This is incomplete, since it does not handle all
+ the pragmas that the Intel compilers understand. */
+int
+arm_process_pragma (p_getc, p_ungetc, pname)
+ int (* p_getc) PARAMS ((void)) ATTRIBUTE_UNUSED;
+ void (* p_ungetc) PARAMS ((int)) ATTRIBUTE_UNUSED;
+ char * pname;
+{
+ /* Should be pragma 'far' or equivalent for callx/balx here. */
+ if (strcmp (pname, "long_calls") == 0)
+ arm_pragma_long_calls = LONG;
+ else if (strcmp (pname, "no_long_calls") == 0)
+ arm_pragma_long_calls = SHORT;
+ else if (strcmp (pname, "long_calls_off") == 0)
+ arm_pragma_long_calls = OFF;
+ else
+ return 0;
+
+ return 1;
+}
+\f
+/* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific
+ attribute for TYPE. The attributes in ATTRIBUTES have previously been
+ assigned to TYPE. */
+int
+arm_valid_type_attribute_p (type, attributes, identifier, args)
+ tree type;
+ tree attributes ATTRIBUTE_UNUSED;
+ tree identifier;
+ tree args;
+{
+ if ( TREE_CODE (type) != FUNCTION_TYPE
+ && TREE_CODE (type) != METHOD_TYPE
+ && TREE_CODE (type) != FIELD_DECL
+ && TREE_CODE (type) != TYPE_DECL)
+ return 0;
+
+ /* Function calls made to this symbol must be done indirectly, because
+ it may lie outside of the 26 bit addressing range of a normal function
+ call. */
+ if (is_attribute_p ("long_call", identifier))
+ return (args == NULL_TREE);
+
+ /* Whereas these functions are always known to reside within the 26 bit
+ addressing range. */
+ if (is_attribute_p ("short_call", identifier))
+ return (args == NULL_TREE);
+
+ return 0;
+}
+
+/* Return 0 if the attributes for two types are incompatible, 1 if they
+ are compatible, and 2 if they are nearly compatible (which causes a
+ warning to be generated). */
+int
+arm_comp_type_attributes (type1, type2)
+ tree type1;
+ tree type2;
+{
+ int l1, l2, s1, s2;
+
+ /* Check for mismatch of non-default calling convention. */
+ if (TREE_CODE (type1) != FUNCTION_TYPE)
+ return 1;
+
+ /* Check for mismatched call attributes. */
+ l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
+ l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
+ s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
+ s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
+
+ /* Only bother to check if an attribute is defined. */
+ if (l1 | l2 | s1 | s2)
+ {
+ /* If one type has an attribute, the other must have the same attribute. */
+ if ((l1 != l2) || (s1 != s2))
+ return 0;
+
+ /* Disallow mixed attributes. */
+ if ((l1 & s2) || (l2 & s1))
+ return 0;
+ }
+
+ return 1;
+}
+
+/* Check the ARM specific attributes on the given function decl.
+ If any of them would prevent the function from being inlined,
+ return a tesxtual description of why not. Otherwise return NULL. */
+const char *
+arm_function_attribute_inlineable_p (fndecl)
+ tree fndecl;
+{
+ if (lookup_attribute ("naked", DECL_MACHINE_ATTRIBUTES (fndecl)))
+ return "naked functions cannot be inlined";
+
+ /* Allow functions with short_call and long_call attributes to be inlined. */
+ return NULL;
+}
+
+/* Encode long_call or short_call attribute by prefixing
+ symbol name in DECL with a special character FLAG. */
+void
+arm_encode_call_attribute (decl, flag)
+ tree decl;
+ char flag;
+{
+ const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
+ int len = strlen (str);
+ char * newstr;
+
+ if (TREE_CODE (decl) != FUNCTION_DECL)
+ return;
+
+ /* Do not allow weak functions to be treated as short call. */
+ if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
+ return;
+
+ if (ggc_p)
+ newstr = ggc_alloc_string (NULL, len + 2);
+ else
+ newstr = permalloc (len + 2);
+
+ sprintf (newstr, "%c%s", flag, str);
+
+ XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
+}
+
+/* Assigns default attributes to newly defined type. This is used to
+ set short_call/long_call attributes for function types of
+ functions defined inside corresponding #pragma scopes. */
+void
+arm_set_default_type_attributes (type)
+ tree type;
+{
+ /* Add __attribute__ ((long_call)) to all functions, when
+ inside #pragma long_calls or __attribute__ ((short_call)),
+ when inside #pragma no_long_calls. */
+ if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
+ {
+ tree type_attr_list, attr_name;
+ type_attr_list = TYPE_ATTRIBUTES (type);
+
+ if (arm_pragma_long_calls == LONG)
+ attr_name = get_identifier ("long_call");
+ else if (arm_pragma_long_calls == SHORT)
+ attr_name = get_identifier ("short_call");
+ else
+ return;
+
+ type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
+ TYPE_ATTRIBUTES (type) = type_attr_list;
+ }
+}
+\f
+/* Return 1 if the operand is a SYMBOL_REF for a function known to be
+ defined within the current compilation unit. If this caanot be
+ determined, then 0 is returned. */
+static int
+current_file_function_operand (sym_ref)
+ rtx sym_ref;
+{
+ /* This is a bit of a fib. A function will have a short call flag
+ applied to its name if it has the short call attribute, or it has
+ already been defined within the current compilation unit. */
+ if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
+ return 1;
+
+ /* The current funciton is always defined within the current compilation
+ unit. if it s a weak defintion however, then this may not be the real
+ defintion of the function, and so we have to say no. */
+ if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
+ && ! DECL_WEAK (current_function_decl))
+ return 1;
+
+ /* We cannot make the determination - default to returning 0. */
+ return 0;
+}
+
+/* Return non-zero if a 32 bit "long_call" should be generated for
+ this call. We generate a long_call if the function:
+
+ a. has an __attribute__((long call))
+ or b. is within the scope of a #pragma long_calls
+ or c. the -mlong-calls command line switch has been specified
+
+ However we do not generate a long call if the function:
+
+ d. has an __attribute__ ((short_call))
+ or e. is inside the scope of a #pragma no_long_calls
+ or f. has an __attribute__ ((section))
+ or g. is defined within the current compilation unit.
+
+ This function will be called by C fragments contained in the machine
+ description file. CALL_REF and CALL_COOKIE correspond to the matched
+ rtl operands. CALL_SYMBOL is used to distinguish between
+ two different callers of the function. It is set to 1 in the
+ "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
+ and "call_value" patterns. This is because of the difference in the
+ SYM_REFs passed by these patterns. */
+int
+arm_is_longcall_p (sym_ref, call_cookie, call_symbol)
+ rtx sym_ref;
+ int call_cookie;
+ int call_symbol;
+{
+ if (! call_symbol)
+ {
+ if (GET_CODE (sym_ref) != MEM)
+ return 0;
+
+ sym_ref = XEXP (sym_ref, 0);
+ }
+
+ if (GET_CODE (sym_ref) != SYMBOL_REF)
+ return 0;
+
+ if (call_cookie & CALL_SHORT)
+ return 0;
+
+ if (TARGET_LONG_CALLS && flag_function_sections)
+ return 1;
+
+ if (current_file_function_operand (sym_ref, VOIDmode))
+ return 0;
+
+ return (call_cookie & CALL_LONG)
+ || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
+ || TARGET_LONG_CALLS;
+}
+\f
int
legitimate_pic_operand_p (x)
rtx x;
#ifdef AOF_ASSEMBLER
/* The AOF assembler can generate relocations for these directly, and
- understands that the PIC register has to be added into the offset.
- */
+ understands that the PIC register has to be added into the offset. */
insn = emit_insn (gen_pic_load_addr_based (reg, orig));
#else
if (subregs)
return gen_rtx_PLUS (Pmode, base, offset);
}
else if (GET_CODE (orig) == LABEL_REF)
- current_function_uses_pic_offset_table = 1;
+ {
+ current_function_uses_pic_offset_table = 1;
+
+ if (NEED_GOT_RELOC)
+ {
+ rtx pic_ref, address = gen_reg_rtx (Pmode);
+
+ emit_insn (gen_pic_load_addr (address, orig));
+ pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address);
+
+ emit_move_insn (address, pic_ref);
+ return address;
+ }
+ }
return orig;
}
static rtx pic_rtx;
int
-is_pic(x)
+is_pic (x)
rtx x;
{
if (x == pic_rtx)
rtx l1, pic_tmp, pic_tmp2, seq;
rtx global_offset_table;
- if (current_function_uses_pic_offset_table == 0)
+ if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
return;
if (! flag_pic)
l1 = gen_label_rtx ();
global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
- /* The PC contains 'dot'+8, but the label L1 is on the next
- instruction, so the offset is only 'dot'+4. */
- pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1),
- GEN_INT (4));
- pic_tmp2 = gen_rtx_CONST (VOIDmode,
+ /* On the ARM the PC register contains 'dot + 8' at the time of the
+ addition. */
+ pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), 8);
+ if (GOT_PCREL)
+ pic_tmp2 = gen_rtx_CONST (VOIDmode,
gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
+ else
+ pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
emit_insn (gen_pic_load_addr (pic_offset_table_rtx, pic_rtx));
- emit_jump_insn (gen_pic_add_dot_plus_eight(l1, pic_offset_table_rtx));
- emit_label (l1);
+ emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
seq = gen_sequence ();
end_sequence ();
|| (X) == arg_pointer_rtx)
int
-arm_rtx_costs (x, code, outer_code)
+arm_rtx_costs (x, code)
rtx x;
- enum rtx_code code, outer_code;
+ enum rtx_code code;
{
enum machine_mode mode = GET_MODE (x);
enum rtx_code subcode;
return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
+ ((REG_OR_SUBREG_REG (XEXP (x, 1))
|| (GET_CODE (XEXP (x, 1)) == CONST_INT
- && const_ok_for_op (INTVAL (XEXP (x, 1)), code, mode)))
+ && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
? 0 : 8));
if (REG_OR_SUBREG_REG (XEXP (x, 0)))
return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
+ ((REG_OR_SUBREG_REG (XEXP (x, 1))
|| (GET_CODE (XEXP (x, 1)) == CONST_INT
- && const_ok_for_op (INTVAL (XEXP (x, 1)), code, mode)))
+ && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
? 0 : 4));
else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
case MULT:
/* There is no point basing this on the tuning, since it is always the
- fast variant if it exists at all */
+ fast variant if it exists at all. */
if (arm_fast_multiply && mode == DImode
&& (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
&& (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
if (GET_CODE (XEXP (x, 1)) == CONST_INT)
{
unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
- & (unsigned HOST_WIDE_INT) 0xffffffff);
+ & (unsigned HOST_WIDE_INT) 0xffffffffUL);
int add_cost = const_ok_for_arm (i) ? 4 : 8;
int j;
- /* Tune as appropriate */
- int booth_unit_size = (arm_fast_multiply ? 8 : 2);
+
+ /* Tune as appropriate. */
+ int booth_unit_size = ((tune_flags & FL_FAST_MULT) ? 8 : 2);
for (j = 0; i && j < 32; j += booth_unit_size)
{
return add_cost;
}
- return ((arm_fast_multiply ? 8 : 30)
+ return (((tune_flags & FL_FAST_MULT) ? 8 : 30)
+ (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
+ (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4));
{
rtx i_pat, d_pat;
- /* XXX This is not strictly true for the FPA. */
+ /* XXX This is not strictly true for the FPA. */
if (REG_NOTE_KIND(link) == REG_DEP_ANTI
|| REG_NOTE_KIND(link) == REG_DEP_OUTPUT)
return 0;
/* This is a load after a store, there is no conflict if the load reads
from a cached area. Assume that loads from the stack, and from the
constant pool are cached, and that others will miss. This is a
- hack. */
+ hack. */
-/* debug_rtx (insn);
- debug_rtx (dep);
- debug_rtx (link);
- fprintf (stderr, "costs %d\n", cost); */
-
if (CONSTANT_POOL_ADDRESS_P (XEXP (SET_SRC (i_pat), 0))
|| reg_mentioned_p (stack_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
|| reg_mentioned_p (frame_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
|| reg_mentioned_p (hard_frame_pointer_rtx,
XEXP (SET_SRC (i_pat), 0)))
- {
-/* fprintf (stderr, "***** Now 1\n"); */
- return 1;
- }
+ return 1;
}
return cost;
}
-/* This code has been fixed for cross compilation. */
+/* This code has been fixed for cross compilation. */
static int fpa_consts_inited = 0;
-char *strings_fpa[8] = {
+char * strings_fpa[8] =
+{
"0", "1", "2", "3",
"4", "5", "0.5", "10"
};
fpa_consts_inited = 1;
}
-/* Return TRUE if rtx X is a valid immediate FPU constant. */
+/* Return TRUE if rtx X is a valid immediate FPU constant. */
int
const_double_rtx_ok_for_fpu (x)
return 0;
}
-/* Return TRUE if rtx X is a valid immediate FPU constant. */
+/* Return TRUE if rtx X is a valid immediate FPU constant. */
int
neg_const_double_rtx_ok_for_fpu (x)
int
reload_memory_operand (op, mode)
rtx op;
- enum machine_mode mode;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
{
int regno = true_regnum (op);
op = XEXP (op, 0);
- /* A sum of anything more complex than reg + reg or reg + const is bad */
+ /* A sum of anything more complex than reg + reg or reg + const is bad. */
if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
&& (! s_register_operand (XEXP (op, 0), VOIDmode)
|| (! s_register_operand (XEXP (op, 1), VOIDmode)
&& GET_CODE (XEXP (op, 1)) != CONST_INT)))
return 1;
- /* Big constants are also bad */
+ /* Big constants are also bad. */
if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT
&& (INTVAL (XEXP (op, 1)) > 0xff
|| -INTVAL (XEXP (op, 1)) > 0xff))
return 1;
- /* Everything else is good, or can will automatically be made so. */
+ /* Everything else is good, or can will automatically be made so. */
return 0;
}
{
if (s_register_operand (op, mode))
return TRUE;
- else if (GET_CODE (op) == CONST_DOUBLE)
- return (const_double_rtx_ok_for_fpu (op));
+
+ if (GET_MODE (op) != mode && mode != VOIDmode)
+ return FALSE;
+
+ if (GET_CODE (op) == CONST_DOUBLE)
+ return const_double_rtx_ok_for_fpu (op);
return FALSE;
}
{
if (s_register_operand (op, mode))
return TRUE;
- else if (GET_CODE (op) == CONST_DOUBLE)
+
+ if (GET_MODE (op) != mode && mode != VOIDmode)
+ return FALSE;
+
+ if (GET_CODE (op) == CONST_DOUBLE)
return (const_double_rtx_ok_for_fpu (op)
|| neg_const_double_rtx_ok_for_fpu (op));
int
power_of_two_operand (op, mode)
rtx op;
- enum machine_mode mode;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
{
if (GET_CODE (op) == CONST_INT)
{
}
/* Return TRUE for a valid operand of a DImode operation.
- Either: REG, CONST_DOUBLE or MEM(DImode_address).
+ Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
Note that this disallows MEM(REG+REG), but allows
MEM(PRE/POST_INC/DEC(REG)). */
if (s_register_operand (op, mode))
return TRUE;
+ if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
+ return FALSE;
+
+ if (GET_CODE (op) == SUBREG)
+ op = SUBREG_REG (op);
+
switch (GET_CODE (op))
{
case CONST_DOUBLE:
}
/* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
- Either: REG, CONST_DOUBLE or MEM(DImode_address).
+ Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
Note that this disallows MEM(REG+REG), but allows
MEM(PRE/POST_INC/DEC(REG)). */
if (s_register_operand (op, mode))
return TRUE;
+ if (mode != VOIDmode && GET_MODE (op) != mode)
+ return FALSE;
+
+ if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op)))
+ return FALSE;
+
+ if (GET_CODE (op) == SUBREG)
+ op = SUBREG_REG (op);
+
switch (GET_CODE (op))
{
case CONST_DOUBLE:
}
}
-/* Return TRUE for valid index operands. */
+/* Return TRUE for valid index operands. */
int
index_operand (op, mode)
/* Return TRUE for valid shifts by a constant. This also accepts any
power of two on the (somewhat overly relaxed) assumption that the
- shift operator in this case was a mult. */
+ shift operator in this case was a mult. */
int
const_shift_operand (op, mode)
}
}
-/* Return TRUE for shift operators. */
+/* Return TRUE for binary logical operators. */
+
+int
+logical_binary_operator (x, mode)
+ rtx x;
+ enum machine_mode mode;
+{
+ if (GET_MODE (x) != mode)
+ return FALSE;
+ else
+ {
+ enum rtx_code code = GET_CODE (x);
+
+ return (code == IOR || code == XOR || code == AND);
+ }
+}
+
+/* Return TRUE for shift operators. */
int
shift_operator (x, mode)
enum rtx_code code = GET_CODE (x);
if (code == MULT)
- return power_of_two_operand (XEXP (x, 1));
+ return power_of_two_operand (XEXP (x, 1), mode);
return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
|| code == ROTATERT);
}
}
-int equality_operator (x, mode)
+/* Return TRUE if x is EQ or NE. */
+int
+equality_operator (x, mode)
rtx x;
- enum machine_mode mode;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
{
return GET_CODE (x) == EQ || GET_CODE (x) == NE;
}
-/* Return TRUE for SMIN SMAX UMIN UMAX operators. */
-
+/* Return TRUE for SMIN SMAX UMIN UMAX operators. */
int
minmax_operator (x, mode)
rtx x;
return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
}
-/* return TRUE if x is EQ or NE */
-
/* Return TRUE if this is the condition code register, if we aren't given
- a mode, accept any class CCmode register */
-
+ a mode, accept any class CCmode register. */
int
cc_register (x, mode)
rtx x;
/* Return TRUE if this is the condition code register, if we aren't given
a mode, accept any class CCmode register which indicates a dominance
expression. */
-
int
dominant_cc_register (x, mode)
rtx x;
symbol_mentioned_p (x)
rtx x;
{
- register char *fmt;
+ register const char * fmt;
register int i;
if (GET_CODE (x) == SYMBOL_REF)
label_mentioned_p (x)
rtx x;
{
- register char *fmt;
+ register const char * fmt;
register int i;
if (GET_CODE (x) == LABEL_REF)
abort ();
}
-/* Return 1 if memory locations are adjacent */
-
+/* Return 1 if memory locations are adjacent. */
int
adjacent_mem_locations (a, b)
rtx a, b;
}
/* Return 1 if OP is a load multiple operation. It is known to be
- parallel and the first section will be tested. */
+ parallel and the first section will be tested. */
int
load_multiple_operation (op, mode)
rtx op;
- enum machine_mode mode;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
{
HOST_WIDE_INT count = XVECLEN (op, 0);
int dest_regno;
|| GET_CODE (XVECEXP (op, 0, 0)) != SET)
return 0;
- /* Check to see if this might be a write-back */
+ /* Check to see if this might be a write-back. */
if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
{
i++;
base = 1;
- /* Now check it more carefully */
+ /* Now check it more carefully. */
if (GET_CODE (SET_DEST (elt)) != REG
|| GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
|| REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
if (GET_CODE (elt) != SET
|| GET_CODE (SET_DEST (elt)) != REG
|| GET_MODE (SET_DEST (elt)) != SImode
- || REGNO (SET_DEST (elt)) != dest_regno + i - base
+ || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
|| GET_CODE (SET_SRC (elt)) != MEM
|| GET_MODE (SET_SRC (elt)) != SImode
|| GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
}
/* Return 1 if OP is a store multiple operation. It is known to be
- parallel and the first section will be tested. */
-
+ parallel and the first section will be tested. */
int
store_multiple_operation (op, mode)
rtx op;
- enum machine_mode mode;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
{
HOST_WIDE_INT count = XVECLEN (op, 0);
int src_regno;
|| GET_CODE (XVECEXP (op, 0, 0)) != SET)
return 0;
- /* Check to see if this might be a write-back */
+ /* Check to see if this might be a write-back. */
if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
{
i++;
base = 1;
- /* Now check it more carefully */
+ /* Now check it more carefully. */
if (GET_CODE (SET_DEST (elt)) != REG
|| GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
|| REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
if (GET_CODE (elt) != SET
|| GET_CODE (SET_SRC (elt)) != REG
|| GET_MODE (SET_SRC (elt)) != SImode
- || REGNO (SET_SRC (elt)) != src_regno + i - base
+ || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
|| GET_CODE (SET_DEST (elt)) != MEM
|| GET_MODE (SET_DEST (elt)) != SImode
|| GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
int
load_multiple_sequence (operands, nops, regs, base, load_offset)
- rtx *operands;
+ rtx * operands;
int nops;
- int *regs;
- int *base;
- HOST_WIDE_INT *load_offset;
+ int * regs;
+ int * base;
+ HOST_WIDE_INT * load_offset;
{
int unsorted_regs[4];
HOST_WIDE_INT unsorted_offsets[4];
}
else
{
- if (base_reg != REGNO (reg))
+ if (base_reg != (int) REGNO (reg))
/* Not addressed from the same base register. */
return 0;
if (unsorted_offsets[order[nops - 1]] == -4)
return 4; /* ldmdb */
- /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm if
- the offset isn't small enough */
+ /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
+ if the offset isn't small enough. The reason 2 ldrs are faster
+ is because these ARMs are able to do more than one cache access
+ in a single cycle. The ARM9 and StrongARM have Harvard caches,
+ whilst the ARM8 has a double bandwidth cache. This means that
+ these cores can do both an instruction fetch and a data fetch in
+ a single cycle, so the trick of calculating the address into a
+ scratch register (one of the result regs) and then doing a load
+ multiple actually becomes slower (and no smaller in code size).
+ That is the transformation
+
+ ldr rd1, [rbase + offset]
+ ldr rd2, [rbase + offset + 4]
+
+ to
+
+ add rd1, rbase, offset
+ ldmia rd1, {rd1, rd2}
+
+ produces worse code -- '3 cycles + any stalls on rd2' instead of
+ '2 cycles + any stalls on rd2'. On ARMs with only one cache
+ access per cycle, the first sequence could never complete in less
+ than 6 cycles, whereas the ldm sequence would only take 5 and
+ would make better use of sequential accesses if not hitting the
+ cache.
+
+ We cheat here and test 'arm_ld_sched' which we currently know to
+ only be true for the ARM8, ARM9 and StrongARM. If this ever
+ changes, then the test below needs to be reworked. */
if (nops == 2 && arm_ld_sched)
return 0;
char *
emit_ldm_seq (operands, nops)
- rtx *operands;
+ rtx * operands;
int nops;
{
int regs[4];
int
store_multiple_sequence (operands, nops, regs, base, load_offset)
- rtx *operands;
+ rtx * operands;
int nops;
- int *regs;
- int *base;
- HOST_WIDE_INT *load_offset;
+ int * regs;
+ int * base;
+ HOST_WIDE_INT * load_offset;
{
int unsorted_regs[4];
HOST_WIDE_INT unsorted_offsets[4];
{
if (i == 0)
{
- base_reg = REGNO(reg);
+ base_reg = REGNO (reg);
unsorted_regs[0] = (GET_CODE (operands[i]) == REG
? REGNO (operands[i])
: REGNO (SUBREG_REG (operands[i])));
}
else
{
- if (base_reg != REGNO (reg))
+ if (base_reg != (int) REGNO (reg))
/* Not addressed from the same base register. */
return 0;
char *
emit_stm_seq (operands, nops)
- rtx *operands;
+ rtx * operands;
int nops;
{
int regs[4];
int
multi_register_push (op, mode)
rtx op;
- enum machine_mode mode;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
{
if (GET_CODE (op) != PARALLEL
|| (GET_CODE (XVECEXP (op, 0, 0)) != SET)
}
\f
-/* Routines for use with attributes */
+/* Routines for use with attributes. */
/* Return nonzero if ATTR is a valid attribute for DECL.
- ATTRIBUTES are any existing attributes and ARGS are the arguments
- supplied with ATTR.
+ ATTRIBUTES are any existing attributes and ARGS are
+ the arguments supplied with ATTR.
Supported attributes:
- naked: don't output any prologue or epilogue code, the user is assumed
- to do the right thing. */
-
+ naked: don't output any prologue or epilogue code,
+ the user is assumed to do the right thing.
+*/
int
-arm_valid_machine_decl_attribute (decl, attributes, attr, args)
+arm_valid_machine_decl_attribute (decl, attr, args)
tree decl;
- tree attributes;
tree attr;
tree args;
{
if (TREE_CODE (func) != FUNCTION_DECL)
abort ();
-
+
a = lookup_attribute ("naked", DECL_MACHINE_ATTRIBUTES (func));
return a != NULL_TREE;
}
\f
-/* Routines for use in generating RTL */
-
+/* Routines for use in generating RTL. */
rtx
arm_gen_load_multiple (base_regno, count, from, up, write_back, unchanging_p,
in_struct_p, scalar_p)
int
arm_gen_movstrqi (operands)
- rtx *operands;
+ rtx * operands;
{
HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
int i;
/* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
if (out_words_to_go)
- {
- rtx sreg;
-
- mem = gen_rtx_MEM (SImode, src);
- RTX_UNCHANGING_P (mem) = src_unchanging_p;
- MEM_IN_STRUCT_P (mem) = src_in_struct_p;
- MEM_SCALAR_P (mem) = src_scalar_p;
- emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
- emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
-
- mem = gen_rtx_MEM (SImode, dst);
- RTX_UNCHANGING_P (mem) = dst_unchanging_p;
- MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
- MEM_SCALAR_P (mem) = dst_scalar_p;
- emit_move_insn (mem, sreg);
- emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
- in_words_to_go--;
-
- if (in_words_to_go) /* Sanity check */
- abort ();
- }
+ {
+ rtx sreg;
+
+ mem = gen_rtx_MEM (SImode, src);
+ RTX_UNCHANGING_P (mem) = src_unchanging_p;
+ MEM_IN_STRUCT_P (mem) = src_in_struct_p;
+ MEM_SCALAR_P (mem) = src_scalar_p;
+ emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
+ emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
+
+ mem = gen_rtx_MEM (SImode, dst);
+ RTX_UNCHANGING_P (mem) = dst_unchanging_p;
+ MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
+ MEM_SCALAR_P (mem) = dst_scalar_p;
+ emit_move_insn (mem, sreg);
+ emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
+ in_words_to_go--;
+
+ if (in_words_to_go) /* Sanity check */
+ abort ();
+ }
if (in_words_to_go)
{
if (part_bytes_reg == NULL)
abort ();
- /* The bytes we want are in the top end of the word */
+ /* The bytes we want are in the top end of the word. */
emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
GEN_INT (8 * (4 - last_bytes))));
part_bytes_reg = tmp;
MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
MEM_SCALAR_P (mem) = dst_scalar_p;
emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));
+
if (--last_bytes)
{
tmp = gen_reg_rtx (SImode);
MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
MEM_SCALAR_P (mem) = dst_scalar_p;
emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));
+
if (--last_bytes)
{
rtx tmp = gen_reg_rtx (SImode);
}
/* If we aren't allowed to generate unaligned addresses, then fail. */
- if (TARGET_SHORT_BY_BYTES
+ if (TARGET_MMU_TRAPS
&& ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))
return NULL;
}
static enum machine_mode
-select_dominance_cc_mode (op, x, y, cond_or)
- enum rtx_code op;
+select_dominance_cc_mode (x, y, cond_or)
rtx x;
rtx y;
HOST_WIDE_INT cond_or;
|| XEXP (x, 2) == const1_rtx)
&& GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
&& GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
- return select_dominance_cc_mode (op, XEXP (x, 0), XEXP (x, 1),
+ return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
INTVAL (XEXP (x, 2)));
if (GET_MODE (x) == QImode && (op == EQ || op == NE))
floating point compare: I don't think that it is needed on the arm. */
rtx
-gen_compare_reg (code, x, y, fp)
+gen_compare_reg (code, x, y)
enum rtx_code code;
rtx x, y;
- int fp;
{
enum machine_mode mode = SELECT_CC_MODE (code, x, y);
rtx cc_reg = gen_rtx_REG (mode, 24);
void
arm_reload_in_hi (operands)
- rtx *operands;
+ rtx * operands;
{
- rtx base = find_replacement (&XEXP (operands[1], 0));
+ rtx ref = operands[1];
+ rtx base, scratch;
+ HOST_WIDE_INT offset = 0;
+
+ if (GET_CODE (ref) == SUBREG)
+ {
+ offset = SUBREG_WORD (ref) * UNITS_PER_WORD;
+ if (BYTES_BIG_ENDIAN)
+ offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (ref)))
+ - MIN (UNITS_PER_WORD,
+ GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref)))));
+ ref = SUBREG_REG (ref);
+ }
+
+ if (GET_CODE (ref) == REG)
+ {
+ /* We have a pseudo which has been spilt onto the stack; there
+ are two cases here: the first where there is a simple
+ stack-slot replacement and a second where the stack-slot is
+ out of range, or is used as a subreg. */
+ if (reg_equiv_mem[REGNO (ref)])
+ {
+ ref = reg_equiv_mem[REGNO (ref)];
+ base = find_replacement (&XEXP (ref, 0));
+ }
+ else
+ /* The slot is out of range, or was dressed up in a SUBREG. */
+ base = reg_equiv_address[REGNO (ref)];
+ }
+ else
+ base = find_replacement (&XEXP (ref, 0));
- emit_insn (gen_zero_extendqisi2 (operands[2], gen_rtx_MEM (QImode, base)));
/* Handle the case where the address is too complex to be offset by 1. */
if (GET_CODE (base) == MINUS
|| (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
{
- rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[0]));
+ rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
base = base_plus;
}
+ else if (GET_CODE (base) == PLUS)
+ {
+ /* The addend must be CONST_INT, or we would have dealt with it above. */
+ HOST_WIDE_INT hi, lo;
+
+ offset += INTVAL (XEXP (base, 1));
+ base = XEXP (base, 0);
+
+ /* Rework the address into a legal sequence of insns. */
+ /* Valid range for lo is -4095 -> 4095 */
+ lo = (offset >= 0
+ ? (offset & 0xfff)
+ : -((-offset) & 0xfff));
+
+ /* Corner case, if lo is the max offset then we would be out of range
+ once we have added the additional 1 below, so bump the msb into the
+ pre-loading insn(s). */
+ if (lo == 4095)
+ lo &= 0x7ff;
+
+ hi = ((((offset - lo) & (HOST_WIDE_INT) 0xFFFFFFFFUL)
+ ^ (HOST_WIDE_INT) 0x80000000UL)
+ - (HOST_WIDE_INT) 0x80000000UL);
+
+ if (hi + lo != offset)
+ abort ();
+
+ if (hi != 0)
+ {
+ rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
+
+ /* Get the base address; addsi3 knows how to handle constants
+ that require more than one insn. */
+ emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
+ base = base_plus;
+ offset = lo;
+ }
+ }
+ scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
+ emit_insn (gen_zero_extendqisi2 (scratch,
+ gen_rtx_MEM (QImode,
+ plus_constant (base,
+ offset))));
emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
gen_rtx_MEM (QImode,
- plus_constant (base, 1))));
- if (BYTES_BIG_ENDIAN)
+ plus_constant (base,
+ offset + 1))));
+ if (! BYTES_BIG_ENDIAN)
emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
gen_rtx_IOR (SImode,
gen_rtx_ASHIFT
(SImode,
gen_rtx_SUBREG (SImode, operands[0], 0),
GEN_INT (8)),
- operands[2])));
+ scratch)));
else
emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
gen_rtx_IOR (SImode,
- gen_rtx_ASHIFT (SImode, operands[2],
+ gen_rtx_ASHIFT (SImode, scratch,
GEN_INT (8)),
gen_rtx_SUBREG (SImode, operands[0],
0))));
}
+/* Handle storing a half-word to memory during reload by synthesising as two
+ byte stores. Take care not to clobber the input values until after we
+ have moved them somewhere safe. This code assumes that if the DImode
+ scratch in operands[2] overlaps either the input value or output address
+ in some way, then that value must die in this insn (we absolutely need
+ two scratch registers for some corner cases). */
void
arm_reload_out_hi (operands)
- rtx *operands;
+ rtx * operands;
{
- rtx base = find_replacement (&XEXP (operands[0], 0));
+ rtx ref = operands[0];
+ rtx outval = operands[1];
+ rtx base, scratch;
+ HOST_WIDE_INT offset = 0;
- if (BYTES_BIG_ENDIAN)
+ if (GET_CODE (ref) == SUBREG)
{
- emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, 1)),
- gen_rtx_SUBREG (QImode, operands[1], 0)));
- emit_insn (gen_lshrsi3 (operands[2],
- gen_rtx_SUBREG (SImode, operands[1], 0),
- GEN_INT (8)));
- emit_insn (gen_movqi (gen_rtx_MEM (QImode, base),
- gen_rtx_SUBREG (QImode, operands[2], 0)));
+ offset = SUBREG_WORD (ref) * UNITS_PER_WORD;
+ if (BYTES_BIG_ENDIAN)
+ offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (ref)))
+ - MIN (UNITS_PER_WORD,
+ GET_MODE_SIZE (GET_MODE (SUBREG_REG (ref)))));
+ ref = SUBREG_REG (ref);
+ }
+
+
+ if (GET_CODE (ref) == REG)
+ {
+ /* We have a pseudo which has been spilt onto the stack; there
+ are two cases here: the first where there is a simple
+ stack-slot replacement and a second where the stack-slot is
+ out of range, or is used as a subreg. */
+ if (reg_equiv_mem[REGNO (ref)])
+ {
+ ref = reg_equiv_mem[REGNO (ref)];
+ base = find_replacement (&XEXP (ref, 0));
+ }
+ else
+ /* The slot is out of range, or was dressed up in a SUBREG. */
+ base = reg_equiv_address[REGNO (ref)];
}
else
+ base = find_replacement (&XEXP (ref, 0));
+
+ scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
+
+ /* Handle the case where the address is too complex to be offset by 1. */
+ if (GET_CODE (base) == MINUS
+ || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
{
- emit_insn (gen_movqi (gen_rtx_MEM (QImode, base),
- gen_rtx_SUBREG (QImode, operands[1], 0)));
- emit_insn (gen_lshrsi3 (operands[2],
- gen_rtx_SUBREG (SImode, operands[1], 0),
- GEN_INT (8)));
- emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, 1)),
- gen_rtx_SUBREG (QImode, operands[2], 0)));
+ rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
+
+ /* Be careful not to destroy OUTVAL. */
+ if (reg_overlap_mentioned_p (base_plus, outval))
+ {
+ /* Updating base_plus might destroy outval, see if we can
+ swap the scratch and base_plus. */
+ if (! reg_overlap_mentioned_p (scratch, outval))
+ {
+ rtx tmp = scratch;
+ scratch = base_plus;
+ base_plus = tmp;
+ }
+ else
+ {
+ rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
+
+ /* Be conservative and copy OUTVAL into the scratch now,
+ this should only be necessary if outval is a subreg
+ of something larger than a word. */
+ /* XXX Might this clobber base? I can't see how it can,
+ since scratch is known to overlap with OUTVAL, and
+ must be wider than a word. */
+ emit_insn (gen_movhi (scratch_hi, outval));
+ outval = scratch_hi;
+ }
+ }
+
+ emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
+ base = base_plus;
}
-}
-\f
-/* Routines for manipulation of the constant pool. */
-/* This is unashamedly hacked from the version in sh.c, since the problem is
- extremely similar. */
+ else if (GET_CODE (base) == PLUS)
+ {
+ /* The addend must be CONST_INT, or we would have dealt with it above. */
+ HOST_WIDE_INT hi, lo;
-/* Arm instructions cannot load a large constant into a register,
- constants have to come from a pc relative load. The reference of a pc
- relative load instruction must be less than 1k infront of the instruction.
- This means that we often have to dump a constant inside a function, and
- generate code to branch around it.
+ offset += INTVAL (XEXP (base, 1));
+ base = XEXP (base, 0);
- It is important to minimize this, since the branches will slow things
- down and make things bigger.
+ /* Rework the address into a legal sequence of insns. */
+ /* Valid range for lo is -4095 -> 4095 */
+ lo = (offset >= 0
+ ? (offset & 0xfff)
+ : -((-offset) & 0xfff));
- Worst case code looks like:
+ /* Corner case, if lo is the max offset then we would be out of range
+ once we have added the additional 1 below, so bump the msb into the
+ pre-loading insn(s). */
+ if (lo == 4095)
+ lo &= 0x7ff;
- ldr rn, L1
- b L2
- align
- L1: .long value
- L2:
- ..
+ hi = ((((offset - lo) & (HOST_WIDE_INT) 0xFFFFFFFFUL)
+ ^ (HOST_WIDE_INT) 0x80000000UL)
+ - (HOST_WIDE_INT) 0x80000000UL);
- ldr rn, L3
- b L4
- align
- L3: .long value
- L4:
- ..
+ if (hi + lo != offset)
+ abort ();
+
+ if (hi != 0)
+ {
+ rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
+
+ /* Be careful not to destroy OUTVAL. */
+ if (reg_overlap_mentioned_p (base_plus, outval))
+ {
+ /* Updating base_plus might destroy outval, see if we
+ can swap the scratch and base_plus. */
+ if (! reg_overlap_mentioned_p (scratch, outval))
+ {
+ rtx tmp = scratch;
+ scratch = base_plus;
+ base_plus = tmp;
+ }
+ else
+ {
+ rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
+
+ /* Be conservative and copy outval into scratch now,
+ this should only be necessary if outval is a
+ subreg of something larger than a word. */
+ /* XXX Might this clobber base? I can't see how it
+ can, since scratch is known to overlap with
+ outval. */
+ emit_insn (gen_movhi (scratch_hi, outval));
+ outval = scratch_hi;
+ }
+ }
- We fix this by performing a scan before scheduling, which notices which
- instructions need to have their operands fetched from the constant table
- and builds the table.
+ /* Get the base address; addsi3 knows how to handle constants
+ that require more than one insn. */
+ emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
+ base = base_plus;
+ offset = lo;
+ }
+ }
+ if (BYTES_BIG_ENDIAN)
+ {
+ emit_insn (gen_movqi (gen_rtx_MEM (QImode,
+ plus_constant (base, offset + 1)),
+ gen_rtx_SUBREG (QImode, outval, 0)));
+ emit_insn (gen_lshrsi3 (scratch,
+ gen_rtx_SUBREG (SImode, outval, 0),
+ GEN_INT (8)));
+ emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
+ gen_rtx_SUBREG (QImode, scratch, 0)));
+ }
+ else
+ {
+ emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
+ gen_rtx_SUBREG (QImode, outval, 0)));
+ emit_insn (gen_lshrsi3 (scratch,
+ gen_rtx_SUBREG (SImode, outval, 0),
+ GEN_INT (8)));
+ emit_insn (gen_movqi (gen_rtx_MEM (QImode,
+ plus_constant (base, offset + 1)),
+ gen_rtx_SUBREG (QImode, scratch, 0)));
+ }
+}
+\f
+/* Routines for manipulation of the constant pool. */
- The algorithm is:
+/* Arm instructions cannot load a large constant directly into a
+ register; they have to come from a pc relative load. The constant
+ must therefore be placed in the addressable range of the pc
+ relative load. Depending on the precise pc relative load
+ instruction the range is somewhere between 256 bytes and 4k. This
+ means that we often have to dump a constant inside a function, and
+ generate code to branch around it.
- scan, find an instruction which needs a pcrel move. Look forward, find th
- last barrier which is within MAX_COUNT bytes of the requirement.
- If there isn't one, make one. Process all the instructions between
- the find and the barrier.
+ It is important to minimize this, since the branches will slow
+ things down and make the code larger.
- In the above example, we can tell that L3 is within 1k of L1, so
- the first move can be shrunk from the 2 insn+constant sequence into
- just 1 insn, and the constant moved to L3 to make:
+ Normally we can hide the table after an existing unconditional
+ branch so that there is no interruption of the flow, but in the
+ worst case the code looks like this:
ldr rn, L1
- ..
+ ...
+ b L2
+ align
+ L1: .long value
+ L2:
+ ...
+
ldr rn, L3
+ ...
b L4
align
- L1: .long value
L3: .long value
L4:
-
- Then the second move becomes the target for the shortening process.
-
- */
+ ...
+
+ We fix this by performing a scan after scheduling, which notices
+ which instructions need to have their operands fetched from the
+ constant table and builds the table.
+
+ The algorithm starts by building a table of all the constants that
+ need fixing up and all the natural barriers in the function (places
+ where a constant table can be dropped without breaking the flow).
+ For each fixup we note how far the pc-relative replacement will be
+ able to reach and the offset of the instruction into the function.
+
+ Having built the table we then group the fixes together to form
+ tables that are as large as possible (subject to addressing
+ constraints) and emit each table of constants after the last
+ barrier that is within range of all the instructions in the group.
+ If a group does not contain a barrier, then we forcibly create one
+ by inserting a jump instruction into the flow. Once the table has
+ been inserted, the insns are then modified to reference the
+ relevant entry in the pool.
+
+ Possible enhancements to the algorithm (not implemented) are:
+
+ 1) ARM instructions (but not Thumb) can use negative offsets, so we
+ could reference back to a previous pool rather than forwards to a
+ new one. For large functions this may reduce the number of pools
+ required.
+
+ 2) For some processors and object formats, there may be benefit in
+ aligning the pools to the start of cache lines; this alignment
+ would need to be taken into account when calculating addressability
+ of a pool. */
typedef struct
{
rtx value; /* Value in table */
HOST_WIDE_INT next_offset;
enum machine_mode mode; /* Mode of value */
-} pool_node;
+} minipool_node;
/* The maximum number of constants that can fit into one pool, since
- the pc relative range is 0...1020 bytes and constants are at least 4
- bytes long */
-
-#define MAX_POOL_SIZE (1020/4)
-static pool_node pool_vector[MAX_POOL_SIZE];
-static int pool_size;
-static rtx pool_vector_label;
+ the pc relative range is 0...4092 bytes and constants are at least 4
+ bytes long. */
+#define MAX_MINIPOOL_SIZE (4092/4)
+static minipool_node minipool_vector[MAX_MINIPOOL_SIZE];
+static int minipool_size;
+static rtx minipool_vector_label;
/* Add a constant to the pool and return its offset within the current
pool.
ADDRESS_ONLY will be non-zero if we really want the address of such
a constant, not the constant itself. */
static HOST_WIDE_INT
-add_constant (x, mode, address_only)
+add_minipool_constant (x, mode)
rtx x;
enum machine_mode mode;
- int * address_only;
{
int i;
HOST_WIDE_INT offset;
-
- * address_only = 0;
- if (mode == SImode && GET_CODE (x) == MEM && CONSTANT_P (XEXP (x, 0))
- && CONSTANT_POOL_ADDRESS_P (XEXP (x, 0)))
- x = get_pool_constant (XEXP (x, 0));
- else if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P(x))
- {
- *address_only = 1;
- mode = get_pool_mode (x);
- x = get_pool_constant (x);
- }
-#ifndef AOF_ASSEMBLER
- else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == 3)
- x = XVECEXP (x, 0, 0);
-#endif
-
-#ifdef AOF_ASSEMBLER
- /* PIC Symbol references need to be converted into offsets into the
- based area. */
- if (flag_pic && GET_CODE (x) == SYMBOL_REF)
- x = aof_pic_entry (x);
-#endif /* AOF_ASSEMBLER */
-
- /* First see if we've already got it */
- for (i = 0; i < pool_size; i++)
+ /* First, see if we've already got it. */
+ for (i = 0; i < minipool_size; i++)
{
- if (GET_CODE (x) == pool_vector[i].value->code
- && mode == pool_vector[i].mode)
+ if (GET_CODE (x) == minipool_vector[i].value->code
+ && mode == minipool_vector[i].mode)
{
if (GET_CODE (x) == CODE_LABEL)
{
- if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
+ if (XINT (x, 3) != XINT (minipool_vector[i].value, 3))
continue;
}
- if (rtx_equal_p (x, pool_vector[i].value))
- return pool_vector[i].next_offset - GET_MODE_SIZE (mode);
+ if (rtx_equal_p (x, minipool_vector[i].value))
+ return minipool_vector[i].next_offset - GET_MODE_SIZE (mode);
}
}
- /* Need a new one */
- pool_vector[pool_size].next_offset = GET_MODE_SIZE (mode);
+ /* Need a new one. */
+ minipool_vector[minipool_size].next_offset = GET_MODE_SIZE (mode);
offset = 0;
- if (pool_size == 0)
- pool_vector_label = gen_label_rtx ();
+ if (minipool_size == 0)
+ minipool_vector_label = gen_label_rtx ();
else
- pool_vector[pool_size].next_offset
- += (offset = pool_vector[pool_size - 1].next_offset);
+ minipool_vector[minipool_size].next_offset
+ += (offset = minipool_vector[minipool_size - 1].next_offset);
- pool_vector[pool_size].value = x;
- pool_vector[pool_size].mode = mode;
- pool_size++;
+ minipool_vector[minipool_size].value = x;
+ minipool_vector[minipool_size].mode = mode;
+ minipool_size++;
return offset;
}
-/* Output the literal table */
+/* Output the literal table. */
static void
-dump_table (scan)
+dump_minipool (scan)
rtx scan;
{
int i;
scan = emit_label_after (gen_label_rtx (), scan);
scan = emit_insn_after (gen_align_4 (), scan);
- scan = emit_label_after (pool_vector_label, scan);
+ scan = emit_label_after (minipool_vector_label, scan);
- for (i = 0; i < pool_size; i++)
+ for (i = 0; i < minipool_size; i++)
{
- pool_node *p = pool_vector + i;
+ minipool_node *p = minipool_vector + i;
switch (GET_MODE_SIZE (p->mode))
{
scan = emit_insn_after (gen_consttable_end (), scan);
scan = emit_barrier_after (scan);
- pool_size = 0;
-}
-
-/* Non zero if the src operand needs to be fixed up */
-static int
-fixit (src, mode, destreg)
- rtx src;
- enum machine_mode mode;
- int destreg;
-{
- if (CONSTANT_P (src))
- {
- if (GET_CODE (src) == CONST_INT)
- return (! const_ok_for_arm (INTVAL (src))
- && ! const_ok_for_arm (~INTVAL (src)));
- if (GET_CODE (src) == CONST_DOUBLE)
- return (GET_MODE (src) == VOIDmode
- || destreg < 16
- || (! const_double_rtx_ok_for_fpu (src)
- && ! neg_const_double_rtx_ok_for_fpu (src)));
- return symbol_mentioned_p (src);
- }
-#ifndef AOF_ASSEMBLER
- else if (GET_CODE (src) == UNSPEC && XINT (src, 1) == 3)
- return 1;
-#endif
- else
- return (mode == SImode && GET_CODE (src) == MEM
- && GET_CODE (XEXP (src, 0)) == SYMBOL_REF
- && CONSTANT_POOL_ADDRESS_P (XEXP (src, 0)));
+ minipool_size = 0;
}
-/* Find the last barrier less than MAX_COUNT bytes from FROM, or create one. */
+/* Find the last barrier less than MAX_COUNT bytes from FROM, or
+ create one. */
static rtx
find_barrier (from, max_count)
rtx from;
if (GET_CODE (from) == BARRIER)
found_barrier = from;
- /* Count the length of this insn */
- if (GET_CODE (from) == INSN
- && GET_CODE (PATTERN (from)) == SET
- && CONSTANT_P (SET_SRC (PATTERN (from)))
- && CONSTANT_POOL_ADDRESS_P (SET_SRC (PATTERN (from))))
- count += 8;
- /* Handle table jumps as a single entity. */
- else if (GET_CODE (from) == JUMP_INSN
- && JUMP_LABEL (from) != 0
- && ((tmp = next_real_insn (JUMP_LABEL (from)))
- == next_real_insn (from))
- && tmp != NULL
- && GET_CODE (tmp) == JUMP_INSN
- && (GET_CODE (PATTERN (tmp)) == ADDR_VEC
- || GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC))
+ /* Count the length of this insn. */
+ if (GET_CODE (from) == JUMP_INSN
+ && JUMP_LABEL (from) != 0
+ && ((tmp = next_real_insn (JUMP_LABEL (from)))
+ == next_real_insn (from))
+ && tmp != NULL
+ && GET_CODE (tmp) == JUMP_INSN
+ && (GET_CODE (PATTERN (tmp)) == ADDR_VEC
+ || GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC))
{
int elt = GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC ? 1 : 0;
count += (get_attr_length (from)
return found_barrier;
}
-/* Non zero if the insn is a move instruction which needs to be fixed. */
-static int
-broken_move (insn)
+struct minipool_fixup
+{
+ struct minipool_fixup *next;
+ rtx insn;
+ int address;
+ rtx *loc;
+ enum machine_mode mode;
+ rtx value;
+ int range;
+};
+
+struct minipool_fixup *minipool_fix_head;
+struct minipool_fixup *minipool_fix_tail;
+
+static void
+push_minipool_barrier (insn, address)
rtx insn;
+ int address;
{
- if (!INSN_DELETED_P (insn)
- && GET_CODE (insn) == INSN
- && GET_CODE (PATTERN (insn)) == SET)
- {
- rtx pat = PATTERN (insn);
- rtx src = SET_SRC (pat);
- rtx dst = SET_DEST (pat);
- int destreg;
- enum machine_mode mode = GET_MODE (dst);
+ struct minipool_fixup *fix
+ = (struct minipool_fixup *) oballoc (sizeof (struct minipool_fixup));
- if (dst == pc_rtx)
- return 0;
+ fix->insn = insn;
+ fix->address = address;
- if (GET_CODE (dst) == REG)
- destreg = REGNO (dst);
- else if (GET_CODE (dst) == SUBREG && GET_CODE (SUBREG_REG (dst)) == REG)
- destreg = REGNO (SUBREG_REG (dst));
- else
- return 0;
+ fix->next = NULL;
+ if (minipool_fix_head != NULL)
+ minipool_fix_tail->next = fix;
+ else
+ minipool_fix_head = fix;
+
+ minipool_fix_tail = fix;
+}
+
+static void
+push_minipool_fix (insn, address, loc, mode, value)
+ rtx insn;
+ int address;
+ rtx *loc;
+ enum machine_mode mode;
+ rtx value;
+{
+ struct minipool_fixup *fix
+ = (struct minipool_fixup *) oballoc (sizeof (struct minipool_fixup));
+
+#ifdef AOF_ASSEMBLER
+ /* PIC symbol refereneces need to be converted into offsets into the
+ based area. */
+ if (flag_pic && GET_MODE == SYMBOL_REF)
+ value = aof_pic_entry (value);
+#endif /* AOF_ASSEMBLER */
+
+ fix->insn = insn;
+ fix->address = address;
+ fix->loc = loc;
+ fix->mode = mode;
+ fix->value = value;
+ fix->range = get_attr_pool_range (insn);
+
+ /* If an insn doesn't have a range defined for it, then it isn't
+ expecting to be reworked by this code. Better to abort now than
+ to generate duff assembly code. */
+ if (fix->range == 0)
+ abort ();
+
+ /* Add it to the chain of fixes. */
+ fix->next = NULL;
+ if (minipool_fix_head != NULL)
+ minipool_fix_tail->next = fix;
+ else
+ minipool_fix_head = fix;
- return fixit (src, mode, destreg);
+ minipool_fix_tail = fix;
+}
+
+static void
+note_invalid_constants (insn, address)
+ rtx insn;
+ int address;
+{
+ int opno;
+
+ /* Extract the operands of the insn. */
+ extract_insn(insn);
+
+ /* Find the alternative selected. */
+ if (! constrain_operands (1))
+ fatal_insn_not_found (insn);
+
+ /* Preprocess the constraints, to extract some useful information. */
+ preprocess_constraints ();
+
+ for (opno = 0; opno < recog_data.n_operands; opno++)
+ {
+ /* Things we need to fix can only occur in inputs. */
+ if (recog_data.operand_type[opno] != OP_IN)
+ continue;
+
+ /* If this alternative is a memory reference, then any mention
+ of constants in this alternative is really to fool reload
+ into allowing us to accept one there. We need to fix them up
+ now so that we output the right code. */
+ if (recog_op_alt[opno][which_alternative].memory_ok)
+ {
+ rtx op = recog_data.operand[opno];
+
+ if (CONSTANT_P (op))
+ push_minipool_fix (insn, address, recog_data.operand_loc[opno],
+ recog_data.operand_mode[opno], op);
+#ifndef AOF_ASSEMBLER
+ else if (GET_CODE (op) == UNSPEC && XINT (op, 1) == 3)
+ push_minipool_fix (insn, address, recog_data.operand_loc[opno],
+ recog_data.operand_mode[opno],
+ XVECEXP (op, 0, 0));
+#endif
+ else if (recog_data.operand_mode[opno] == SImode
+ && GET_CODE (op) == MEM
+ && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
+ && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
+ push_minipool_fix (insn, address, recog_data.operand_loc[opno],
+ recog_data.operand_mode[opno],
+ get_pool_constant (XEXP (op, 0)));
+ }
}
- return 0;
}
void
rtx first;
{
rtx insn;
- int count_size;
-
-#if 0
- /* The ldr instruction can work with up to a 4k offset, and most constants
- will be loaded with one of these instructions; however, the adr
- instruction and the ldf instructions only work with a 1k offset. This
- code needs to be rewritten to use the 4k offset when possible, and to
- adjust when a 1k offset is needed. For now we just use a 1k offset
- from the start. */
- count_size = 4000;
-
- /* Floating point operands can't work further than 1024 bytes from the
- PC, so to make things simple we restrict all loads for such functions.
- */
- if (TARGET_HARD_FLOAT)
- {
- int regno;
-
- for (regno = 16; regno < 24; regno++)
- if (regs_ever_live[regno])
- {
- count_size = 1000;
- break;
- }
- }
-#else
- count_size = 1000;
-#endif /* 0 */
+ int address = 0;
+ struct minipool_fixup *fix;
+
+ minipool_fix_head = minipool_fix_tail = NULL;
- for (insn = first; insn; insn = NEXT_INSN (insn))
+ /* The first insn must always be a note, or the code below won't
+ scan it properly. */
+ if (GET_CODE (first) != NOTE)
+ abort ();
+
+ /* Scan all the insns and record the operands that will need fixing. */
+ for (insn = next_nonnote_insn (first); insn; insn = next_nonnote_insn (insn))
{
- if (broken_move (insn))
- {
- /* This is a broken move instruction, scan ahead looking for
- a barrier to stick the constant table behind */
- rtx scan;
- rtx barrier = find_barrier (insn, count_size);
- /* Now find all the moves between the points and modify them */
- for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
+ if (GET_CODE (insn) == BARRIER)
+ push_minipool_barrier(insn, address);
+ else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN
+ || GET_CODE (insn) == JUMP_INSN)
+ {
+ rtx table;
+
+ note_invalid_constants (insn, address);
+ address += get_attr_length (insn);
+ /* If the insn is a vector jump, add the size of the table
+ and skip the table. */
+ if (GET_CODE (insn) == JUMP_INSN
+ && JUMP_LABEL (insn) != NULL
+ && ((table = next_real_insn (JUMP_LABEL (insn)))
+ == next_real_insn (insn))
+ && table != NULL
+ && GET_CODE (table) == JUMP_INSN
+ && (GET_CODE (PATTERN (table)) == ADDR_VEC
+ || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
{
- if (broken_move (scan))
- {
- /* This is a broken move instruction, add it to the pool */
- rtx pat = PATTERN (scan);
- rtx src = SET_SRC (pat);
- rtx dst = SET_DEST (pat);
- enum machine_mode mode = GET_MODE (dst);
- HOST_WIDE_INT offset;
- rtx newinsn = scan;
- rtx newsrc;
- rtx addr;
- int scratch;
- int address_only;
-
- /* If this is an HImode constant load, convert it into
- an SImode constant load. Since the register is always
- 32 bits this is safe. We have to do this, since the
- load pc-relative instruction only does a 32-bit load. */
- if (mode == HImode)
- {
- mode = SImode;
- if (GET_CODE (dst) != REG)
- abort ();
- PUT_MODE (dst, SImode);
- }
+ int elt = GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC ? 1 : 0;
- offset = add_constant (src, mode, &address_only);
- addr = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
- pool_vector_label),
- offset);
-
- /* If we only want the address of the pool entry, or
- for wide moves to integer regs we need to split
- the address calculation off into a separate insn.
- If necessary, the load can then be done with a
- load-multiple. This is safe, since we have
- already noted the length of such insns to be 8,
- and we are immediately over-writing the scratch
- we have grabbed with the final result. */
- if ((address_only || GET_MODE_SIZE (mode) > 4)
- && (scratch = REGNO (dst)) < 16)
- {
- rtx reg;
+ address += GET_MODE_SIZE (SImode) * XVECLEN (PATTERN (table),
+ elt);
+ insn = table;
+ }
+ }
+ }
- if (mode == SImode)
- reg = dst;
- else
- reg = gen_rtx_REG (SImode, scratch);
+ /* Now scan the fixups and perform the required changes. */
+ for (fix = minipool_fix_head; fix; fix = fix->next)
+ {
+ struct minipool_fixup *ftmp;
+ struct minipool_fixup *last_barrier = NULL;
+ int max_range;
+ rtx barrier;
+ struct minipool_fixup *this_fix;
+ int new_minipool_size = 0;
+
+ /* Skip any further barriers before the next fix. */
+ while (fix && GET_CODE (fix->insn) == BARRIER)
+ fix = fix->next;
+
+ if (fix == NULL)
+ break;
- newinsn = emit_insn_after (gen_movaddr (reg, addr),
- newinsn);
- addr = reg;
- }
+ ftmp = fix;
+ max_range = fix->address + fix->range;
- if (! address_only)
- {
- newsrc = gen_rtx_MEM (mode, addr);
-
- /* XXX Fixme -- I think the following is bogus. */
- /* Build a jump insn wrapper around the move instead
- of an ordinary insn, because we want to have room for
- the target label rtx in fld[7], which an ordinary
- insn doesn't have. */
- newinsn
- = emit_jump_insn_after (gen_rtx_SET (VOIDmode, dst,
- newsrc),
- newinsn);
- JUMP_LABEL (newinsn) = pool_vector_label;
-
- /* But it's still an ordinary insn */
- PUT_CODE (newinsn, INSN);
- }
+ /* Find all the other fixes that can live in the same pool. */
+ while (ftmp->next && ftmp->next->address < max_range
+ && (GET_CODE (ftmp->next->insn) == BARRIER
+ /* Ensure we can reach the constant inside the pool. */
+ || ftmp->next->range > new_minipool_size))
+ {
+ ftmp = ftmp->next;
+ if (GET_CODE (ftmp->insn) == BARRIER)
+ last_barrier = ftmp;
+ else
+ {
+ /* Does this fix constrain the range we can search? */
+ if (ftmp->address + ftmp->range - new_minipool_size < max_range)
+ max_range = ftmp->address + ftmp->range - new_minipool_size;
- /* Kill old insn */
- delete_insn (scan);
- scan = newinsn;
- }
+ new_minipool_size += GET_MODE_SIZE (ftmp->mode);
}
- dump_table (barrier);
- insn = scan;
}
+
+ /* If we found a barrier, drop back to that; any fixes that we could
+ have reached but come after the barrier will now go in the next
+ mini-pool. */
+ if (last_barrier != NULL)
+ {
+ barrier = last_barrier->insn;
+ ftmp = last_barrier;
+ }
+ /* ftmp is last fix that we can fit into this pool and we
+ failed to find a barrier that we could use. Insert a new
+ barrier in the code and arrange to jump around it. */
+ else
+ {
+ /* Check that there isn't another fix that is in range that
+ we couldn't fit into this pool because the pool was
+ already too large: we need to put the pool before such an
+ instruction. */
+ if (ftmp->next && ftmp->next->address < max_range)
+ max_range = ftmp->address;
+
+ barrier = find_barrier (ftmp->insn, max_range - ftmp->address);
+ }
+
+ /* Scan over the fixes we have identified for this pool, fixing them
+ up and adding the constants to the pool itself. */
+ for (this_fix = fix; this_fix && ftmp->next != this_fix;
+ this_fix = this_fix->next)
+ if (GET_CODE (this_fix->insn) != BARRIER)
+ {
+ int offset = add_minipool_constant (this_fix->value,
+ this_fix->mode);
+ rtx addr
+ = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
+ minipool_vector_label),
+ offset);
+ *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
+ }
+
+ dump_minipool (barrier);
+ fix = ftmp;
}
+
+ /* From now on we must synthesize any constants that we can't handle
+ directly. This can happen if the RTL gets split during final
+ instruction generation. */
+ after_arm_reorg = 1;
}
\f
/* If the rtx is the correct value then return the string of the number.
In this way we can ensure that valid double constants are generated even
- when cross compiling. */
+ when cross compiling. */
char *
fp_immediate_constant (x)
rtx x;
/* As for fp_immediate_constant, but value is passed directly, not in rtx. */
static char *
fp_const_from_val (r)
- REAL_VALUE_TYPE *r;
+ REAL_VALUE_TYPE * r;
{
int i;
must follow the register list. */
void
-print_multi_reg (stream, instr, mask, hat)
- FILE *stream;
- char *instr;
- int mask, hat;
+print_multi_reg (stream, instr, reg, mask, hat)
+ FILE * stream;
+ char * instr;
+ int reg;
+ int mask;
+ int hat;
{
int i;
int not_first = FALSE;
fputc ('\t', stream);
- fprintf (stream, instr, REGISTER_PREFIX);
+ asm_fprintf (stream, instr, reg);
fputs (", {", stream);
+
for (i = 0; i < 16; i++)
if (mask & (1 << i))
{
if (not_first)
fprintf (stream, ", ");
- fprintf (stream, "%s%s", REGISTER_PREFIX, reg_names[i]);
+
+ asm_fprintf (stream, "%r", i);
not_first = TRUE;
}
fprintf (stream, "}%s\n", hat ? "^" : "");
}
-/* Output a 'call' insn. */
+/* Output a 'call' insn. */
char *
output_call (operands)
- rtx *operands;
+ rtx * operands;
{
- /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
+ /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
- if (REGNO (operands[0]) == 14)
+ if (REGNO (operands[0]) == LR_REGNUM)
{
- operands[0] = gen_rtx_REG (SImode, 12);
+ operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
output_asm_insn ("mov%?\t%0, %|lr", operands);
}
+
output_asm_insn ("mov%?\t%|lr, %|pc", operands);
- if (TARGET_THUMB_INTERWORK)
+ if (TARGET_INTERWORK)
output_asm_insn ("bx%?\t%0", operands);
else
output_asm_insn ("mov%?\t%|pc, %0", operands);
static int
eliminate_lr2ip (x)
- rtx *x;
+ rtx * x;
{
int something_changed = 0;
- rtx x0 = *x;
+ rtx x0 = * x;
int code = GET_CODE (x0);
register int i, j;
- register char *fmt;
+ register const char * fmt;
switch (code)
{
case REG:
- if (REGNO (x0) == 14)
+ if (REGNO (x0) == LR_REGNUM)
{
- *x = gen_rtx_REG (SImode, 12);
+ *x = gen_rtx_REG (SImode, IP_REGNUM);
return 1;
}
return 0;
default:
- /* Scan through the sub-elements and change any references there */
+ /* Scan through the sub-elements and change any references there. */
fmt = GET_RTX_FORMAT (code);
+
for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
if (fmt[i] == 'e')
something_changed |= eliminate_lr2ip (&XEXP (x0, i));
else if (fmt[i] == 'E')
for (j = 0; j < XVECLEN (x0, i); j++)
something_changed |= eliminate_lr2ip (&XVECEXP (x0, i, j));
+
return something_changed;
}
}
-/* Output a 'call' insn that is a reference in memory. */
+/* Output a 'call' insn that is a reference in memory. */
char *
output_call_mem (operands)
- rtx *operands;
+ rtx * operands;
{
- operands[0] = copy_rtx (operands[0]); /* Be ultra careful */
- /* Handle calls using lr by using ip (which may be clobbered in subr anyway).
- */
+ operands[0] = copy_rtx (operands[0]); /* Be ultra careful. */
+ /* Handle calls using lr by using ip (which may be clobbered in subr anyway). */
if (eliminate_lr2ip (&operands[0]))
output_asm_insn ("mov%?\t%|ip, %|lr", operands);
- if (TARGET_THUMB_INTERWORK)
+ if (TARGET_INTERWORK)
{
output_asm_insn ("ldr%?\t%|ip, %0", operands);
output_asm_insn ("mov%?\t%|lr, %|pc", operands);
char *
output_mov_long_double_fpu_from_arm (operands)
- rtx *operands;
+ rtx * operands;
{
int arm_reg0 = REGNO (operands[1]);
rtx ops[3];
- if (arm_reg0 == 12)
- abort();
+ if (arm_reg0 == IP_REGNUM)
+ abort ();
ops[0] = gen_rtx_REG (SImode, arm_reg0);
ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
+
return "";
}
char *
output_mov_long_double_arm_from_fpu (operands)
- rtx *operands;
+ rtx * operands;
{
int arm_reg0 = REGNO (operands[0]);
rtx ops[3];
- if (arm_reg0 == 12)
- abort();
+ if (arm_reg0 == IP_REGNUM)
+ abort ();
ops[0] = gen_rtx_REG (SImode, arm_reg0);
ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
OPERANDS[1] is the source. */
char *
output_mov_long_double_arm_from_arm (operands)
- rtx *operands;
+ rtx * operands;
{
- /* We have to be careful here because the two might overlap */
+ /* We have to be careful here because the two might overlap. */
int dest_start = REGNO (operands[0]);
int src_start = REGNO (operands[1]);
rtx ops[2];
char *
output_mov_double_fpu_from_arm (operands)
- rtx *operands;
+ rtx * operands;
{
int arm_reg0 = REGNO (operands[1]);
rtx ops[2];
- if (arm_reg0 == 12)
- abort();
+ if (arm_reg0 == IP_REGNUM)
+ abort ();
+
ops[0] = gen_rtx_REG (SImode, arm_reg0);
ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
char *
output_mov_double_arm_from_fpu (operands)
- rtx *operands;
+ rtx * operands;
{
int arm_reg0 = REGNO (operands[0]);
rtx ops[2];
- if (arm_reg0 == 12)
- abort();
+ if (arm_reg0 == IP_REGNUM)
+ abort ();
ops[0] = gen_rtx_REG (SImode, arm_reg0);
ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
char *
output_move_double (operands)
- rtx *operands;
+ rtx * operands;
{
enum rtx_code code0 = GET_CODE (operands[0]);
enum rtx_code code1 = GET_CODE (operands[1]);
int reg0 = REGNO (operands[0]);
otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
+
if (code1 == REG)
{
int reg1 = REGNO (operands[1]);
- if (reg1 == 12)
- abort();
+ if (reg1 == IP_REGNUM)
+ abort ();
- /* Ensure the second source is not overwritten */
+ /* Ensure the second source is not overwritten. */
if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
- output_asm_insn("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
+ output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
else
- output_asm_insn("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
+ output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
}
else if (code1 == CONST_DOUBLE)
{
otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
}
+
output_mov_immediate (operands);
output_mov_immediate (otherops);
}
operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
}
#else
- /* Sign extend the intval into the high-order word */
+ /* Sign extend the intval into the high-order word. */
if (WORDS_BIG_ENDIAN)
{
otherops[1] = operands[1];
break;
case PRE_INC:
- abort (); /* Should never happen now */
+ abort (); /* Should never happen now. */
break;
case PRE_DEC:
break;
case POST_DEC:
- abort (); /* Should never happen now */
+ abort (); /* Should never happen now. */
break;
case LABEL_REF:
break;
default:
- if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1)))
+ if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
+ GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
{
otherops[0] = operands[0];
otherops[1] = XEXP (XEXP (operands[1], 0), 0);
}
else
output_asm_insn ("sub%?\t%0, %1, %2", otherops);
+
return "ldm%?ia\t%0, %M0";
}
else
}
}
else
- abort(); /* Constraints should prevent this */
+ abort (); /* Constraints should prevent this. */
}
else if (code0 == MEM && code1 == REG)
{
- if (REGNO (operands[1]) == 12)
- abort();
+ if (REGNO (operands[1]) == IP_REGNUM)
+ abort ();
switch (GET_CODE (XEXP (operands[0], 0)))
{
break;
case PRE_INC:
- abort (); /* Should never happen now */
+ abort (); /* Should never happen now. */
break;
case PRE_DEC:
break;
case POST_DEC:
- abort (); /* Should never happen now */
+ abort (); /* Should never happen now. */
break;
case PLUS:
}
}
else
- abort(); /* Constraints should prevent this */
+ abort (); /* Constraints should prevent this */
return "";
}
char *
output_mov_immediate (operands)
- rtx *operands;
+ rtx * operands;
{
HOST_WIDE_INT n = INTVAL (operands[1]);
int n_ones = 0;
return "";
}
- /* If all else fails, make it out of ORRs or BICs as appropriate. */
+ /* If all else fails, make it out of ORRs or BICs as appropriate. */
for (i=0; i < 32; i++)
if (n & 1 << i)
n_ones++;
- if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
+ if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
output_multi_immediate(operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1,
~n);
else
char *
output_add_immediate (operands)
- rtx *operands;
+ rtx * operands;
{
HOST_WIDE_INT n = INTVAL (operands[2]);
static char *
output_multi_immediate (operands, instr1, instr2, immed_op, n)
- rtx *operands;
- char *instr1, *instr2;
+ rtx * operands;
+ char * instr1, * instr2;
int immed_op;
HOST_WIDE_INT n;
{
if (n == 0)
{
operands[immed_op] = const0_rtx;
- output_asm_insn (instr1, operands); /* Quick and easy output */
+ output_asm_insn (instr1, operands); /* Quick and easy output. */
}
else
{
int i;
char *instr = instr1;
- /* Note that n is never zero here (which would give no output) */
+ /* Note that n is never zero here (which would give no output). */
for (i = 0; i < 32; i += 2)
{
if (n & (3 << i))
for the operation code. The returned result should not be overwritten.
OP is the rtx code of the shift.
On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
- shift. */
+ shift. */
static char *
shift_op (op, amountp)
rtx op;
HOST_WIDE_INT *amountp;
{
- char *mnem;
+ char * mnem;
enum rtx_code code = GET_CODE (op);
if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
}
-/* Obtain the shift from the POWER of two. */
-
+/* Obtain the shift from the POWER of two. */
static HOST_WIDE_INT
int_log2 (power)
HOST_WIDE_INT power;
/* Output a .ascii pseudo-op, keeping track of lengths. This is because
/bin/as is horribly restrictive. */
+#define MAX_ASCII_LEN 51
void
output_ascii_pseudo_op (stream, p, len)
- FILE *stream;
- unsigned char *p;
+ FILE * stream;
+ const unsigned char * p;
int len;
{
int i;
- int len_so_far = 1000;
- int chars_so_far = 0;
+ int len_so_far = 0;
+ fputs ("\t.ascii\t\"", stream);
+
for (i = 0; i < len; i++)
{
register int c = p[i];
- if (len_so_far > 50)
+ if (len_so_far >= MAX_ASCII_LEN)
{
- if (chars_so_far)
- fputs ("\"\n", stream);
- fputs ("\t.ascii\t\"", stream);
+ fputs ("\"\n\t.ascii\t\"", stream);
len_so_far = 0;
- chars_so_far = 0;
}
- if (c == '\"' || c == '\\')
+ switch (c)
{
- putc('\\', stream);
- len_so_far++;
- }
+ case TARGET_TAB:
+ fputs ("\\t", stream);
+ len_so_far += 2;
+ break;
+
+ case TARGET_FF:
+ fputs ("\\f", stream);
+ len_so_far += 2;
+ break;
+
+ case TARGET_BS:
+ fputs ("\\b", stream);
+ len_so_far += 2;
+ break;
+
+ case TARGET_CR:
+ fputs ("\\r", stream);
+ len_so_far += 2;
+ break;
+
+ case TARGET_NEWLINE:
+ fputs ("\\n", stream);
+ c = p [i + 1];
+ if ((c >= ' ' && c <= '~')
+ || c == TARGET_TAB)
+ /* This is a good place for a line break. */
+ len_so_far = MAX_ASCII_LEN;
+ else
+ len_so_far += 2;
+ break;
+
+ case '\"':
+ case '\\':
+ putc ('\\', stream);
+ len_so_far ++;
+ /* drop through. */
- if (c >= ' ' && c < 0177)
- {
- putc (c, stream);
- len_so_far++;
- }
- else
- {
- fprintf (stream, "\\%03o", c);
- len_so_far +=4;
+ default:
+ if (c >= ' ' && c <= '~')
+ {
+ putc (c, stream);
+ len_so_far ++;
+ }
+ else
+ {
+ fprintf (stream, "\\%03o", c);
+ len_so_far += 4;
+ }
+ break;
}
-
- chars_so_far++;
}
fputs ("\"\n", stream);
NOTE: This code does not check for side-effect expressions in a SET_SRC:
such a check should not be needed because these only update an existing
value within a register; the register must still be set elsewhere within
- the function. */
-
+ the function. */
static int
pattern_really_clobbers_lr (x)
rtx x;
switch (GET_CODE (SET_DEST (x)))
{
case REG:
- return REGNO (SET_DEST (x)) == 14;
+ return REGNO (SET_DEST (x)) == LR_REGNUM;
case SUBREG:
if (GET_CODE (XEXP (SET_DEST (x), 0)) == REG)
- return REGNO (XEXP (SET_DEST (x), 0)) == 14;
+ return REGNO (XEXP (SET_DEST (x), 0)) == LR_REGNUM;
if (GET_CODE (XEXP (SET_DEST (x), 0)) == MEM)
return 0;
switch (GET_CODE (XEXP (x, 0)))
{
case REG:
- return REGNO (XEXP (x, 0)) == 14;
+ return REGNO (XEXP (x, 0)) == LR_REGNUM;
case SUBREG:
if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG)
- return REGNO (XEXP (XEXP (x, 0), 0)) == 14;
+ return REGNO (XEXP (XEXP (x, 0), 0)) == LR_REGNUM;
abort ();
default:
case NOTE:
case CODE_LABEL:
case JUMP_INSN: /* Jump insns only change the PC (and conds) */
- case INLINE_HEADER:
break;
case INSN:
case CALL_INSN:
/* Don't yet know how to handle those calls that are not to a
- SYMBOL_REF */
+ SYMBOL_REF. */
if (GET_CODE (PATTERN (insn)) != PARALLEL)
abort ();
return 1;
break;
- default: /* Don't recognize it, be safe */
+ default: /* Don't recognize it, be safe. */
return 1;
}
if ((next = next_nonnote_insn (insn)) == NULL)
return 1;
- /* No need to worry about lr if the call never returns */
+ /* No need to worry about lr if the call never returns. */
if (GET_CODE (next) == BARRIER)
break;
- if (GET_CODE (next) == INSN && GET_CODE (PATTERN (next)) == USE
+ if (GET_CODE (next) == INSN
+ && GET_CODE (PATTERN (next)) == USE
&& (GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
&& (REGNO (SET_DEST (XVECEXP (PATTERN (insn), 0, 0)))
== REGNO (XEXP (PATTERN (next), 0))))
}
}
- /* We have reached the end of the chain so lr was _not_ clobbered */
+ /* We have reached the end of the chain so lr was _not_ clobbered. */
return 0;
}
{
char instr[100];
int reg, live_regs = 0;
- int volatile_func = (optimize > 0
- && TREE_THIS_VOLATILE (current_function_decl));
+ int volatile_func = arm_volatile_func ();
return_used_this_function = 1;
- if (volatile_func)
+ if (TARGET_ABORT_NORETURN && volatile_func)
{
- rtx ops[2];
/* If this function was declared non-returning, and we have found a tail
- call, then we have to trust that the called function won't return. */
- if (! really_return)
- return "";
-
- /* Otherwise, trap an attempted return by aborting. */
- ops[0] = operand;
- ops[1] = gen_rtx_SYMBOL_REF (Pmode, "abort");
- assemble_external_libcall (ops[1]);
- output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
+ call, then we have to trust that the called function won't return. */
+ if (really_return)
+ {
+ rtx ops[2];
+
+ /* Otherwise, trap an attempted return by aborting. */
+ ops[0] = operand;
+ ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
+ : "abort");
+ assemble_external_libcall (ops[1]);
+ output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
+ }
+
return "";
}
if (current_function_calls_alloca && ! really_return)
- abort();
+ abort ();
for (reg = 0; reg <= 10; reg++)
if (regs_ever_live[reg] && ! call_used_regs[reg])
live_regs++;
- if (live_regs || (regs_ever_live[14] && ! lr_save_eliminated))
+ if (flag_pic && ! TARGET_SINGLE_PIC_BASE
+ && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
+ live_regs++;
+
+ if (live_regs || (regs_ever_live[LR_REGNUM] && ! lr_save_eliminated))
live_regs++;
if (frame_pointer_needed)
live_regs += 4;
- if (live_regs)
+ /* On some ARM architectures it is faster to use LDR rather than LDM to
+ load a single register. On other architectures, the cost is the same. */
+ if (live_regs == 1
+ && regs_ever_live[LR_REGNUM]
+ && ! lr_save_eliminated
+ /* FIXME: We ought to handle the case TARGET_APCS_32 is true,
+ really_return is true, and only the PC needs restoring. */
+ && ! really_return)
+ {
+ output_asm_insn (reverse ? "ldr%?%D0\t%|lr, [%|sp], #4"
+ : "ldr%?%d0\t%|lr, [%|sp], #4", &operand);
+ }
+ else if (live_regs)
{
- if (lr_save_eliminated || ! regs_ever_live[14])
+ if (lr_save_eliminated || ! regs_ever_live[LR_REGNUM])
live_regs++;
if (frame_pointer_needed)
reverse ? "ldm%?%D0fd\t%|sp!, {" : "ldm%?%d0fd\t%|sp!, {");
for (reg = 0; reg <= 10; reg++)
- if (regs_ever_live[reg] && ! call_used_regs[reg])
+ if (regs_ever_live[reg]
+ && (! call_used_regs[reg]
+ || (flag_pic && ! TARGET_SINGLE_PIC_BASE
+ && reg == PIC_OFFSET_TABLE_REGNUM)))
{
strcat (instr, "%|");
strcat (instr, reg_names[reg]);
strcat (instr, reg_names[13]);
strcat (instr, ", ");
strcat (instr, "%|");
- strcat (instr, TARGET_THUMB_INTERWORK || (! really_return)
- ? reg_names[14] : reg_names[15] );
+ strcat (instr, TARGET_INTERWORK || (! really_return)
+ ? reg_names[LR_REGNUM] : reg_names[PC_REGNUM] );
}
else
{
strcat (instr, "%|");
- if (TARGET_THUMB_INTERWORK && really_return)
- strcat (instr, reg_names[12]);
+ if (TARGET_INTERWORK && really_return)
+ strcat (instr, reg_names[IP_REGNUM]);
else
- strcat (instr, really_return ? reg_names[15] : reg_names[14]);
+ strcat (instr, really_return ? reg_names[PC_REGNUM] : reg_names[LR_REGNUM]);
}
strcat (instr, (TARGET_APCS_32 || !really_return) ? "}" : "}^");
output_asm_insn (instr, &operand);
- if (TARGET_THUMB_INTERWORK && really_return)
+ if (TARGET_INTERWORK && really_return)
{
strcpy (instr, "bx%?");
strcat (instr, reverse ? "%D0" : "%d0");
}
else if (really_return)
{
- if (TARGET_THUMB_INTERWORK)
+ if (TARGET_INTERWORK)
sprintf (instr, "bx%%?%%%s0\t%%|lr", reverse ? "D" : "d");
else
sprintf (instr, "mov%%?%%%s0%s\t%%|pc, %%|lr",
Such functions never return, and many memory cycles can be saved
by not storing register values that will never be needed again.
This optimization was added to speed up context switching in a
- kernel application. */
-
+ kernel application. */
int
arm_volatile_func ()
{
- return (optimize > 0 && TREE_THIS_VOLATILE (current_function_decl));
+ return (optimize > 0
+ && current_function_nothrow
+ && TREE_THIS_VOLATILE (current_function_decl));
+}
+
+/* Write the function name into the code section, directly preceding
+ the function prologue.
+
+ Code will be output similar to this:
+ t0
+ .ascii "arm_poke_function_name", 0
+ .align
+ t1
+ .word 0xff000000 + (t1 - t0)
+ arm_poke_function_name
+ mov ip, sp
+ stmfd sp!, {fp, ip, lr, pc}
+ sub fp, ip, #4
+
+ When performing a stack backtrace, code can inspect the value
+ of 'pc' stored at 'fp' + 0. If the trace function then looks
+ at location pc - 12 and the top 8 bits are set, then we know
+ that there is a function name embedded immediately preceding this
+ location and has length ((pc[-3]) & 0xff000000).
+
+ We assume that pc is declared as a pointer to an unsigned long.
+
+ It is of no benefit to output the function name if we are assembling
+ a leaf function. These function types will not contain a stack
+ backtrace structure, therefore it is not possible to determine the
+ function name. */
+
+void
+arm_poke_function_name (stream, name)
+ FILE * stream;
+ char * name;
+{
+ unsigned long alignlength;
+ unsigned long length;
+ rtx x;
+
+ length = strlen (name) + 1;
+ alignlength = (length + 3) & ~3;
+
+ ASM_OUTPUT_ASCII (stream, name, length);
+ ASM_OUTPUT_ALIGN (stream, 2);
+ x = GEN_INT (0xff000000UL + alignlength);
+ ASM_OUTPUT_INT (stream, x);
}
/* The amount of stack adjustment that happens here, in output_return and in
no stack frame requirement and no live registers execpt for `lr'. If we
can guarantee that by making all function calls into tail calls and that
lr is not clobbered in any other way, then there is no need to push lr
- onto the stack. */
-
+ onto the stack. */
void
output_func_prologue (f, frame_size)
- FILE *f;
+ FILE * f;
int frame_size;
{
int reg, live_regs_mask = 0;
- int volatile_func = (optimize > 0
- && TREE_THIS_VOLATILE (current_function_decl));
+ int volatile_func = arm_volatile_func ();
/* Nonzero if we must stuff some register arguments onto the stack as if
they were passed there. */
int store_arg_regs = 0;
if (arm_ccfsm_state || arm_target_insn)
- abort (); /* Sanity check */
+ abort (); /* Sanity check. */
if (arm_naked_function_p (current_function_decl))
return;
return_used_this_function = 0;
lr_save_eliminated = 0;
- fprintf (f, "\t%s args = %d, pretend = %d, frame = %d\n",
- ASM_COMMENT_START, current_function_args_size,
- current_function_pretend_args_size, frame_size);
- fprintf (f, "\t%s frame_needed = %d, current_function_anonymous_args = %d\n",
- ASM_COMMENT_START, frame_pointer_needed,
- current_function_anonymous_args);
+ asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %d\n",
+ current_function_args_size,
+ current_function_pretend_args_size, frame_size);
+ asm_fprintf (f, "\t%@ frame_needed = %d, current_function_anonymous_args = %d\n",
+ frame_pointer_needed,
+ current_function_anonymous_args);
if (volatile_func)
- fprintf (f, "\t%s Volatile function.\n", ASM_COMMENT_START);
+ asm_fprintf (f, "\t%@ Volatile function.\n");
if (current_function_anonymous_args && current_function_pretend_args_size)
store_arg_regs = 1;
if (regs_ever_live[reg] && ! call_used_regs[reg])
live_regs_mask |= (1 << reg);
+ if (flag_pic && ! TARGET_SINGLE_PIC_BASE
+ && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
+ live_regs_mask |= (1 << PIC_OFFSET_TABLE_REGNUM);
+
if (frame_pointer_needed)
live_regs_mask |= 0xD800;
- else if (regs_ever_live[14])
+ else if (regs_ever_live[LR_REGNUM])
{
if (! current_function_args_size
&& ! function_really_clobbers_lr (get_insns ()))
lr_save_eliminated = 1;
else
- live_regs_mask |= 0x4000;
+ live_regs_mask |= 1 << LR_REGNUM;
}
if (live_regs_mask)
{
- /* if a di mode load/store multiple is used, and the base register
+ /* If a di mode load/store multiple is used, and the base register
is r3, then r4 can become an ever live register without lr
doing so, in this case we need to push lr as well, or we
- will fail to get a proper return. */
-
- live_regs_mask |= 0x4000;
+ will fail to get a proper return. */
+ live_regs_mask |= 1 << LR_REGNUM;
lr_save_eliminated = 0;
}
if (lr_save_eliminated)
- fprintf (f,"\t%s I don't think this function clobbers lr\n",
- ASM_COMMENT_START);
+ asm_fprintf (f,"\t%@ I don't think this function clobbers lr\n");
#ifdef AOF_ASSEMBLER
if (flag_pic)
- fprintf (f, "\tmov\t%sip, %s%s\n", REGISTER_PREFIX, REGISTER_PREFIX,
- reg_names[PIC_OFFSET_TABLE_REGNUM]);
+ asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
#endif
}
-
-void
-output_func_epilogue (f, frame_size)
- FILE *f;
- int frame_size;
+char *
+arm_output_epilogue ()
{
- int reg, live_regs_mask = 0;
- /* If we need this then it will always be at least this much */
+ int reg;
+ int live_regs_mask = 0;
+ /* If we need this, then it will always be at least this much. */
int floats_offset = 12;
rtx operands[3];
- int volatile_func = (optimize > 0
- && TREE_THIS_VOLATILE (current_function_decl));
+ int frame_size = get_frame_size ();
+ FILE *f = asm_out_file;
+ int volatile_func = arm_volatile_func ();
if (use_return_insn (FALSE) && return_used_this_function)
- {
- if ((frame_size + current_function_outgoing_args_size) != 0
- && !(frame_pointer_needed && TARGET_APCS))
- abort ();
- goto epilogue_done;
- }
+ return "";
/* Naked functions don't have epilogues. */
if (arm_naked_function_p (current_function_decl))
- goto epilogue_done;
+ return "";
/* A volatile function should never return. Call abort. */
if (TARGET_ABORT_NORETURN && volatile_func)
{
- rtx op = gen_rtx_SYMBOL_REF (Pmode, "abort");
+ rtx op;
+ op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
assemble_external_libcall (op);
output_asm_insn ("bl\t%a0", &op);
- goto epilogue_done;
+ return "";
}
for (reg = 0; reg <= 10; reg++)
floats_offset += 4;
}
+ /* If we aren't loading the PIC register, don't stack it even though it may
+ be live. */
+ if (flag_pic && ! TARGET_SINGLE_PIC_BASE
+ && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
+ {
+ live_regs_mask |= (1 << PIC_OFFSET_TABLE_REGNUM);
+ floats_offset += 4;
+ }
+
if (frame_pointer_needed)
{
if (arm_fpu_arch == FP_SOFT2)
if (regs_ever_live[reg] && ! call_used_regs[reg])
{
floats_offset += 12;
- fprintf (f, "\tldfe\t%s%s, [%sfp, #-%d]\n", REGISTER_PREFIX,
- reg_names[reg], REGISTER_PREFIX, floats_offset);
+ asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
+ reg, FP_REGNUM, floats_offset);
}
}
else
if (regs_ever_live[reg] && ! call_used_regs[reg])
{
floats_offset += 12;
- /* We can't unstack more than four registers at once */
+
+ /* We can't unstack more than four registers at once. */
if (start_reg - reg == 3)
{
- fprintf (f, "\tlfm\t%s%s, 4, [%sfp, #-%d]\n",
- REGISTER_PREFIX, reg_names[reg],
- REGISTER_PREFIX, floats_offset);
+ asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
+ reg, FP_REGNUM, floats_offset);
start_reg = reg - 1;
}
}
else
{
if (reg != start_reg)
- fprintf (f, "\tlfm\t%s%s, %d, [%sfp, #-%d]\n",
- REGISTER_PREFIX, reg_names[reg + 1],
- start_reg - reg, REGISTER_PREFIX, floats_offset);
-
+ asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
+ reg + 1, start_reg - reg,
+ FP_REGNUM, floats_offset);
start_reg = reg - 1;
}
}
/* Just in case the last register checked also needs unstacking. */
if (reg != start_reg)
- fprintf (f, "\tlfm\t%s%s, %d, [%sfp, #-%d]\n",
- REGISTER_PREFIX, reg_names[reg + 1],
- start_reg - reg, REGISTER_PREFIX, floats_offset);
+ asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
+ reg + 1, start_reg - reg,
+ FP_REGNUM, floats_offset);
}
- if (TARGET_THUMB_INTERWORK)
+ if (TARGET_INTERWORK)
{
live_regs_mask |= 0x6800;
- print_multi_reg (f, "ldmea\t%sfp", live_regs_mask, FALSE);
- fprintf (f, "\tbx\t%slr\n", REGISTER_PREFIX);
+ print_multi_reg (f, "ldmea\t%r", FP_REGNUM, live_regs_mask, FALSE);
+ asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
}
else
{
live_regs_mask |= 0xA800;
- print_multi_reg (f, "ldmea\t%sfp", live_regs_mask,
+ print_multi_reg (f, "ldmea\t%r", FP_REGNUM, live_regs_mask,
TARGET_APCS_32 ? FALSE : TRUE);
}
}
{
for (reg = 16; reg < 24; reg++)
if (regs_ever_live[reg] && ! call_used_regs[reg])
- fprintf (f, "\tldfe\t%s%s, [%ssp], #12\n", REGISTER_PREFIX,
- reg_names[reg], REGISTER_PREFIX);
+ asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
+ reg, SP_REGNUM);
}
else
{
{
if (reg - start_reg == 3)
{
- fprintf (f, "\tlfmfd\t%s%s, 4, [%ssp]!\n",
- REGISTER_PREFIX, reg_names[start_reg],
- REGISTER_PREFIX);
+ asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
+ start_reg, SP_REGNUM);
start_reg = reg + 1;
}
}
else
{
if (reg != start_reg)
- fprintf (f, "\tlfmfd\t%s%s, %d, [%ssp]!\n",
- REGISTER_PREFIX, reg_names[start_reg],
- reg - start_reg, REGISTER_PREFIX);
-
+ asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
+ start_reg, reg - start_reg,
+ SP_REGNUM);
+
start_reg = reg + 1;
}
}
/* Just in case the last register checked also needs unstacking. */
if (reg != start_reg)
- fprintf (f, "\tlfmfd\t%s%s, %d, [%ssp]!\n",
- REGISTER_PREFIX, reg_names[start_reg],
- reg - start_reg, REGISTER_PREFIX);
+ asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
+ start_reg, reg - start_reg, SP_REGNUM);
}
- if (current_function_pretend_args_size == 0 && regs_ever_live[14])
+ if (current_function_pretend_args_size == 0 && regs_ever_live[LR_REGNUM])
{
- if (TARGET_THUMB_INTERWORK)
+ if (TARGET_INTERWORK)
{
if (! lr_save_eliminated)
- live_regs_mask |= 0x4000;
+ live_regs_mask |= 1 << LR_REGNUM;
if (live_regs_mask != 0)
- print_multi_reg (f, "ldmfd\t%ssp!", live_regs_mask, FALSE);
-
- fprintf (f, "\tbx\t%slr\n", REGISTER_PREFIX);
+ print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, live_regs_mask, FALSE);
+
+ asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
}
else if (lr_save_eliminated)
- fprintf (f, (TARGET_APCS_32 ? "\tmov\t%spc, %slr\n"
- : "\tmovs\t%spc, %slr\n"),
- REGISTER_PREFIX, REGISTER_PREFIX, f);
+ asm_fprintf (f,
+ TARGET_APCS_32 ? "\tmov\t%r, %r\n" : "\tmovs\t%r, %r\n",
+ PC_REGNUM, LR_REGNUM);
else
- print_multi_reg (f, "ldmfd\t%ssp!", live_regs_mask | 0x8000,
+ print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, live_regs_mask | 0x8000,
TARGET_APCS_32 ? FALSE : TRUE);
}
else
{
- if (live_regs_mask || regs_ever_live[14])
+ if (live_regs_mask || regs_ever_live[LR_REGNUM])
{
- /* Restore the integer regs, and the return address into lr */
+ /* Restore the integer regs, and the return address into lr. */
if (! lr_save_eliminated)
- live_regs_mask |= 0x4000;
+ live_regs_mask |= 1 << LR_REGNUM;
if (live_regs_mask != 0)
- print_multi_reg (f, "ldmfd\t%ssp!", live_regs_mask, FALSE);
+ print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, live_regs_mask, FALSE);
}
if (current_function_pretend_args_size)
{
- /* Unwind the pre-pushed regs */
+ /* Unwind the pre-pushed regs. */
operands[0] = operands[1] = stack_pointer_rtx;
operands[2] = GEN_INT (current_function_pretend_args_size);
output_add_immediate (operands);
}
- /* And finally, go home */
- if (TARGET_THUMB_INTERWORK)
- fprintf (f, "\tbx\t%slr\n", REGISTER_PREFIX);
+ /* And finally, go home. */
+ if (TARGET_INTERWORK)
+ asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
else if (TARGET_APCS_32)
- fprintf (f, "\tmov\t%spc, %slr\n", REGISTER_PREFIX, REGISTER_PREFIX );
+ asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
else
- fprintf (f, "\tmovs\t%spc, %slr\n", REGISTER_PREFIX, REGISTER_PREFIX );
+ asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
}
}
-epilogue_done:
+ return "";
+}
+
+void
+output_func_epilogue (frame_size)
+ int frame_size;
+{
+ if (use_return_insn (FALSE) && return_used_this_function
+ && (frame_size + current_function_outgoing_args_size) != 0
+ && ! (frame_pointer_needed && TARGET_APCS))
+ abort ();
+ /* Reset the ARM-specific per-function variables. */
current_function_anonymous_args = 0;
+ after_arm_reorg = 0;
}
-static void
+/* Generate and emit an insn that we will recognize as a push_multi.
+ Unfortunately, since this insn does not reflect very well the actual
+ semantics of the operation, we need to annotate the insn for the benefit
+ of DWARF2 frame unwind information. */
+static rtx
emit_multi_reg_push (mask)
int mask;
{
int num_regs = 0;
int i, j;
rtx par;
+ rtx dwarf;
+ rtx tmp, reg;
for (i = 0; i < 16; i++)
if (mask & (1 << i))
abort ();
par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
+ dwarf = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
+ RTX_FRAME_RELATED_P (dwarf) = 1;
for (i = 0; i < 16; i++)
{
if (mask & (1 << i))
{
+ reg = gen_rtx_REG (SImode, i);
+
XVECEXP (par, 0, 0)
= gen_rtx_SET (VOIDmode,
gen_rtx_MEM (BLKmode,
gen_rtx_PRE_DEC (BLKmode,
stack_pointer_rtx)),
gen_rtx_UNSPEC (BLKmode,
- gen_rtvec (1,
- gen_rtx_REG (SImode, i)),
+ gen_rtvec (1, reg),
2));
+
+ tmp = gen_rtx_SET (VOIDmode,
+ gen_rtx_MEM (SImode,
+ gen_rtx_PRE_DEC (BLKmode,
+ stack_pointer_rtx)),
+ reg);
+ RTX_FRAME_RELATED_P (tmp) = 1;
+ XVECEXP (dwarf, 0, num_regs - 1) = tmp;
+
break;
}
}
{
if (mask & (1 << i))
{
- XVECEXP (par, 0, j)
- = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, i));
+ reg = gen_rtx_REG (SImode, i);
+
+ XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
+
+ tmp = gen_rtx_SET (VOIDmode,
+ gen_rtx_MEM (SImode,
+ gen_rtx_PRE_DEC (BLKmode,
+ stack_pointer_rtx)),
+ reg);
+ RTX_FRAME_RELATED_P (tmp) = 1;
+ XVECEXP (dwarf, 0, num_regs - j - 1) = tmp;
+
j++;
}
}
- emit_insn (par);
+ par = emit_insn (par);
+ REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
+ REG_NOTES (par));
+ return par;
}
-static void
+static rtx
emit_sfm (base_reg, count)
int base_reg;
int count;
{
rtx par;
+ rtx dwarf;
+ rtx tmp, reg;
int i;
par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
+ dwarf = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
+ RTX_FRAME_RELATED_P (dwarf) = 1;
+
+ reg = gen_rtx_REG (XFmode, base_reg++);
XVECEXP (par, 0, 0)
= gen_rtx_SET (VOIDmode,
gen_rtx_MEM (BLKmode,
gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
gen_rtx_UNSPEC (BLKmode,
- gen_rtvec (1, gen_rtx_REG (XFmode,
- base_reg++)),
+ gen_rtvec (1, reg),
2));
+ tmp
+ = gen_rtx_SET (VOIDmode,
+ gen_rtx_MEM (XFmode,
+ gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
+ reg);
+ RTX_FRAME_RELATED_P (tmp) = 1;
+ XVECEXP (dwarf, 0, count - 1) = tmp;
+
for (i = 1; i < count; i++)
- XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode,
- gen_rtx_REG (XFmode, base_reg++));
+ {
+ reg = gen_rtx_REG (XFmode, base_reg++);
+ XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
+
+ tmp = gen_rtx_SET (VOIDmode,
+ gen_rtx_MEM (XFmode,
+ gen_rtx_PRE_DEC (BLKmode,
+ stack_pointer_rtx)),
+ reg);
+ RTX_FRAME_RELATED_P (tmp) = 1;
+ XVECEXP (dwarf, 0, count - i - 1) = tmp;
+ }
- emit_insn (par);
+ par = emit_insn (par);
+ REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
+ REG_NOTES (par));
+ return par;
}
void
+ current_function_outgoing_args_size));
int live_regs_mask = 0;
int store_arg_regs = 0;
- int volatile_func = (optimize > 0
- && TREE_THIS_VOLATILE (current_function_decl));
+ /* If this function doesn't return, then there is no need to push
+ the call-saved regs. */
+ int volatile_func = arm_volatile_func ();
+ rtx insn;
/* Naked functions don't have prologues. */
if (arm_naked_function_p (current_function_decl))
store_arg_regs = 1;
if (! volatile_func)
- for (reg = 0; reg <= 10; reg++)
- if (regs_ever_live[reg] && ! call_used_regs[reg])
- live_regs_mask |= 1 << reg;
+ {
+ for (reg = 0; reg <= 10; reg++)
+ if (regs_ever_live[reg] && ! call_used_regs[reg])
+ live_regs_mask |= 1 << reg;
- if (! volatile_func && regs_ever_live[14])
- live_regs_mask |= 0x4000;
+ if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
+ live_regs_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
+
+ if (regs_ever_live[LR_REGNUM])
+ live_regs_mask |= 1 << LR_REGNUM;
+ }
if (frame_pointer_needed)
{
live_regs_mask |= 0xD800;
- emit_insn (gen_movsi (gen_rtx_REG (SImode, 12),
- stack_pointer_rtx));
+ insn = emit_insn (gen_movsi (gen_rtx_REG (SImode, IP_REGNUM),
+ stack_pointer_rtx));
+ RTX_FRAME_RELATED_P (insn) = 1;
}
if (current_function_pretend_args_size)
{
if (store_arg_regs)
- emit_multi_reg_push ((0xf0 >> (current_function_pretend_args_size / 4))
- & 0xf);
+ insn = emit_multi_reg_push
+ ((0xf0 >> (current_function_pretend_args_size / 4)) & 0xf);
else
- emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
- GEN_INT (-current_function_pretend_args_size)));
+ insn = emit_insn
+ (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
+ GEN_INT (-current_function_pretend_args_size)));
+ RTX_FRAME_RELATED_P (insn) = 1;
}
if (live_regs_mask)
{
/* If we have to push any regs, then we must push lr as well, or
we won't get a proper return. */
- live_regs_mask |= 0x4000;
- emit_multi_reg_push (live_regs_mask);
+ live_regs_mask |= 1 << LR_REGNUM;
+ insn = emit_multi_reg_push (live_regs_mask);
+ RTX_FRAME_RELATED_P (insn) = 1;
}
- /* For now the integer regs are still pushed in output_func_epilogue (). */
-
+ /* And now the floating point regs. */
if (! volatile_func)
{
if (arm_fpu_arch == FP_SOFT2)
{
for (reg = 23; reg > 15; reg--)
if (regs_ever_live[reg] && ! call_used_regs[reg])
- emit_insn (gen_rtx_SET
- (VOIDmode,
- gen_rtx_MEM (XFmode,
- gen_rtx_PRE_DEC (XFmode,
- stack_pointer_rtx)),
- gen_rtx_REG (XFmode, reg)));
+ {
+ insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
+ insn = gen_rtx_MEM (XFmode, insn);
+ insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
+ gen_rtx_REG (XFmode, reg)));
+ RTX_FRAME_RELATED_P (insn) = 1;
+ }
}
else
{
{
if (start_reg - reg == 3)
{
- emit_sfm (reg, 4);
+ insn = emit_sfm (reg, 4);
+ RTX_FRAME_RELATED_P (insn) = 1;
start_reg = reg - 1;
}
}
else
{
if (start_reg != reg)
- emit_sfm (reg + 1, start_reg - reg);
+ {
+ insn = emit_sfm (reg + 1, start_reg - reg);
+ RTX_FRAME_RELATED_P (insn) = 1;
+ }
start_reg = reg - 1;
}
}
if (start_reg != reg)
- emit_sfm (reg + 1, start_reg - reg);
+ {
+ insn = emit_sfm (reg + 1, start_reg - reg);
+ RTX_FRAME_RELATED_P (insn) = 1;
+ }
}
}
if (frame_pointer_needed)
- emit_insn (gen_addsi3 (hard_frame_pointer_rtx, gen_rtx_REG (SImode, 12),
- (GEN_INT
- (-(4 + current_function_pretend_args_size)))));
+ {
+ insn = GEN_INT (-(4 + current_function_pretend_args_size));
+ insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
+ gen_rtx_REG (SImode, IP_REGNUM),
+ insn));
+ RTX_FRAME_RELATED_P (insn) = 1;
+ }
if (amount != const0_rtx)
{
- emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, amount));
+ insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
+ amount));
+ RTX_FRAME_RELATED_P (insn) = 1;
emit_insn (gen_rtx_CLOBBER (VOIDmode,
gen_rtx_MEM (BLKmode, stack_pointer_rtx)));
}
void
arm_print_operand (stream, x, code)
- FILE *stream;
+ FILE * stream;
rtx x;
int code;
{
case 'B':
if (GET_CODE (x) == CONST_INT)
- fprintf (stream,
-#if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
- "%d",
-#else
- "%ld",
-#endif
- ARM_SIGN_EXTEND (~ INTVAL (x)));
+ {
+ HOST_WIDE_INT val;
+ val = ARM_SIGN_EXTEND (~ INTVAL (x));
+ fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
+ }
else
{
putc ('~', stream);
case 'S':
{
HOST_WIDE_INT val;
- char *shift = shift_op (x, &val);
+ char * shift = shift_op (x, & val);
if (shift)
{
- fprintf (stream, ", %s ", shift_op (x, &val));
+ fprintf (stream, ", %s ", shift_op (x, & val));
if (val == -1)
arm_print_operand (stream, XEXP (x, 1), 0);
else
- fprintf (stream,
-#if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
- "#%d",
-#else
- "#%ld",
-#endif
- val);
+ {
+ fputc ('#', stream);
+ fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
+ }
}
}
return;
return;
case 'M':
- fprintf (stream, "{%s%s-%s%s}", REGISTER_PREFIX, reg_names[REGNO (x)],
- REGISTER_PREFIX, reg_names[REGNO (x) - 1
- + ((GET_MODE_SIZE (GET_MODE (x))
- + GET_MODE_SIZE (SImode) - 1)
- / GET_MODE_SIZE (SImode))]);
+ asm_fprintf (stream, "{%r-%r}",
+ REGNO (x), REGNO (x) + NUM_REGS (GET_MODE (x)) - 1);
return;
case 'd':
else if (GET_CODE (x) == CONST_DOUBLE)
fprintf (stream, "#%s", fp_immediate_constant (x));
else if (GET_CODE (x) == NEG)
- abort (); /* This should never happen now. */
+ abort (); /* This should never happen now. */
else
{
fputc ('#', stream);
}
}
}
-
\f
/* A finite state machine takes care of noticing whether or not instructions
can be conditionally executed, and thus decrease execution time and code
void
-final_prescan_insn (insn, opvec, noperands)
+arm_final_prescan_insn (insn)
rtx insn;
- rtx *opvec;
- int noperands;
{
/* BODY will hold the body of INSN. */
register rtx body = PATTERN (insn);
out what the conditions are when the jump isn't taken. */
int jump_clobbers = 0;
- /* If we start with a return insn, we only succeed if we find another one. */
+ /* If we start with a return insn, we only succeed if we find another one. */
int seeking_return = 0;
/* START_INSN will hold the insn from where we start looking. This is the
/* Succeed if the following insn is the target label.
Otherwise fail.
If return insns are used then the last insn in a function
- will be a barrier. */
+ will be a barrier. */
this_insn = next_nonnote_insn (this_insn);
if (this_insn && this_insn == label)
{
case CALL_INSN:
/* If using 32-bit addresses the cc is not preserved over
- calls */
+ calls. */
if (TARGET_APCS_32)
{
/* Succeed if the following insn is the target label,
/* If this is an unconditional branch to the same label, succeed.
If it is to another label, do nothing. If it is conditional,
fail. */
- /* XXX Probably, the tests for SET and the PC are unnecessary. */
+ /* XXX Probably, the tests for SET and the PC are unnecessary. */
scanbody = PATTERN (this_insn);
if (GET_CODE (scanbody) == SET
if (reverse || then_not_else)
arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
}
- /* restore recog_operand (getting the attributes of other insns can
+
+ /* Restore recog_data (getting the attributes of other insns can
destroy this array, but final.c assumes that it remains intact
across this call; since the insn has been recognized already we
- call recog direct). */
+ call recog direct). */
recog (PATTERN (insn), insn, NULL_PTR);
}
}
+/* Return the length of a function name prefix
+ that starts with the character 'c'. */
+static int
+arm_get_strip_length (char c)
+{
+ switch (c)
+ {
+ ARM_NAME_ENCODING_LENGTHS
+ default: return 0;
+ }
+}
+
+/* Return a pointer to a function's name with any
+ and all prefix encodings stripped from it. */
+const char *
+arm_strip_name_encoding (const char * name)
+{
+ int skip;
+
+ while ((skip = arm_get_strip_length (* name)))
+ name += skip;
+
+ return name;
+}
+
#ifdef AOF_ASSEMBLER
-/* Special functions only needed when producing AOF syntax assembler. */
+/* Special functions only needed when producing AOF syntax assembler. */
rtx aof_pic_label = NULL_RTX;
struct pic_chain
{
- struct pic_chain *next;
- char *symname;
+ struct pic_chain * next;
+ char * symname;
};
-static struct pic_chain *aof_pic_chain = NULL;
+static struct pic_chain * aof_pic_chain = NULL;
rtx
aof_pic_entry (x)
rtx x;
{
- struct pic_chain **chainp;
+ struct pic_chain ** chainp;
int offset;
if (aof_pic_label == NULL_RTX)
{
+ /* We mark this here and not in arm_add_gc_roots() to avoid
+ polluting even more code with ifdefs, and because it never
+ contains anything useful until we assign to it here. */
+ ggc_add_rtx_root (&aof_pic_label, 1);
/* This needs to persist throughout the compilation. */
end_temporary_allocation ();
aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
void
aof_dump_pic_table (f)
- FILE *f;
+ FILE * f;
{
- struct pic_chain *chain;
+ struct pic_chain * chain;
if (aof_pic_chain == NULL)
return;
- fprintf (f, "\tAREA |%s$$adcons|, BASED %s%s\n",
- reg_names[PIC_OFFSET_TABLE_REGNUM], REGISTER_PREFIX,
- reg_names[PIC_OFFSET_TABLE_REGNUM]);
+ asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
+ PIC_OFFSET_TABLE_REGNUM,
+ PIC_OFFSET_TABLE_REGNUM);
fputs ("|x$adcons|\n", f);
for (chain = aof_pic_chain; chain; chain = chain->next)
struct import
{
- struct import *next;
- char *name;
+ struct import * next;
+ char * name;
};
-static struct import *imports_list = NULL;
+static struct import * imports_list = NULL;
void
aof_add_import (name)
- char *name;
+ char * name;
{
- struct import *new;
+ struct import * new;
for (new = imports_list; new; new = new->next)
if (new->name == name)
void
aof_delete_import (name)
- char *name;
+ char * name;
{
- struct import **old;
+ struct import ** old;
for (old = &imports_list; *old; old = & (*old)->next)
{
void
aof_dump_imports (f)
- FILE *f;
+ FILE * f;
{
/* The AOF assembler needs this to cause the startup code to be extracted
from the library. Brining in __main causes the whole thing to work
projects / gcc.git / blobdiff