[arm][aarch64] Make no_insn issue to nothing

[gcc.git] / gcc / config / arm / arm1136jfs.md

diff --git a/gcc/config/arm/arm1136jfs.md b/gcc/config/arm/arm1136jfs.md
index 3030182acca42e21c715334aac670721ddc7d926..e7fd53afe33f99d19714be7fe6c577089d621371 100644 (file)
--- a/gcc/config/arm/arm1136jfs.md
+++ b/gcc/config/arm/arm1136jfs.md
@@ -1,5 +1,5 @@
 ;; ARM 1136J[F]-S Pipeline Description
-;; Copyright (C) 2003-2013 Free Software Foundation, Inc.
+;; Copyright (C) 2003-2019 Free Software Foundation, Inc.
 ;; Written by CodeSourcery, LLC.
 ;;
 ;; This file is part of GCC.
@@ -75,13 +75,21 @@
 ;; ALU operations with no shifted operand
 (define_insn_reservation "11_alu_op" 2
  (and (eq_attr "tune" "arm1136js,arm1136jfs")
-      (eq_attr "type" "alu_reg,simple_alu_imm"))
+      (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+                       alu_sreg,alus_sreg,logic_reg,logics_reg,\
+                       adc_imm,adcs_imm,adc_reg,adcs_reg,\
+                       adr,bfm,rev,\
+                       shift_imm,shift_reg,\
+                       mov_imm,mov_reg,mvn_imm,mvn_reg,\
+                       multiple"))
  "e_1,e_2,e_3,e_wb")
 
 ;; ALU operations with a shift-by-constant operand
 (define_insn_reservation "11_alu_shift_op" 2
  (and (eq_attr "tune" "arm1136js,arm1136jfs")
-      (eq_attr "type" "simple_alu_shift,alu_shift"))
+      (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
+                       logic_shift_imm,logics_shift_imm,\
+                       extend,mov_shift,mvn_shift"))
  "e_1,e_2,e_3,e_wb")
 
 ;; ALU operations with a shift-by-register operand
@@ -90,7 +98,9 @@
 ;; the shift stage.
 (define_insn_reservation "11_alu_shift_reg_op" 3
  (and (eq_attr "tune" "arm1136js,arm1136jfs")
-      (eq_attr "type" "alu_shift_reg"))
+      (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
+                       logic_shift_reg,logics_shift_reg,\
+                       mov_shift_reg,mvn_shift_reg"))
  "e_1*2,e_2,e_3,e_wb")
 
 ;; alu_ops can start sooner, if there is no shifter dependency
@@ -284,7 +294,7 @@
 
 (define_insn_reservation "11_load1" 3
  (and (eq_attr "tune" "arm1136js,arm1136jfs")
-      (eq_attr "type" "load1"))
+      (eq_attr "type" "load_4"))
  "l_a+e_1,l_dc1,l_dc2,l_wb")
 
 ;; Load byte results are not available until the writeback stage, where
@@ -297,7 +307,7 @@
 
 (define_insn_reservation "11_store1" 0
  (and (eq_attr "tune" "arm1136js,arm1136jfs")
-      (eq_attr "type" "store1"))
+      (eq_attr "type" "store_4"))
  "l_a+e_1,l_dc1,l_dc2,l_wb")
 
 ;; Load/store double words into adjacent registers.  The timing and
@@ -305,12 +315,12 @@
 ;; aligned.  This model assumes that it is.
 (define_insn_reservation "11_load2" 3
  (and (eq_attr "tune" "arm1136js,arm1136jfs")
-      (eq_attr "type" "load2"))
+      (eq_attr "type" "load_8"))
  "l_a+e_1,l_dc1,l_dc2,l_wb")
 
 (define_insn_reservation "11_store2" 0
  (and (eq_attr "tune" "arm1136js,arm1136jfs")
-      (eq_attr "type" "store2"))
+      (eq_attr "type" "store_8"))
  "l_a+e_1,l_dc1,l_dc2,l_wb")
 
 ;; Load/store multiple registers.  Two registers are stored per cycle.
@@ -318,12 +328,12 @@
 ;; optimistically schedule a low latency.
 (define_insn_reservation "11_load34" 4
  (and (eq_attr "tune" "arm1136js,arm1136jfs")
-      (eq_attr "type" "load3,load4"))
+      (eq_attr "type" "load_12,load_16"))
  "l_a+e_1,l_dc1*2,l_dc2,l_wb")
 
 (define_insn_reservation "11_store34" 0
  (and (eq_attr "tune" "arm1136js,arm1136jfs")
-      (eq_attr "type" "store3,store4"))
+      (eq_attr "type" "store_12,store_16"))
  "l_a+e_1,l_dc1*2,l_dc2,l_wb")
 
 ;; A store can start immediately after an alu op, if that alu op does