;; ARM Thumb-2 Machine Description
-;; Copyright (C) 2007, 2008 Free Software Foundation, Inc.
+;; Copyright (C) 2007, 2008, 2010 Free Software Foundation, Inc.
;; Written by CodeSourcery, LLC.
;;
;; This file is part of GCC.
(set_attr "length" "10,10,14")]
)
-(define_insn "*thumb2_notsi_shiftsi"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
- (not:SI (match_operator:SI 3 "shift_operator"
- [(match_operand:SI 1 "s_register_operand" "r")
- (match_operand:SI 2 "const_int_operand" "M")])))]
- "TARGET_THUMB2"
- "mvn%?\\t%0, %1%S3"
- [(set_attr "predicable" "yes")
- (set_attr "shift" "1")
- (set_attr "type" "alu_shift")]
-)
-
-(define_insn "*thumb2_notsi_shiftsi_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator"
- [(match_operand:SI 1 "s_register_operand" "r")
- (match_operand:SI 2 "const_int_operand" "M")]))
- (const_int 0)))
- (set (match_operand:SI 0 "s_register_operand" "=r")
- (not:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])))]
- "TARGET_THUMB2"
- "mvn%.\\t%0, %1%S3"
- [(set_attr "conds" "set")
- (set_attr "shift" "1")
- (set_attr "type" "alu_shift")]
-)
-
-(define_insn "*thumb2_not_shiftsi_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator"
- [(match_operand:SI 1 "s_register_operand" "r")
- (match_operand:SI 2 "const_int_operand" "M")]))
- (const_int 0)))
- (clobber (match_scratch:SI 0 "=r"))]
- "TARGET_THUMB2"
- "mvn%.\\t%0, %1%S3"
- [(set_attr "conds" "set")
- (set_attr "shift" "1")
- (set_attr "type" "alu_shift")]
-)
-
;; Thumb-2 does not have rsc, so use a clever trick with shifter operands.
(define_insn "*thumb2_negdi2"
[(set (match_operand:DI 0 "s_register_operand" "=&r,r")
(set_attr "length" "10,8")]
)
-(define_insn "*thumb2_movdi"
- [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m")
- (match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,r"))]
- "TARGET_THUMB2
- && !(TARGET_HARD_FLOAT && (TARGET_MAVERICK || TARGET_VFP))
- && !TARGET_IWMMXT"
- "*
- switch (which_alternative)
- {
- case 0:
- case 1:
- case 2:
- return \"#\";
- default:
- return output_move_double (operands);
- }
- "
- [(set_attr "length" "8,12,16,8,8")
- (set_attr "type" "*,*,*,load2,store2")
- (set_attr "pool_range" "*,*,*,4096,*")
- (set_attr "neg_pool_range" "*,*,*,0,*")]
-)
-
+;; We have two alternatives here for memory loads (and similarly for stores)
+;; to reflect the fact that the permissible constant pool ranges differ
+;; between ldr instructions taking low regs and ldr instructions taking high
+;; regs. The high register alternatives are not taken into account when
+;; choosing register preferences in order to reflect their expense.
(define_insn "*thumb2_movsi_insn"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m")
- (match_operand:SI 1 "general_operand" "rk ,I,K,j,mi,rk"))]
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,l ,*hk,m,*m")
+ (match_operand:SI 1 "general_operand" "rk ,I,K,j,mi,*mi,l,*hk"))]
"TARGET_THUMB2 && ! TARGET_IWMMXT
&& !(TARGET_HARD_FLOAT && TARGET_VFP)
&& ( register_operand (operands[0], SImode)
mvn%?\\t%0, #%B1
movw%?\\t%0, %1
ldr%?\\t%0, %1
+ ldr%?\\t%0, %1
+ str%?\\t%1, %0
str%?\\t%1, %0"
- [(set_attr "type" "*,*,*,*,load1,store1")
+ [(set_attr "type" "*,*,*,*,load1,load1,store1,store1")
(set_attr "predicable" "yes")
- (set_attr "pool_range" "*,*,*,*,4096,*")
- (set_attr "neg_pool_range" "*,*,*,*,0,*")]
+ (set_attr "pool_range" "*,*,*,*,1020,4096,*,*")
+ (set_attr "neg_pool_range" "*,*,*,*,0,0,*,*")]
)
-;; ??? We can probably do better with thumb2
-(define_insn "pic_load_addr_thumb2"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
- (unspec:SI [(match_operand:SI 1 "" "mX")] UNSPEC_PIC_SYM))]
- "TARGET_THUMB2 && flag_pic"
- "ldr%?\\t%0, %1"
- [(set_attr "type" "load1")
- (set_attr "pool_range" "4096")
- (set_attr "neg_pool_range" "0")]
-)
-
-;; Set reg to the address of this instruction plus four. The low two
-;; bits of the PC are always read as zero, so ensure the instructions is
-;; word aligned.
-(define_insn "pic_load_dot_plus_four"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (unspec:SI [(const_int 4)
- (match_operand 1 "" "")]
- UNSPEC_PIC_BASE))]
+(define_insn "tls_load_dot_plus_four"
+ [(set (match_operand:SI 0 "register_operand" "=l,l,r,r")
+ (mem:SI (unspec:SI [(match_operand:SI 2 "register_operand" "0,1,0,1")
+ (const_int 4)
+ (match_operand 3 "" "")]
+ UNSPEC_PIC_BASE)))
+ (clobber (match_scratch:SI 1 "=X,l,X,r"))]
"TARGET_THUMB2"
"*
- assemble_align(BITS_PER_WORD);
(*targetm.asm_out.internal_label) (asm_out_file, \"LPIC\",
- INTVAL (operands[1]));
- /* We use adr because some buggy gas assemble add r8, pc, #0
- to add.w r8, pc, #0, not addw r8, pc, #0. */
- asm_fprintf (asm_out_file, \"\\tadr\\t%r, %LLPIC%d + 4\\n\",
- REGNO(operands[0]), (int)INTVAL (operands[1]));
- return \"\";
+ INTVAL (operands[3]));
+ return \"add\\t%2, %|pc\;ldr%?\\t%0, [%2]\";
"
- [(set_attr "length" "6")]
+ [(set_attr "length" "4,4,6,6")]
)
;; Thumb-2 always has load/store halfword instructions, so we can avoid a lot
;; of the messiness associated with the ARM patterns.
(define_insn "*thumb2_movhi_insn"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r")
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r")
(match_operand:HI 1 "general_operand" "rI,n,r,m"))]
- "TARGET_THUMB2"
+ "TARGET_THUMB2
+ && (register_operand (operands[0], HImode)
+ || register_operand (operands[1], HImode))"
"@
mov%?\\t%0, %1\\t%@ movhi
movw%?\\t%0, %L1\\t%@ movhi
(set_attr "neg_pool_range" "*,*,*,250")]
)
-(define_insn "*thumb2_movsf_soft_insn"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
- (match_operand:SF 1 "general_operand" "r,mE,r"))]
- "TARGET_THUMB2
- && TARGET_SOFT_FLOAT
- && (GET_CODE (operands[0]) != MEM
- || register_operand (operands[1], SFmode))"
- "@
- mov%?\\t%0, %1
- ldr%?\\t%0, %1\\t%@ float
- str%?\\t%1, %0\\t%@ float"
- [(set_attr "predicable" "yes")
- (set_attr "type" "*,load1,store1")
- (set_attr "pool_range" "*,4096,*")
- (set_attr "neg_pool_range" "*,0,*")]
-)
-
-(define_insn "*thumb2_movdf_soft_insn"
- [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=r,r,r,r,m")
- (match_operand:DF 1 "soft_df_operand" "rDa,Db,Dc,mF,r"))]
- "TARGET_THUMB2 && TARGET_SOFT_FLOAT
- && ( register_operand (operands[0], DFmode)
- || register_operand (operands[1], DFmode))"
- "*
- switch (which_alternative)
- {
- case 0:
- case 1:
- case 2:
- return \"#\";
- default:
- return output_move_double (operands);
- }
- "
- [(set_attr "length" "8,12,16,8,8")
- (set_attr "type" "*,*,*,load2,store2")
- (set_attr "pool_range" "1020")
- (set_attr "neg_pool_range" "0")]
-)
-
-(define_insn "*thumb2_cmpsi_shiftsi"
- [(set (reg:CC CC_REGNUM)
- (compare:CC (match_operand:SI 0 "s_register_operand" "r")
- (match_operator:SI 3 "shift_operator"
- [(match_operand:SI 1 "s_register_operand" "r")
- (match_operand:SI 2 "const_int_operand" "M")])))]
- "TARGET_THUMB2"
- "cmp%?\\t%0, %1%S3"
- [(set_attr "conds" "set")
- (set_attr "shift" "1")
- (set_attr "type" "alu_shift")]
-)
-
-(define_insn "*thumb2_cmpsi_shiftsi_swp"
- [(set (reg:CC_SWP CC_REGNUM)
- (compare:CC_SWP (match_operator:SI 3 "shift_operator"
- [(match_operand:SI 1 "s_register_operand" "r")
- (match_operand:SI 2 "const_int_operand" "M")])
- (match_operand:SI 0 "s_register_operand" "r")))]
- "TARGET_THUMB2"
- "cmp%?\\t%0, %1%S3"
- [(set_attr "conds" "set")
- (set_attr "shift" "1")
- (set_attr "type" "alu_shift")]
-)
-
(define_insn "*thumb2_cmpsi_neg_shiftsi"
[(set (reg:CC CC_REGNUM)
(compare:CC (match_operand:SI 0 "s_register_operand" "r")
(not:SI (match_operator:SI 1 "arm_comparison_operator"
[(match_operand 2 "cc_register" "") (const_int 0)])))]
"TARGET_THUMB2"
- "ite\\t%D1\;mov%D1\\t%0, #0\;mvn%d1\\t%0, #1"
+ "ite\\t%D1\;mvn%D1\\t%0, #0\;mvn%d1\\t%0, #1"
[(set_attr "conds" "use")
(set_attr "length" "10")]
)
;; addresses will have the thumb bit set correctly.
-;; Patterns to allow combination of arithmetic, cond code and shifts
-
-(define_insn "*thumb2_arith_shiftsi"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
- (match_operator:SI 1 "shiftable_operator"
- [(match_operator:SI 3 "shift_operator"
- [(match_operand:SI 4 "s_register_operand" "r")
- (match_operand:SI 5 "const_int_operand" "M")])
- (match_operand:SI 2 "s_register_operand" "r")]))]
- "TARGET_THUMB2"
- "%i1%?\\t%0, %2, %4%S3"
- [(set_attr "predicable" "yes")
- (set_attr "shift" "4")
- (set_attr "type" "alu_shift")]
-)
-
-;; ??? What does this splitter do? Copied from the ARM version
-(define_split
- [(set (match_operand:SI 0 "s_register_operand" "")
- (match_operator:SI 1 "shiftable_operator"
- [(match_operator:SI 2 "shiftable_operator"
- [(match_operator:SI 3 "shift_operator"
- [(match_operand:SI 4 "s_register_operand" "")
- (match_operand:SI 5 "const_int_operand" "")])
- (match_operand:SI 6 "s_register_operand" "")])
- (match_operand:SI 7 "arm_rhs_operand" "")]))
- (clobber (match_operand:SI 8 "s_register_operand" ""))]
- "TARGET_32BIT"
- [(set (match_dup 8)
- (match_op_dup 2 [(match_op_dup 3 [(match_dup 4) (match_dup 5)])
- (match_dup 6)]))
- (set (match_dup 0)
- (match_op_dup 1 [(match_dup 8) (match_dup 7)]))]
- "")
-
-(define_insn "*thumb2_arith_shiftsi_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (match_operator:SI 1 "shiftable_operator"
- [(match_operator:SI 3 "shift_operator"
- [(match_operand:SI 4 "s_register_operand" "r")
- (match_operand:SI 5 "const_int_operand" "M")])
- (match_operand:SI 2 "s_register_operand" "r")])
- (const_int 0)))
- (set (match_operand:SI 0 "s_register_operand" "=r")
- (match_op_dup 1 [(match_op_dup 3 [(match_dup 4) (match_dup 5)])
- (match_dup 2)]))]
- "TARGET_32BIT"
- "%i1%.\\t%0, %2, %4%S3"
- [(set_attr "conds" "set")
- (set_attr "shift" "4")
- (set_attr "type" "alu_shift")]
-)
-
-(define_insn "*thumb2_arith_shiftsi_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV (match_operator:SI 1 "shiftable_operator"
- [(match_operator:SI 3 "shift_operator"
- [(match_operand:SI 4 "s_register_operand" "r")
- (match_operand:SI 5 "const_int_operand" "M")])
- (match_operand:SI 2 "s_register_operand" "r")])
- (const_int 0)))
- (clobber (match_scratch:SI 0 "=r"))]
- "TARGET_THUMB2"
- "%i1%.\\t%0, %2, %4%S3"
- [(set_attr "conds" "set")
- (set_attr "shift" "4")
- (set_attr "type" "alu_shift")]
-)
-
-(define_insn "*thumb2_sub_shiftsi"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
- (minus:SI (match_operand:SI 1 "s_register_operand" "r")
- (match_operator:SI 2 "shift_operator"
- [(match_operand:SI 3 "s_register_operand" "r")
- (match_operand:SI 4 "const_int_operand" "M")])))]
- "TARGET_THUMB2"
- "sub%?\\t%0, %1, %3%S2"
- [(set_attr "predicable" "yes")
- (set_attr "shift" "3")
- (set_attr "type" "alu_shift")]
-)
-
-(define_insn "*thumb2_sub_shiftsi_compare0"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
- (minus:SI (match_operand:SI 1 "s_register_operand" "r")
- (match_operator:SI 2 "shift_operator"
- [(match_operand:SI 3 "s_register_operand" "r")
- (match_operand:SI 4 "const_int_operand" "M")]))
- (const_int 0)))
- (set (match_operand:SI 0 "s_register_operand" "=r")
- (minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3)
- (match_dup 4)])))]
- "TARGET_THUMB2"
- "sub%.\\t%0, %1, %3%S2"
- [(set_attr "conds" "set")
- (set_attr "shift" "3")
- (set_attr "type" "alu_shift")]
-)
-
-(define_insn "*thumb2_sub_shiftsi_compare0_scratch"
- [(set (reg:CC_NOOV CC_REGNUM)
- (compare:CC_NOOV
- (minus:SI (match_operand:SI 1 "s_register_operand" "r")
- (match_operator:SI 2 "shift_operator"
- [(match_operand:SI 3 "s_register_operand" "r")
- (match_operand:SI 4 "const_int_operand" "M")]))
- (const_int 0)))
- (clobber (match_scratch:SI 0 "=r"))]
- "TARGET_THUMB2"
- "sub%.\\t%0, %1, %3%S2"
- [(set_attr "conds" "set")
- (set_attr "shift" "3")
- (set_attr "type" "alu_shift")]
-)
-
(define_insn "*thumb2_and_scc"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(and:SI (match_operator:SI 1 "arm_comparison_operator"
(set_attr "length" "6,10")]
)
-(define_insn "*thumb2_compare_scc"
- [(set (match_operand:SI 0 "s_register_operand" "=r,r")
- (match_operator:SI 1 "arm_comparison_operator"
- [(match_operand:SI 2 "s_register_operand" "r,r")
- (match_operand:SI 3 "arm_add_operand" "rI,L")]))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_THUMB2"
- "*
- if (operands[3] == const0_rtx)
- {
- if (GET_CODE (operands[1]) == LT)
- return \"lsr\\t%0, %2, #31\";
-
- if (GET_CODE (operands[1]) == GE)
- return \"mvn\\t%0, %2\;lsr\\t%0, %0, #31\";
-
- if (GET_CODE (operands[1]) == EQ)
- return \"rsbs\\t%0, %2, #1\;it\\tcc\;movcc\\t%0, #0\";
- }
-
- if (GET_CODE (operands[1]) == NE)
- {
- if (which_alternative == 1)
- return \"adds\\t%0, %2, #%n3\;it\\tne\;movne\\t%0, #1\";
- return \"subs\\t%0, %2, %3\;it\\tne\;movne\\t%0, #1\";
- }
- if (which_alternative == 1)
- output_asm_insn (\"cmn\\t%2, #%n3\", operands);
- else
- output_asm_insn (\"cmp\\t%2, %3\", operands);
- return \"ite\\t%D1\;mov%D1\\t%0, #0\;mov%d1\\t%0, #1\";
- "
- [(set_attr "conds" "clob")
- (set_attr "length" "14")]
-)
-
(define_insn "*thumb2_cond_move"
[(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
(if_then_else:SI (match_operator 3 "equality_operator"
;; Zero and sign extension instructions.
-(define_insn_and_split "*thumb2_zero_extendsidi2"
- [(set (match_operand:DI 0 "s_register_operand" "=r")
- (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r")))]
- "TARGET_THUMB2"
- "mov%?\\t%Q0, %1\;mov%?\\t%R0, #0"
- "&& reload_completed"
- [(set (match_dup 0) (match_dup 1))]
- "
- {
- rtx lo_part = gen_lowpart (SImode, operands[0]);
- if (!REG_P (lo_part) || REGNO (lo_part) != REGNO (operands[1]))
- emit_move_insn (lo_part, operands[1]);
- operands[0] = gen_highpart (SImode, operands[0]);
- operands[1] = const0_rtx;
- }
- "
- [(set_attr "length" "8")
- (set_attr "ce_count" "2")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn_and_split "*thumb2_zero_extendhidi2"
- [(set (match_operand:DI 0 "s_register_operand" "=r,r")
- (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
- "TARGET_THUMB2"
- "@
- uxth%?\\t%Q0, %1\;mov%?\\t%R0, #0
- ldr%(h%)\\t%Q0, %1\;mov%?\\t%R0, #0"
- "&& reload_completed"
- [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
- (set (match_dup 2) (match_dup 3))]
- "
- {
- operands[2] = gen_highpart (SImode, operands[0]);
- operands[0] = gen_lowpart (SImode, operands[0]);
- operands[3] = const0_rtx;
- }
- "
- [(set_attr "length" "8")
- (set_attr "ce_count" "2")
- (set_attr "predicable" "yes")
- (set_attr "type" "*,load_byte")
- (set_attr "pool_range" "*,4092")
- (set_attr "neg_pool_range" "*,250")]
-)
-
-(define_insn_and_split "*thumb2_zero_extendqidi2"
- [(set (match_operand:DI 0 "s_register_operand" "=r,r")
- (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
- "TARGET_THUMB2"
- "@
- uxtb%?\\t%Q0, %1\;mov%?\\t%R0, #0
- ldr%(b%)\\t%Q0, %1\;mov%?\\t%R0, #0"
- "&& reload_completed"
- [(set (match_dup 0) (zero_extend:SI (match_dup 1)))
- (set (match_dup 2) (match_dup 3))]
- "
- {
- operands[2] = gen_highpart (SImode, operands[0]);
- operands[0] = gen_lowpart (SImode, operands[0]);
- operands[3] = const0_rtx;
- }
- "
- [(set_attr "length" "8")
- (set_attr "ce_count" "2")
- (set_attr "predicable" "yes")
- (set_attr "type" "*,load_byte")
- (set_attr "pool_range" "*,4092")
- (set_attr "neg_pool_range" "*,250")]
-)
-
-(define_insn_and_split "*thumb2_extendsidi2"
- [(set (match_operand:DI 0 "s_register_operand" "=r")
- (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r")))]
- "TARGET_THUMB2"
- "mov%?\\t%Q0, %1\;asr?\\t%R0, %1, #31"
- "&& reload_completed"
- [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 31)))]
- {
- rtx lo_part = gen_lowpart (SImode, operands[0]);
-
- if (!REG_P (lo_part) || REGNO (lo_part) != REGNO (operands[1]))
- emit_move_insn (lo_part, operands[1]);
- operands[0] = gen_highpart (SImode, operands[0]);
- }
- [(set_attr "length" "8")
- (set_attr "ce_count" "2")
- (set_attr "shift" "1")
- (set_attr "predicable" "yes")]
-)
-
-(define_insn_and_split "*thumb2_extendhidi2"
- [(set (match_operand:DI 0 "s_register_operand" "=r,r")
- (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
- "TARGET_THUMB2"
- "@
- sxth%?\\t%Q0, %1\;asr%?\\t%R0, %Q0, #31
- ldrsh%?\\t%Q0, %1\;asr%?\\t%R0, %Q0, #31"
- "&& reload_completed"
- [(set (match_dup 0) (sign_extend:SI (match_dup 1)))
- (set (match_dup 2) (ashiftrt:SI (match_dup 0) (const_int 31)))]
- "
- {
- operands[2] = gen_highpart (SImode, operands[0]);
- operands[0] = gen_lowpart (SImode, operands[0]);
- }
- "
- [(set_attr "length" "8")
- (set_attr "ce_count" "2")
- (set_attr "predicable" "yes")
- (set_attr "type" "*,load_byte")
- (set_attr "pool_range" "*,4092")
- (set_attr "neg_pool_range" "*,250")]
-)
-
-(define_insn_and_split "*thumb2_extendqidi2"
- [(set (match_operand:DI 0 "s_register_operand" "=r,r")
- (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
- "TARGET_THUMB2"
- "@
- sxtb%?\\t%Q0, %1\;asr%?\\t%R0, %Q0, #31
- ldrsb%?\\t%Q0, %1\;asr%?\\t%R0, %Q0, #31"
- "&& reload_completed"
- [(set (match_dup 0) (sign_extend:SI (match_dup 1)))
- (set (match_dup 2) (ashiftrt:SI (match_dup 0) (const_int 31)))]
- "
- {
- operands[2] = gen_highpart (SImode, operands[0]);
- operands[0] = gen_lowpart (SImode, operands[0]);
- }
- "
- [(set_attr "length" "8")
- (set_attr "ce_count" "2")
- (set_attr "predicable" "yes")
- (set_attr "type" "*,load_byte")
- (set_attr "pool_range" "*,4092")
- (set_attr "neg_pool_range" "*,250")]
-)
-
;; All supported Thumb2 implementations are armv6, so only that case is
;; provided.
(define_insn "*thumb2_extendqisi_v6"
(set_attr "neg_pool_range" "*,250")]
)
-(define_insn "*thumb2_zero_extendqisi2_v6"
+(define_insn "thumb2_zero_extendqisi2_v6"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
"TARGET_THUMB2 && arm_arch6"
(set_attr "length" "20")]
)
+;; Note: this is not predicable, to avoid issues with linker-generated
+;; interworking stubs.
+(define_insn "*thumb2_return"
+ [(return)]
+ "TARGET_THUMB2 && USE_RETURN_INSN (FALSE)"
+ "*
+ {
+ return output_return_instruction (const_true_rtx, TRUE, FALSE);
+ }"
+ [(set_attr "type" "load1")
+ (set_attr "length" "12")]
+)
+
(define_insn_and_split "thumb2_eh_return"
[(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")]
VUNSPEC_EH_RETURN)
}"
)
-;; Peepholes and insns for 16-bit flag clobbering instructions.
-;; The conditional forms of these instructions do not clobber CC.
-;; However by the time peepholes are run it is probably too late to do
-;; anything useful with this information.
-(define_peephole2
- [(set (match_operand:SI 0 "low_register_operand" "")
- (match_operator:SI 3 "thumb_16bit_operator"
- [(match_operand:SI 1 "low_register_operand" "")
- (match_operand:SI 2 "low_register_operand" "")]))]
- "TARGET_THUMB2
- && (rtx_equal_p(operands[0], operands[1])
- || GET_CODE(operands[3]) == PLUS
- || GET_CODE(operands[3]) == MINUS)
- && peep2_regno_dead_p(0, CC_REGNUM)"
- [(parallel
- [(set (match_dup 0)
- (match_op_dup 3
- [(match_dup 1)
- (match_dup 2)]))
- (clobber (reg:CC CC_REGNUM))])]
- ""
-)
-
(define_insn "*thumb2_alusi3_short"
[(set (match_operand:SI 0 "s_register_operand" "=l")
(match_operator:SI 3 "thumb_16bit_operator"
(match_operand:SI 2 "low_reg_or_int_operand" "")]))]
"TARGET_THUMB2
&& peep2_regno_dead_p(0, CC_REGNUM)
+ && (CONST_INT_P (operands[2]) || operands[1] == operands[0])
&& ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
|| REG_P(operands[2]))"
[(parallel
)
(define_insn "*thumb2_shiftsi3_short"
- [(set (match_operand:SI 0 "low_register_operand" "=l")
+ [(set (match_operand:SI 0 "low_register_operand" "=l,l")
(match_operator:SI 3 "shift_operator"
- [(match_operand:SI 1 "low_register_operand" "l")
- (match_operand:SI 2 "low_reg_or_int_operand" "lM")]))
+ [(match_operand:SI 1 "low_register_operand" "0,l")
+ (match_operand:SI 2 "low_reg_or_int_operand" "l,M")]))
(clobber (reg:CC CC_REGNUM))]
"TARGET_THUMB2 && reload_completed
&& ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
)
(define_insn "*thumb2_addsi_short"
- [(set (match_operand:SI 0 "low_register_operand" "=l")
- (plus:SI (match_operand:SI 1 "low_register_operand" "l")
- (match_operand:SI 2 "low_reg_or_int_operand" "lIL")))
+ [(set (match_operand:SI 0 "low_register_operand" "=l,l")
+ (plus:SI (match_operand:SI 1 "low_register_operand" "l,0")
+ (match_operand:SI 2 "low_reg_or_int_operand" "lPt,Ps")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_THUMB2 && reload_completed"
"*
(set_attr "length" "2")]
)
-(define_insn "divsi3"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
- (div:SI (match_operand:SI 1 "s_register_operand" "r")
- (match_operand:SI 2 "s_register_operand" "r")))]
- "TARGET_THUMB2 && arm_arch_hwdiv"
- "sdiv%?\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "insn" "sdiv")]
-)
-
-(define_insn "udivsi3"
- [(set (match_operand:SI 0 "s_register_operand" "=r")
- (udiv:SI (match_operand:SI 1 "s_register_operand" "r")
- (match_operand:SI 2 "s_register_operand" "r")))]
- "TARGET_THUMB2 && arm_arch_hwdiv"
- "udiv%?\t%0, %1, %2"
- [(set_attr "predicable" "yes")
- (set_attr "insn" "udiv")]
-)
-
(define_insn "*thumb2_subsi_short"
[(set (match_operand:SI 0 "low_register_operand" "=l")
(minus:SI (match_operand:SI 1 "low_register_operand" "l")
(set_attr "length" "2")]
)
+(define_peephole2
+ [(set (match_operand:CC 0 "cc_register" "")
+ (compare:CC (match_operand:SI 1 "low_register_operand" "")
+ (match_operand:SI 2 "const_int_operand" "")))]
+ "TARGET_THUMB2
+ && peep2_reg_dead_p (1, operands[1])
+ && satisfies_constraint_Pw (operands[2])"
+ [(parallel
+ [(set (match_dup 0) (compare:CC (match_dup 1) (match_dup 2)))
+ (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 3)))])]
+ "operands[3] = GEN_INT (- INTVAL (operands[2]));"
+)
+
+(define_peephole2
+ [(match_scratch:SI 3 "l")
+ (set (match_operand:CC 0 "cc_register" "")
+ (compare:CC (match_operand:SI 1 "low_register_operand" "")
+ (match_operand:SI 2 "const_int_operand" "")))]
+ "TARGET_THUMB2
+ && satisfies_constraint_Px (operands[2])"
+ [(parallel
+ [(set (match_dup 0) (compare:CC (match_dup 1) (match_dup 2)))
+ (set (match_dup 3) (plus:SI (match_dup 1) (match_dup 4)))])]
+ "operands[4] = GEN_INT (- INTVAL (operands[2]));"
+)
+
+(define_insn "thumb2_addsi3_compare0"
+ [(set (reg:CC_NOOV CC_REGNUM)
+ (compare:CC_NOOV
+ (plus:SI (match_operand:SI 1 "s_register_operand" "l, 0, r")
+ (match_operand:SI 2 "arm_add_operand" "lPt,Ps,rIL"))
+ (const_int 0)))
+ (set (match_operand:SI 0 "s_register_operand" "=l,l,r")
+ (plus:SI (match_dup 1) (match_dup 2)))]
+ "TARGET_THUMB2"
+ "*
+ HOST_WIDE_INT val;
+
+ if (GET_CODE (operands[2]) == CONST_INT)
+ val = INTVAL (operands[2]);
+ else
+ val = 0;
+
+ if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val)))
+ return \"subs\\t%0, %1, #%n2\";
+ else
+ return \"adds\\t%0, %1, %2\";
+ "
+ [(set_attr "conds" "set")
+ (set_attr "length" "2,2,4")]
+)
+
+(define_insn "*thumb2_addsi3_compare0_scratch"
+ [(set (reg:CC_NOOV CC_REGNUM)
+ (compare:CC_NOOV
+ (plus:SI (match_operand:SI 0 "s_register_operand" "l, r")
+ (match_operand:SI 1 "arm_add_operand" "lPv,rIL"))
+ (const_int 0)))]
+ "TARGET_THUMB2"
+ "*
+ HOST_WIDE_INT val;
+
+ if (GET_CODE (operands[1]) == CONST_INT)
+ val = INTVAL (operands[1]);
+ else
+ val = 0;
+
+ if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val)))
+ return \"cmp\\t%0, #%n1\";
+ else
+ return \"cmn\\t%0, %1\";
+ "
+ [(set_attr "conds" "set")
+ (set_attr "length" "2,4")]
+)
+
;; 16-bit encodings of "muls" and "mul<c>". We only use these when
;; optimizing for size since "muls" is slow on all known
;; implementations and since "mul<c>" will be generated by
(if_then_else
(and (ge (minus (match_dup 1) (pc)) (const_int 2))
(le (minus (match_dup 1) (pc)) (const_int 128))
- (eq (symbol_ref ("which_alternative")) (const_int 0)))
+ (not (match_test "which_alternative")))
(const_int 2)
(const_int 8)))]
)
(if_then_else
(and (ge (minus (match_dup 1) (pc)) (const_int 2))
(le (minus (match_dup 1) (pc)) (const_int 128))
- (eq (symbol_ref ("which_alternative")) (const_int 0)))
+ (not (match_test "which_alternative")))
(const_int 2)
(const_int 8)))]
)
(set_attr "length" "2")]
)
-(define_insn "orsi_notsi_si"
+(define_insn "*orsi_notsi_si"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(ior:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
(match_operand:SI 1 "s_register_operand" "r")))]
[(set_attr "predicable" "yes")]
)
-(define_insn "*thumb_orsi_not_shiftsi_si"
+(define_insn "*orsi_not_shiftsi_si"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(ior:SI (not:SI (match_operator:SI 4 "shift_operator"
[(match_operand:SI 2 "s_register_operand" "r")
(set_attr "type" "alu_shift")]
)
-(define_insn_and_split "*thumb2_iorsi3"
- [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
- (ior:SI (match_operand:SI 1 "s_register_operand" "r,r,r")
- (match_operand:SI 2 "reg_or_int_operand" "rI,K,?n")))]
- "TARGET_THUMB2"
- "@
- orr%?\\t%0, %1, %2
- orn%?\\t%0, %1, #%B2
- #"
+(define_peephole2
+ [(set (match_operand:CC_NOOV 0 "cc_register" "")
+ (compare:CC_NOOV (zero_extract:SI
+ (match_operand:SI 1 "low_register_operand" "")
+ (const_int 1)
+ (match_operand:SI 2 "const_int_operand" ""))
+ (const_int 0)))
+ (match_scratch:SI 3 "l")
+ (set (pc)
+ (if_then_else (match_operator:CC_NOOV 4 "equality_operator"
+ [(match_dup 0) (const_int 0)])
+ (match_operand 5 "" "")
+ (match_operand 6 "" "")))]
"TARGET_THUMB2
- && GET_CODE (operands[2]) == CONST_INT
- && !(const_ok_for_arm (INTVAL (operands[2]))
- || const_ok_for_arm (~INTVAL (operands[2])))"
- [(clobber (const_int 0))]
+ && (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32)"
+ [(parallel [(set (match_dup 0)
+ (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
+ (const_int 0)))
+ (clobber (match_dup 3))])
+ (set (pc)
+ (if_then_else (match_op_dup 4 [(match_dup 0) (const_int 0)])
+ (match_dup 5) (match_dup 6)))]
"
- arm_split_constant (IOR, SImode, curr_insn,
- INTVAL (operands[2]), operands[0], operands[1], 0);
- DONE;
+ operands[2] = GEN_INT (31 - INTVAL (operands[2]));
+ operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? LT : GE,
+ VOIDmode, operands[0], const0_rtx);
+ ")
+
+(define_peephole2
+ [(set (match_operand:CC_NOOV 0 "cc_register" "")
+ (compare:CC_NOOV (zero_extract:SI
+ (match_operand:SI 1 "low_register_operand" "")
+ (match_operand:SI 2 "const_int_operand" "")
+ (const_int 0))
+ (const_int 0)))
+ (match_scratch:SI 3 "l")
+ (set (pc)
+ (if_then_else (match_operator:CC_NOOV 4 "equality_operator"
+ [(match_dup 0) (const_int 0)])
+ (match_operand 5 "" "")
+ (match_operand 6 "" "")))]
+ "TARGET_THUMB2
+ && (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 32)"
+ [(parallel [(set (match_dup 0)
+ (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
+ (const_int 0)))
+ (clobber (match_dup 3))])
+ (set (pc)
+ (if_then_else (match_op_dup 4 [(match_dup 0) (const_int 0)])
+ (match_dup 5) (match_dup 6)))]
"
- [(set_attr "length" "4,4,16")
- (set_attr "predicable" "yes")]
-)
+ operands[2] = GEN_INT (32 - INTVAL (operands[2]));
+ ")
+
+;; Define the subtract-one-and-jump insns so loop.c
+;; knows what to generate.
+(define_expand "doloop_end"
+ [(use (match_operand 0 "" "")) ; loop pseudo
+ (use (match_operand 1 "" "")) ; iterations; zero if unknown
+ (use (match_operand 2 "" "")) ; max iterations
+ (use (match_operand 3 "" "")) ; loop level
+ (use (match_operand 4 "" ""))] ; label
+ "TARGET_32BIT"
+ "
+ {
+ /* Currently SMS relies on the do-loop pattern to recognize loops
+ where (1) the control part consists of all insns defining and/or
+ using a certain 'count' register and (2) the loop count can be
+ adjusted by modifying this register prior to the loop.
+ ??? The possible introduction of a new block to initialize the
+ new IV can potentially affect branch optimizations. */
+ if (optimize > 0 && flag_modulo_sched)
+ {
+ rtx s0;
+ rtx bcomp;
+ rtx loc_ref;
+ rtx cc_reg;
+ rtx insn;
+ rtx cmp;
+
+ /* Only use this on innermost loops. */
+ if (INTVAL (operands[3]) > 1)
+ FAIL;
+
+ if (GET_MODE (operands[0]) != SImode)
+ FAIL;
+
+ s0 = operands [0];
+ if (TARGET_THUMB2)
+ insn = emit_insn (gen_thumb2_addsi3_compare0 (s0, s0, GEN_INT (-1)));
+ else
+ insn = emit_insn (gen_addsi3_compare0 (s0, s0, GEN_INT (-1)));
+
+ cmp = XVECEXP (PATTERN (insn), 0, 0);
+ cc_reg = SET_DEST (cmp);
+ bcomp = gen_rtx_NE (VOIDmode, cc_reg, const0_rtx);
+ loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands [4]);
+ emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
+ gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp,
+ loc_ref, pc_rtx)));
+ DONE;
+ }else
+ FAIL;
+ }")
+
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