static struct machine_function * ix86_init_machine_status (void);
static rtx ix86_function_value (const_tree, const_tree, bool);
static bool ix86_function_value_regno_p (const unsigned int);
-static unsigned int ix86_function_arg_boundary (enum machine_mode,
+static unsigned int ix86_function_arg_boundary (machine_mode,
const_tree);
static rtx ix86_static_chain (const_tree, bool);
static int ix86_function_regparm (const_tree, const_tree);
static void ix86_compute_frame_layout (struct ix86_frame *);
-static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
+static bool ix86_expand_vector_init_one_nonzero (bool, machine_mode,
rtx, rtx, int);
static void ix86_add_new_builtins (HOST_WIDE_INT);
static tree ix86_canonical_va_list_type (tree);
for (i = 0; i < n_operands; i++)
{
rtx op = recog_data.operand[i];
- enum machine_mode mode = GET_MODE (op);
+ machine_mode mode = GET_MODE (op);
const operand_alternative *op_alt;
int offset = 0;
bool win;
/* Return if we do not know how to pass TYPE solely in registers. */
static bool
-ix86_must_pass_in_stack (enum machine_mode mode, const_tree type)
+ix86_must_pass_in_stack (machine_mode mode, const_tree type)
{
if (must_pass_in_stack_var_size_or_pad (mode, type))
return true;
/* Return 1 if pseudo register should be created and used to hold
GOT address for PIC code. */
-static bool
+bool
ix86_use_pseudo_pic_reg (void)
{
if ((TARGET_64BIT
}
else
{
- rtx insn = emit_insn (gen_set_got (pic_offset_table_rtx));
+ /* If there is future mcount call in the function it is more profitable
+ to emit SET_GOT into ABI defined REAL_PIC_OFFSET_TABLE_REGNUM. */
+ rtx reg = crtl->profile
+ ? gen_rtx_REG (Pmode, REAL_PIC_OFFSET_TABLE_REGNUM)
+ : pic_offset_table_rtx;
+ rtx insn = emit_insn (gen_set_got (reg));
RTX_FRAME_RELATED_P (insn) = 1;
+ if (crtl->profile)
+ emit_move_insn (pic_offset_table_rtx, reg);
add_reg_note (insn, REG_CFA_FLUSH_QUEUE, NULL_RTX);
}
If INT_RETURN is true, warn ABI change if the vector mode isn't
available for function return value. */
-static enum machine_mode
+static machine_mode
type_natural_mode (const_tree type, const CUMULATIVE_ARGS *cum,
bool in_return)
{
- enum machine_mode mode = TYPE_MODE (type);
+ machine_mode mode = TYPE_MODE (type);
if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
{
/* ??? Generic code allows us to create width 1 vectors. Ignore. */
&& TYPE_VECTOR_SUBPARTS (type) > 1)
{
- enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
+ machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
mode = MIN_MODE_VECTOR_FLOAT;
go ahead and use it. Otherwise we have to build a PARALLEL instead. */
static rtx
-gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
+gen_reg_or_parallel (machine_mode mode, machine_mode orig_mode,
unsigned int regno)
{
rtx tmp;
*/
static int
-classify_argument (enum machine_mode mode, const_tree type,
+classify_argument (machine_mode mode, const_tree type,
enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
{
HOST_WIDE_INT bytes =
class. Return true iff parameter should be passed in memory. */
static bool
-examine_argument (enum machine_mode mode, const_tree type, int in_return,
+examine_argument (machine_mode mode, const_tree type, int in_return,
int *int_nregs, int *sse_nregs)
{
enum x86_64_reg_class regclass[MAX_CLASSES];
FUNCTION_ARG for the detailed description. */
static rtx
-construct_container (enum machine_mode mode, enum machine_mode orig_mode,
+construct_container (machine_mode mode, machine_mode orig_mode,
const_tree type, int in_return, int nintregs, int nsseregs,
const int *intreg, int sse_regno)
{
static bool issued_sse_ret_error;
static bool issued_x87_ret_error;
- enum machine_mode tmpmode;
+ machine_mode tmpmode;
int bytes =
(mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
enum x86_64_reg_class regclass[MAX_CLASSES];
may not be available.) */
static void
-function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
+function_arg_advance_32 (CUMULATIVE_ARGS *cum, machine_mode mode,
const_tree type, HOST_WIDE_INT bytes,
HOST_WIDE_INT words)
{
}
static void
-function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
+function_arg_advance_64 (CUMULATIVE_ARGS *cum, machine_mode mode,
const_tree type, HOST_WIDE_INT words, bool named)
{
int int_nregs, sse_nregs;
may not be available.) */
static void
-ix86_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
+ix86_function_arg_advance (cumulative_args_t cum_v, machine_mode mode,
const_tree type, bool named)
{
CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
(otherwise it is an extra parameter matching an ellipsis). */
static rtx
-function_arg_32 (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
- enum machine_mode orig_mode, const_tree type,
+function_arg_32 (const CUMULATIVE_ARGS *cum, machine_mode mode,
+ machine_mode orig_mode, const_tree type,
HOST_WIDE_INT bytes, HOST_WIDE_INT words)
{
/* Avoid the AL settings for the Unix64 ABI. */
}
static rtx
-function_arg_64 (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
- enum machine_mode orig_mode, const_tree type, bool named)
+function_arg_64 (const CUMULATIVE_ARGS *cum, machine_mode mode,
+ machine_mode orig_mode, const_tree type, bool named)
{
/* Handle a hidden AL argument containing number of registers
for varargs x86-64 functions. */
}
static rtx
-function_arg_ms_64 (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
- enum machine_mode orig_mode, bool named,
+function_arg_ms_64 (const CUMULATIVE_ARGS *cum, machine_mode mode,
+ machine_mode orig_mode, bool named,
HOST_WIDE_INT bytes)
{
unsigned int regno;
ellipsis). */
static rtx
-ix86_function_arg (cumulative_args_t cum_v, enum machine_mode omode,
+ix86_function_arg (cumulative_args_t cum_v, machine_mode omode,
const_tree type, bool named)
{
CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
- enum machine_mode mode = omode;
+ machine_mode mode = omode;
HOST_WIDE_INT bytes, words;
rtx arg;
appropriate for passing a pointer to that type. */
static bool
-ix86_pass_by_reference (cumulative_args_t cum_v, enum machine_mode mode,
+ix86_pass_by_reference (cumulative_args_t cum_v, machine_mode mode,
const_tree type, bool)
{
CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
static bool
ix86_compat_aligned_value_p (const_tree type)
{
- enum machine_mode mode = TYPE_MODE (type);
+ machine_mode mode = TYPE_MODE (type);
if (((TARGET_SSE && SSE_REG_MODE_P (mode))
|| mode == TDmode
|| mode == TFmode
compatibility with previous versions of GCC. */
static unsigned int
-ix86_compat_function_arg_boundary (enum machine_mode mode,
+ix86_compat_function_arg_boundary (machine_mode mode,
const_tree type, unsigned int align)
{
/* In 32bit, only _Decimal128 and __float128 are aligned to their
static bool
ix86_contains_aligned_value_p (const_tree type)
{
- enum machine_mode mode = TYPE_MODE (type);
+ machine_mode mode = TYPE_MODE (type);
if (mode == XFmode || mode == XCmode)
return false;
specified mode and type. */
static unsigned int
-ix86_function_arg_boundary (enum machine_mode mode, const_tree type)
+ix86_function_arg_boundary (machine_mode mode, const_tree type)
{
unsigned int align;
if (type)
otherwise, FUNC is 0. */
static rtx
-function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
+function_value_32 (machine_mode orig_mode, machine_mode mode,
const_tree fntype, const_tree fn)
{
unsigned int regno;
}
static rtx
-function_value_64 (enum machine_mode orig_mode, enum machine_mode mode,
+function_value_64 (machine_mode orig_mode, machine_mode mode,
const_tree valtype)
{
rtx ret;
}
static rtx
-function_value_ms_64 (enum machine_mode orig_mode, enum machine_mode mode,
+function_value_ms_64 (machine_mode orig_mode, machine_mode mode,
const_tree valtype)
{
unsigned int regno = AX_REG;
static rtx
ix86_function_value_1 (const_tree valtype, const_tree fntype_or_decl,
- enum machine_mode orig_mode, enum machine_mode mode)
+ machine_mode orig_mode, machine_mode mode)
{
const_tree fn, fntype;
static rtx
ix86_function_value (const_tree valtype, const_tree fntype_or_decl, bool)
{
- enum machine_mode mode, orig_mode;
+ machine_mode mode, orig_mode;
orig_mode = TYPE_MODE (valtype);
mode = type_natural_mode (valtype, NULL, true);
/* Pointer function arguments and return values are promoted to
word_mode. */
-static enum machine_mode
-ix86_promote_function_mode (const_tree type, enum machine_mode mode,
+static machine_mode
+ix86_promote_function_mode (const_tree type, machine_mode mode,
int *punsignedp, const_tree fntype,
int for_return)
{
should be accessed using BLKmode. */
static bool
-ix86_member_type_forces_blk (const_tree field, enum machine_mode mode)
+ix86_member_type_forces_blk (const_tree field, machine_mode mode)
{
/* Union with XFmode must be in BLKmode. */
return (mode == XFmode
}
rtx
-ix86_libcall_value (enum machine_mode mode)
+ix86_libcall_value (machine_mode mode)
{
return ix86_function_value_1 (NULL, NULL, mode, mode);
}
#ifdef SUBTARGET_RETURN_IN_MEMORY
return SUBTARGET_RETURN_IN_MEMORY (type, fntype);
#else
- const enum machine_mode mode = type_natural_mode (type, NULL, true);
+ const machine_mode mode = type_natural_mode (type, NULL, true);
HOST_WIDE_INT size;
if (TARGET_64BIT)
if (ix86_varargs_fpr_size)
{
- enum machine_mode smode;
+ machine_mode smode;
rtx_code_label *label;
rtx test;
}
static void
-ix86_setup_incoming_varargs (cumulative_args_t cum_v, enum machine_mode mode,
+ix86_setup_incoming_varargs (cumulative_args_t cum_v, machine_mode mode,
tree type, int *, int no_rtl)
{
CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
rtx container;
int indirect_p = 0;
tree ptrtype;
- enum machine_mode nat_mode;
+ machine_mode nat_mode;
unsigned int arg_boundary;
/* Only 64bit target needs something special. */
{
rtx slot = XVECEXP (container, 0, i);
rtx reg = XEXP (slot, 0);
- enum machine_mode mode = GET_MODE (reg);
+ machine_mode mode = GET_MODE (reg);
tree piece_type;
tree addr_type;
tree daddr_type;
int
standard_80387_constant_p (rtx x)
{
- enum machine_mode mode = GET_MODE (x);
+ machine_mode mode = GET_MODE (x);
REAL_VALUE_TYPE r;
int
standard_sse_constant_p (rtx x)
{
- enum machine_mode mode = GET_MODE (x);
+ machine_mode mode = GET_MODE (x);
if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
return 1;
static bool
ix86_save_reg (unsigned int regno, bool maybe_eh_return)
{
- if (pic_offset_table_rtx
- && !ix86_use_pseudo_pic_reg ()
- && regno == REAL_PIC_OFFSET_TABLE_REGNUM
- && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
- || crtl->profile
- || crtl->calls_eh_return
- || crtl->uses_const_pool
- || cfun->has_nonlocal_label))
- return ix86_select_alt_pic_regnum () == INVALID_REGNUM;
+ if (regno == REAL_PIC_OFFSET_TABLE_REGNUM
+ && pic_offset_table_rtx)
+ {
+ if (ix86_use_pseudo_pic_reg ())
+ {
+ /* REAL_PIC_OFFSET_TABLE_REGNUM used by call to
+ _mcount in prologue. */
+ if (!TARGET_64BIT && flag_pic && crtl->profile)
+ return true;
+ }
+ else if (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
+ || crtl->profile
+ || crtl->calls_eh_return
+ || crtl->uses_const_pool
+ || cfun->has_nonlocal_label)
+ return ix86_select_alt_pic_regnum () == INVALID_REGNUM;
+ }
if (crtl->calls_eh_return && maybe_eh_return)
{
/* Emit a single register save at CFA - CFA_OFFSET. */
static void
-ix86_emit_save_reg_using_mov (enum machine_mode mode, unsigned int regno,
+ix86_emit_save_reg_using_mov (machine_mode mode, unsigned int regno,
HOST_WIDE_INT cfa_offset)
{
struct machine_function *m = cfun->machine;
crtl->stack_realign_finalized = true;
}
+/* Delete SET_GOT right after entry block if it is allocated to reg. */
+
+static void
+ix86_elim_entry_set_got (rtx reg)
+{
+ basic_block bb = ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb;
+ rtx_insn *c_insn = BB_HEAD (bb);
+ if (!NONDEBUG_INSN_P (c_insn))
+ c_insn = next_nonnote_nondebug_insn (c_insn);
+ if (c_insn && NONJUMP_INSN_P (c_insn))
+ {
+ rtx pat = PATTERN (c_insn);
+ if (GET_CODE (pat) == PARALLEL)
+ {
+ rtx vec = XVECEXP (pat, 0, 0);
+ if (GET_CODE (vec) == SET
+ && XINT (XEXP (vec, 1), 1) == UNSPEC_SET_GOT
+ && REGNO (XEXP (vec, 0)) == REGNO (reg))
+ delete_insn (c_insn);
+ }
+ }
+}
+
/* Expand the prologue into a bunch of separate insns. */
void
if (!sse_registers_saved)
ix86_emit_save_sse_regs_using_mov (frame.sse_reg_save_offset);
+ /* For the mcount profiling on 32 bit PIC mode we need to emit SET_GOT
+ in PROLOGUE. */
+ if (!TARGET_64BIT && pic_offset_table_rtx && crtl->profile && !flag_fentry)
+ {
+ rtx pic = gen_rtx_REG (Pmode, REAL_PIC_OFFSET_TABLE_REGNUM);
+ insn = emit_insn (gen_set_got (pic));
+ RTX_FRAME_RELATED_P (insn) = 1;
+ add_reg_note (insn, REG_CFA_FLUSH_QUEUE, NULL_RTX);
+ emit_insn (gen_prologue_use (pic));
+ /* Deleting already emmitted SET_GOT if exist and allocated to
+ REAL_PIC_OFFSET_TABLE_REGNUM. */
+ ix86_elim_entry_set_got (pic);
+ }
+
if (crtl->drap_reg && !crtl->stack_realign_needed)
{
/* vDRAP is setup but after reload it turns out stack realign
requires to two regs - that would mean more pseudos with longer
lifetimes. */
static int
-ix86_address_cost (rtx x, enum machine_mode, addr_space_t, bool)
+ix86_address_cost (rtx x, machine_mode, addr_space_t, bool)
{
struct ix86_address parts;
int cost = 1;
satisfies CONSTANT_P. */
static bool
-ix86_legitimate_constant_p (enum machine_mode, rtx x)
+ix86_legitimate_constant_p (machine_mode, rtx x)
{
switch (GET_CODE (x))
{
is checked above. */
static bool
-ix86_cannot_force_const_mem (enum machine_mode mode, rtx x)
+ix86_cannot_force_const_mem (machine_mode mode, rtx x)
{
/* We can always put integral constants and vectors in memory. */
switch (GET_CODE (x))
0 if it should not. */
bool
-ix86_legitimize_reload_address (rtx x, enum machine_mode, int opnum, int type,
+ix86_legitimize_reload_address (rtx x, machine_mode, int opnum, int type,
int)
{
/* Reload can generate:
static rtx
ix86_validate_address_register (rtx op)
{
- enum machine_mode mode = GET_MODE (op);
+ machine_mode mode = GET_MODE (op);
/* Only SImode or DImode registers can form the address. */
if (mode != SImode && mode != DImode)
be recognized. */
static bool
-ix86_legitimate_address_p (enum machine_mode, rtx addr, bool strict)
+ix86_legitimate_address_p (machine_mode, rtx addr, bool strict)
{
struct ix86_address parts;
rtx base, index, disp;
else
{
rtx base = legitimize_pic_address (op0, reg);
- enum machine_mode mode = GET_MODE (base);
+ machine_mode mode = GET_MODE (base);
new_rtx
= legitimize_pic_address (op1, base == reg ? NULL_RTX : reg);
/* Load the thread pointer. If TO_REG is true, force it into a register. */
static rtx
-get_thread_pointer (enum machine_mode tp_mode, bool to_reg)
+get_thread_pointer (machine_mode tp_mode, bool to_reg)
{
rtx tp = gen_rtx_UNSPEC (ptr_mode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
{
rtx dest, base, off;
rtx pic = NULL_RTX, tp = NULL_RTX;
- enum machine_mode tp_mode = Pmode;
+ machine_mode tp_mode = Pmode;
int type;
/* Fall back to global dynamic model if tool chain cannot support local
See comments by legitimize_pic_address in i386.c for details. */
static rtx
-ix86_legitimize_address (rtx x, rtx, enum machine_mode mode)
+ix86_legitimize_address (rtx x, rtx, machine_mode mode)
{
int changed = 0;
unsigned log;
}
\f
static void
-put_condition_code (enum rtx_code code, enum machine_mode mode, bool reverse,
+put_condition_code (enum rtx_code code, machine_mode mode, bool reverse,
bool fp, FILE *file)
{
const char *suffix;
that parallel "operands". */
void
-split_double_mode (enum machine_mode mode, rtx operands[],
+split_double_mode (machine_mode mode, rtx operands[],
int num, rtx lo_half[], rtx hi_half[])
{
- enum machine_mode half_mode;
+ machine_mode half_mode;
unsigned int byte;
switch (mode)
}
void
-ix86_expand_move (enum machine_mode mode, rtx operands[])
+ix86_expand_move (machine_mode mode, rtx operands[])
{
rtx op0, op1;
enum tls_model model;
}
void
-ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
+ix86_expand_vector_move (machine_mode mode, rtx operands[])
{
rtx op0 = operands[0], op1 = operands[1];
unsigned int align = GET_MODE_ALIGNMENT (mode);
rtx (*extract) (rtx, rtx, rtx);
rtx (*load_unaligned) (rtx, rtx);
rtx (*store_unaligned) (rtx, rtx);
- enum machine_mode mode;
+ machine_mode mode;
switch (GET_MODE (op0))
{
*/
void
-ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
+ix86_expand_vector_move_misalign (machine_mode mode, rtx operands[])
{
rtx op0, op1, orig_op0 = NULL_RTX, m;
rtx (*load_unaligned) (rtx, rtx);
operand order. Returns true if the operands should be swapped. */
static bool
-ix86_swap_binary_operands_p (enum rtx_code code, enum machine_mode mode,
+ix86_swap_binary_operands_p (enum rtx_code code, machine_mode mode,
rtx operands[])
{
rtx dst = operands[0];
destination in operands[0], a copy operation will be required. */
rtx
-ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
+ix86_fixup_binary_operands (enum rtx_code code, machine_mode mode,
rtx operands[])
{
rtx dst = operands[0];
void
ix86_fixup_binary_operands_no_copy (enum rtx_code code,
- enum machine_mode mode, rtx operands[])
+ machine_mode mode, rtx operands[])
{
rtx dst = ix86_fixup_binary_operands (code, mode, operands);
gcc_assert (dst == operands[0]);
memory references (one output, two input) in a single insn. */
void
-ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
+ix86_expand_binary_operator (enum rtx_code code, machine_mode mode,
rtx operands[])
{
rtx src1, src2, dst, op, clob;
the given OPERANDS. */
void
-ix86_expand_vector_logical_operator (enum rtx_code code, enum machine_mode mode,
+ix86_expand_vector_logical_operator (enum rtx_code code, machine_mode mode,
rtx operands[])
{
rtx op1 = NULL_RTX, op2 = NULL_RTX;
appropriate constraints. */
bool
-ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
+ix86_binary_operator_ok (enum rtx_code code, machine_mode mode,
rtx operands[3])
{
rtx dst = operands[0];
memory references (one output, one input) in a single insn. */
void
-ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
+ix86_expand_unary_operator (enum rtx_code code, machine_mode mode,
rtx operands[])
{
int matching_memory;
divisor are within the range [0-255]. */
void
-ix86_split_idivmod (enum machine_mode mode, rtx operands[],
+ix86_split_idivmod (machine_mode mode, rtx operands[],
bool signed_p)
{
rtx_code_label *end_label, *qimode_label;
matches destination. RTX includes clobber of FLAGS_REG. */
static void
-ix86_emit_binop (enum rtx_code code, enum machine_mode mode,
+ix86_emit_binop (enum rtx_code code, machine_mode mode,
rtx dst, rtx src)
{
rtx op, clob;
at lea position. */
void
-ix86_split_lea_for_addr (rtx_insn *insn, rtx operands[], enum machine_mode mode)
+ix86_split_lea_for_addr (rtx_insn *insn, rtx operands[], machine_mode mode)
{
unsigned int regno0, regno1, regno2;
struct ix86_address parts;
bool
ix86_unary_operator_ok (enum rtx_code,
- enum machine_mode,
+ machine_mode,
rtx operands[2])
{
/* If one of operands is memory, source and destination must match. */
void
ix86_split_convert_uns_si_sse (rtx operands[])
{
- enum machine_mode vecmode;
+ machine_mode vecmode;
rtx value, large, zero_or_two31, input, two31, x;
large = operands[1];
{
rtx tmp[8];
REAL_VALUE_TYPE TWO16r;
- enum machine_mode intmode = GET_MODE (val);
- enum machine_mode fltmode = GET_MODE (target);
+ machine_mode intmode = GET_MODE (val);
+ machine_mode fltmode = GET_MODE (target);
rtx (*cvt) (rtx, rtx);
if (intmode == V4SImode)
{
REAL_VALUE_TYPE TWO31r;
rtx two31r, tmp[4];
- enum machine_mode mode = GET_MODE (val);
- enum machine_mode scalarmode = GET_MODE_INNER (mode);
- enum machine_mode intmode = GET_MODE_SIZE (mode) == 32 ? V8SImode : V4SImode;
+ machine_mode mode = GET_MODE (val);
+ machine_mode scalarmode = GET_MODE_INNER (mode);
+ machine_mode intmode = GET_MODE_SIZE (mode) == 32 ? V8SImode : V4SImode;
rtx (*cmp) (rtx, rtx, rtx, rtx);
int i;
register. */
rtx
-ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
+ix86_build_const_vector (machine_mode mode, bool vect, rtx value)
{
int i, n_elt;
rtvec v;
- enum machine_mode scalar_mode;
+ machine_mode scalar_mode;
switch (mode)
{
a mask excluding the sign bit. */
rtx
-ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
+ix86_build_signbit_mask (machine_mode mode, bool vect, bool invert)
{
- enum machine_mode vec_mode, imode;
+ machine_mode vec_mode, imode;
HOST_WIDE_INT hi, lo;
int shift = 63;
rtx v;
/* Generate code for floating point ABS or NEG. */
void
-ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
+ix86_expand_fp_absneg_operator (enum rtx_code code, machine_mode mode,
rtx operands[])
{
rtx mask, set, dst, src;
bool use_sse = false;
bool vector_mode = VECTOR_MODE_P (mode);
- enum machine_mode vmode = mode;
+ machine_mode vmode = mode;
if (vector_mode)
use_sse = true;
void
ix86_expand_copysign (rtx operands[])
{
- enum machine_mode mode, vmode;
+ machine_mode mode, vmode;
rtx dest, op0, op1, mask, nmask;
dest = operands[0];
void
ix86_split_copysign_const (rtx operands[])
{
- enum machine_mode mode, vmode;
+ machine_mode mode, vmode;
rtx dest, op0, mask, x;
dest = operands[0];
void
ix86_split_copysign_var (rtx operands[])
{
- enum machine_mode mode, vmode;
+ machine_mode mode, vmode;
rtx dest, scratch, op0, op1, mask, nmask, x;
dest = operands[0];
CC mode is at least as constrained as REQ_MODE. */
bool
-ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
+ix86_match_ccmode (rtx insn, machine_mode req_mode)
{
rtx set;
- enum machine_mode set_mode;
+ machine_mode set_mode;
set = PATTERN (insn);
if (GET_CODE (set) == PARALLEL)
static rtx
ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
{
- enum machine_mode cmpmode;
+ machine_mode cmpmode;
rtx tmp, flags;
cmpmode = SELECT_CC_MODE (code, op0, op1);
/* Figure out whether to use ordered or unordered fp comparisons.
Return the appropriate mode to use. */
-enum machine_mode
+machine_mode
ix86_fp_compare_mode (enum rtx_code)
{
/* ??? In order to make all comparisons reversible, we do all comparisons
return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
}
-enum machine_mode
+machine_mode
ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
{
- enum machine_mode mode = GET_MODE (op0);
+ machine_mode mode = GET_MODE (op0);
if (SCALAR_FLOAT_MODE_P (mode))
{
mode which is compatible with both. Otherwise, return
VOIDmode. */
-static enum machine_mode
-ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
+static machine_mode
+ix86_cc_modes_compatible (machine_mode m1, machine_mode m2)
{
if (m1 == m2)
return m1;
static enum rtx_code
ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
{
- enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
+ machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
rtx op0 = *pop0, op1 = *pop1;
- enum machine_mode op_mode = GET_MODE (op0);
+ machine_mode op_mode = GET_MODE (op0);
int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
/* All of the unordered compare instructions only work on registers.
static rtx
ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch)
{
- enum machine_mode fpcmp_mode, intcmp_mode;
+ machine_mode fpcmp_mode, intcmp_mode;
rtx tmp, tmp2;
fpcmp_mode = ix86_fp_compare_mode (code);
void
ix86_expand_branch (enum rtx_code code, rtx op0, rtx op1, rtx label)
{
- enum machine_mode mode = GET_MODE (op0);
+ machine_mode mode = GET_MODE (op0);
rtx tmp;
switch (mode)
rtx lo[2], hi[2];
rtx_code_label *label2;
enum rtx_code code1, code2, code3;
- enum machine_mode submode;
+ machine_mode submode;
if (CONSTANT_P (op0) && !CONSTANT_P (op1))
{
static bool
ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
{
- enum machine_mode mode =
+ machine_mode mode =
GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
/* Do not handle double-mode compares that go through special path. */
enum rtx_code code = GET_CODE (operands[1]), compare_code;
rtx_insn *compare_seq;
rtx compare_op;
- enum machine_mode mode = GET_MODE (operands[0]);
+ machine_mode mode = GET_MODE (operands[0]);
bool sign_bit_compare_p = false;
rtx op0 = XEXP (operands[1], 0);
rtx op1 = XEXP (operands[1], 1);
if (diff < 0)
{
- enum machine_mode cmp_mode = GET_MODE (op0);
+ machine_mode cmp_mode = GET_MODE (op0);
HOST_WIDE_INT tmp;
tmp = ct, ct = cf, cf = tmp;
{
if (cf == 0)
{
- enum machine_mode cmp_mode = GET_MODE (op0);
+ machine_mode cmp_mode = GET_MODE (op0);
cf = ct;
ct = 0;
ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
rtx cmp_op1, rtx if_true, rtx if_false)
{
- enum machine_mode mode;
+ machine_mode mode;
bool is_min;
rtx tmp;
ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
rtx op_true, rtx op_false)
{
- enum machine_mode mode = GET_MODE (dest);
- enum machine_mode cmp_ops_mode = GET_MODE (cmp_op0);
+ machine_mode mode = GET_MODE (dest);
+ machine_mode cmp_ops_mode = GET_MODE (cmp_op0);
/* In general case result of comparison can differ from operands' type. */
- enum machine_mode cmp_mode;
+ machine_mode cmp_mode;
/* In AVX512F the result of comparison is an integer mask. */
bool maskcmp = false;
static void
ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
{
- enum machine_mode mode = GET_MODE (dest);
- enum machine_mode cmpmode = GET_MODE (cmp);
+ machine_mode mode = GET_MODE (dest);
+ machine_mode cmpmode = GET_MODE (cmp);
/* In AVX512F the result of comparison is an integer mask. */
bool maskcmp = (mode != cmpmode && TARGET_AVX512F);
bool
ix86_expand_fp_movcc (rtx operands[])
{
- enum machine_mode mode = GET_MODE (operands[0]);
+ machine_mode mode = GET_MODE (operands[0]);
enum rtx_code code = GET_CODE (operands[1]);
rtx tmp, compare_op;
rtx op0 = XEXP (operands[1], 0);
if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
{
- enum machine_mode cmode;
+ machine_mode cmode;
/* Since we've no cmove for sse registers, don't force bad register
allocation just to gain access to it. Deny movcc when the
bool
ix86_expand_int_vcond (rtx operands[])
{
- enum machine_mode data_mode = GET_MODE (operands[0]);
- enum machine_mode mode = GET_MODE (operands[4]);
+ machine_mode data_mode = GET_MODE (operands[0]);
+ machine_mode mode = GET_MODE (operands[4]);
enum rtx_code code = GET_CODE (operands[3]);
bool negate = false;
rtx x, cop0, cop1;
{
rtx target, op0, op1;
unsigned char perm[MAX_VECT_LEN];
- enum machine_mode vmode;
+ machine_mode vmode;
unsigned char nelt;
bool one_operand_p;
bool testing_p;
{
/* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
expander, so args are either in d, or in op0, op1 etc. */
- enum machine_mode mode = GET_MODE (d ? d->op0 : op0);
- enum machine_mode maskmode = mode;
+ machine_mode mode = GET_MODE (d ? d->op0 : op0);
+ machine_mode maskmode = mode;
rtx (*gen) (rtx, rtx, rtx, rtx) = NULL;
switch (mode)
rtx op1 = operands[2];
rtx mask = operands[3];
rtx t1, t2, t3, t4, t5, t6, t7, t8, vt, vt2, vec[32];
- enum machine_mode mode = GET_MODE (op0);
- enum machine_mode maskmode = GET_MODE (mask);
+ machine_mode mode = GET_MODE (op0);
+ machine_mode maskmode = GET_MODE (mask);
int w, e, i;
bool one_operand_shuffle = rtx_equal_p (op0, op1);
void
ix86_expand_sse_unpack (rtx dest, rtx src, bool unsigned_p, bool high_p)
{
- enum machine_mode imode = GET_MODE (src);
+ machine_mode imode = GET_MODE (src);
rtx tmp;
if (TARGET_SSE4_1)
{
rtx (*unpack)(rtx, rtx);
rtx (*extract)(rtx, rtx) = NULL;
- enum machine_mode halfmode = BLKmode;
+ machine_mode halfmode = BLKmode;
switch (imode)
{
rtx compare_op;
rtx val = const0_rtx;
bool fpcmp = false;
- enum machine_mode mode;
+ machine_mode mode;
rtx op0 = XEXP (operands[1], 0);
rtx op1 = XEXP (operands[1], 1);
in the right order. Maximally three parts are generated. */
static int
-ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
+ix86_split_to_parts (rtx operand, rtx *parts, machine_mode mode)
{
int size;
if (GET_CODE (operand) == CONST_VECTOR)
{
- enum machine_mode imode = int_mode_for_mode (mode);
+ machine_mode imode = int_mode_for_mode (mode);
/* Caution: if we looked through a constant pool memory above,
the operand may actually have a different mode now. That's
ok, since we want to pun this all the way back to an integer. */
split_double_mode (mode, &operand, 1, &parts[0], &parts[1]);
if (mode == XFmode || mode == TFmode)
{
- enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
+ machine_mode upper_mode = mode==XFmode ? SImode : DImode;
if (REG_P (operand))
{
gcc_assert (reload_completed);
int nparts, i, j;
int push = 0;
int collisions = 0;
- enum machine_mode mode = GET_MODE (operands[0]);
+ machine_mode mode = GET_MODE (operands[0]);
bool collisionparts[4];
/* The DFmode expanders may ask us to move double.
a sequence of add instructions. */
static void
-ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
+ix86_expand_ashl_const (rtx operand, int count, machine_mode mode)
{
rtx (*insn)(rtx, rtx, rtx);
}
void
-ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
+ix86_split_ashl (rtx *operands, rtx scratch, machine_mode mode)
{
rtx (*gen_ashl3)(rtx, rtx, rtx);
rtx (*gen_shld)(rtx, rtx, rtx);
pentium4 a bit; no one else seems to care much either way. */
else
{
- enum machine_mode half_mode;
+ machine_mode half_mode;
rtx (*gen_lshr3)(rtx, rtx, rtx);
rtx (*gen_and3)(rtx, rtx, rtx);
rtx (*gen_xor3)(rtx, rtx, rtx);
}
void
-ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
+ix86_split_ashr (rtx *operands, rtx scratch, machine_mode mode)
{
rtx (*gen_ashr3)(rtx, rtx, rtx)
= mode == DImode ? gen_ashrsi3 : gen_ashrdi3;
}
void
-ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
+ix86_split_lshr (rtx *operands, rtx scratch, machine_mode mode)
{
rtx (*gen_lshr3)(rtx, rtx, rtx)
= mode == DImode ? gen_lshrsi3 : gen_lshrdi3;
/* Return mode for the memcpy/memset loop counter. Prefer SImode over
DImode for constant loop counts. */
-static enum machine_mode
+static machine_mode
counter_mode (rtx count_exp)
{
if (GET_MODE (count_exp) != VOIDmode)
static void
expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
rtx destptr, rtx srcptr, rtx value,
- rtx count, enum machine_mode mode, int unroll,
+ rtx count, machine_mode mode, int unroll,
int expected_size, bool issetmem)
{
rtx_code_label *out_label, *top_label;
rtx iter, tmp;
- enum machine_mode iter_mode = counter_mode (count);
+ machine_mode iter_mode = counter_mode (count);
int piece_size_n = GET_MODE_SIZE (mode) * unroll;
rtx piece_size = GEN_INT (piece_size_n);
rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
expand_set_or_movmem_via_rep (rtx destmem, rtx srcmem,
rtx destptr, rtx srcptr, rtx value, rtx orig_value,
rtx count,
- enum machine_mode mode, bool issetmem)
+ machine_mode mode, bool issetmem)
{
rtx destexp;
rtx srcexp;
{
rtx dst = destmem, src = *srcmem, adjust, tempreg;
enum insn_code code;
- enum machine_mode move_mode;
+ machine_mode move_mode;
int piece_size, i;
/* Find the widest mode in which we could perform moves.
{
rtx dst = destmem, adjust;
enum insn_code code;
- enum machine_mode move_mode;
+ machine_mode move_mode;
int piece_size, i;
/* Find the widest mode in which we could perform moves.
rtx done_label, bool issetmem)
{
rtx_code_label *label = ix86_expand_aligntest (count, size, false);
- enum machine_mode mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 1);
+ machine_mode mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 1);
rtx modesize;
int n;
static void
expand_set_or_movmem_prologue_epilogue_by_misaligned_moves (rtx destmem, rtx srcmem,
rtx *destptr, rtx *srcptr,
- enum machine_mode mode,
+ machine_mode mode,
rtx value, rtx vec_value,
rtx *count,
rtx_code_label **done_label,
decide_alignment (int align,
enum stringop_alg alg,
int expected_size,
- enum machine_mode move_mode)
+ machine_mode move_mode)
{
int desired_align = 0;
synth_mult by unwinding the sequence by hand on CPUs with
slow multiply. */
static rtx
-promote_duplicated_reg (enum machine_mode mode, rtx val)
+promote_duplicated_reg (machine_mode mode, rtx val)
{
- enum machine_mode valmode = GET_MODE (val);
+ machine_mode valmode = GET_MODE (val);
rtx tmp;
int nops = mode == DImode ? 3 : 2;
int dynamic_check;
bool need_zero_guard = false;
bool noalign;
- enum machine_mode move_mode = VOIDmode;
+ machine_mode move_mode = VOIDmode;
int unroll_factor = 1;
/* TODO: Once value ranges are available, fill in proper data. */
unsigned HOST_WIDE_INT min_size = 0;
for (i = 0; i < cregs_size; i++)
{
int regno = x86_64_ms_sysv_extra_clobbered_registers[i];
- enum machine_mode mode = SSE_REGNO_P (regno) ? TImode : DImode;
+ machine_mode mode = SSE_REGNO_P (regno) ? TImode : DImode;
clobber_reg (&use, gen_rtx_REG (mode, regno));
}
which slot to use. */
rtx
-assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
+assign_386_stack_local (machine_mode mode, enum ix86_stack_slot n)
{
struct stack_local_entry *s;
object. */
unsigned int
-ix86_local_alignment (tree exp, enum machine_mode mode,
+ix86_local_alignment (tree exp, machine_mode mode,
unsigned int align)
{
tree type, decl;
alignment that the object would ordinarily have. */
unsigned int
-ix86_minimum_alignment (tree exp, enum machine_mode mode,
+ix86_minimum_alignment (tree exp, machine_mode mode,
unsigned int align)
{
tree type, decl;
gcc_assert (tcode > IX86_BT_LAST_PRIM);
if (tcode <= IX86_BT_LAST_VECT)
{
- enum machine_mode mode;
+ machine_mode mode;
index = tcode - IX86_BT_LAST_PRIM - 1;
itype = ix86_get_builtin_type (ix86_builtin_type_vect_base[index]);
where we expect a vector. To avoid crashing, use one of the vector
clear instructions. */
static rtx
-safe_vector_operand (rtx x, enum machine_mode mode)
+safe_vector_operand (rtx x, machine_mode mode)
{
if (x == const0_rtx)
x = CONST0_RTX (mode);
tree arg1 = CALL_EXPR_ARG (exp, 1);
rtx op0 = expand_normal (arg0);
rtx op1 = expand_normal (arg1);
- enum machine_mode tmode = insn_data[icode].operand[0].mode;
- enum machine_mode mode0 = insn_data[icode].operand[1].mode;
- enum machine_mode mode1 = insn_data[icode].operand[2].mode;
+ machine_mode tmode = insn_data[icode].operand[0].mode;
+ machine_mode mode0 = insn_data[icode].operand[1].mode;
+ machine_mode mode1 = insn_data[icode].operand[2].mode;
if (VECTOR_MODE_P (mode0))
op0 = safe_vector_operand (op0, mode0);
int num_memory = 0;
struct {
rtx op;
- enum machine_mode mode;
+ machine_mode mode;
} args[4];
- enum machine_mode tmode = insn_data[icode].operand[0].mode;
+ machine_mode tmode = insn_data[icode].operand[0].mode;
switch (m_type)
{
tree arg = CALL_EXPR_ARG (exp, i);
rtx op = expand_normal (arg);
int adjust = (comparison_p) ? 1 : 0;
- enum machine_mode mode = insn_data[icode].operand[i+adjust+1].mode;
+ machine_mode mode = insn_data[icode].operand[i+adjust+1].mode;
if (last_arg_constant && i == nargs - 1)
{
rtx pat;
tree arg0 = CALL_EXPR_ARG (exp, 0);
rtx op1, op0 = expand_normal (arg0);
- enum machine_mode tmode = insn_data[icode].operand[0].mode;
- enum machine_mode mode0 = insn_data[icode].operand[1].mode;
+ machine_mode tmode = insn_data[icode].operand[0].mode;
+ machine_mode mode0 = insn_data[icode].operand[1].mode;
if (optimize || !target
|| GET_MODE (target) != tmode
rtx op0 = expand_normal (arg0);
rtx op1 = expand_normal (arg1);
rtx op2;
- enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
- enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
- enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
+ machine_mode tmode = insn_data[d->icode].operand[0].mode;
+ machine_mode mode0 = insn_data[d->icode].operand[1].mode;
+ machine_mode mode1 = insn_data[d->icode].operand[2].mode;
enum rtx_code comparison = d->comparison;
if (VECTOR_MODE_P (mode0))
tree arg1 = CALL_EXPR_ARG (exp, 1);
rtx op0 = expand_normal (arg0);
rtx op1 = expand_normal (arg1);
- enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
- enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
+ machine_mode mode0 = insn_data[d->icode].operand[0].mode;
+ machine_mode mode1 = insn_data[d->icode].operand[1].mode;
enum rtx_code comparison = d->comparison;
if (VECTOR_MODE_P (mode0))
rtx pat;
tree arg0 = CALL_EXPR_ARG (exp, 0);
rtx op1, op0 = expand_normal (arg0);
- enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
- enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
+ machine_mode tmode = insn_data[d->icode].operand[0].mode;
+ machine_mode mode0 = insn_data[d->icode].operand[1].mode;
if (optimize || target == 0
|| GET_MODE (target) != tmode
rtx op0 = expand_normal (arg0);
rtx op1 = expand_normal (arg1);
rtx op2;
- enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
- enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
- enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
+ machine_mode tmode = insn_data[d->icode].operand[0].mode;
+ machine_mode mode0 = insn_data[d->icode].operand[1].mode;
+ machine_mode mode1 = insn_data[d->icode].operand[2].mode;
if (optimize || target == 0
|| GET_MODE (target) != tmode
tree arg1 = CALL_EXPR_ARG (exp, 1);
rtx op0 = expand_normal (arg0);
rtx op1 = expand_normal (arg1);
- enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
- enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
+ machine_mode mode0 = insn_data[d->icode].operand[0].mode;
+ machine_mode mode1 = insn_data[d->icode].operand[1].mode;
enum rtx_code comparison = d->comparison;
if (VECTOR_MODE_P (mode0))
rtx op2 = expand_normal (arg2);
rtx op3 = expand_normal (arg3);
rtx op4 = expand_normal (arg4);
- enum machine_mode tmode0, tmode1, modev2, modei3, modev4, modei5, modeimm;
+ machine_mode tmode0, tmode1, modev2, modei3, modev4, modei5, modeimm;
tmode0 = insn_data[d->icode].operand[0].mode;
tmode1 = insn_data[d->icode].operand[1].mode;
emit_insn
(gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
gen_rtx_fmt_ee (EQ, QImode,
- gen_rtx_REG ((enum machine_mode) d->flag,
+ gen_rtx_REG ((machine_mode) d->flag,
FLAGS_REG),
const0_rtx)));
return SUBREG_REG (target);
rtx op0 = expand_normal (arg0);
rtx op1 = expand_normal (arg1);
rtx op2 = expand_normal (arg2);
- enum machine_mode tmode0, tmode1, modev2, modev3, modeimm;
+ machine_mode tmode0, tmode1, modev2, modev3, modeimm;
tmode0 = insn_data[d->icode].operand[0].mode;
tmode1 = insn_data[d->icode].operand[1].mode;
emit_insn
(gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
gen_rtx_fmt_ee (EQ, QImode,
- gen_rtx_REG ((enum machine_mode) d->flag,
+ gen_rtx_REG ((machine_mode) d->flag,
FLAGS_REG),
const0_rtx)));
return SUBREG_REG (target);
struct
{
rtx op;
- enum machine_mode mode;
+ machine_mode mode;
} args[6];
bool last_arg_count = false;
enum insn_code icode = d->icode;
const struct insn_data_d *insn_p = &insn_data[icode];
- enum machine_mode tmode = insn_p->operand[0].mode;
- enum machine_mode rmode = VOIDmode;
+ machine_mode tmode = insn_p->operand[0].mode;
+ machine_mode rmode = VOIDmode;
bool swap = false;
enum rtx_code comparison = d->comparison;
{
tree arg = CALL_EXPR_ARG (exp, i);
rtx op = expand_normal (arg);
- enum machine_mode mode = insn_p->operand[i + 1].mode;
+ machine_mode mode = insn_p->operand[i + 1].mode;
bool match = insn_p->operand[i + 1].predicate (op, mode);
if (last_arg_count && (i + 1) == nargs)
rtx op3 = expand_normal (arg3);
enum insn_code icode = d->icode;
const struct insn_data_d *insn_p = &insn_data[icode];
- enum machine_mode mode0 = insn_p->operand[0].mode;
- enum machine_mode mode1 = insn_p->operand[1].mode;
+ machine_mode mode0 = insn_p->operand[0].mode;
+ machine_mode mode1 = insn_p->operand[1].mode;
enum rtx_code comparison = UNEQ;
bool need_ucomi = false;
struct
{
rtx op;
- enum machine_mode mode;
+ machine_mode mode;
} args[6];
enum insn_code icode = d->icode;
const struct insn_data_d *insn_p = &insn_data[icode];
- enum machine_mode tmode = insn_p->operand[0].mode;
+ machine_mode tmode = insn_p->operand[0].mode;
unsigned int nargs_constant = 0;
unsigned int redundant_embed_rnd = 0;
{
tree arg = CALL_EXPR_ARG (exp, i);
rtx op = expand_normal (arg);
- enum machine_mode mode = insn_p->operand[i + 1].mode;
+ machine_mode mode = insn_p->operand[i + 1].mode;
bool match = insn_p->operand[i + 1].predicate (op, mode);
if (i == nargs - nargs_constant)
struct
{
rtx op;
- enum machine_mode mode;
+ machine_mode mode;
} args[3];
enum insn_code icode = d->icode;
bool last_arg_constant = false;
const struct insn_data_d *insn_p = &insn_data[icode];
- enum machine_mode tmode = insn_p->operand[0].mode;
+ machine_mode tmode = insn_p->operand[0].mode;
enum { load, store } klass;
switch ((enum ix86_builtin_func_type) d->flag)
for (i = 0; i < nargs; i++)
{
- enum machine_mode mode = insn_p->operand[i + 1].mode;
+ machine_mode mode = insn_p->operand[i + 1].mode;
bool match;
arg = CALL_EXPR_ARG (exp, i + arg_adjust);
static rtx
ix86_expand_vec_init_builtin (tree type, tree exp, rtx target)
{
- enum machine_mode tmode = TYPE_MODE (type);
- enum machine_mode inner_mode = GET_MODE_INNER (tmode);
+ machine_mode tmode = TYPE_MODE (type);
+ machine_mode inner_mode = GET_MODE_INNER (tmode);
int i, n_elt = GET_MODE_NUNITS (tmode);
rtvec v = rtvec_alloc (n_elt);
static rtx
ix86_expand_vec_ext_builtin (tree exp, rtx target)
{
- enum machine_mode tmode, mode0;
+ machine_mode tmode, mode0;
tree arg0, arg1;
int elt;
rtx op0;
static rtx
ix86_expand_vec_set_builtin (tree exp)
{
- enum machine_mode tmode, mode1;
+ machine_mode tmode, mode1;
tree arg0, arg1, arg2;
int elt;
rtx op0, op1, target;
static rtx
ix86_expand_builtin (tree exp, rtx target, rtx subtarget,
- enum machine_mode mode, int ignore)
+ machine_mode mode, int ignore)
{
const struct builtin_description *d;
size_t i;
tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
tree arg0, arg1, arg2, arg3, arg4;
rtx op0, op1, op2, op3, op4, pat, insn;
- enum machine_mode mode0, mode1, mode2, mode3, mode4;
+ machine_mode mode0, mode1, mode2, mode3, mode4;
unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
/* For CPU builtins that can be folded, fold first and expand the fold. */
ix86_builtin_vectorized_function (tree fndecl, tree type_out,
tree type_in)
{
- enum machine_mode in_mode, out_mode;
+ machine_mode in_mode, out_mode;
int in_n, out_n;
enum built_in_function fn = DECL_FUNCTION_CODE (fndecl);
tree fntype, new_fndecl, args;
unsigned arity;
const char *bname;
- enum machine_mode el_mode, in_mode;
+ machine_mode el_mode, in_mode;
int n, in_n;
/* The SVML is suitable for unsafe math only. */
tree fntype, new_fndecl, args;
unsigned arity;
const char *bname;
- enum machine_mode el_mode, in_mode;
+ machine_mode el_mode, in_mode;
int n, in_n;
/* The ACML is 64bits only and suitable for unsafe math only as
The return value is 0 for no match and the imm8+1 for a match. */
int
-avx_vpermilp_parallel (rtx par, enum machine_mode mode)
+avx_vpermilp_parallel (rtx par, machine_mode mode)
{
unsigned i, nelt = GET_MODE_NUNITS (mode);
unsigned mask = 0;
The return value is 0 for no match and the imm8+1 for a match. */
int
-avx_vperm2f128_parallel (rtx par, enum machine_mode mode)
+avx_vperm2f128_parallel (rtx par, machine_mode mode)
{
unsigned i, nelt = GET_MODE_NUNITS (mode), nelt2 = nelt / 2;
unsigned mask = 0;
static reg_class_t
ix86_preferred_reload_class (rtx x, reg_class_t regclass)
{
- enum machine_mode mode = GET_MODE (x);
+ machine_mode mode = GET_MODE (x);
/* We're only allowed to return a subclass of CLASS. Many of the
following checks fail for NO_REGS, so eliminate that early. */
static reg_class_t
ix86_preferred_output_reload_class (rtx x, reg_class_t regclass)
{
- enum machine_mode mode = GET_MODE (x);
+ machine_mode mode = GET_MODE (x);
/* Restrict the output reload class to the register bank that we are doing
math on. If we would like not to return a subset of CLASS, reject this
static reg_class_t
ix86_secondary_reload (bool in_p, rtx x, reg_class_t rclass,
- enum machine_mode mode, secondary_reload_info *sri)
+ machine_mode mode, secondary_reload_info *sri)
{
/* Double-word spills from general registers to non-offsettable memory
references (zero-extended addresses) require special handling. */
static inline bool
inline_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
- enum machine_mode mode, int strict)
+ machine_mode mode, int strict)
{
if (lra_in_progress && (class1 == NO_REGS || class2 == NO_REGS))
return false;
bool
ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
- enum machine_mode mode, int strict)
+ machine_mode mode, int strict)
{
return inline_secondary_memory_needed (class1, class2, mode, strict);
}
except in the FP regs, where a single reg is always enough. */
static unsigned char
-ix86_class_max_nregs (reg_class_t rclass, enum machine_mode mode)
+ix86_class_max_nregs (reg_class_t rclass, machine_mode mode)
{
if (MAYBE_INTEGER_CLASS_P (rclass))
{
modes FROM to TO. */
bool
-ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
+ix86_cannot_change_mode_class (machine_mode from, machine_mode to,
enum reg_class regclass)
{
if (from == to)
Q_REGS classes.
*/
static inline int
-inline_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
+inline_memory_move_cost (machine_mode mode, enum reg_class regclass,
int in)
{
int cost;
}
static int
-ix86_memory_move_cost (enum machine_mode mode, reg_class_t regclass,
+ix86_memory_move_cost (machine_mode mode, reg_class_t regclass,
bool in)
{
return inline_memory_move_cost (mode, (enum reg_class) regclass, in ? 1 : 0);
general registers. */
static int
-ix86_register_move_cost (enum machine_mode mode, reg_class_t class1_i,
+ix86_register_move_cost (machine_mode mode, reg_class_t class1_i,
reg_class_t class2_i)
{
enum reg_class class1 = (enum reg_class) class1_i;
MODE. */
bool
-ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
+ix86_hard_regno_mode_ok (int regno, machine_mode mode)
{
/* Flags and only flags can only hold CCmode values. */
if (CC_REGNO_P (regno))
tieable integer mode. */
static bool
-ix86_tieable_integer_mode_p (enum machine_mode mode)
+ix86_tieable_integer_mode_p (machine_mode mode)
{
switch (mode)
{
can also hold MODE1. */
bool
-ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
+ix86_modes_tieable_p (machine_mode mode1, machine_mode mode2)
{
if (mode1 == mode2)
return true;
/* Return the cost of moving between two registers of mode MODE. */
static int
-ix86_set_reg_reg_cost (enum machine_mode mode)
+ix86_set_reg_reg_cost (machine_mode mode)
{
unsigned int units = UNITS_PER_WORD;
rtx mask;
enum rtx_code code = (enum rtx_code) code_i;
enum rtx_code outer_code = (enum rtx_code) outer_code_i;
- enum machine_mode mode = GET_MODE (x);
+ machine_mode mode = GET_MODE (x);
const struct processor_costs *cost = speed ? ix86_cost : &ix86_size_cost;
switch (code)
== GET_MODE_SIZE (mode))
{
int is_mulwiden = 0;
- enum machine_mode inner_mode = GET_MODE (op0);
+ machine_mode inner_mode = GET_MODE (op0);
if (GET_CODE (op0) == GET_CODE (op1))
is_mulwiden = 1, op1 = XEXP (op1, 0);
int
x86_field_alignment (tree field, int computed)
{
- enum machine_mode mode;
+ machine_mode mode;
tree type = TREE_TYPE (field);
if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
/* If profitable, negate (without causing overflow) integer constant
of mode MODE at location LOC. Return true in this case. */
bool
-x86_maybe_negate_const_int (rtx *loc, enum machine_mode mode)
+x86_maybe_negate_const_int (rtx *loc, machine_mode mode)
{
HOST_WIDE_INT val;
{
rtx_code_label *neglab, *donelab;
rtx i0, i1, f0, in, out;
- enum machine_mode mode, inmode;
+ machine_mode mode, inmode;
inmode = GET_MODE (operands[1]);
gcc_assert (inmode == SImode || inmode == DImode);
/* Get a vector mode of the same size as the original but with elements
twice as wide. This is only guaranteed to apply to integral vectors. */
-static inline enum machine_mode
-get_mode_wider_vector (enum machine_mode o)
+static inline machine_mode
+get_mode_wider_vector (machine_mode o)
{
/* ??? Rely on the ordering that genmodes.c gives to vectors. */
- enum machine_mode n = GET_MODE_WIDER_MODE (o);
+ machine_mode n = GET_MODE_WIDER_MODE (o);
gcc_assert (GET_MODE_NUNITS (o) == GET_MODE_NUNITS (n) * 2);
gcc_assert (GET_MODE_SIZE (o) == GET_MODE_SIZE (n));
return n;
fill target with val via vec_duplicate. */
static bool
-ix86_vector_duplicate_value (enum machine_mode mode, rtx target, rtx val)
+ix86_vector_duplicate_value (machine_mode mode, rtx target, rtx val)
{
bool ok;
rtx_insn *insn;
with all elements equal to VAR. Return true if successful. */
static bool
-ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
+ix86_expand_vector_init_duplicate (bool mmx_ok, machine_mode mode,
rtx target, rtx val)
{
bool ok;
widen:
/* Replicate the value once into the next wider mode and recurse. */
{
- enum machine_mode smode, wsmode, wvmode;
+ machine_mode smode, wsmode, wvmode;
rtx x;
smode = GET_MODE_INNER (mode);
return ix86_vector_duplicate_value (mode, target, val);
else
{
- enum machine_mode hvmode = (mode == V16HImode ? V8HImode : V16QImode);
+ machine_mode hvmode = (mode == V16HImode ? V8HImode : V16QImode);
rtx x = gen_reg_rtx (hvmode);
ok = ix86_expand_vector_init_duplicate (false, hvmode, x, val);
return ix86_vector_duplicate_value (mode, target, val);
else
{
- enum machine_mode hvmode = (mode == V32HImode ? V16HImode : V32QImode);
+ machine_mode hvmode = (mode == V32HImode ? V16HImode : V32QImode);
rtx x = gen_reg_rtx (hvmode);
ok = ix86_expand_vector_init_duplicate (false, hvmode, x, val);
if successful. */
static bool
-ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
+ix86_expand_vector_init_one_nonzero (bool mmx_ok, machine_mode mode,
rtx target, rtx var, int one_var)
{
- enum machine_mode vsimode;
+ machine_mode vsimode;
rtx new_target;
rtx x, tmp;
bool use_vector_set = false;
except ONE_VAR are constants. Return true if successful. */
static bool
-ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
+ix86_expand_vector_init_one_var (bool mmx_ok, machine_mode mode,
rtx target, rtx vals, int one_var)
{
rtx var = XVECEXP (vals, 0, one_var);
- enum machine_mode wmode;
+ machine_mode wmode;
rtx const_vec, x;
const_vec = copy_rtx (vals);
and none identical. */
static void
-ix86_expand_vector_init_concat (enum machine_mode mode,
+ix86_expand_vector_init_concat (machine_mode mode,
rtx target, rtx *ops, int n)
{
- enum machine_mode cmode, hmode = VOIDmode, gmode = VOIDmode;
+ machine_mode cmode, hmode = VOIDmode, gmode = VOIDmode;
rtx first[16], second[8], third[4];
rtvec v;
int i, j;
and none identical. */
static void
-ix86_expand_vector_init_interleave (enum machine_mode mode,
+ix86_expand_vector_init_interleave (machine_mode mode,
rtx target, rtx *ops, int n)
{
- enum machine_mode first_imode, second_imode, third_imode, inner_mode;
+ machine_mode first_imode, second_imode, third_imode, inner_mode;
int i, j;
rtx op0, op1;
rtx (*gen_load_even) (rtx, rtx, rtx);
all values variable, and none identical. */
static void
-ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
+ix86_expand_vector_init_general (bool mmx_ok, machine_mode mode,
rtx target, rtx vals)
{
rtx ops[64], op0, op1, op2, op3, op4, op5;
- enum machine_mode half_mode = VOIDmode;
- enum machine_mode quarter_mode = VOIDmode;
+ machine_mode half_mode = VOIDmode;
+ machine_mode quarter_mode = VOIDmode;
int n, i;
switch (mode)
{
int i, j, n_elts, n_words, n_elt_per_word;
- enum machine_mode inner_mode;
+ machine_mode inner_mode;
rtx words[4], shift;
inner_mode = GET_MODE_INNER (mode);
void
ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
{
- enum machine_mode mode = GET_MODE (target);
- enum machine_mode inner_mode = GET_MODE_INNER (mode);
+ machine_mode mode = GET_MODE (target);
+ machine_mode inner_mode = GET_MODE_INNER (mode);
int n_elts = GET_MODE_NUNITS (mode);
int n_var = 0, one_var = -1;
bool all_same = true, all_const_zero = true;
void
ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
{
- enum machine_mode mode = GET_MODE (target);
- enum machine_mode inner_mode = GET_MODE_INNER (mode);
- enum machine_mode half_mode;
+ machine_mode mode = GET_MODE (target);
+ machine_mode inner_mode = GET_MODE_INNER (mode);
+ machine_mode half_mode;
bool use_vec_merge = false;
rtx tmp;
static rtx (*gen_extract[6][2]) (rtx, rtx)
void
ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
{
- enum machine_mode mode = GET_MODE (vec);
- enum machine_mode inner_mode = GET_MODE_INNER (mode);
+ machine_mode mode = GET_MODE (vec);
+ machine_mode inner_mode = GET_MODE_INNER (mode);
bool use_vec_extr = false;
rtx tmp;
ix86_expand_reduc (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
{
rtx half, dst, vec = in;
- enum machine_mode mode = GET_MODE (in);
+ machine_mode mode = GET_MODE (in);
int i;
/* SSE4 has a special instruction for V8HImode UMIN reduction. */
\f
/* Target hook for scalar_mode_supported_p. */
static bool
-ix86_scalar_mode_supported_p (enum machine_mode mode)
+ix86_scalar_mode_supported_p (machine_mode mode)
{
if (DECIMAL_FLOAT_MODE_P (mode))
return default_decimal_float_supported_p ();
/* Implements target hook vector_mode_supported_p. */
static bool
-ix86_vector_mode_supported_p (enum machine_mode mode)
+ix86_vector_mode_supported_p (machine_mode mode)
{
if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
return true;
/* Implement target hook libgcc_floating_mode_supported_p. */
static bool
-ix86_libgcc_floating_mode_supported_p (enum machine_mode mode)
+ix86_libgcc_floating_mode_supported_p (machine_mode mode)
{
switch (mode)
{
}
/* Target hook for c_mode_for_suffix. */
-static enum machine_mode
+static machine_mode
ix86_c_mode_for_suffix (char suffix)
{
if (suffix == 'q')
/* Worker function for REVERSE_CONDITION. */
enum rtx_code
-ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
+ix86_reverse_condition (enum rtx_code code, machine_mode mode)
{
return (mode != CCFPmode && mode != CCFPUmode
? reverse_condition (code)
/* Emit code for round calculation. */
void ix86_emit_i387_round (rtx op0, rtx op1)
{
- enum machine_mode inmode = GET_MODE (op1);
- enum machine_mode outmode = GET_MODE (op0);
+ machine_mode inmode = GET_MODE (op1);
+ machine_mode outmode = GET_MODE (op0);
rtx e1, e2, res, tmp, tmp1, half;
rtx scratch = gen_reg_rtx (HImode);
rtx flags = gen_rtx_REG (CCNOmode, FLAGS_REG);
/* Output code to perform a Newton-Rhapson approximation of a single precision
floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
-void ix86_emit_swdivsf (rtx res, rtx a, rtx b, enum machine_mode mode)
+void ix86_emit_swdivsf (rtx res, rtx a, rtx b, machine_mode mode)
{
rtx x0, x1, e0, e1;
/* Output code to perform a Newton-Rhapson approximation of a
single precision floating point [reciprocal] square root. */
-void ix86_emit_swsqrtsf (rtx res, rtx a, enum machine_mode mode,
+void ix86_emit_swsqrtsf (rtx res, rtx a, machine_mode mode,
bool recip)
{
rtx x0, e0, e1, e2, e3, mthree, mhalf;
static void
ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
{
- enum machine_mode mode = GET_MODE (sign);
+ machine_mode mode = GET_MODE (sign);
rtx sgn = gen_reg_rtx (mode);
if (mask == NULL_RTX)
{
- enum machine_mode vmode;
+ machine_mode vmode;
if (mode == SFmode)
vmode = V4SFmode;
static rtx
ix86_expand_sse_fabs (rtx op0, rtx *smask)
{
- enum machine_mode vmode, mode = GET_MODE (op0);
+ machine_mode vmode, mode = GET_MODE (op0);
rtx xa, mask;
xa = gen_reg_rtx (mode);
ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
bool swap_operands)
{
- enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
+ machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
rtx_code_label *label;
rtx tmp;
bool swap_operands)
{
rtx (*insn)(rtx, rtx, rtx, rtx);
- enum machine_mode mode = GET_MODE (op0);
+ machine_mode mode = GET_MODE (op0);
rtx mask = gen_reg_rtx (mode);
if (swap_operands)
/* Generate and return a rtx of mode MODE for 2**n where n is the number
of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
static rtx
-ix86_gen_TWO52 (enum machine_mode mode)
+ix86_gen_TWO52 (machine_mode mode)
{
REAL_VALUE_TYPE TWO52r;
rtx TWO52;
tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
return (long)tmp;
*/
- enum machine_mode mode = GET_MODE (op1);
+ machine_mode mode = GET_MODE (op1);
const struct real_format *fmt;
REAL_VALUE_TYPE pred_half, half_minus_pred_half;
rtx adj;
xi -= (double)xi > op1 ? 1 : 0;
return xi;
*/
- enum machine_mode fmode = GET_MODE (op1);
- enum machine_mode imode = GET_MODE (op0);
+ machine_mode fmode = GET_MODE (op1);
+ machine_mode imode = GET_MODE (op0);
rtx ireg, freg, tmp;
rtx_code_label *label;
xa = xa + 2**52 - 2**52;
return copysign (xa, operand1);
*/
- enum machine_mode mode = GET_MODE (operand0);
+ machine_mode mode = GET_MODE (operand0);
rtx res, xa, TWO52, mask;
rtx_code_label *label;
x2 -= -1;
return x2;
*/
- enum machine_mode mode = GET_MODE (operand0);
+ machine_mode mode = GET_MODE (operand0);
rtx xa, TWO52, tmp, one, res, mask;
rtx_code_label *label;
return copysign (x2, x);
return x2;
*/
- enum machine_mode mode = GET_MODE (operand0);
+ machine_mode mode = GET_MODE (operand0);
rtx xa, xi, TWO52, tmp, one, res, mask;
rtx_code_label *label;
x2 = copysign (xa2, x);
return x2;
*/
- enum machine_mode mode = GET_MODE (operand0);
+ machine_mode mode = GET_MODE (operand0);
rtx xa, xa2, dxa, TWO52, tmp, half, mhalf, one, res, mask;
rtx_code_label *label;
return copysign (x2, x);
return x2;
*/
- enum machine_mode mode = GET_MODE (operand0);
+ machine_mode mode = GET_MODE (operand0);
rtx xa, xi, TWO52, res, mask;
rtx_code_label *label;
void
ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
{
- enum machine_mode mode = GET_MODE (operand0);
+ machine_mode mode = GET_MODE (operand0);
rtx xa, mask, TWO52, one, res, smask, tmp;
rtx_code_label *label;
xa = (double)(long)(xa + nextafter (0.5, 0.0));
return copysign (xa, x);
*/
- enum machine_mode mode = GET_MODE (operand0);
+ machine_mode mode = GET_MODE (operand0);
rtx res, TWO52, xa, xi, half, mask;
rtx_code_label *label;
const struct real_format *fmt;
void
ix86_expand_round_sse4 (rtx op0, rtx op1)
{
- enum machine_mode mode = GET_MODE (op0);
+ machine_mode mode = GET_MODE (op0);
rtx e1, e2, res, half;
const struct real_format *fmt;
REAL_VALUE_TYPE pred_half, half_minus_pred_half;
const unsigned char *perm, unsigned nelt,
bool testing_p)
{
- enum machine_mode v2mode;
+ machine_mode v2mode;
rtx x;
bool ok;
static bool
expand_vec_perm_blend (struct expand_vec_perm_d *d)
{
- enum machine_mode vmode = d->vmode;
+ machine_mode vmode = d->vmode;
unsigned i, mask, nelt = d->nelt;
rtx target, op0, op1, x;
rtx rperm[32], vperm;
instead. */
static bool
-valid_perm_using_mode_p (enum machine_mode vmode, struct expand_vec_perm_d *d)
+valid_perm_using_mode_p (machine_mode vmode, struct expand_vec_perm_d *d)
{
unsigned int i, j, chunk;
{
unsigned i, nelt, eltsz, mask;
unsigned char perm[64];
- enum machine_mode vmode = V16QImode;
+ machine_mode vmode = V16QImode;
rtx rperm[64], vperm, target, op0, op1;
nelt = d->nelt;
{
unsigned i, which, nelt = d->nelt;
struct expand_vec_perm_d dcopy, dcopy1;
- enum machine_mode vmode = d->vmode;
+ machine_mode vmode = d->vmode;
bool ok;
/* Use the same checks as in expand_vec_perm_blend. */
expand_vec_perm_broadcast_1 (struct expand_vec_perm_d *d)
{
unsigned elt = d->perm[0], nelt2 = d->nelt / 2;
- enum machine_mode vmode = d->vmode;
+ machine_mode vmode = d->vmode;
unsigned char perm2[4];
rtx op0 = d->op0, dest;
bool ok;
/* Implement targetm.vectorize.vec_perm_const_ok. */
static bool
-ix86_vectorize_vec_perm_const_ok (enum machine_mode vmode,
+ix86_vectorize_vec_perm_const_ok (machine_mode vmode,
const unsigned char *sel)
{
struct expand_vec_perm_d d;
void
ix86_expand_vecop_qihi (enum rtx_code code, rtx dest, rtx op1, rtx op2)
{
- enum machine_mode qimode = GET_MODE (dest);
- enum machine_mode himode;
+ machine_mode qimode = GET_MODE (dest);
+ machine_mode himode;
rtx (*gen_il) (rtx, rtx, rtx);
rtx (*gen_ih) (rtx, rtx, rtx);
rtx op1_l, op1_h, op2_l, op2_h, res_l, res_h;
static bool
const_vector_equal_evenodd_p (rtx op)
{
- enum machine_mode mode = GET_MODE (op);
+ machine_mode mode = GET_MODE (op);
int i, nunits = GET_MODE_NUNITS (mode);
if (GET_CODE (op) != CONST_VECTOR
|| nunits != CONST_VECTOR_NUNITS (op))
ix86_expand_mul_widen_evenodd (rtx dest, rtx op1, rtx op2,
bool uns_p, bool odd_p)
{
- enum machine_mode mode = GET_MODE (op1);
- enum machine_mode wmode = GET_MODE (dest);
+ machine_mode mode = GET_MODE (op1);
+ machine_mode wmode = GET_MODE (dest);
rtx x;
rtx orig_op1 = op1, orig_op2 = op2;
ix86_expand_mul_widen_hilo (rtx dest, rtx op1, rtx op2,
bool uns_p, bool high_p)
{
- enum machine_mode wmode = GET_MODE (dest);
- enum machine_mode mode = GET_MODE (op1);
+ machine_mode wmode = GET_MODE (dest);
+ machine_mode mode = GET_MODE (op1);
rtx t1, t2, t3, t4, mask;
switch (mode)
void
ix86_expand_sse2_mulvxdi3 (rtx op0, rtx op1, rtx op2)
{
- enum machine_mode mode = GET_MODE (op0);
+ machine_mode mode = GET_MODE (op0);
rtx t1, t2, t3, t4, t5, t6;
if (TARGET_AVX512DQ && mode == V8DImode)
}
else
{
- enum machine_mode nmode;
+ machine_mode nmode;
rtx (*umul) (rtx, rtx, rtx);
if (mode == V2DImode)
void
ix86_expand_sse2_abs (rtx target, rtx input)
{
- enum machine_mode mode = GET_MODE (target);
+ machine_mode mode = GET_MODE (target);
rtx tmp0, tmp1, x;
switch (mode)
case V4SImode:
case V2DImode:
{
- enum machine_mode srcmode, dstmode;
+ machine_mode srcmode, dstmode;
rtx (*pinsr)(rtx, rtx, rtx, rtx);
srcmode = mode_for_size (size, MODE_INT, 0);
enabled for other processors. */
static int
-ix86_reassociation_width (unsigned int, enum machine_mode mode)
+ix86_reassociation_width (unsigned int, machine_mode mode)
{
int res = 1;
/* ??? No autovectorization into MMX or 3DNOW until we can reliably
place emms and femms instructions. */
-static enum machine_mode
-ix86_preferred_simd_mode (enum machine_mode mode)
+static machine_mode
+ix86_preferred_simd_mode (machine_mode mode)
{
if (!TARGET_SSE)
return word_mode;
and of class RCLASS for spilling instead of memory. Return NO_REGS
if it is not possible or non-profitable. */
static reg_class_t
-ix86_spill_class (reg_class_t rclass, enum machine_mode mode)
+ix86_spill_class (reg_class_t rclass, machine_mode mode)
{
if (TARGET_SSE && TARGET_GENERAL_REGS_SSE_SPILL && ! TARGET_MMX
&& (mode == SImode || (TARGET_64BIT && mode == DImode))
if (const_rtx x = *iter)
if (MEM_P (x))
{
- enum machine_mode mode = GET_MODE (x);
+ machine_mode mode = GET_MODE (x);
unsigned int n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
if (n_words > 4)
mem_count += 2;
projects / gcc.git / blobdiff