const int lea; /* cost of a lea instruction */
const int shift_var; /* variable shift costs */
const int shift_const; /* constant shift costs */
- const int mult_init[5]; /* cost of starting a multiply
+ const int mult_init[5]; /* cost of starting a multiply
in QImode, HImode, SImode, DImode, TImode*/
const int mult_bit; /* cost of multiply per each bit set */
- const int divide[5]; /* cost of a divide/mod
+ const int divide[5]; /* cost of a divide/mod
in QImode, HImode, SImode, DImode, TImode*/
int movsx; /* The cost of movsx operation. */
int movzx; /* The cost of movzx operation. */
#define MASK_MMX 0x00002000 /* Support MMX regs/builtins */
#define MASK_SSE 0x00004000 /* Support SSE regs/builtins */
#define MASK_SSE2 0x00008000 /* Support SSE2 regs/builtins */
-#define MASK_PNI 0x00010000 /* Support PNI regs/builtins */
+#define MASK_SSE3 0x00010000 /* Support SSE3 regs/builtins */
#define MASK_3DNOW 0x00020000 /* Support 3Dnow builtins */
#define MASK_3DNOW_A 0x00040000 /* Support Athlon 3Dnow builtins */
#define MASK_128BIT_LONG_DOUBLE 0x00080000 /* long double size is 128bit */
This is because FreeBSD lacks these in the math-emulator-code */
#define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387)
+/* Generate 387 floating point intrinsics for the current target. */
+#define TARGET_USE_FANCY_MATH_387 (! TARGET_NO_FANCY_MATH_387)
+
/* Don't create frame pointers for leaf functions */
#define TARGET_OMIT_LEAF_FRAME_POINTER \
(target_flags & MASK_OMIT_LEAF_FRAME_POINTER)
#endif
#endif
+#define HAS_LONG_COND_BRANCH 1
+#define HAS_LONG_UNCOND_BRANCH 1
+
/* Avoid adding %gs:0 in TLS references; use %gs:address directly. */
#define TARGET_TLS_DIRECT_SEG_REFS (target_flags & MASK_TLS_DIRECT_SEG_REFS)
#define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)
#define TARGET_K8 (ix86_tune == PROCESSOR_K8)
#define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)
+#define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)
#define TUNEMASK (1 << ix86_tune)
extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
extern const int x86_sse_partial_reg_dependency, x86_sse_partial_regs;
extern const int x86_sse_typeless_stores, x86_sse_load0_by_pxor;
extern const int x86_use_ffreep, x86_sse_partial_regs_for_cvtsd2ss;
-extern const int x86_inter_unit_moves;
+extern const int x86_inter_unit_moves, x86_schedule;
extern int x86_prefetch_sse;
#define TARGET_USE_LEAVE (x86_use_leave & TUNEMASK)
#define TARGET_USE_FFREEP (x86_use_ffreep & TUNEMASK)
#define TARGET_REP_MOVL_OPTIMAL (x86_rep_movl_optimal & TUNEMASK)
#define TARGET_INTER_UNIT_MOVES (x86_inter_unit_moves & TUNEMASK)
+#define TARGET_FOUR_JUMP_LIMIT (x86_four_jump_limit & TUNEMASK)
+#define TARGET_SCHEDULE (x86_schedule & TUNEMASK)
#define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE)
#define TARGET_SSE ((target_flags & MASK_SSE) != 0)
#define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
-#define TARGET_PNI ((target_flags & MASK_PNI) != 0)
+#define TARGET_SSE3 ((target_flags & MASK_SSE3) != 0)
#define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
#define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
&& (ix86_fpmath & FPMATH_387))
N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \
{ "no-sse2", -MASK_SSE2, \
N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \
- { "pni", MASK_PNI, \
- N_("Support MMX, SSE, SSE2 and PNI built-in functions and code generation") },\
- { "no-pni", -MASK_PNI, \
- N_("Do not support MMX, SSE, SSE2 and PNI built-in functions and code generation") },\
+ { "sse3", MASK_SSE3, \
+ N_("Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation") },\
+ { "no-sse3", -MASK_SSE3, \
+ N_("Do not support MMX, SSE, SSE2 and SSE3 built-in functions and code generation") },\
{ "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \
N_("sizeof(long double) is 16") }, \
{ "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \
redefines this to 1. */
#define TARGET_MACHO 0
+/* Subtargets may reset this to 1 in order to enable 96-bit long double
+ with the rounding mode forced to 53 bits. */
+#define TARGET_96_ROUND_53_LONG_DOUBLE 0
+
/* This macro is similar to `TARGET_SWITCHES' but defines names of
command options that have values. Its definition is an
initializer with a subgrouping for each command option.
{ \
case '3': \
builtin_define ("__tune_pentium3__"); \
- /* Fall through. */ \
+ /* FALLTHRU */ \
case '2': \
builtin_define ("__tune_pentium2__"); \
break; \
builtin_define ("__tune_k8__"); \
else if (TARGET_PENTIUM4) \
builtin_define ("__tune_pentium4__"); \
+ else if (TARGET_NOCONA) \
+ builtin_define ("__tune_nocona__"); \
\
if (TARGET_MMX) \
builtin_define ("__MMX__"); \
builtin_define ("__SSE__"); \
if (TARGET_SSE2) \
builtin_define ("__SSE2__"); \
- if (TARGET_PNI) \
- builtin_define ("__PNI__"); \
+ if (TARGET_SSE3) \
+ builtin_define ("__SSE3__"); \
if (TARGET_SSE_MATH && TARGET_SSE) \
builtin_define ("__SSE_MATH__"); \
if (TARGET_SSE_MATH && TARGET_SSE2) \
builtin_define ("__pentium4"); \
builtin_define ("__pentium4__"); \
} \
+ else if (ix86_arch == PROCESSOR_NOCONA) \
+ { \
+ builtin_define ("__nocona"); \
+ builtin_define ("__nocona__"); \
+ } \
} \
while (0)
#define TARGET_CPU_DEFAULT_athlon 11
#define TARGET_CPU_DEFAULT_athlon_sse 12
#define TARGET_CPU_DEFAULT_k8 13
+#define TARGET_CPU_DEFAULT_pentium_m 14
+#define TARGET_CPU_DEFAULT_prescott 15
+#define TARGET_CPU_DEFAULT_nocona 16
#define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
"pentiumpro", "pentium2", "pentium3", \
"pentium4", "k6", "k6-2", "k6-3",\
- "athlon", "athlon-4", "k8"}
+ "athlon", "athlon-4", "k8", \
+ "pentium-m", "prescott", "nocona"}
#ifndef CC1_SPEC
#define CC1_SPEC "%(cc1_cpu) "
\f
/* target machine storage layout */
-#define LONG_DOUBLE_TYPE_SIZE 96
+#define LONG_DOUBLE_TYPE_SIZE 80
/* Set the value of FLT_EVAL_METHOD in float.h. When using only the
FPU, assume that the fpcw is set to extended precision; when using
#define INT_TYPE_SIZE 32
#define FLOAT_TYPE_SIZE 32
#define LONG_TYPE_SIZE BITS_PER_WORD
-#define MAX_WCHAR_TYPE_SIZE 32
#define DOUBLE_TYPE_SIZE 64
#define LONG_LONG_TYPE_SIZE 64
#if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT
#define MAX_BITS_PER_WORD 64
-#define MAX_LONG_TYPE_SIZE 64
#else
#define MAX_BITS_PER_WORD 32
-#define MAX_LONG_TYPE_SIZE 32
#endif
/* Define this if most significant byte of a word is the lowest numbered. */
and are not available for the register allocator.
On the 80386, the stack pointer is such, as is the arg pointer.
- The value is a mask - bit 1 is set for fixed registers
- for 32bit target, while 2 is set for fixed registers for 64bit.
- Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
+ The value is zero if the register is not fixed on either 32 or
+ 64 bit targets, one if the register if fixed on both 32 and 64
+ bit targets, two if it is only fixed on 32bit targets and three
+ if its only fixed on 64bit targets.
+ Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
*/
#define FIXED_REGISTERS \
/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
-{ 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \
+{ 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
/*arg,flags,fpsr,dir,frame*/ \
- 3, 3, 3, 3, 3, \
+ 1, 1, 1, 1, 1, \
/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
0, 0, 0, 0, 0, 0, 0, 0, \
/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
0, 0, 0, 0, 0, 0, 0, 0, \
/* r8, r9, r10, r11, r12, r13, r14, r15*/ \
- 1, 1, 1, 1, 1, 1, 1, 1, \
+ 2, 2, 2, 2, 2, 2, 2, 2, \
/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
- 1, 1, 1, 1, 1, 1, 1, 1}
+ 2, 2, 2, 2, 2, 2, 2, 2}
/* 1 for registers not available across function calls.
and the register where structure-value addresses are passed.
Aside from that, you can include as many other registers as you like.
- The value is a mask - bit 1 is set for call used
- for 32bit target, while 2 is set for call used for 64bit.
- Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
+ The value is zero if the register is not fixed on either 32 or
+ 64 bit targets, one if the register if fixed on both 32 and 64
+ bit targets, two if it is only fixed on 32bit targets and three
+ if its only fixed on 64bit targets.
+ Proper values are computed in the CONDITIONAL_REGISTER_USAGE.
*/
#define CALL_USED_REGISTERS \
/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
-{ 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \
+{ 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
/*arg,flags,fpsr,dir,frame*/ \
- 3, 3, 3, 3, 3, \
+ 1, 1, 1, 1, 1, \
/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
- 3, 3, 3, 3, 3, 3, 3, 3, \
+ 1, 1, 1, 1, 1, 1, 1, 1, \
/*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
- 3, 3, 3, 3, 3, 3, 3, 3, \
+ 1, 1, 1, 1, 1, 1, 1, 1, \
/* r8, r9, r10, r11, r12, r13, r14, r15*/ \
- 3, 3, 3, 3, 1, 1, 1, 1, \
+ 1, 1, 1, 1, 2, 2, 2, 2, \
/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
- 3, 3, 3, 3, 3, 3, 3, 3} \
+ 1, 1, 1, 1, 1, 1, 1, 1} \
/* Order in which to allocate registers. Each register must be
listed once, even those in FIXED_REGISTERS. List frame pointer
int i; \
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
{ \
- fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \
- call_used_regs[i] = (call_used_regs[i] \
- & (TARGET_64BIT ? 2 : 1)) != 0; \
+ if (fixed_regs[i] > 1) \
+ fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2)); \
+ if (call_used_regs[i] > 1) \
+ call_used_regs[i] = (call_used_regs[i] \
+ == (TARGET_64BIT ? 3 : 2)); \
} \
if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
{ \
((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
|| (MODE) == V2SImode || (MODE) == SImode)
-#define VECTOR_MODE_SUPPORTED_P(MODE) \
- (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \
- : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 \
- : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0)
+#define UNITS_PER_SIMD_WORD \
+ (TARGET_SSE ? 16 : TARGET_MMX || TARGET_3DNOW ? 8 : 0)
#define VALID_FP_MODE_P(MODE) \
((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \
#define FIRST_STACK_REG FIRST_FLOAT_REG
#define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
-#define FLAGS_REG 17
-#define FPSR_REG 18
-#define DIRFLAG_REG 19
-
#define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
#define LAST_SSE_REG (FIRST_SSE_REG + 7)
/* This is overridden by <cygwin.h>. */
#define MS_AGGREGATE_RETURN 0
+/* This is overridden by <netware.h>. */
+#define KEEP_AGGREGATE_RETURN_POINTER 0
\f
/* Define the classes of registers for register constraints in the
machine description. Also define ranges of constants.
the constraint letter C. If C is not defined as an extra
constraint, the value returned should be 0 regardless of VALUE. */
-#define EXTRA_CONSTRAINT(VALUE, D) \
- ((D) == 'e' ? x86_64_sign_extended_value (VALUE) \
- : (D) == 'Z' ? x86_64_zero_extended_value (VALUE) \
- : (D) == 'C' ? standard_sse_constant_p (VALUE) \
+#define EXTRA_CONSTRAINT(VALUE, D) \
+ ((D) == 'e' ? x86_64_immediate_operand (VALUE, VOIDmode) \
+ : (D) == 'Z' ? x86_64_zext_immediate_operand (VALUE, VOIDmode) \
+ : (D) == 'C' ? standard_sse_constant_p (VALUE) \
: 0)
/* Place additional restrictions on the register class to use when it
|| ((CLASS) == FP_SECOND_REG))
/* Return a class of registers that cannot change FROM mode to TO mode.
-
+
x87 registers can't do subreg as all values are reformated to extended
precision. XMM registers does not support with nonzero offsets equal
to 4, 8 and 12 otherwise valid for integer registers. Since we can't
|| MAYBE_MMX_CLASS_P (CLASS) \
: GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
? reg_classes_intersect_p (FLOAT_REGS, (CLASS)) : 0)
-
-/* A C statement that adds to CLOBBERS any hard regs the port wishes
- to automatically clobber for all asms.
-
- We do this in the new i386 backend to maintain source compatibility
- with the old cc0-based compiler. */
-
-#define MD_ASM_CLOBBERS(CLOBBERS) \
- do { \
- (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), \
- (CLOBBERS)); \
- (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), \
- (CLOBBERS)); \
- (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), \
- (CLOBBERS)); \
- } while (0)
\f
/* Stack layout; function entry, exit and calling. */
which. */
#define REG_PARM_STACK_SPACE(FNDECL) 0
-/* Define as a C expression that evaluates to nonzero if we do not know how
- to pass TYPE solely in registers. The file expr.h defines a
- definition that is usually appropriate, refer to expr.h for additional
- documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be
- computed in the stack and then loaded into a register. */
-#define MUST_PASS_IN_STACK(MODE, TYPE) ix86_must_pass_in_stack ((MODE), (TYPE))
-
/* Value is the number of bytes of arguments automatically
popped when returning from a subroutine call.
FUNDECL is the declaration node of the function (as a tree),
for a call to a function whose data type is FNTYPE.
For a library call, FNTYPE is 0. */
-#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL) \
+#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL))
/* Update the data in CUM to advance over an argument
#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
-/* A C expression that indicates when an argument must be passed by
- reference. If nonzero for an argument, a copy of that argument is
- made in memory and a pointer to the argument is passed instead of
- the argument itself. The pointer is passed in whatever way is
- appropriate for passing a pointer to that type. */
-
-#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
- function_arg_pass_by_reference(&CUM, MODE, TYPE, NAMED)
-
/* Implement `va_start' for varargs and stdarg. */
#define EXPAND_BUILTIN_VA_START(VALIST, NEXTARG) \
ix86_va_start (VALIST, NEXTARG)
-/* Implement `va_arg'. */
-#define EXPAND_BUILTIN_VA_ARG(VALIST, TYPE) \
- ix86_va_arg ((VALIST), (TYPE))
-
#define TARGET_ASM_FILE_END ix86_file_end
#define NEED_INDICATE_EXEC_STACK 0
been eliminated by then. */
-/* Non strict versions, pseudos are ok */
+/* Non strict versions, pseudos are ok. */
#define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
(REGNO (X) < STACK_POINTER_REGNUM \
|| (REGNO (X) >= FIRST_REX_INT_REG \
for the index in the tablejump instruction. */
#define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode)
-/* Define as C expression which evaluates to nonzero if the tablejump
- instruction expects the table to contain offsets from the address of the
- table.
- Do not define this if the table should contain absolute addresses. */
-/* #define CASE_VECTOR_PC_RELATIVE 1 */
-
/* Define this as 1 if `char' should by default be signed; else as 0. */
#define DEFAULT_SIGNED_CHAR 1
#define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
/* If a memory-to-memory move would take MOVE_RATIO or more simple
- move-instruction pairs, we will do a movstr or libcall instead.
+ move-instruction pairs, we will do a movmem or libcall instead.
Increasing the value will always make code faster, but eventually
incurs high cost in increased code size.
#define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
+/* If a clear memory operation would take CLEAR_RATIO or more simple
+ move-instruction sequences, we will do a clrmem or libcall instead. */
+
+#define CLEAR_RATIO (optimize_size ? 2 \
+ : ix86_cost->move_ratio > 6 ? 6 : ix86_cost->move_ratio)
+
/* Define if shifts truncate the shift count
which implies one can omit a sign-extension or zero-extension
of a shift count. */
faster than one with a register address. */
#define NO_FUNCTION_CSE
-
-/* Define this macro if it is as good or better for a function to call
- itself with an explicit address than to call an address kept in a
- register. */
-
-#define NO_RECURSIVE_FUNCTION_CSE
\f
/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
return the mode to be used for the comparison.
/* A C expression whose value is reversed condition code of the CODE for
comparison done in CC_MODE mode. */
-#define REVERSE_CONDITION(CODE, MODE) \
- ((MODE) != CCFPmode && (MODE) != CCFPUmode ? reverse_condition (CODE) \
- : reverse_condition_maybe_unordered (CODE))
+#define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE))
\f
/* Control the assembler format that we output, to the extent
#define JUMP_TABLES_IN_TEXT_SECTION \
(!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA)
-/* A C statement that outputs an address constant appropriate to
- for DWARF debugging. */
-
-#define ASM_OUTPUT_DWARF_ADDR_CONST(FILE, X) \
- i386_dwarf_output_addr_const ((FILE), (X))
-
/* Emit a dtp-relative reference to a TLS variable. */
#ifdef HAVE_AS_TLS
#define RET return ""
#define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx))
\f
-/* Define the codes that are matched by predicates in i386.c. */
-
-#define PREDICATE_CODES \
- {"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \
- SYMBOL_REF, LABEL_REF, CONST}}, \
- {"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \
- SYMBOL_REF, LABEL_REF, CONST}}, \
- {"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \
- SYMBOL_REF, LABEL_REF, CONST}}, \
- {"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \
- SYMBOL_REF, LABEL_REF, CONST}}, \
- {"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \
- SYMBOL_REF, LABEL_REF, CONST}}, \
- {"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \
- SYMBOL_REF, LABEL_REF, CONST}}, \
- {"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \
- SYMBOL_REF, LABEL_REF}}, \
- {"shiftdi_operand", {SUBREG, REG, MEM}}, \
- {"const_int_1_31_operand", {CONST_INT}}, \
- {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
- {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
- LABEL_REF, SUBREG, REG, MEM}}, \
- {"pic_symbolic_operand", {CONST}}, \
- {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \
- {"sibcall_insn_operand", {REG, SUBREG, SYMBOL_REF}}, \
- {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \
- {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \
- {"const1_operand", {CONST_INT}}, \
- {"const248_operand", {CONST_INT}}, \
- {"const_0_to_3_operand", {CONST_INT}}, \
- {"const_0_to_7_operand", {CONST_INT}}, \
- {"const_0_to_15_operand", {CONST_INT}}, \
- {"const_0_to_255_operand", {CONST_INT}}, \
- {"incdec_operand", {CONST_INT}}, \
- {"mmx_reg_operand", {REG}}, \
- {"reg_no_sp_operand", {SUBREG, REG}}, \
- {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \
- SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \
- {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \
- {"index_register_operand", {SUBREG, REG}}, \
- {"flags_reg_operand", {REG}}, \
- {"q_regs_operand", {SUBREG, REG}}, \
- {"non_q_regs_operand", {SUBREG, REG}}, \
- {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \
- ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \
- GE, UNGE, LTGT, UNEQ}}, \
- {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \
- ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \
- }}, \
- {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \
- GTU, UNORDERED, ORDERED, UNLE, UNLT, \
- UNGE, UNGT, LTGT, UNEQ }}, \
- {"ix86_carry_flag_operator", {LTU, LT, UNLT, GT, UNGT, LE, UNLE, \
- GE, UNGE, LTGT, UNEQ}}, \
- {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \
- {"ext_register_operand", {SUBREG, REG}}, \
- {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \
- {"mult_operator", {MULT}}, \
- {"div_operator", {DIV}}, \
- {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \
- UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \
- UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \
- LSHIFTRT, ROTATERT}}, \
- {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \
- {"memory_displacement_operand", {MEM}}, \
- {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
- LABEL_REF, SUBREG, REG, MEM, AND}}, \
- {"long_memory_operand", {MEM}}, \
- {"tls_symbolic_operand", {SYMBOL_REF}}, \
- {"global_dynamic_symbolic_operand", {SYMBOL_REF}}, \
- {"local_dynamic_symbolic_operand", {SYMBOL_REF}}, \
- {"initial_exec_symbolic_operand", {SYMBOL_REF}}, \
- {"local_exec_symbolic_operand", {SYMBOL_REF}}, \
- {"any_fp_register_operand", {REG}}, \
- {"register_and_not_any_fp_reg_operand", {REG}}, \
- {"fp_register_operand", {REG}}, \
- {"register_and_not_fp_reg_operand", {REG}}, \
- {"zero_extended_scalar_load_operand", {MEM}}, \
- {"vector_move_operand", {CONST_VECTOR, SUBREG, REG, MEM}}, \
- {"no_seg_address_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
- LABEL_REF, SUBREG, REG, MEM, PLUS, MULT}},
-
-/* A list of predicates that do special things with modes, and so
- should not elicit warnings for VOIDmode match_operand. */
-
-#define SPECIAL_MODE_PREDICATES \
- "ext_register_operand",
-\f
/* Which processor to schedule for. The cpu attribute defines a list that
mirrors this list, so changes to i386.md must be made at the same time. */
PROCESSOR_ATHLON,
PROCESSOR_PENTIUM4,
PROCESSOR_K8,
+ PROCESSOR_NOCONA,
PROCESSOR_max
};
extern int ix86_regparm;
extern const char *ix86_regparm_string;
-extern int ix86_preferred_stack_boundary;
+extern unsigned int ix86_preferred_stack_boundary;
extern const char *ix86_preferred_stack_boundary_string;
extern int ix86_branch_cost;
Post-reload pass may be later used to eliminate the redundant fildcw if
needed. */
-enum fp_cw_mode {FP_CW_STORED, FP_CW_UNINITIALIZED, FP_CW_ANY};
/* Define this macro if the port needs extra instructions inserted
for mode switching in an optimizing compilation. */
starting counting at zero - determines the integer that is used to
refer to the mode-switched entity in question. */
-#define NUM_MODES_FOR_MODE_SWITCHING { FP_CW_ANY }
+#define NUM_MODES_FOR_MODE_SWITCHING { I387_CW_ANY }
/* ENTITY is an integer specifying a mode-switched entity. If
`OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
return an integer value not larger than the corresponding element
in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
- must be switched into prior to the execution of INSN. */
+ must be switched into prior to the execution of INSN.
+
+ The mode UNINITIALIZED is used to force re-load of possibly previously
+ stored control word after function call. The mode ANY specify that
+ function has no requirements on the control word and make no changes
+ in the bits we are interested in. */
#define MODE_NEEDED(ENTITY, I) \
(GET_CODE (I) == CALL_INSN \
|| (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \
|| GET_CODE (PATTERN (I)) == ASM_INPUT))\
- ? FP_CW_UNINITIALIZED \
- : recog_memoized (I) < 0 || get_attr_type (I) != TYPE_FISTP \
- ? FP_CW_ANY \
- : FP_CW_STORED)
+ ? I387_CW_UNINITIALIZED \
+ : recog_memoized (I) < 0 \
+ ? I387_CW_ANY \
+ : get_attr_i387_cw (I))
/* This macro specifies the order in which modes for ENTITY are
processed. 0 is the highest priority. */
are to be inserted. */
#define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
- ((MODE) == FP_CW_STORED \
+ ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \
? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \
- assign_386_stack_local (HImode, 2)), 0\
+ assign_386_stack_local (HImode, 2), \
+ MODE), 0 \
: 0)
\f
/* Avoid renaming of stack registers, as doing so in combination with
projects / gcc.git / blobdiff