Enable VBMI2 support [6/7]

[gcc.git] / gcc / config / i386 / sse.md

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 73560d897d7f2eb25314849c2c781813de2073ef..5a92444000761f0ed06da5b00cd62209510bebf3 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -164,6 +164,7 @@
   ;; For AVX512VBMI2 support
   UNSPEC_VPSHLD
   UNSPEC_VPSHRD
+  UNSPEC_VPSHRDV
 ])
 
 (define_c_enum "unspecv" [
@@ -20114,3 +20115,59 @@
   "TARGET_AVX512VBMI2"
   "vpshld<ssemodesuffix>\t{%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3 }"
    [(set_attr ("prefix") ("evex"))])
+
+(define_insn "vpshrdv_<mode>"
+  [(set (match_operand:VI248_VLBW 0 "register_operand" "=v")
+       (unspec:VI248_VLBW
+         [(match_operand:VI248_VLBW 1 "register_operand" "0")
+          (match_operand:VI248_VLBW 2 "register_operand" "v")
+          (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")
+] UNSPEC_VPSHRDV))]
+  "TARGET_AVX512VBMI2"
+  "vpshrdv<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3 }"
+   [(set_attr ("prefix") ("evex"))
+   (set_attr "mode" "<sseinsnmode>")])
+
+(define_insn "vpshrdv_<mode>_mask"
+  [(set (match_operand:VI248_VLBW 0 "register_operand" "=v")
+       (vec_merge:VI248_VLBW (unspec:VI248_VLBW
+         [(match_operand:VI248_VLBW 1 "register_operand" "0")
+          (match_operand:VI248_VLBW 2 "register_operand" "v")
+          (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")
+       ] UNSPEC_VPSHRDV)
+           (match_dup 1)
+           (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk"))
+)]
+  "TARGET_AVX512VBMI2"
+  "vpshrdv<ssemodesuffix>\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3 }"
+   [(set_attr ("prefix") ("evex"))
+   (set_attr "mode" "<sseinsnmode>")])
+
+(define_expand "vpshrdv_<mode>_maskz"
+  [(match_operand:VI248_VLBW 0 "register_operand")
+   (match_operand:VI248_VLBW 1 "register_operand")
+   (match_operand:VI248_VLBW 2 "register_operand")
+   (match_operand:VI248_VLBW 3 "nonimmediate_operand")
+   (match_operand:<avx512fmaskmode> 4 "register_operand")]
+  "TARGET_AVX512VBMI2"
+{
+  emit_insn (gen_vpshrdv_<mode>_maskz_1 (
+    operands[0], operands[1], operands[2], operands[3],
+    CONST0_RTX (<MODE>mode), operands[4]));
+  DONE;
+})
+
+(define_insn "vpshrdv_<mode>_maskz_1"
+  [(set (match_operand:VI248_VLBW 0 "register_operand" "=v")
+       (vec_merge:VI248_VLBW (unspec:VI248_VLBW
+         [(match_operand:VI248_VLBW 1 "register_operand" "0")
+          (match_operand:VI248_VLBW 2 "register_operand" "v")
+          (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")
+       ] UNSPEC_VPSHRDV)
+         (match_operand:VI248_VLBW 4 "const0_operand" "C")
+          (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk"))
+)]
+  "TARGET_AVX512VBMI2"
+  "vpshrdv<ssemodesuffix>\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }"
+   [(set_attr ("prefix") ("evex"))
+   (set_attr "mode" "<sseinsnmode>")])