/* Subroutines used for code generation on intel 80960.
- Copyright (C) 1992, 1995 Free Software Foundation, Inc.
+ Copyright (C) 1992, 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
Contributed by Steven McGeady, Intel Corp.
Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
-
-#include <stdio.h>
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA. */
#include "config.h"
+#include <stdio.h>
#include "rtl.h"
#include "regs.h"
#include "hard-reg-set.h"
#include "flags.h"
#include "tree.h"
#include "insn-codes.h"
-#include "assert.h"
#include "expr.h"
+#include "except.h"
#include "function.h"
#include "recog.h"
#include <math.h>
/* ??? This is incomplete, since it does not handle all pragmas that the
intel compilers understand. */
-void
-process_pragma (finput)
+int
+process_pragma (finput, t)
FILE *finput;
+ tree t;
{
- int c;
int i;
+ register int c;
+ register char *pname;
+
+ if (TREE_CODE (t) != IDENTIFIER_NODE)
+ return 0;
- c = getc (finput);
- while (c == ' ' || c == '\t')
- c = getc (finput);
+ pname = IDENTIFIER_POINTER (t);
- if (c == 'a'
- && getc (finput) == 'l'
- && getc (finput) == 'i'
- && getc (finput) == 'g'
- && getc (finput) == 'n'
- && ((c = getc (finput)) == ' ' || c == '\t' || c == '\n'))
+ if (strcmp (pname, "align") == 0)
{
char buf[20];
char *s = buf;
int align;
- while (c == ' ' || c == '\t')
+ do {
c = getc (finput);
+ } while (c == ' ' || c == '\t');
+
if (c == '(')
c = getc (finput);
while (c >= '0' && c <= '9')
}
*s = '\0';
+ /* We had to read a non-numerical character to get out of the
+ while loop---often a newline. So, we have to put it back to
+ make sure we continue to parse everything properly. */
+ ungetc (c, finput);
+
align = atoi (buf);
switch (align)
{
- missing identifier means next struct
- alignment rules for bitfields need more investigation */
+
+ return 1;
}
/* Should be pragma 'far' or equivalent for callx/balx here. */
- ungetc (c, finput);
+ return 0;
}
/* Initialize variables before compiling any files. */
return (register_operand (op, mode) || literal (op, mode));
}
+/* Return truth value of whether OP can be used as an operands in a three
+ address logic insn, possibly complementing OP, of mode MODE. */
+
+int
+logic_operand (op, mode)
+ rtx op;
+ enum machine_mode mode;
+{
+ return (register_operand (op, mode)
+ || (GET_CODE (op) == CONST_INT
+ && INTVAL(op) >= -32 && INTVAL(op) < 32));
+}
+
/* Return true if OP is a register or a valid floating point literal. */
int
if (GET_CODE (x) == REG)
return 1;
#endif
+ /* This is a MEMA operand -- it's free. */
+ if (GET_CODE (x) == CONST_INT
+ && INTVAL (x) >= 0
+ && INTVAL (x) < 4096)
+ return 0;
+
if (GET_CODE (x) == PLUS)
{
rtx base = XEXP (x, 0);
rtx *operands;
enum machine_mode mode;
{
- register rtx operand0 = operands[0];
- register rtx operand1 = operands[1];
-
/* We can only store registers to memory. */
- if (GET_CODE (operand0) == MEM && GET_CODE (operand1) != REG)
- operands[1] = force_reg (mode, operand1);
+ if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) != REG)
+ operands[1] = force_reg (mode, operands[1]);
+
+ /* Storing multi-word values in unaligned hard registers to memory may
+ require a scratch since we have to store them a register at a time and
+ adding 4 to the memory address may not yield a valid insn. */
+ /* ??? We don't always need the scratch, but that would complicate things.
+ Maybe later. */
+ /* ??? We must also handle stores to pseudos here, because the pseudo may be
+ replaced with a MEM later. This would be cleaner if we didn't have
+ a separate pattern for unaligned DImode/TImode stores. */
+ if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
+ && (GET_CODE (operands[0]) == MEM
+ || (GET_CODE (operands[0]) == REG
+ && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
+ && GET_CODE (operands[1]) == REG
+ && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
+ && ! HARD_REGNO_MODE_OK (REGNO (operands[1]), mode))
+ {
+ emit_insn (gen_rtx (PARALLEL, VOIDmode,
+ gen_rtvec (2,
+ gen_rtx (SET, VOIDmode,
+ operands[0], operands[1]),
+ gen_rtx (CLOBBER, VOIDmode,
+ gen_rtx (SCRATCH, Pmode)))));
+ return 1;
+ }
return 0;
}
+
+/* Output assembler to move a double word value. */
+
+char *
+i960_output_move_double (dst, src)
+ rtx dst, src;
+{
+ rtx operands[5];
+
+ if (GET_CODE (dst) == REG
+ && GET_CODE (src) == REG)
+ {
+ if ((REGNO (src) & 1)
+ || (REGNO (dst) & 1))
+ {
+ /* We normally copy the low-numbered register first. However, if
+ the second source register is the same as the first destination
+ register, we must copy in the opposite order. */
+ if (REGNO (src) + 1 == REGNO (dst))
+ return "mov %D1,%D0\n\tmov %1,%0";
+ else
+ return "mov %1,%0\n\tmov %D1,%D0";
+ }
+ else
+ return "movl %1,%0";
+ }
+ else if (GET_CODE (dst) == REG
+ && GET_CODE (src) == CONST_INT
+ && CONST_OK_FOR_LETTER_P (INTVAL (src), 'I'))
+ {
+ if (REGNO (dst) & 1)
+ return "mov %1,%0\n\tmov 0,%D0";
+ else
+ return "movl %1,%0";
+ }
+ else if (GET_CODE (dst) == REG
+ && GET_CODE (src) == MEM)
+ {
+ if (REGNO (dst) & 1)
+ {
+ /* One can optimize a few cases here, but you have to be
+ careful of clobbering registers used in the address and
+ edge conditions. */
+ operands[0] = dst;
+ operands[1] = src;
+ operands[2] = gen_rtx (REG, Pmode, REGNO (dst) + 1);
+ operands[3] = gen_rtx (MEM, word_mode, operands[2]);
+ operands[4] = adj_offsettable_operand (operands[3], UNITS_PER_WORD);
+ output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0", operands);
+ return "";
+ }
+ else
+ return "ldl %1,%0";
+ }
+ else if (GET_CODE (dst) == MEM
+ && GET_CODE (src) == REG)
+ {
+ if (REGNO (src) & 1)
+ {
+ /* This is handled by emit_move_sequence so we shouldn't get here. */
+ abort ();
+ }
+ return "stl %1,%0";
+ }
+ else
+ abort ();
+}
+
+/* Output assembler to move a quad word value. */
+
+char *
+i960_output_move_quad (dst, src)
+ rtx dst, src;
+{
+ rtx operands[7];
+
+ if (GET_CODE (dst) == REG
+ && GET_CODE (src) == REG)
+ {
+ if ((REGNO (src) & 3)
+ || (REGNO (dst) & 3))
+ {
+ /* We normally copy starting with the low numbered register.
+ However, if there is an overlap such that the first dest reg
+ is <= the last source reg but not < the first source reg, we
+ must copy in the opposite order. */
+ if (REGNO (dst) <= REGNO (src) + 3
+ && REGNO (dst) >= REGNO (src))
+ return "mov %F1,%F0\n\tmov %E1,%E0\n\tmov %D1,%D0\n\tmov %1,%0";
+ else
+ return "mov %1,%0\n\tmov %D1,%D0\n\tmov %E1,%E0\n\tmov %F1,%F0";
+ }
+ else
+ return "movq %1,%0";
+ }
+ else if (GET_CODE (dst) == REG
+ && GET_CODE (src) == CONST_INT
+ && CONST_OK_FOR_LETTER_P (INTVAL (src), 'I'))
+ {
+ if (REGNO (dst) & 3)
+ return "mov %1,%0\n\tmov 0,%D0\n\tmov 0,%E0\n\tmov 0,%F0";
+ else
+ return "movq %1,%0";
+ }
+ else if (GET_CODE (dst) == REG
+ && GET_CODE (src) == MEM)
+ {
+ if (REGNO (dst) & 3)
+ {
+ /* One can optimize a few cases here, but you have to be
+ careful of clobbering registers used in the address and
+ edge conditions. */
+ operands[0] = dst;
+ operands[1] = src;
+ operands[2] = gen_rtx (REG, Pmode, REGNO (dst) + 3);
+ operands[3] = gen_rtx (MEM, word_mode, operands[2]);
+ operands[4] = adj_offsettable_operand (operands[3], UNITS_PER_WORD);
+ operands[5] = adj_offsettable_operand (operands[4], UNITS_PER_WORD);
+ operands[6] = adj_offsettable_operand (operands[5], UNITS_PER_WORD);
+ output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0\n\tld %5,%E0\n\tld %6,%F0", operands);
+ return "";
+ }
+ else
+ return "ldq %1,%0";
+ }
+ else if (GET_CODE (dst) == MEM
+ && GET_CODE (src) == REG)
+ {
+ if (REGNO (src) & 3)
+ {
+ /* This is handled by emit_move_sequence so we shouldn't get here. */
+ abort ();
+ }
+ return "stq %1,%0";
+ }
+ else
+ abort ();
+}
\f
/* Emit insns to load a constant to non-floating point registers.
Uses several strategies to try to use as few insns as possible. */
output_asm_insn ("# ldconst %1,%0",operands);
operands[0] = gen_rtx (REG, SImode, REGNO (dst));
- operands[1] = gen_rtx (CONST_INT, VOIDmode, value);
+ operands[1] = GEN_INT (value);
output_asm_insn (i960_output_ldconst (operands[0], operands[1]),
operands);
return "";
{
if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
return "lda %1,%0";
- operands[1] = gen_rtx (CONST_INT, VOIDmode, rsrc1 - 31);
+ operands[1] = GEN_INT (rsrc1 - 31);
output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands);
return "";
}
if (rsrc1 >= -31)
{
/* return 'sub -(%1),0,%0' */
- operands[1] = gen_rtx (CONST_INT, VOIDmode, - rsrc1);
+ operands[1] = GEN_INT (- rsrc1);
output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands);
return "";
}
/* ldconst -32 -> not 31,X */
if (rsrc1 == -32)
{
- operands[1] = gen_rtx (CONST_INT, VOIDmode, ~rsrc1);
+ operands[1] = GEN_INT (~rsrc1);
output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands);
return "";
}
/* If const is a single bit. */
if (bitpos (rsrc1) >= 0)
{
- operands[1] = gen_rtx (CONST_INT, VOIDmode, bitpos (rsrc1));
+ operands[1] = GEN_INT (bitpos (rsrc1));
output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands);
return "";
}
if (bitstr (rsrc1, &s, &e) < 6)
{
rsrc2 = ((unsigned int) rsrc1) >> s;
- operands[1] = gen_rtx (CONST_INT, VOIDmode, rsrc2);
- operands[2] = gen_rtx (CONST_INT, VOIDmode, s);
+ operands[1] = GEN_INT (rsrc2);
+ operands[2] = GEN_INT (s);
output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands);
return "";
}
if (epilogue_string[0] != '\0')
fprintf (file, "%s", epilogue_string);
- /* Must clear g14 on return. */
+ /* Must clear g14 on return if this function set it.
+ Only varargs/stdarg functions modify g14. */
- if (current_function_args_size != 0
- || VARARGS_STDARG_FUNCTION (current_function_decl))
+ if (VARARGS_STDARG_FUNCTION (current_function_decl))
fprintf (file, "\tmov 0,g14\n");
fprintf (file, "\tret\n");
output_asm_insn ("callx %0", operands);
+ /* If the caller sets g14 to the address of the argblock, then the caller
+ must clear it after the return. */
+
if (current_function_args_size != 0 || varargs_stdarg_function)
output_asm_insn ("mov r3,g14", operands);
+ else if (argsize > 48)
+ output_asm_insn ("mov 0,g14", operands);
return "";
}
return lbuf;
}
- if (current_function_args_size != 0
- || VARARGS_STDARG_FUNCTION (current_function_decl))
+ /* Must clear g14 on return if this function set it.
+ Only varargs/stdarg functions modify g14. */
+
+ if (VARARGS_STDARG_FUNCTION (current_function_decl))
output_asm_insn ("mov 0,g14", 0);
if (i960_leaf_ret_reg >= 0)
switch (code)
{
case 'D':
- /* Second reg of a double. */
+ /* Second reg of a double or quad. */
fprintf (file, "%s", reg_names[REGNO (x)+1]);
break;
+ case 'E':
+ /* Third reg of a quad. */
+ fprintf (file, "%s", reg_names[REGNO (x)+2]);
+ break;
+
+ case 'F':
+ /* Fourth reg of a quad. */
+ fprintf (file, "%s", reg_names[REGNO (x)+3]);
+ break;
+
case 0:
fprintf (file, "%s", reg_names[REGNO (x)]);
break;
}
else if (rtxcode == CONST_INT)
{
- if (INTVAL (x) > 9999 || INTVAL (x) < -999)
- fprintf (file, "0x%x", INTVAL (x));
+ HOST_WIDE_INT val = INTVAL (x);
+ if (code == 'C')
+ val = ~val;
+ if (val > 9999 || val < -999)
+ fprintf (file, "0x%x", val);
else
- fprintf (file, "%d", INTVAL (x));
+ fprintf (file, "%d", val);
return;
}
else if (rtxcode == CONST_DOUBLE)
}
#endif
\f
-/* Modes for condition codes. */
-#define C_MODES \
- ((1 << (int) CCmode) | (1 << (int) CC_UNSmode) | (1<< (int) CC_CHKmode))
-
-/* Modes for single-word (and smaller) quantities. */
-#define S_MODES \
- (~C_MODES \
- & ~ ((1 << (int) DImode) | (1 << (int) TImode) \
- | (1 << (int) DFmode) | (1 << (int) XFmode)))
-/* Modes for double-word (and smaller) quantities. */
-#define D_MODES \
- (~C_MODES \
- & ~ ((1 << (int) TImode) | (1 << (int) XFmode)))
+int
+hard_regno_mode_ok (regno, mode)
+ int regno;
+ enum machine_mode mode;
+{
+ if (regno < 32)
+ {
+ switch (mode)
+ {
+ case CCmode: case CC_UNSmode: case CC_CHKmode:
+ return 0;
-/* Modes for quad-word quantities. */
-#define T_MODES (~C_MODES)
+ case DImode: case DFmode:
+ return (regno & 1) == 0;
-/* Modes for single-float quantities. */
-#define SF_MODES ((1 << (int) SFmode))
+ case TImode: case XFmode:
+ return (regno & 3) == 0;
-/* Modes for double-float quantities. */
-#define DF_MODES (SF_MODES | (1 << (int) DFmode) | (1 << (int) SCmode))
+ default:
+ return 1;
+ }
+ }
+ else if (regno >= 32 && regno < 36)
+ {
+ switch (mode)
+ {
+ case SFmode: case DFmode: case XFmode:
+ case SCmode: case DCmode:
+ return 1;
-/* Modes for quad-float quantities. */
-#define XF_MODES (DF_MODES | (1 << (int) XFmode) | (1 << (int) DCmode))
+ default:
+ return 0;
+ }
+ }
+ else if (regno == 36)
+ {
+ switch (mode)
+ {
+ case CCmode: case CC_UNSmode: case CC_CHKmode:
+ return 1;
-unsigned int hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] = {
- T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
- T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
- T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
- T_MODES, S_MODES, D_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
+ default:
+ return 0;
+ }
+ }
+ else if (regno == 37)
+ return 0;
- XF_MODES, XF_MODES, XF_MODES, XF_MODES, C_MODES};
+ abort ();
+}
\f
/* Return the minimum alignment of an expression rtx X in bytes. This takes
else if (mode == VOIDmode)
{
/* End of parm list. */
- assert (type != 0 && TYPE_MODE (type) == VOIDmode);
+ if (type == 0 || TYPE_MODE (type) != VOIDmode)
+ abort ();
size = 1;
}
else
size = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
if (type == 0)
- align = size;
+ {
+ /* ??? This is a hack to properly correct the alignment of XFmode
+ values without affecting anything else. */
+ if (size == 3)
+ align = 4;
+ else
+ align = size;
+ }
else if (TYPE_ALIGN (type) >= BITS_PER_WORD)
align = TYPE_ALIGN (type) / BITS_PER_WORD;
else
subsequent arguments are placed on the stack.
Additionally, parameters with an alignment requirement stronger than
- a word must be be aligned appropriately. */
+ a word must be aligned appropriately. Note that this means that a
+ 64 bit object with a 32 bit alignment is not 64 bit aligned and may be
+ passed in an odd/even register pair. */
/* Update CUM to advance past an argument described by MODE and TYPE. */