;;- Machine description for GNU compiler -- S/390 / zSeries version.
-;; Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+;; Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
;; Ulrich Weigand (uweigand@de.ibm.com).
;; This file is part of GNU CC.
-
+
;; GNU CC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2, or (at your option)
;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
;;
+;; Processor type. This attribute must exactly match the processor_type
+;; enumeration in s390.h.
+
+(define_attr "cpu" "g5,g6,z900"
+ (const (symbol_ref "s390_cpu")))
;; Define an insn type attribute. This is used in function unit delay
;; computations.
-(define_attr "type" "none,integer,load,lr,la,lm,stm,cs,vs,store,imul,lmul,fmul,idiv,ldiv,fdiv,branch,jsr,other,o2,o3"
- (const_string "integer"))
+(define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
+ cs,vs,store,imul,idiv,
+ branch,jsr,fsimpd,fsimps,
+ floadd,floads,fstored, fstores,
+ fmuld,fmuls,fdivd,fdivs,
+ ftoi,itof,fsqrtd,fsqrts,
+ other,o2,o3"
+ (const_string "integer"))
-;; Insn are devide in two classes:
-;; mem: Insn accessing memory
-;; reg: Insn operands all in registers
+;; Operand type. Used to default length attribute values
-(define_attr "atype" "reg,mem"
- (const_string "reg"))
+(define_attr "op_type"
+ "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE"
+ (const_string "RX"))
+
+;; Insn are devide in two classes:
+;; agen: Insn using agen
+;; reg: Insn not using agen
+
+(define_attr "atype" "agen,reg"
+(cond [ (eq_attr "op_type" "E") (const_string "reg")
+ (eq_attr "op_type" "RR") (const_string "reg")
+ (eq_attr "op_type" "RX") (const_string "agen")
+ (eq_attr "op_type" "RI") (const_string "reg")
+ (eq_attr "op_type" "RRE") (const_string "reg")
+ (eq_attr "op_type" "RS") (const_string "agen")
+ (eq_attr "op_type" "RSI") (const_string "agen")
+ (eq_attr "op_type" "S") (const_string "agen")
+ (eq_attr "op_type" "SI") (const_string "agen")
+ (eq_attr "op_type" "SS") (const_string "agen")
+ (eq_attr "op_type" "SSE") (const_string "agen")
+ (eq_attr "op_type" "RXE") (const_string "agen")
+ (eq_attr "op_type" "RSE") (const_string "agen")
+ (eq_attr "op_type" "RIL") (const_string "agen")]
+ (const_string "reg")))
;; Generic pipeline function unit.
(define_function_unit "integer" 1 0
(eq_attr "type" "integer") 1 1)
+(define_function_unit "integer" 1 0
+ (eq_attr "type" "fsimpd") 1 1)
+
+(define_function_unit "integer" 1 0
+ (eq_attr "type" "fsimps") 1 1)
+
(define_function_unit "integer" 1 0
(eq_attr "type" "load") 1 1)
+(define_function_unit "integer" 1 0
+ (eq_attr "type" "floadd") 1 1)
+
+(define_function_unit "integer" 1 0
+ (eq_attr "type" "floads") 1 1)
+
(define_function_unit "integer" 1 0
(eq_attr "type" "la") 1 1)
+(define_function_unit "integer" 1 0
+ (eq_attr "type" "larl") 1 1)
+
(define_function_unit "integer" 1 0
(eq_attr "type" "lr") 1 1)
+(define_function_unit "integer" 1 0
+ (eq_attr "type" "branch") 1 1)
+
(define_function_unit "integer" 1 0
(eq_attr "type" "store") 1 1)
+(define_function_unit "integer" 1 0
+ (eq_attr "type" "fstored") 1 1)
+
+(define_function_unit "integer" 1 0
+ (eq_attr "type" "fstores") 1 1)
+
(define_function_unit "integer" 1 0
(eq_attr "type" "lm") 2 2)
(eq_attr "type" "imul") 7 7)
(define_function_unit "integer" 1 0
- (eq_attr "type" "fmul") 6 6)
+ (eq_attr "type" "fmuld") 6 6)
+
+(define_function_unit "integer" 1 0
+ (eq_attr "type" "fmuls") 6 6)
(define_function_unit "integer" 1 0
(eq_attr "type" "idiv") 33 33)
(define_function_unit "integer" 1 0
- (eq_attr "type" "fdiv") 33 33)
+ (eq_attr "type" "fdivd") 33 33)
+
+(define_function_unit "integer" 1 0
+ (eq_attr "type" "fdivs") 33 33)
+
+(define_function_unit "integer" 1 0
+ (eq_attr "type" "fsqrtd") 30 30)
+
+(define_function_unit "integer" 1 0
+ (eq_attr "type" "fsqrts") 30 30)
+
+(define_function_unit "integer" 1 0
+ (eq_attr "type" "ftoi") 2 2)
+
+(define_function_unit "integer" 1 0
+ (eq_attr "type" "itof") 2 2)
(define_function_unit "integer" 1 0
(eq_attr "type" "o2") 2 2)
(define_function_unit "integer" 1 0
(eq_attr "type" "other") 5 5)
-;; Operand type. Used to default length attribute values
+;; Pipeline description for z900
-(define_attr "op_type"
- "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE"
- (const_string "RX"))
+(include "2064.md")
;; Length in bytes.
(eq_attr "op_type" "RRE") (const_int 4)
(eq_attr "op_type" "RS") (const_int 4)
(eq_attr "op_type" "RSI") (const_int 4)
- (eq_attr "op_type" "RX") (const_int 4)
(eq_attr "op_type" "S") (const_int 4)
(eq_attr "op_type" "SI") (const_int 4)
(eq_attr "op_type" "SS") (const_int 6)
operands[2] = GEN_INT (block << shift);
return \"tm\\t%0,%b2\";
}"
- [(set_attr "op_type" "SI")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SI")])
; Test-under-Mask instructions
plus_constant (XEXP (operands[0], 0), part));
return \"tm\\t%0,%b1\";
}"
- [(set_attr "op_type" "SI")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SI")])
(define_insn "*tmsi_mem"
[(set (reg 33)
plus_constant (XEXP (operands[0], 0), part));
return \"tm\\t%0,%b1\";
}"
- [(set_attr "op_type" "SI")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SI")])
(define_insn "*tmhi_mem"
[(set (reg 33)
plus_constant (XEXP (operands[0], 0), part));
return \"tm\\t%0,%b1\";
}"
- [(set_attr "op_type" "SI")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SI")])
(define_insn "*tmqi_mem"
[(set (reg 33)
(match_operand:SI 2 "immediate_operand" "n")))]
"s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
"tm\\t%0,%b1"
- [(set_attr "op_type" "SI")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SI")])
(define_insn "*tmdi_reg"
[(set (reg 33)
(match_operand:DI 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
"srda\\t%0,0"
- [(set_attr "op_type" "RS")])
+ [(set_attr "op_type" "RS")
+ (set_attr "atype" "reg")])
+
(define_insn "*tstsi"
[(set (reg 33)
"@
ltr\\t%2,%0
icm\\t%2,15,%0"
- [(set_attr "op_type" "RR,RS")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RR,RS")])
(define_insn "*tstsi_cconly"
[(set (reg 33)
"@
ltr\\t%0,%0
icm\\t%2,15,%0"
- [(set_attr "op_type" "RR,RS")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RR,RS")])
(define_insn "*tstsi_cconly2"
[(set (reg 33)
"ltr\\t%0,%0"
[(set_attr "op_type" "RR")])
+(define_insn "*tsthiCCT"
+ [(set (reg 33)
+ (compare (match_operand:HI 0 "nonimmediate_operand" "?Q,d")
+ (match_operand:HI 1 "const0_operand" "")))
+ (set (match_operand:HI 2 "register_operand" "=d,0")
+ (match_dup 0))]
+ "s390_match_ccmode(insn, CCTmode)"
+ "@
+ icm\\t%2,3,%0
+ tml\\t%0,65535"
+ [(set_attr "op_type" "RS,RI")])
+
+(define_insn "*tsthiCCT_cconly"
+ [(set (reg 33)
+ (compare (match_operand:HI 0 "nonimmediate_operand" "?Q,d")
+ (match_operand:HI 1 "const0_operand" "")))
+ (clobber (match_scratch:HI 2 "=d,X"))]
+ "s390_match_ccmode(insn, CCTmode)"
+ "@
+ icm\\t%2,3,%0
+ tml\\t%0,65535"
+ [(set_attr "op_type" "RS,RI")])
+
(define_insn "*tsthi"
[(set (reg 33)
(compare (match_operand:HI 0 "s_operand" "Q")
(match_dup 0))]
"s390_match_ccmode(insn, CCSmode)"
"icm\\t%2,3,%0"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RS")])
(define_insn "*tsthi_cconly"
[(set (reg 33)
(clobber (match_scratch:HI 2 "=d"))]
"s390_match_ccmode(insn, CCSmode)"
"icm\\t%2,3,%0"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RS")])
+
+(define_insn "*tstqiCCT"
+ [(set (reg 33)
+ (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,d")
+ (match_operand:QI 1 "const0_operand" "")))
+ (set (match_operand:QI 2 "register_operand" "=d,0")
+ (match_dup 0))]
+ "s390_match_ccmode(insn, CCTmode)"
+ "@
+ icm\\t%2,1,%0
+ tml\\t%0,255"
+ [(set_attr "op_type" "RS,RI")])
+
+(define_insn "*tstqiCCT_cconly"
+ [(set (reg 33)
+ (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,d")
+ (match_operand:QI 1 "const0_operand" "")))]
+ "s390_match_ccmode(insn, CCTmode)"
+ "@
+ cli\\t%0,0
+ tml\\t%0,255"
+ [(set_attr "op_type" "SI,RI")])
(define_insn "*tstqi"
[(set (reg 33)
(match_dup 0))]
"s390_match_ccmode(insn, CCSmode)"
"icm\\t%2,1,%0"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RS")])
(define_insn "*tstqi_cconly"
[(set (reg 33)
(clobber (match_scratch:QI 2 "=d"))]
"s390_match_ccmode(insn, CCSmode)"
"icm\\t%2,1,%0"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "mem")])
-
+ [(set_attr "op_type" "RS")])
; Compare (signed) instructions
"@
cgfr\\t%0,%1
cgf\\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXE")])
(define_insn "*cmpdi_ccs"
[(set (reg 33)
cgr\\t%0,%1
cghi\\t%0,%c1
cg\\t%0,%1"
- [(set_attr "op_type" "RRE,RI,RXE")
- (set_attr "atype" "reg,reg,mem")])
+ [(set_attr "op_type" "RRE,RI,RXE")])
(define_insn "*cmpsi_ccs_sign"
[(set (reg 33)
(match_operand:SI 0 "register_operand" "d")))]
"s390_match_ccmode(insn, CCSRmode)"
"ch\\t%0,%1"
- [(set_attr "op_type" "RX")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RX")])
(define_insn "*cmpsi_ccs"
[(set (reg 33)
cr\\t%0,%1
chi\\t%0,%c1
c\\t%0,%1"
- [(set_attr "op_type" "RR,RI,RX")
- (set_attr "atype" "reg,reg,mem")])
+ [(set_attr "op_type" "RR,RI,RX")])
; Compare (unsigned) instructions
"@
clgfr\\t%0,%1
clgf\\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXE")])
(define_insn "*cmpdi_ccu"
[(set (reg 33)
"@
clgr\\t%0,%1
clg\\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXE")])
(define_insn "*cmpsi_ccu"
[(set (reg 33)
"@
clr\\t%0,%1
cl\\t%0,%1"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RR,RX")])
(define_insn "*cmphi_ccu"
[(set (reg 33)
(match_operand:HI 1 "s_imm_operand" "Q")))]
"s390_match_ccmode(insn, CCUmode)"
"clm\\t%0,3,%1"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RS")])
(define_insn "*cmpqi_ccu"
[(set (reg 33)
(match_operand:QI 1 "s_imm_operand" "Q")))]
"s390_match_ccmode(insn, CCUmode)"
"clm\\t%0,1,%1"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RS")])
(define_insn "*cli"
[(set (reg 33)
(match_operand:QI 1 "immediate_operand" "n")))]
"s390_match_ccmode (insn, CCUmode)"
"cli\\t%0,%b1"
- [(set_attr "op_type" "SI")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SI")])
(define_insn "*cmpdi_ccu_mem"
[(set (reg 33)
(match_operand:DI 1 "s_imm_operand" "Q")))]
"s390_match_ccmode(insn, CCUmode)"
"clc\\t%O0(8,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
(define_insn "*cmpsi_ccu_mem"
[(set (reg 33)
(match_operand:SI 1 "s_imm_operand" "Q")))]
"s390_match_ccmode(insn, CCUmode)"
"clc\\t%O0(4,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
(define_insn "*cmphi_ccu_mem"
[(set (reg 33)
(match_operand:HI 1 "s_imm_operand" "Q")))]
"s390_match_ccmode(insn, CCUmode)"
"clc\\t%O0(2,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
(define_insn "*cmpqi_ccu_mem"
[(set (reg 33)
(match_operand:QI 1 "s_imm_operand" "Q")))]
"s390_match_ccmode(insn, CCUmode)"
"clc\\t%O0(1,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
; DF instructions
(match_operand:DF 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"ltdbr\\t%0,%0"
- [(set_attr "op_type" "RRE")])
+ [(set_attr "op_type" "RRE")
+ (set_attr "type" "fsimpd")])
(define_insn "*cmpdf_ccs_0_ibm"
[(set (reg 33)
(match_operand:DF 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"ltdr\\t%0,%0"
- [(set_attr "op_type" "RR")])
+ [(set_attr "op_type" "RR")
+ (set_attr "type" "fsimpd")])
(define_insn "*cmpdf_ccs"
[(set (reg 33)
cdbr\\t%0,%1
cdb\\t%0,%1"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fsimpd")])
(define_insn "*cmpdf_ccs_ibm"
[(set (reg 33)
cdr\\t%0,%1
cd\\t%0,%1"
[(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fsimpd")])
; SF instructions
(match_operand:SF 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"ltebr\\t%0,%0"
- [(set_attr "op_type" "RRE")])
+ [(set_attr "op_type" "RRE")
+ (set_attr "type" "fsimps")])
(define_insn "*cmpsf_ccs_0_ibm"
[(set (reg 33)
(match_operand:SF 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lter\\t%0,%0"
- [(set_attr "op_type" "RR")])
+ [(set_attr "op_type" "RR")
+ (set_attr "type" "fsimps")])
(define_insn "*cmpsf_ccs"
[(set (reg 33)
"@
cebr\\t%0,%1
ceb\\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "type" "fsimps")])
(define_insn "*cmpsf_ccs"
[(set (reg 33)
"@
cer\\t%0,%1
ce\\t%0,%1"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RR,RX")
+ (set_attr "type" "fsimps")])
;;
#
#
mvc\\t%O0(16,%R0),%1"
- [(set_attr "op_type" "RSE,RSE,NN,NN,SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RSE,RSE,NN,NN,SS")])
(define_split
[(set (match_operand:TI 0 "nonimmediate_operand" "")
&& CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
&& !FP_REG_P (operands[0])"
"lghi\\t%0,%h1"
- [(set_attr "op_type" "RI")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RI")])
(define_insn "*movdi_lli"
[(set (match_operand:DI 0 "register_operand" "=d")
default: abort ();
}
}"
- [(set_attr "op_type" "RI")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RI")])
(define_insn "*movdi_larl"
[(set (match_operand:DI 0 "register_operand" "=d")
&& !FP_REG_P (operands[0])"
"larl\\t%0,%1"
[(set_attr "op_type" "RIL")
- (set_attr "atype" "reg")
- (set_attr "type" "la")])
+ (set_attr "type" "larl")])
(define_insn "*movdi_64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,Q")
std\\t%1,%0
mvc\\t%O0(8,%R0),%1"
[(set_attr "op_type" "RRE,RXE,RXE,RR,RX,RX,SS")
- (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
+ (set_attr "type" "lr,load,store,floadd,floadd,fstored,cs")])
(define_insn "*movdi_31"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,m,!*f,!*f,!m,Q")
std\\t%1,%0
mvc\\t%O0(8,%R0),%1"
[(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RX,SS")
- (set_attr "atype" "mem,mem,*,*,reg,mem,mem,mem")])
+ (set_attr "type" "lm,stm,*,*,floadd,floadd,fstored,cs")])
(define_split
[(set (match_operand:DI 0 "nonimmediate_operand" "")
ste\\t%1,%0
mvc\\t%O0(4,%R0),%1"
[(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
- (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
+ (set_attr "type" "lr,load,store,floads,floads,fstores,cs")])
(define_peephole2
[(set (match_operand:SI 0 "register_operand" "")
lh\\t%0,%1
sth\\t%1,%0
mvc\\t%O0(2,%R0),%1"
- [(set_attr "op_type" "RR,RI,RX,RX,SS")
- (set_attr "atype" "reg,reg,mem,mem,mem")])
+ [(set_attr "op_type" "RR,RI,RX,RX,SS")])
(define_peephole2
[(set (match_operand:HI 0 "register_operand" "")
mvi\\t%0,%b1
mvc\\t%O0(1,%R0),%1"
[(set_attr "op_type" "RR,RI,RXE,RX,SI,SS")
- (set_attr "atype" "reg,reg,mem,mem,mem,mem")])
-
+ (set_attr "type" "lr,*,*,store,store,cs")])
(define_insn "movqi"
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,Q")
stc\\t%1,%0
mvi\\t%0,%b1
mvc\\t%O0(1,%R0),%1"
- [(set_attr "op_type" "RR,RI,RX,RX,SI,SS")
- (set_attr "atype" "reg,reg,mem,mem,mem,mem")])
+ [(set_attr "op_type" "RR,RI,RX,RX,SI,SS")])
(define_peephole2
[(set (match_operand:QI 0 "nonimmediate_operand" "")
(match_operand:QI 1 "memory_operand" "m"))]
""
"ic\\t%0,%1"
- [(set_attr "op_type" "RX")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RX")])
;
; movstricthi instruction pattern(s).
(clobber (reg:CC 33))]
""
"icm\\t%0,3,%1"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RS")])
;
lr\\t%0,%1
l\\t%0,%1"
[(set_attr "op_type" "RR,RS")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "lr,load")])
;
stg\\t%1,%0
mvc\\t%O0(8,%R0),%1"
[(set_attr "op_type" "RR,RX,RX,RRE,RXE,RXE,SS")
- (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
+ (set_attr "type" "floadd,floadd,fstored,lr,load,store,cs")])
(define_insn "*movdf_31"
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,Q,d,m,Q")
#
mvc\\t%O0(8,%R0),%1"
[(set_attr "op_type" "RR,RX,RX,RS,RS,NN,NN,SS")
- (set_attr "atype" "reg,mem,mem,mem,mem,*,*,mem")])
+ (set_attr "type" "floadd,floadd,fstored,lm,stm,*,*,cs")])
(define_split
[(set (match_operand:DF 0 "nonimmediate_operand" "")
st\\t%1,%0
mvc\\t%O0(4,%R0),%1"
[(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
- (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
+ (set_attr "type" "floads,floads,fstores,lr,load,store,cs")])
;
; load_multiple pattern(s).
return \"lmg\\t%1,%0,%2\";
}"
[(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")
(set_attr "type" "lm")])
(define_insn "*load_multiple_si"
return \"lm\\t%1,%0,%2\";
}"
[(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")
(set_attr "type" "lm")])
;
return \"stmg\\t%2,%0,%1\";
}"
[(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")
(set_attr "type" "stm")])
return \"stm\\t%2,%0,%1\";
}"
[(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")
(set_attr "type" "stm")])
;;
}"
[(set_attr "op_type" "SS,NN")
(set_attr "type" "cs,cs")
- (set_attr "atype" "mem,mem")
+ (set_attr "atype" "*,agen")
(set_attr "length" "*,14")])
(define_insn "movstr_short_31"
}"
[(set_attr "op_type" "SS,NN")
(set_attr "type" "cs,cs")
- (set_attr "atype" "mem,mem")
+ (set_attr "atype" "*,agen")
(set_attr "length" "*,14")])
; Move a block of arbitrary length.
"mvcle\\t%0,%1,0\;jo\\t.-4"
[(set_attr "op_type" "NN")
(set_attr "type" "vs")
- (set_attr "atype" "mem")
(set_attr "length" "8")])
(define_insn "movstr_long_31"
"mvcle\\t%0,%1,0\;jo\\t.-4"
[(set_attr "op_type" "NN")
(set_attr "type" "vs")
- (set_attr "atype" "mem")
(set_attr "length" "8")])
;
}"
[(set_attr "op_type" "SS,NN")
(set_attr "type" "cs,cs")
- (set_attr "atype" "mem,mem")
+ (set_attr "atype" "*,agen")
(set_attr "length" "*,14")])
(define_insn "clrstr_short_31"
}"
[(set_attr "op_type" "SS,NN")
(set_attr "type" "cs,cs")
- (set_attr "atype" "mem,mem")
+ (set_attr "atype" "*,agen")
(set_attr "length" "*,14")])
; Clear a block of arbitrary length.
"TARGET_64BIT"
"mvcle\\t%0,%1,0\;jo\\t.-4"
[(set_attr "op_type" "NN")
- (set_attr "atype" "mem")
(set_attr "type" "vs")
(set_attr "length" "8")])
"!TARGET_64BIT"
"mvcle\\t%0,%1,0\;jo\\t.-4"
[(set_attr "op_type" "NN")
- (set_attr "atype" "mem")
(set_attr "type" "vs")
(set_attr "length" "8")])
}"
[(set_attr "op_type" "SS,NN")
(set_attr "type" "cs,cs")
- (set_attr "atype" "mem,mem")
+ (set_attr "atype" "*,agen")
(set_attr "length" "*,14")])
(define_insn "cmpstr_short_31"
}"
[(set_attr "op_type" "SS,NN")
(set_attr "type" "cs,cs")
- (set_attr "atype" "mem,mem")
+ (set_attr "atype" "*,agen")
(set_attr "length" "*,14")])
; Compare a block of arbitrary length.
"TARGET_64BIT"
"clcl\\t%0,%1"
[(set_attr "op_type" "RR")
- (set_attr "atype" "mem")
(set_attr "type" "vs")])
(define_insn "cmpstr_long_31"
"!TARGET_64BIT"
"clcl\\t%0,%1"
[(set_attr "op_type" "RR")
- (set_attr "atype" "mem")
(set_attr "type" "vs")])
; Convert condition code to integer in range (-1, 0, 1)
}"
[(set_attr "op_type" "NN")
(set_attr "length" "16")
- (set_attr "atype" "reg")
(set_attr "type" "other")])
(define_insn "cmpint_di"
}"
[(set_attr "op_type" "NN")
(set_attr "length" "22")
- (set_attr "atype" "reg")
(set_attr "type" "other")])
(clobber (reg:CC 33))]
""
"icm\\t%0,8,%1"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RS")])
(define_insn "*sethighhisi"
[(set (match_operand:SI 0 "register_operand" "=d")
(clobber (reg:CC 33))]
""
"icm\\t%0,12,%1"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RS")])
(define_insn "*sethighqidi_64"
[(set (match_operand:DI 0 "register_operand" "=d")
(clobber (reg:CC 33))]
"TARGET_64BIT"
"icmh\\t%0,8,%1"
- [(set_attr "op_type" "RSE")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RSE")])
(define_insn "*sethighqidi_31"
[(set (match_operand:DI 0 "register_operand" "=d")
(clobber (reg:CC 33))]
"!TARGET_64BIT"
"icm\\t%0,8,%1"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RS")])
(define_insn_and_split "*extractqi"
[(set (match_operand:SI 0 "register_operand" "=d")
operands[1] = change_address (operands[1], QImode, 0);
}"
[(set_attr "type" "o2")
- (set_attr "atype" "mem")])
+ (set_attr "atype" "agen")])
(define_insn_and_split "*extracthi"
[(set (match_operand:SI 0 "register_operand" "=d")
operands[1] = change_address (operands[1], HImode, 0);
}"
[(set_attr "type" "o2")
- (set_attr "atype" "mem")])
+ (set_attr "atype" "agen")])
;
; extendsidi2 instruction pattern(s).
"@
lgfr\\t%0,%1
lgf\\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXE")])
;
; extendhidi2 instruction pattern(s).
(sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"lgh\\t%0,%1"
- [(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RXE")])
;
; extendqidi2 instruction pattern(s).
(sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
""
"lh\\t%0,%1"
- [(set_attr "op_type" "RX")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RX")])
;
; extendqisi2 instruction pattern(s).
"@
llgfr\\t%0,%1
llgf\\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXE")])
;
; zero_extendhidi2 instruction pattern(s).
(zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgh\\t%0,%1"
- [(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RXE")])
;
; zero_extendqidi2 instruction pattern(s)
(zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgc\\t%0,%1"
- [(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RXE")])
;
; zero_extendhisi2 instruction pattern(s).
(zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgh\\t%0,%1"
- [(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RXE")])
(define_insn_and_split "*zero_extendhisi2_31"
[(set (match_operand:SI 0 "register_operand" "=&d")
(clobber (reg:CC 33))])]
"operands[2] = gen_lowpart (HImode, operands[0]);"
[(set_attr "type" "o2")
- (set_attr "atype" "mem")])
+ (set_attr "atype" "agen")])
;
; zero_extendqisi2 instruction pattern(s).
(zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgc\\t%0,%1"
- [(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RXE")])
(define_insn_and_split "*zero_extendqisi2_31"
[(set (match_operand:SI 0 "register_operand" "=&d")
(set (strict_low_part (match_dup 2)) (match_dup 1))]
"operands[2] = gen_lowpart (QImode, operands[0]);"
[(set_attr "type" "o2")
- (set_attr "atype" "mem")])
+ (set_attr "atype" "agen")])
;
; zero_extendqihi2 instruction pattern(s).
(zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgc\\t%0,%1"
- [(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RXE")])
(define_insn_and_split "*zero_extendqihi2_31"
[(set (match_operand:HI 0 "register_operand" "=&d")
(set (strict_low_part (match_dup 2)) (match_dup 1))]
"operands[2] = gen_lowpart (QImode, operands[0]);"
[(set_attr "type" "o2")
- (set_attr "atype" "mem")])
+ (set_attr "atype" "agen")])
;
"TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cgdbr\\t%0,%h2,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "other")])
+ (set_attr "type" "ftoi")])
;
; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
return \"l\\t%0,%N4\";
}"
[(set_attr "op_type" "NN")
- (set_attr "type" "other")
+ (set_attr "type" "ftoi")
+ (set_attr "atype" "agen")
(set_attr "length" "20")])
;
"TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cgebr\\t%0,%h2,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "other")])
+ (set_attr "type" "ftoi")])
;
; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cfebr\\t%0,%h2,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "other")])
+ (set_attr "type" "ftoi")])
;
; floatdidf2 instruction pattern(s).
"TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cegbr\\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "other" )])
+ (set_attr "type" "itof" )])
;
; floatsidf2 instruction pattern(s).
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cdfbr\\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "other" )])
+ (set_attr "type" "itof" )])
(define_insn "floatsidf2_ibm"
[(set (match_operand:DF 0 "register_operand" "=f")
}"
[(set_attr "op_type" "NN")
(set_attr "type" "other" )
+ (set_attr "atype" "agen")
(set_attr "length" "20")])
;
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cefbr\\t%0,%1"
[(set_attr "op_type" "RRE")
- (set_attr "type" "other" )])
+ (set_attr "type" "itof" )])
;
; truncdfsf2 instruction pattern(s).
lrer\\t%0,%1
le\\t%0,%1"
[(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "floads,floads")])
;
; extendsfdf2 instruction pattern(s).
"@
ldebr\\t%0,%1
ldeb\\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")])
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "type" "floads,floads")])
(define_insn "extendsfdf2_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
"@
sdr\\t%0,%0\;ler\\t%0,%1
sdr\\t%0,%0\;le\\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")
+ [(set_attr "op_type" "NN,NN")
+ (set_attr "atype" "reg,agen")
+ (set_attr "length" "4,6")
(set_attr "type" "o2,o2")])
&& preferred_la_operand_p (operands[1], 1)"
"#"
[(set_attr "op_type" "RX")
- (set_attr "atype" "mem")
(set_attr "type" "la")])
(define_split
"@
agfr\\t%0,%2
agf\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXE")])
(define_insn "*adddi3_zero_cc"
[(set (reg 33)
"@
algfr\\t%0,%2
algf\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXE")])
(define_insn "*adddi3_zero_cconly"
[(set (reg 33)
"@
algfr\\t%0,%2
algf\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXE")])
(define_insn "*adddi3_zero"
[(set (match_operand:DI 0 "register_operand" "=d,d")
"@
algfr\\t%0,%2
algf\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXE")])
(define_insn "*adddi3_imm_cc"
[(set (reg 33)
&& s390_match_ccmode (insn, CCAmode)
&& CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
"aghi\\t%0,%h2"
- [(set_attr "op_type" "RI")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RI")])
(define_insn "*adddi3_cc"
[(set (reg 33)
"@
algr\\t%0,%2
alg\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXE")])
(define_insn "*adddi3_cconly"
[(set (reg 33)
"@
algr\\t%0,%2
alg\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXE")])
(define_insn "*adddi3_cconly2"
[(set (reg 33)
"@
algr\\t%0,%2
alg\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXE")])
(define_insn "*adddi3_64"
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
agr\\t%0,%2
aghi\\t%0,%h2
ag\\t%0,%2"
- [(set_attr "op_type" "RRE,RI,RXE")
- (set_attr "atype" "reg,reg,mem")])
+ [(set_attr "op_type" "RRE,RI,RXE")])
(define_insn_and_split "*adddi3_31"
[(set (match_operand:DI 0 "register_operand" "=&d")
"TARGET_64BIT"
"la\\t%0,%a1"
[(set_attr "op_type" "RX")
- (set_attr "atype" "mem")
(set_attr "type" "la")])
(define_expand "reload_indi"
&& preferred_la_operand_p (operands[1], 1)"
"#"
[(set_attr "op_type" "RX")
- (set_attr "atype" "mem")
(set_attr "type" "la")])
(define_split
"s390_match_ccmode (insn, CCAmode)
&& CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
"ahi\\t%0,%h2"
- [(set_attr "op_type" "RI")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RI")])
(define_insn "*addsi3_carry1_cc"
[(set (reg 33)
"@
alr\\t%0,%2
al\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RR,RX")])
(define_insn "*addsi3_carry1_cconly"
[(set (reg 33)
"@
alr\\t%0,%2
al\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RR,RX")])
(define_insn "*addsi3_carry2_cc"
[(set (reg 33)
"@
alr\\t%0,%2
al\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RR,RX")])
(define_insn "*addsi3_carry2_cconly"
[(set (reg 33)
"@
alr\\t%0,%2
al\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RR,RX")])
(define_insn "*addsi3_cc"
[(set (reg 33)
"@
alr\\t%0,%2
al\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RR,RX")])
(define_insn "*addsi3_cconly"
[(set (reg 33)
"@
alr\\t%0,%2
al\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RR,RX")])
(define_insn "*addsi3_cconly2"
[(set (reg 33)
"@
alr\\t%0,%2
al\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RR,RX")])
(define_insn "*addsi3_sign"
[(set (match_operand:SI 0 "register_operand" "=d")
(clobber (reg:CC 33))]
""
"ah\\t%0,%2"
- [(set_attr "op_type" "RX")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RX")])
(define_insn "*addsi3_sub"
[(set (match_operand:SI 0 "register_operand" "=d")
(clobber (reg:CC 33))]
""
"ah\\t%0,%2"
- [(set_attr "op_type" "RX")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RX")])
(define_insn "addsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d,d")
ar\\t%0,%2
ahi\\t%0,%h2
a\\t%0,%2"
- [(set_attr "op_type" "RR,RI,RX")
- (set_attr "atype" "reg,reg,mem")])
+ [(set_attr "op_type" "RR,RI,RX")])
(define_insn "*la_31"
[(set (match_operand:SI 0 "register_operand" "=d")
"!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
"la\\t%0,%a1"
[(set_attr "op_type" "RX")
- (set_attr "atype" "mem")
(set_attr "type" "la")])
(define_insn "*la_31_and"
"!TARGET_64BIT"
"la\\t%0,%a1"
[(set_attr "op_type" "RX")
- (set_attr "atype" "mem")
(set_attr "type" "la")])
(define_insn_and_split "*la_31_and_cc"
(and:SI (match_dup 1) (const_int 2147483647)))]
""
[(set_attr "op_type" "RX")
- (set_attr "atype" "mem")
(set_attr "type" "la")])
(define_insn "force_la_31"
"!TARGET_64BIT"
"la\\t%0,%a1"
[(set_attr "op_type" "RX")
- (set_attr "atype" "mem")
(set_attr "type" "la")])
(define_expand "reload_insi"
adbr\\t%0,%2
adb\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fsimpd,fsimpd")])
(define_insn "*adddf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
adr\\t%0,%2
ad\\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fsimpd,fsimpd")])
;
; addsf3 instruction pattern(s).
aebr\\t%0,%2
aeb\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fsimps,fsimps")])
(define_insn "*addsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
aer\\t%0,%2
ae\\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fsimps,fsimps")])
;;
"@
sgfr\\t%0,%2
sgf\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXE")])
(define_insn "*subdi3_zero_cc"
[(set (reg 33)
"@
slgfr\\t%0,%2
slgf\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXE")])
(define_insn "*subdi3_zero_cconly"
[(set (reg 33)
"@
slgfr\\t%0,%2
slgf\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXE")])
(define_insn "*subdi3_zero"
[(set (match_operand:DI 0 "register_operand" "=d,d")
"@
slgfr\\t%0,%2
slgf\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXE")])
(define_insn "*subdi3_cc"
[(set (reg 33)
"@
slgr\\t%0,%2
slg\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXE")])
(define_insn "*subdi3_cconly"
[(set (reg 33)
"@
slgr\\t%0,%2
slg\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXE")])
(define_insn "*subdi3_64"
[(set (match_operand:DI 0 "register_operand" "=d,d")
"@
sgr\\t%0,%2
sg\\t%0,%2"
- [(set_attr "op_type" "RRE,RRE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RRE")])
(define_insn_and_split "*subdi3_31"
[(set (match_operand:DI 0 "register_operand" "=&d")
"@
slr\\t%0,%2
sl\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RR,RX")])
(define_insn "*subsi3_borrow_cconly"
[(set (reg 33)
"@
slr\\t%0,%2
sl\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RR,RX")])
(define_insn "*subsi3_cc"
[(set (reg 33)
"@
slr\\t%0,%2
sl\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RR,RX")])
(define_insn "*subsi3_cconly"
[(set (reg 33)
"@
slr\\t%0,%2
sl\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RR,RX")])
(define_insn "*subsi3_sign"
[(set (match_operand:SI 0 "register_operand" "=d")
(clobber (reg:CC 33))]
""
"sh\\t%0,%2"
- [(set_attr "op_type" "RX")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RX")])
(define_insn "*subsi3_sub"
[(set (match_operand:SI 0 "register_operand" "=d")
(clobber (reg:CC 33))]
""
"sh\\t%0,%2"
- [(set_attr "op_type" "RX")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "RX")])
(define_insn "subsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d")
"@
sr\\t%0,%2
s\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RR,RX")])
;
sdbr\\t%0,%2
sdb\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fsimpd,fsimpd")])
(define_insn "*subdf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
sdr\\t%0,%2
sd\\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fsimpd,fsimpd")])
;
; subsf3 instruction pattern(s).
sebr\\t%0,%2
seb\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fsimps,fsimps")])
(define_insn "*subsf3_ibm"
[(set (match_operand:SF 0 "register_operand" "=f,f")
ser\\t%0,%2
se\\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fsimps,fsimps")])
;;
msgfr\\t%0,%2
msgf\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")
(set_attr "type" "imul")])
mghi\\t%0,%h2
msg\\t%0,%2"
[(set_attr "op_type" "RRE,RI,RXE")
- (set_attr "atype" "reg,reg,mem")
(set_attr "type" "imul")])
;
mhi\\t%0,%h2
ms\\t%0,%2"
[(set_attr "op_type" "RRE,RI,RX")
- (set_attr "atype" "reg,reg,mem")
(set_attr "type" "imul")])
;
mr\\t%0,%2
m\\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")
(set_attr "type" "imul")])
;
mdbr\\t%0,%2
mdb\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fmul")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fmuld")])
(define_insn "*muldf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
mdr\\t%0,%2
md\\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "fmul")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fmuld")])
;
; mulsf3 instruction pattern(s).
meebr\\t%0,%2
meeb\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fmul")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fmuls")])
(define_insn "*mulsf3_ibm"
[(set (match_operand:SF 0 "register_operand" "=f,f")
mer\\t%0,%2
me\\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "fmul")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fmuls")])
;;
dsgr\\t%0,%2
dsg\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "idiv")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "idiv")])
(define_insn "divmodtisi3"
[(set (match_operand:TI 0 "register_operand" "=d,d")
dsgfr\\t%0,%2
dsgf\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "idiv")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "idiv")])
;
; udivmoddi4 instruction pattern(s).
dlgr\\t%0,%2
dlg\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "idiv")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "idiv")])
;
; divmodsi4 instruction pattern(s).
dr\\t%0,%2
d\\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "idiv")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "idiv")])
;
; udivsi3 and umodsi3 instruction pattern(s).
ddbr\\t%0,%2
ddb\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fdiv")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fdivd")])
(define_insn "*divdf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
ddr\\t%0,%2
dd\\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "fdiv")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fdivd")])
;
; divsf3 instruction pattern(s).
debr\\t%0,%2
deb\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fdiv")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fdivs")])
(define_insn "*divsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
der\\t%0,%2
de\\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "type" "fdiv")
- (set_attr "atype" "reg,mem")])
+ (set_attr "type" "fdivs")])
;;
"@
ngr\\t%0,%2
ng\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXE")])
(define_insn "*anddi3_cconly"
[(set (reg 33)
"@
ngr\\t%0,%2
ng\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXE")])
(define_insn "*anddi3_ni"
[(set (match_operand:DI 0 "register_operand" "=d")
default: abort ();
}
}"
- [(set_attr "op_type" "RI")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RI")])
(define_insn "anddi3"
[(set (match_operand:DI 0 "register_operand" "=d,d")
"@
ngr\\t%0,%2
ng\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXE")])
(define_insn "*anddi3_ss"
[(set (match_operand:DI 0 "s_operand" "=Q")
(clobber (reg:CC 33))]
""
"nc\\t%O0(8,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
(define_insn "*anddi3_ss_inv"
[(set (match_operand:DI 0 "s_operand" "=Q")
(clobber (reg:CC 33))]
""
"nc\\t%O0(8,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
;
; andsi3 instruction pattern(s).
"@
nr\\t%0,%2
n\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RR,RX")])
(define_insn "*andsi3_cconly"
[(set (reg 33)
"@
nr\\t%0,%2
n\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RR,RX")])
(define_insn "*andsi3_ni"
[(set (match_operand:SI 0 "register_operand" "=d")
default: abort ();
}
}"
- [(set_attr "op_type" "RI")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RI")])
(define_insn "andsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d")
"@
nr\\t%0,%2
n\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RR,RX")])
(define_insn "*andsi3_ss"
[(set (match_operand:SI 0 "s_operand" "=Q")
(clobber (reg:CC 33))]
""
"nc\\t%O0(4,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
(define_insn "*andsi3_ss_inv"
[(set (match_operand:SI 0 "s_operand" "=Q")
(clobber (reg:CC 33))]
""
"nc\\t%O0(4,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
;
; andhi3 instruction pattern(s).
"@
nr\\t%0,%2
nill\\t%0,%x2"
- [(set_attr "op_type" "RR,RI")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RR,RI")])
(define_insn "andhi3"
[(set (match_operand:HI 0 "register_operand" "=d")
(clobber (reg:CC 33))]
""
"nr\\t%0,%2"
- [(set_attr "op_type" "RR")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RR")])
(define_insn "*andhi3_ss"
[(set (match_operand:HI 0 "s_operand" "=Q")
(clobber (reg:CC 33))]
""
"nc\\t%O0(2,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
(define_insn "*andhi3_ss_inv"
[(set (match_operand:HI 0 "s_operand" "=Q")
(clobber (reg:CC 33))]
""
"nc\\t%O0(2,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
;
; andqi3 instruction pattern(s).
"@
nr\\t%0,%2
nill\\t%0,%b2"
- [(set_attr "op_type" "RR,RI")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RR,RI")])
(define_insn "andqi3"
[(set (match_operand:QI 0 "register_operand" "=d")
(clobber (reg:CC 33))]
""
"nr\\t%0,%2"
- [(set_attr "op_type" "RR")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RR")])
(define_insn "*andqi3_ss"
[(set (match_operand:QI 0 "s_operand" "=Q,Q")
"@
ni\\t%0,%b1
nc\\t%O0(1,%R0),%1"
- [(set_attr "op_type" "SI,SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SI,SS")])
(define_insn "*andqi3_ss_inv"
[(set (match_operand:QI 0 "s_operand" "=Q,Q")
"@
ni\\t%0,%b1
nc\\t%O0(1,%R0),%1"
- [(set_attr "op_type" "SI,SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SI,SS")])
;;
"@
ogr\\t%0,%2
og\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXE")])
(define_insn "*iordi3_cconly"
[(set (reg 33)
"@
ogr\\t%0,%2
og\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXE")])
(define_insn "*iordi3_oi"
[(set (match_operand:DI 0 "register_operand" "=d")
default: abort ();
}
}"
- [(set_attr "op_type" "RI")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RI")])
(define_insn "iordi3"
[(set (match_operand:DI 0 "register_operand" "=d,d")
"@
ogr\\t%0,%2
og\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXE")])
(define_insn "*iordi3_ss"
[(set (match_operand:DI 0 "s_operand" "=Q")
(clobber (reg:CC 33))]
""
"oc\\t%O0(8,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
(define_insn "*iordi3_ss_inv"
[(set (match_operand:DI 0 "s_operand" "=Q")
(clobber (reg:CC 33))]
""
"oc\\t%O0(8,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
;
; iorsi3 instruction pattern(s).
"@
or\\t%0,%2
o\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RR,RX")])
(define_insn "*iorsi3_cconly"
[(set (reg 33)
"@
or\\t%0,%2
o\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RR,RX")])
(define_insn "*iorsi3_oi"
[(set (match_operand:SI 0 "register_operand" "=d")
default: abort ();
}
}"
- [(set_attr "op_type" "RI")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RI")])
(define_insn "iorsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d")
"@
or\\t%0,%2
o\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RR,RX")])
(define_insn "*iorsi3_ss"
[(set (match_operand:SI 0 "s_operand" "=Q")
(clobber (reg:CC 33))]
""
"oc\\t%O0(4,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
(define_insn "*iorsi3_ss_inv"
[(set (match_operand:SI 0 "s_operand" "=Q")
(clobber (reg:CC 33))]
""
"oc\\t%O0(4,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
;
; iorhi3 instruction pattern(s).
"@
or\\t%0,%2
oill\\t%0,%x2"
- [(set_attr "op_type" "RR,RI")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RR,RI")])
(define_insn "iorhi3"
[(set (match_operand:HI 0 "register_operand" "=d")
(clobber (reg:CC 33))]
""
"or\\t%0,%2"
- [(set_attr "op_type" "RR")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RR")])
(define_insn "*iorhi3_ss"
[(set (match_operand:HI 0 "s_operand" "=Q")
(clobber (reg:CC 33))]
""
"oc\\t%O0(2,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
(define_insn "*iorhi3_ss_inv"
[(set (match_operand:HI 0 "s_operand" "=Q")
(clobber (reg:CC 33))]
""
"oc\\t%O0(2,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
;
; iorqi3 instruction pattern(s).
"@
or\\t%0,%2
oill\\t%0,%b2"
- [(set_attr "op_type" "RR,RI")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RR,RI")])
(define_insn "iorqi3"
[(set (match_operand:QI 0 "register_operand" "=d")
(clobber (reg:CC 33))]
""
"or\\t%0,%2"
- [(set_attr "op_type" "RR")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RR")])
(define_insn "*iorqi3_ss"
[(set (match_operand:QI 0 "s_operand" "=Q,Q")
"@
oi\\t%0,%b1
oc\\t%O0(1,%R0),%1"
- [(set_attr "op_type" "SI,SS")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "SI,SS")])
(define_insn "*iorqi3_ss_inv"
[(set (match_operand:QI 0 "s_operand" "=Q,Q")
"@
oi\\t%0,%b1
oc\\t%O0(1,%R0),%1"
- [(set_attr "op_type" "SI,SS")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "SI,SS")])
;;
"@
xgr\\t%0,%2
xg\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXE")])
(define_insn "*xordi3_cconly"
[(set (reg 33)
"@
xgr\\t%0,%2
xr\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXE")])
(define_insn "xordi3"
[(set (match_operand:DI 0 "register_operand" "=d,d")
"@
xgr\\t%0,%2
xg\\t%0,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RRE,RXE")])
(define_insn "*xordi3_ss"
[(set (match_operand:DI 0 "s_operand" "=Q")
(clobber (reg:CC 33))]
""
"xc\\t%O0(8,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
(define_insn "*xordi3_ss_inv"
[(set (match_operand:DI 0 "s_operand" "=Q")
(clobber (reg:CC 33))]
""
"xc\\t%O0(8,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
;
; xorsi3 instruction pattern(s).
"@
xr\\t%0,%2
x\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RR,RX")])
(define_insn "*xorsi3_cconly"
[(set (reg 33)
"@
xr\\t%0,%2
x\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RR,RX")])
(define_insn "xorsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d")
"@
xr\\t%0,%2
x\\t%0,%2"
- [(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")])
+ [(set_attr "op_type" "RR,RX")])
(define_insn "*xorsi3_ss"
[(set (match_operand:SI 0 "s_operand" "=Q")
(clobber (reg:CC 33))]
""
"xc\\t%O0(4,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
(define_insn "*xorsi3_ss_inv"
[(set (match_operand:SI 0 "s_operand" "=Q")
(clobber (reg:CC 33))]
""
"xc\\t%O0(4,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
;
; xorhi3 instruction pattern(s).
(clobber (reg:CC 33))]
""
"xc\\t%O0(2,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
(define_insn "*xorhi3_ss_inv"
[(set (match_operand:HI 0 "s_operand" "=Q")
(clobber (reg:CC 33))]
""
"xc\\t%O0(2,%R0),%1"
- [(set_attr "op_type" "SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SS")])
;
; xorqi3 instruction pattern(s).
(clobber (reg:CC 33))]
""
"xr\\t%0,%2"
- [(set_attr "op_type" "RR")
- (set_attr "atype" "reg")])
+ [(set_attr "op_type" "RR")])
(define_insn "*xorqi3_ss"
[(set (match_operand:QI 0 "s_operand" "=Q,Q")
"@
xi\\t%0,%b1
xc\\t%O0(1,%R0),%1"
- [(set_attr "op_type" "SI,SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SI,SS")])
(define_insn "*xorqi3_ss_inv"
[(set (match_operand:QI 0 "s_operand" "=Q,Q")
"@
xi\\t%0,%b1
xc\\t%O0(1,%R0),%1"
- [(set_attr "op_type" "SI,SS")
- (set_attr "atype" "mem")])
+ [(set_attr "op_type" "SI,SS")])
;;
output_asm_insn (\"lcr\\t%N0,%N1\", operands);
output_asm_insn (\"je\\t%l0\", xop);
output_asm_insn (\"bctr\\t%0,0\", operands);
- ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
+ (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
CODE_LABEL_NUMBER (xop[0]));
return \"\";
}"
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lcdbr\\t%0,%1"
- [(set_attr "op_type" "RRE")])
+ [(set_attr "op_type" "RRE")
+ (set_attr "type" "fsimpd")])
(define_insn "*negdf2_ibm"
[(set (match_operand:DF 0 "register_operand" "=f")
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lcdr\\t%0,%1"
- [(set_attr "op_type" "RR")])
+ [(set_attr "op_type" "RR")
+ (set_attr "type" "fsimpd")])
;
; negsf2 instruction pattern(s).
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lcebr\\t%0,%1"
- [(set_attr "op_type" "RRE")])
+ [(set_attr "op_type" "RRE")
+ (set_attr "type" "fsimps")])
(define_insn "*negsf2"
[(set (match_operand:SF 0 "register_operand" "=f")
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lcer\\t%0,%1"
- [(set_attr "op_type" "RR")])
+ [(set_attr "op_type" "RR")
+ (set_attr "type" "fsimps")])
;;
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lpdbr\\t%0,%1"
- [(set_attr "op_type" "RRE")])
+ [(set_attr "op_type" "RRE")
+ (set_attr "type" "fsimpd")])
(define_insn "*absdf2_ibm"
[(set (match_operand:DF 0 "register_operand" "=f")
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lpdr\\t%0,%1"
- [(set_attr "op_type" "RR")])
+ [(set_attr "op_type" "RR")
+ (set_attr "type" "fsimpd")])
;
; abssf2 instruction pattern(s).
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lpebr\\t%0,%1"
- [(set_attr "op_type" "RRE")])
+ [(set_attr "op_type" "RRE")
+ (set_attr "type" "fsimps")])
(define_insn "*abssf2_ibm"
[(set (match_operand:SF 0 "register_operand" "=f")
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lper\\t%0,%1"
- [(set_attr "op_type" "RR")])
+ [(set_attr "op_type" "RR")
+ (set_attr "type" "fsimps")])
;;
;;- Square root instructions.
"@
sqdbr\\t%0,%1
sqdb\\t%0,%1"
- [(set_attr "op_type" "RRE,RSE")])
+ [(set_attr "op_type" "RRE,RSE")
+ (set_attr "type" "fsqrtd")])
;
; sqrtsf2 instruction pattern(s).
"@
sqebr\\t%0,%1
sqeb\\t%0,%1"
- [(set_attr "op_type" "RRE,RSE")])
+ [(set_attr "op_type" "RRE,RSE")
+ (set_attr "type" "fsqrts")])
;;
;;- One complement instructions.
"@
rllg\\t%0,%1,%c2
rllg\\t%0,%1,0(%2)"
- [(set_attr "op_type" "RSE")])
+ [(set_attr "op_type" "RSE")
+ (set_attr "atype" "reg")])
;
; rotlsi3 instruction pattern(s).
"@
rll\\t%0,%1,%c2
rll\\t%0,%1,0(%2)"
- [(set_attr "op_type" "RSE")])
+ [(set_attr "op_type" "RSE")
+ (set_attr "atype" "reg")])
;;
"@
sldl\\t%0,%c2
sldl\\t%0,0(%2)"
- [(set_attr "op_type" "RS")])
+ [(set_attr "op_type" "RS")
+ (set_attr "atype" "reg")])
(define_insn "*ashldi3_64"
[(set (match_operand:DI 0 "register_operand" "=d,d")
"@
sllg\\t%0,%1,%2
sllg\\t%0,%1,0(%2)"
- [(set_attr "op_type" "RSE")])
+ [(set_attr "op_type" "RSE")
+ (set_attr "atype" "reg")])
;
; ashrdi3 instruction pattern(s).
"@
srda\\t%0,%c2
srda\\t%0,0(%2)"
- [(set_attr "op_type" "RS")])
+ [(set_attr "op_type" "RS")
+ (set_attr "atype" "reg")])
(define_insn "*ashrdi3_cconly_31"
[(set (reg 33)
"@
srda\\t%0,%c2
srda\\t%0,0(%2)"
- [(set_attr "op_type" "RS")])
+ [(set_attr "op_type" "RS")
+ (set_attr "atype" "reg")])
(define_insn "*ashrdi3_31"
[(set (match_operand:DI 0 "register_operand" "=d,d")
"@
srda\\t%0,%c2
srda\\t%0,0(%2)"
- [(set_attr "op_type" "RS")])
-
+ [(set_attr "op_type" "RS")
+ (set_attr "atype" "reg")])
+
(define_insn "*ashrdi3_cc_64"
[(set (reg 33)
(compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
"@
srag\\t%0,%1,%c2
srag\\t%0,%1,0(%2)"
- [(set_attr "op_type" "RSE")])
+ [(set_attr "op_type" "RSE")
+ (set_attr "atype" "reg")])
(define_insn "*ashrdi3_cconly_64"
[(set (reg 33)
"@
srag\\t%0,%1,%c2
srag\\t%0,%1,0(%2)"
- [(set_attr "op_type" "RSE")])
+ [(set_attr "op_type" "RSE")
+ (set_attr "atype" "reg")])
(define_insn "*ashrdi3_64"
[(set (match_operand:DI 0 "register_operand" "=d,d")
"@
srag\\t%0,%1,%c2
srag\\t%0,%1,0(%2)"
- [(set_attr "op_type" "RSE")])
+ [(set_attr "op_type" "RSE")
+ (set_attr "atype" "reg")])
+
;
; ashlsi3 instruction pattern(s).
"@
sll\\t%0,%c2
sll\\t%0,0(%2)"
- [(set_attr "op_type" "RS")])
+ [(set_attr "op_type" "RS")
+ (set_attr "atype" "reg")])
;
; ashrsi3 instruction pattern(s).
"@
sra\\t%0,%c2
sra\\t%0,0(%2)"
- [(set_attr "op_type" "RS")])
+ [(set_attr "op_type" "RS")
+ (set_attr "atype" "reg")])
+
(define_insn "*ashrsi3_cconly"
[(set (reg 33)
"@
sra\\t%0,%c2
sra\\t%0,0(%2)"
- [(set_attr "op_type" "RS")])
+ [(set_attr "op_type" "RS")
+ (set_attr "atype" "reg")])
(define_insn "ashrsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d")
"@
sra\\t%0,%c2
sra\\t%0,0(%2)"
- [(set_attr "op_type" "RS")])
+ [(set_attr "op_type" "RS")
+ (set_attr "atype" "reg")])
;;
"@
srdl\\t%0,%c2
srdl\\t%0,0(%2)"
- [(set_attr "op_type" "RS,RS")])
+ [(set_attr "op_type" "RS,RS")
+ (set_attr "atype" "reg")])
(define_insn "*lshrdi3_64"
[(set (match_operand:DI 0 "register_operand" "=d,d")
"@
srlg\\t%0,%1,%c2
srlg\\t%0,%1,0(%2)"
- [(set_attr "op_type" "RSE,RSE")])
+ [(set_attr "op_type" "RSE,RSE")
+ (set_attr "atype" "reg")])
;
; lshrsi3 instruction pattern(s).
"@
srl\\t%0,%c2
srl\\t%0,0(%2)"
- [(set_attr "op_type" "RS")])
+ [(set_attr "op_type" "RS")
+ (set_attr "atype" "reg")])
;;
abort ();
}"
[(set_attr "op_type" "RI")
+ (set_attr "type" "branch")
(set (attr "length")
(cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
(const_int 4)
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
- (set_attr "atype" "mem")])
+ (set_attr "type" "branch")
+ (set_attr "atype" "agen")])
;;
abort ();
}"
[(set_attr "op_type" "RI")
+ (set_attr "type" "branch")
(set (attr "length")
(cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
(const_int 4)
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
- (set_attr "atype" "mem")])
+ (set_attr "type" "branch")
+ (set_attr "atype" "agen")])
;;
;;- Trap instructions.
[(trap_if (const_int 1) (const_int 0))]
""
"j\\t.+2"
- [(set_attr "op_type" "RX")])
+ [(set_attr "op_type" "RX")
+ (set_attr "type" "branch")])
(define_expand "conditional_trap"
[(set (match_dup 2) (match_dup 3))
(const_int 0))]
""
"j%C0\\t.+2";
- [(set_attr "op_type" "RX")])
+ [(set_attr "op_type" "RI")
+ (set_attr "type" "branch")])
;;
;;- Loop instructions.
abort ();
}"
[(set_attr "op_type" "RI")
+ (set_attr "type" "branch")
(set (attr "length")
(cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
(const_int 4)
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
- (set_attr "atype" "mem")])
+ (set_attr "type" "branch")
+ (set_attr "atype" "agen")])
(define_split
[(set (pc)
abort ();
}"
[(set_attr "op_type" "RI")
+ (set_attr "type" "branch")
(set (attr "length")
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
(const_int 4) (const_int 12)))])
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RRE") (const_string "RXE")))
- (set_attr "atype" "mem")])
+ (set_attr "type" "branch")
+ (set_attr "atype" "agen")])
(define_split
[(set (pc)
abort ();
}"
[(set_attr "op_type" "RI")
+ (set_attr "type" "branch")
(set (attr "length")
(cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
(const_int 4)
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
- (set_attr "atype" "mem")])
+ (set_attr "type" "branch")
+ (set_attr "atype" "agen")])
;
; casesi instruction pattern(s).
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
- (set_attr "atype" "mem")])
+ (set_attr "type" "branch")
+ (set_attr "atype" "agen")])
(define_expand "casesi"
[(match_operand:SI 0 "general_operand" "")
"basr\\t%2,%0"
[(set_attr "op_type" "RR")
(set_attr "type" "jsr")
- (set_attr "atype" "mem")])
+ (set_attr "atype" "agen")])
(define_insn "basr_31"
[(call (mem:QI (match_operand:SI 0 "register_operand" "a"))
"basr\\t%2,%0"
[(set_attr "op_type" "RR")
(set_attr "type" "jsr")
- (set_attr "atype" "mem")])
+ (set_attr "atype" "agen")])
(define_insn "bas_64"
[(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
"TARGET_64BIT"
"bas\\t%2,%a0"
[(set_attr "op_type" "RX")
- (set_attr "type" "jsr")
- (set_attr "atype" "mem")])
+ (set_attr "type" "jsr")])
(define_insn "bas_31"
[(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
"!TARGET_64BIT"
"bas\\t%2,%a0"
[(set_attr "op_type" "RX")
- (set_attr "type" "jsr")
- (set_attr "atype" "mem")])
+ (set_attr "type" "jsr")])
;
"TARGET_64BIT"
"basr\\t%3,%1"
[(set_attr "op_type" "RR")
- (set_attr "type" "jsr")])
+ (set_attr "type" "jsr")
+ (set_attr "atype" "agen")])
(define_insn "basr_r_31"
[(set (match_operand 0 "register_operand" "=df")
"basr\\t%3,%1"
[(set_attr "op_type" "RR")
(set_attr "type" "jsr")
- (set_attr "atype" "mem")])
+ (set_attr "atype" "agen")])
(define_insn "bas_r_64"
[(set (match_operand 0 "register_operand" "=df")
"TARGET_64BIT"
"bas\\t%3,%a1"
[(set_attr "op_type" "RX")
- (set_attr "type" "jsr")
- (set_attr "atype" "mem")])
+ (set_attr "type" "jsr")])
(define_insn "bas_r_31"
[(set (match_operand 0 "register_operand" "=df")
"!TARGET_64BIT"
"bas\\t%3,%a1"
[(set_attr "op_type" "RX")
- (set_attr "type" "jsr")
- (set_attr "atype" "mem")])
+ (set_attr "type" "jsr")])
;;
"TARGET_64BIT"
"larl\\t%0,%1"
[(set_attr "op_type" "RIL")
- (set_attr "type" "la")])
+ (set_attr "type" "larl")])
(define_insn "reload_anchor"
[(set (match_operand:SI 0 "register_operand" "=a")
"l\\t%0,0(%1)\;la\\t%0,0(%0,%1)"
[(set_attr "op_type" "NN")
(set_attr "type" "la")
+ (set_attr "atype" "agen")
(set_attr "length" "8")])
(define_insn "pool"
"br\\t%0"
[(set_attr "op_type" "RR")
(set_attr "type" "jsr")
- (set_attr "atype" "mem")])
+ (set_attr "atype" "agen")])
(define_insn "*return_di"
[(return)
"br\\t%0"
[(set_attr "op_type" "RR")
(set_attr "type" "jsr")
- (set_attr "atype" "mem")])
+ (set_attr "atype" "agen")])
-
-(define_insn "lit"
- [(set (reg 13) (pc))
- (unspec_volatile [(const_int 0)] 200)]
+(define_insn "literal_pool_31"
+ [(unspec_volatile [(const_int 0)] 300)
+ (set (match_operand:SI 0 "register_operand" "=a")
+ (label_ref (match_operand 1 "" "")))
+ (use (label_ref (match_operand 2 "" "")))]
""
"*
{
- s390_output_constant_pool (asm_out_file);
- return \"\";
+ if (s390_nr_constants) {
+ output_asm_insn (\"bras\\t%0,%2\", operands);
+ s390_output_constant_pool (operands[1], operands[2]);
+ }
+ return \"\";
}"
[(set_attr "op_type" "NN")
- (set_attr "length" "6")
- (set_attr "type" "integer")])
+ (set_attr "type" "larl")])
+(define_insn "literal_pool_64"
+ [(unspec_volatile [(const_int 0)] 300)
+ (set (match_operand:DI 0 "register_operand" "=a")
+ (label_ref (match_operand 1 "" "")))
+ (use (label_ref (match_operand 2 "" "")))]
+ ""
+ "*
+{
+ if (s390_nr_constants) {
+ output_asm_insn (\"larl\\t%0,%1\", operands);
+ s390_output_constant_pool (operands[1], operands[2]);
+ }
+ return \"\";
+}"
+ [(set_attr "op_type" "NN")
+ (set_attr "type" "larl")])
projects / gcc.git / blobdiff