;;- Machine description for GNU compiler -- S/390 / zSeries version.
-;; Copyright (C) 1999-2015 Free Software Foundation, Inc.
+;; Copyright (C) 1999-2017 Free Software Foundation, Inc.
;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
;; Ulrich Weigand (uweigand@de.ibm.com) and
;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
; Copy CC as is into the lower 2 bits of an integer register
UNSPEC_CC_TO_INT
+ ; The right hand side of an setmem
+ UNSPEC_REPLICATE_BYTE
+
; GOT/PLT and lt-relative accesses
UNSPEC_LTREL_OFFSET
UNSPEC_LTREL_BASE
UNSPEC_SP_SET
UNSPEC_SP_TEST
+ ; Split stack support
+ UNSPEC_STACK_CHECK
+
; Test Data Class (TDC)
UNSPEC_TDC_INSN
UNSPEC_FPINT_CEIL
UNSPEC_FPINT_NEARBYINT
UNSPEC_FPINT_RINT
- ])
+
+ UNSPEC_LCBB
+
+ ; Vector
+ UNSPEC_VEC_SMULT_HI
+ UNSPEC_VEC_UMULT_HI
+ UNSPEC_VEC_SMULT_LO
+ UNSPEC_VEC_SMULT_EVEN
+ UNSPEC_VEC_UMULT_EVEN
+ UNSPEC_VEC_SMULT_ODD
+ UNSPEC_VEC_UMULT_ODD
+
+ UNSPEC_VEC_VMAL
+ UNSPEC_VEC_VMAH
+ UNSPEC_VEC_VMALH
+ UNSPEC_VEC_VMAE
+ UNSPEC_VEC_VMALE
+ UNSPEC_VEC_VMAO
+ UNSPEC_VEC_VMALO
+
+ UNSPEC_VEC_GATHER
+ UNSPEC_VEC_EXTRACT
+ UNSPEC_VEC_INSERT_AND_ZERO
+ UNSPEC_VEC_LOAD_BNDRY
+ UNSPEC_VEC_LOAD_LEN
+ UNSPEC_VEC_MERGEH
+ UNSPEC_VEC_MERGEL
+ UNSPEC_VEC_PACK
+ UNSPEC_VEC_PACK_SATURATE
+ UNSPEC_VEC_PACK_SATURATE_CC
+ UNSPEC_VEC_PACK_SATURATE_GENCC
+ UNSPEC_VEC_PACK_UNSIGNED_SATURATE
+ UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC
+ UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC
+ UNSPEC_VEC_PERM
+ UNSPEC_VEC_PERMI
+ UNSPEC_VEC_EXTEND
+ UNSPEC_VEC_STORE_LEN
+ UNSPEC_VEC_UNPACKH
+ UNSPEC_VEC_UNPACKH_L
+ UNSPEC_VEC_UNPACKL
+ UNSPEC_VEC_UNPACKL_L
+ UNSPEC_VEC_ADDC
+ UNSPEC_VEC_ADDE_U128
+ UNSPEC_VEC_ADDEC_U128
+ UNSPEC_VEC_AVG
+ UNSPEC_VEC_AVGU
+ UNSPEC_VEC_CHECKSUM
+ UNSPEC_VEC_GFMSUM
+ UNSPEC_VEC_GFMSUM_128
+ UNSPEC_VEC_GFMSUM_ACCUM
+ UNSPEC_VEC_GFMSUM_ACCUM_128
+ UNSPEC_VEC_SET
+
+ UNSPEC_VEC_VSUMG
+ UNSPEC_VEC_VSUMQ
+ UNSPEC_VEC_VSUM
+ UNSPEC_VEC_RL_MASK
+ UNSPEC_VEC_SLL
+ UNSPEC_VEC_SLB
+ UNSPEC_VEC_SLDB
+ UNSPEC_VEC_SRAL
+ UNSPEC_VEC_SRAB
+ UNSPEC_VEC_SRL
+ UNSPEC_VEC_SRLB
+
+ UNSPEC_VEC_SUBC
+ UNSPEC_VEC_SUBE_U128
+ UNSPEC_VEC_SUBEC_U128
+
+ UNSPEC_VEC_TEST_MASK
+
+ UNSPEC_VEC_VFAE
+ UNSPEC_VEC_VFAECC
+
+ UNSPEC_VEC_VFEE
+ UNSPEC_VEC_VFEECC
+ UNSPEC_VEC_VFENE
+ UNSPEC_VEC_VFENECC
+
+ UNSPEC_VEC_VISTR
+ UNSPEC_VEC_VISTRCC
+
+ UNSPEC_VEC_VSTRC
+ UNSPEC_VEC_VSTRCCC
+
+ UNSPEC_VEC_VCDGB
+ UNSPEC_VEC_VCDLGB
+
+ UNSPEC_VEC_VCGDB
+ UNSPEC_VEC_VCLGDB
+
+ UNSPEC_VEC_VFIDB
+
+ UNSPEC_VEC_VLDEB
+ UNSPEC_VEC_VLEDB
+
+ UNSPEC_VEC_VFTCIDB
+ UNSPEC_VEC_VFTCIDBCC
+])
;;
;; UNSPEC_VOLATILE usage
; Set and get floating point control register
UNSPECV_SFPC
UNSPECV_EFPC
+
+ ; Split stack support
+ UNSPECV_SPLIT_STACK_CALL
+ UNSPECV_SPLIT_STACK_DATA
+
+ UNSPECV_OSC_BREAK
])
;;
(BASE_REGNUM 13)
; Return address register.
(RETURN_REGNUM 14)
+ ; Stack pointer register.
+ (STACK_REGNUM 15)
; Condition code register.
(CC_REGNUM 33)
; Thread local storage pointer register.
[
; General purpose registers
(GPR0_REGNUM 0)
+ (GPR1_REGNUM 1)
+ (GPR2_REGNUM 2)
+ (GPR6_REGNUM 6)
; Floating point registers.
(FPR0_REGNUM 16)
(FPR1_REGNUM 20)
(FPR13_REGNUM 30)
(FPR14_REGNUM 27)
(FPR15_REGNUM 31)
+ (VR0_REGNUM 16)
+ (VR16_REGNUM 38)
+ (VR23_REGNUM 45)
+ (VR24_REGNUM 46)
+ (VR31_REGNUM 53)
])
+; Rounding modes for binary floating point numbers
+(define_constants
+ [(BFP_RND_CURRENT 0)
+ (BFP_RND_NEAREST_TIE_AWAY_FROM_0 1)
+ (BFP_RND_PREP_FOR_SHORT_PREC 3)
+ (BFP_RND_NEAREST_TIE_TO_EVEN 4)
+ (BFP_RND_TOWARD_0 5)
+ (BFP_RND_TOWARD_INF 6)
+ (BFP_RND_TOWARD_MINF 7)])
+
+; Rounding modes for decimal floating point numbers
+; 1-7 were introduced with the floating point extension facility
+; available with z196
+; With these rounding modes (1-7) a quantum exception might occur
+; which is suppressed for the other modes.
+(define_constants
+ [(DFP_RND_CURRENT 0)
+ (DFP_RND_NEAREST_TIE_AWAY_FROM_0_QUANTEXC 1)
+ (DFP_RND_CURRENT_QUANTEXC 2)
+ (DFP_RND_PREP_FOR_SHORT_PREC_QUANTEXC 3)
+ (DFP_RND_NEAREST_TIE_TO_EVEN_QUANTEXC 4)
+ (DFP_RND_TOWARD_0_QUANTEXC 5)
+ (DFP_RND_TOWARD_INF_QUANTEXC 6)
+ (DFP_RND_TOWARD_MINF_QUANTEXC 7)
+ (DFP_RND_NEAREST_TIE_TO_EVEN 8)
+ (DFP_RND_TOWARD_0 9)
+ (DFP_RND_TOWARD_INF 10)
+ (DFP_RND_TOWARD_MINF 11)
+ (DFP_RND_NEAREST_TIE_AWAY_FROM_0 12)
+ (DFP_RND_NEAREST_TIE_TO_0 13)
+ (DFP_RND_AWAY_FROM_0 14)
+ (DFP_RND_PREP_FOR_SHORT_PREC 15)])
+
;;
;; PFPO GPR0 argument format
;;
;; Used to determine defaults for length and other attribute values.
(define_attr "op_type"
- "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS"
+ "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX"
(const_string "NN"))
;; Instruction type attribute used for scheduling.
;; reg: Instruction does not use the agen unit
(define_attr "atype" "agen,reg"
- (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR")
+ (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF")
(const_string "reg")
(const_string "agen")))
;; Length in bytes.
(define_attr "length" ""
- (cond [(eq_attr "op_type" "E,RR") (const_int 2)
- (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)]
+ (cond [(eq_attr "op_type" "E,RR") (const_int 2)
+ (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF") (const_int 4)]
(const_int 6)))
(const (symbol_ref "s390_tune_attr")))
(define_attr "cpu_facility"
- "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vec"
+ "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vx,z13"
(const_string "standard"))
(define_attr "enabled" ""
(match_test "TARGET_ZEC12"))
(const_int 1)
- (and (eq_attr "cpu_facility" "vec")
+ (and (eq_attr "cpu_facility" "vx")
(match_test "TARGET_VX"))
- (const_int 1)]
+ (const_int 1)
+
+ (and (eq_attr "cpu_facility" "z13")
+ (match_test "TARGET_Z13"))
+ (const_int 1)
+ ]
(const_int 0)))
;; Pipeline description for z900. For lack of anything better,
;; Pipeline description for zEC12
(include "2827.md")
+;; Pipeline description for z13
+(include "2964.md")
+
;; Predicates
(include "predicates.md")
;; Iterators
+(define_mode_iterator ALL [TI DI SI HI QI TF DF SF TD DD SD V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF])
+
;; These mode iterators allow floating point patterns to be generated from the
;; same template.
(define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")
(SD "TARGET_HARD_DFP")])
(define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")])
-(define_mode_iterator FPALL [TF DF SF TD DD SD])
(define_mode_iterator BFP [TF DF SF])
(define_mode_iterator DFP [TD DD])
(define_mode_iterator DFP_ALL [TD DD SD])
;; This mode iterator allows the integer patterns to be defined from the
;; same template.
(define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
-(define_mode_iterator INTALL [TI DI SI HI QI])
(define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI])
+(define_mode_iterator SINT [SI HI QI])
;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
;; the same template.
;; fp register operands. The following attributes allow to merge the bfp and
;; dfp variants in a single insn definition.
-;; This attribute is used to set op_type accordingly.
-(define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
- (DD "RRR") (SD "RRR")])
-
-;; This attribute is used in the operand constraint list in order to have the
-;; first and the second operand match for bfp modes.
-(define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
-
-;; This attribute is used in the operand list of the instruction to have an
-;; additional operand for the dfp instructions.
-(define_mode_attr op1 [(TF "") (DF "") (SF "")
- (TD "%1,") (DD "%1,") (SD "%1,")])
-
+;; These mode attributes are supposed to be used in the `enabled' insn
+;; attribute to disable certain alternatives for certain modes.
+(define_mode_attr nBFP [(TF "0") (DF "0") (SF "0") (TD "*") (DD "*") (DD "*")])
+(define_mode_attr nDFP [(TF "*") (DF "*") (SF "*") (TD "0") (DD "0") (DD "0")])
+(define_mode_attr DSF [(TF "0") (DF "*") (SF "*") (TD "0") (DD "0") (SD "0")])
+(define_mode_attr DFDI [(TF "0") (DF "*") (SF "0")
+ (TD "0") (DD "0") (DD "0")
+ (TI "0") (DI "*") (SI "0")])
;; This attribute is used in the operand constraint list
;; for instructions dealing with the sign bit of 32 or 64bit fp values.
;; target operand uses the same fp register.
(define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
-;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
-;; This is used to disable the memory alternative in TFmode patterns.
-(define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
-
;; This attribute adds b for bfp instructions and t for dfp instructions and is used
;; within instruction mnemonics.
(define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
;; In place of GET_MODE_BITSIZE (<MODE>mode)
(define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
+;; 64 - bitsize
+(define_mode_attr bitoff [(DI "0") (SI "32") (HI "48") (QI "56")])
+(define_mode_attr bitoff_plus [(DI "") (SI "32+") (HI "48+") (QI "56+")])
+
+;; In place of GET_MODE_SIZE (<MODE>mode)
+(define_mode_attr modesize [(DI "8") (SI "4")])
;; Allow return and simple_return to be defined from a single template.
(define_code_iterator ANY_RETURN [return simple_return])
+
+
+; Condition code modes generated by vector fp comparisons. These will
+; be used also in single element mode.
+(define_mode_iterator VFCMP [CCVEQ CCVFH CCVFHE])
+; Used with VFCMP to expand part of the mnemonic
+; For fp we have a mismatch: eq in the insn name - e in asm
+(define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")])
+(define_mode_attr insn_cmp [(CCVEQ "eq") (CCVIH "h") (CCVIHU "hl") (CCVFH "h") (CCVFHE "he")])
+
+;; Subst pattern definitions
+(include "subst.md")
+
+(include "vector.md")
+
;;
;;- Compare instructions.
;;
tm\t%S0,%b1
tmy\t%S0,%b1"
[(set_attr "op_type" "SI,SIY")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_super,z10_super")])
(define_insn "*tmdi_reg"
(compare
(ashiftrt:DI
(ashift:DI
- (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
+ (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,T") 0)
(const_int 32)) (const_int 32))
(match_operand:DI 1 "const0_operand" "")))
(set (match_operand:DI 2 "register_operand" "=d,d")
; ltr, lt, ltgr, ltg
(define_insn "*tst<mode>_extimm"
[(set (reg CC_REGNUM)
- (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
+ (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T")
(match_operand:GPR 1 "const0_operand" "")))
(set (match_operand:GPR 2 "register_operand" "=d,d")
(match_dup 0))]
; ltr, lt, ltgr, ltg
(define_insn "*tst<mode>_cconly_extimm"
[(set (reg CC_REGNUM)
- (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
+ (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T")
(match_operand:GPR 1 "const0_operand" "")))
(clobber (match_scratch:GPR 2 "=X,d"))]
"s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
icm\t%2,15,%S0
icmy\t%2,15,%S0"
[(set_attr "op_type" "RR,RS,RSY")
+ (set_attr "cpu_facility" "*,*,longdisp")
(set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
(define_insn "*tstsi_cconly"
icm\t%2,15,%S0
icmy\t%2,15,%S0"
[(set_attr "op_type" "RR,RS,RSY")
+ (set_attr "cpu_facility" "*,*,longdisp")
(set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
(define_insn "*tstdi_cconly_31"
icmy\t%2,<icm_lo>,%S0
tml\t%0,<max_uint>"
[(set_attr "op_type" "RS,RSY,RI")
+ (set_attr "cpu_facility" "*,longdisp,*")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
(define_insn "*tsthiCCT_cconly"
icmy\t%2,3,%S0
tml\t%0,65535"
[(set_attr "op_type" "RS,RSY,RI")
+ (set_attr "cpu_facility" "*,longdisp,*")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
(define_insn "*tstqiCCT_cconly"
cliy\t%S0,0
tml\t%0,255"
[(set_attr "op_type" "SI,SIY,RI")
+ (set_attr "cpu_facility" "*,longdisp,*")
(set_attr "z10prop" "z10_super,z10_super,z10_super")])
(define_insn "*tst<mode>"
icm\t%2,<icm_lo>,%S0
icmy\t%2,<icm_lo>,%S0"
[(set_attr "op_type" "RS,RSY")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1")])
(define_insn "*tst<mode>_cconly"
icm\t%2,<icm_lo>,%S0
icmy\t%2,<icm_lo>,%S0"
[(set_attr "op_type" "RS,RSY")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1")])
(define_insn "*cmpdi_cct"
[(set (reg CC_REGNUM)
(compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
- (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
+ (match_operand:DI 1 "general_operand" "d,K,Os,T,BQ")))]
"s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
"@
cgr\t%0,%1
cy\t%0,%1
#"
[(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
+ (set_attr "cpu_facility" "*,*,*,*,longdisp,*")
(set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
; Compare (signed) instructions
(define_insn "*cmpdi_ccs_sign"
[(set (reg CC_REGNUM)
(compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
- "d,RT,b"))
+ "d,T,b"))
(match_operand:DI 0 "register_operand" "d, d,d")))]
"s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
"@
chy\t%0,%1
chrl\t%0,%1"
[(set_attr "op_type" "RX,RXY,RIL")
- (set_attr "cpu_facility" "*,*,z10")
+ (set_attr "cpu_facility" "*,longdisp,z10")
(set_attr "type" "*,*,larl")
(set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
(define_insn "*cmpdi_ccs_signhi_rl"
[(set (reg CC_REGNUM)
- (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
+ (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "T,b"))
(match_operand:GPR 0 "register_operand" "d,d")))]
"s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
"@
c<y>\t%0,%1
c<g>rl\t%0,%1"
[(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
- (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
+ (set_attr "cpu_facility" "*,*,z10,extimm,*,longdisp,z10")
(set_attr "type" "*,*,*,*,*,*,larl")
(set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
(define_insn "*cmpdi_ccu_zero"
[(set (reg CC_REGNUM)
(compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
- "d,RT,b"))
- (match_operand:DI 0 "register_operand" "d, d,d")))]
+ "d,T,b"))
+ (match_operand:DI 0 "register_operand" "d,d,d")))]
"s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
"@
clgfr\t%0,%1
(define_insn "*cmpdi_ccu"
[(set (reg CC_REGNUM)
(compare (match_operand:DI 0 "nonimmediate_operand"
- "d, d,d,Q, d, Q,BQ")
+ "d, d,d,Q,d, Q,BQ")
(match_operand:DI 1 "general_operand"
- "d,Op,b,D,RT,BQ,Q")))]
+ "d,Op,b,D,T,BQ,Q")))]
"s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
"@
clgr\t%0,%1
#
#"
[(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
- (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
+ (set_attr "cpu_facility" "*,extimm,z10,z10,*,longdisp,*,*")
(set_attr "type" "*,*,larl,*,*,*,*,*")
(set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
#
#"
[(set_attr "op_type" "RS,RSY,SIL,SS,SS")
- (set_attr "cpu_facility" "*,*,z10,*,*")
+ (set_attr "cpu_facility" "*,longdisp,z10,*,*")
(set_attr "z10prop" "*,*,z10_super,*,*")])
(define_insn "*cmpqi_ccu"
#
#"
[(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
+ (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*")
(set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
; (TF|DF|SF|TD|DD|SD) instructions
+
+; load and test instructions turn SNaN into QNaN what is not
+; acceptable if the target will be used afterwards. On the other hand
+; they are quite convenient for implementing comparisons with 0.0. So
+; try to enable them via splitter if the value isn't needed anymore.
+
; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
(define_insn "*cmp<mode>_ccs_0"
[(set (reg CC_REGNUM)
- (compare (match_operand:FP 0 "register_operand" "f")
- (match_operand:FP 1 "const0_operand" "")))]
+ (compare (match_operand:FP 0 "register_operand" "f")
+ (match_operand:FP 1 "const0_operand" "")))
+ (clobber (match_operand:FP 2 "register_operand" "=0"))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
"lt<xde><bt>r\t%0,%0"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimp<mode>")])
+(define_split
+ [(set (match_operand 0 "cc_reg_operand")
+ (compare (match_operand:FP 1 "register_operand")
+ (match_operand:FP 2 "const0_operand")))]
+ "TARGET_HARD_FLOAT && REG_P (operands[1]) && dead_or_set_p (insn, operands[1])"
+ [(parallel
+ [(set (match_dup 0) (match_dup 3))
+ (clobber (match_dup 1))])]
+ {
+ /* s390_match_ccmode requires the compare to have the same CC mode
+ as the CC destination register. */
+ operands[3] = gen_rtx_COMPARE (GET_MODE (operands[0]),
+ operands[1], operands[2]);
+ })
+
+
; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb
(define_insn "*cmp<mode>_ccs"
[(set (reg CC_REGNUM)
(compare (match_operand:FP 0 "register_operand" "f,f")
- (match_operand:FP 1 "general_operand" "f,<Rf>")))]
+ (match_operand:FP 1 "general_operand" "f,R")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
"@
c<xde><bt>r\t%0,%1
c<xde>b\t%0,%1"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimp<mode>")])
-
+ (set_attr "type" "fsimp<mode>")
+ (set_attr "enabled" "*,<DSF>")])
+
+; wfcedbs, wfchdbs, wfchedbs
+(define_insn "*vec_cmp<insn_cmp>df_cconly"
+ [(set (reg:VFCMP CC_REGNUM)
+ (compare:VFCMP (match_operand:DF 0 "register_operand" "v")
+ (match_operand:DF 1 "register_operand" "v")))
+ (clobber (match_scratch:V2DI 2 "=v"))]
+ "TARGET_VX && TARGET_HARD_FLOAT"
+ "wfc<asm_fcmp>dbs\t%v2,%v0,%v1"
+ [(set_attr "op_type" "VRR")])
; Compare and Branch instructions
; movti instruction pattern(s).
;
+; FIXME: More constants are possible by enabling jxx, jyy constraints
+; for TImode (use double-int for the calculations)
(define_insn "movti"
- [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
- (match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
+ [(set (match_operand:TI 0 "nonimmediate_operand" "=d,S,v, v, v,v,d,v,R, d,o")
+ (match_operand:TI 1 "general_operand" " S,d,v,j00,jm1,d,v,R,v,dPT,d"))]
"TARGET_ZARCH"
"@
lmg\t%0,%N0,%S1
stmg\t%1,%N1,%S0
+ vlr\t%v0,%v1
+ vzero\t%v0
+ vone\t%v0
+ vlvgp\t%v0,%1,%N1
+ #
+ vl\t%v0,%1
+ vst\t%v1,%0
#
#"
- [(set_attr "op_type" "RSY,RSY,*,*")
- (set_attr "type" "lm,stm,*,*")])
+ [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*")
+ (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*")
+ (set_attr "cpu_facility" "*,*,vx,vx,vx,vx,vx,vx,vx,*,*")])
(define_split
[(set (match_operand:TI 0 "nonimmediate_operand" "")
(match_operand:TI 1 "general_operand" ""))]
"TARGET_ZARCH && reload_completed
+ && !s_operand (operands[0], TImode)
+ && !s_operand (operands[1], TImode)
&& s390_split_ok_p (operands[0], operands[1], TImode, 0)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
[(set (match_operand:TI 0 "nonimmediate_operand" "")
(match_operand:TI 1 "general_operand" ""))]
"TARGET_ZARCH && reload_completed
+ && !s_operand (operands[0], TImode)
+ && !s_operand (operands[1], TImode)
&& s390_split_ok_p (operands[0], operands[1], TImode, 1)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
operands[5] = operand_subword (operands[1], 0, 0, TImode);
})
+; Use part of the TImode target reg to perform the address
+; calculation. If the TImode value is supposed to be copied into a VR
+; this splitter is not necessary.
(define_split
[(set (match_operand:TI 0 "register_operand" "")
(match_operand:TI 1 "memory_operand" ""))]
"TARGET_ZARCH && reload_completed
+ && !VECTOR_REG_P (operands[0])
&& !s_operand (operands[1], VOIDmode)"
[(set (match_dup 0) (match_dup 1))]
{
})
+; Split a VR -> GPR TImode move into 2 vector load GR from VR element.
+; For the higher order bits we do simply a DImode move while the
+; second part is done via vec extract. Both will end up as vlgvg.
+(define_split
+ [(set (match_operand:TI 0 "register_operand" "")
+ (match_operand:TI 1 "register_operand" ""))]
+ "TARGET_VX && reload_completed
+ && GENERAL_REG_P (operands[0])
+ && VECTOR_REG_P (operands[1])"
+ [(set (match_dup 2) (match_dup 4))
+ (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)]
+ UNSPEC_VEC_EXTRACT))]
+{
+ operands[2] = operand_subword (operands[0], 0, 0, TImode);
+ operands[3] = operand_subword (operands[0], 1, 0, TImode);
+ operands[4] = gen_rtx_REG (DImode, REGNO (operands[1]));
+ operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1]));
+})
+
;
; Patterns used for secondary reloads
;
; Unfortunately there is no such variant for QI, TI and FP mode moves.
; These patterns are also used for unaligned SI and DI accesses.
-(define_expand "reload<INTALL:mode><P:mode>_tomem_z10"
- [(parallel [(match_operand:INTALL 0 "memory_operand" "")
- (match_operand:INTALL 1 "register_operand" "=d")
- (match_operand:P 2 "register_operand" "=&a")])]
+(define_expand "reload<ALL:mode><P:mode>_tomem_z10"
+ [(parallel [(match_operand:ALL 0 "memory_operand" "")
+ (match_operand:ALL 1 "register_operand" "=d")
+ (match_operand:P 2 "register_operand" "=&a")])]
"TARGET_Z10"
{
s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
DONE;
})
-(define_expand "reload<INTALL:mode><P:mode>_toreg_z10"
- [(parallel [(match_operand:INTALL 0 "register_operand" "=d")
- (match_operand:INTALL 1 "memory_operand" "")
- (match_operand:P 2 "register_operand" "=a")])]
- "TARGET_Z10"
-{
- s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
- DONE;
-})
-
-(define_expand "reload<FPALL:mode><P:mode>_tomem_z10"
- [(parallel [(match_operand:FPALL 0 "memory_operand" "")
- (match_operand:FPALL 1 "register_operand" "=d")
- (match_operand:P 2 "register_operand" "=&a")])]
- "TARGET_Z10"
-{
- s390_reload_symref_address (operands[1], operands[0], operands[2], 1);
- DONE;
-})
-
-(define_expand "reload<FPALL:mode><P:mode>_toreg_z10"
- [(parallel [(match_operand:FPALL 0 "register_operand" "=d")
- (match_operand:FPALL 1 "memory_operand" "")
- (match_operand:P 2 "register_operand" "=a")])]
+(define_expand "reload<ALL:mode><P:mode>_toreg_z10"
+ [(parallel [(match_operand:ALL 0 "register_operand" "=d")
+ (match_operand:ALL 1 "memory_operand" "")
+ (match_operand:P 2 "register_operand" "=a")])]
"TARGET_Z10"
{
s390_reload_symref_address (operands[0], operands[1], operands[2], 0);
DONE;
})
-; Handles assessing a non-offsetable memory address
+; Not all the indirect memory access instructions support the full
+; format (long disp + index + base). So whenever a move from/to such
+; an address is required and the instruction cannot deal with it we do
+; a load address into a scratch register first and use this as the new
+; base register.
+; This in particular is used for:
+; - non-offsetable memory accesses for multiword moves
+; - full vector reg moves with long displacements
-(define_expand "reload<mode>_nonoffmem_in"
+(define_expand "reload<mode>_la_in"
[(parallel [(match_operand 0 "register_operand" "")
(match_operand 1 "" "")
(match_operand:P 2 "register_operand" "=&a")])]
DONE;
})
-(define_expand "reload<mode>_nonoffmem_out"
+(define_expand "reload<mode>_la_out"
[(parallel [(match_operand 0 "" "")
(match_operand 1 "register_operand" "")
(match_operand:P 2 "register_operand" "=&a")])]
(define_insn "*movdi_64"
[(set (match_operand:DI 0 "nonimmediate_operand"
- "=d,d,d,d,d,d,d,d,f,d,d,d,d,d,
- RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t")
+ "=d, d, d, d, d, d, d, d,f,d,d,d,d,d,T,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d,v,R")
(match_operand:DI 1 "general_operand"
- "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
- d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
+ " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,T,d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,R,v"))]
"TARGET_ZARCH"
"@
lghi\t%0,%h1
#
#
stam\t%1,%N1,%S0
- lam\t%0,%N0,%S1"
+ lam\t%0,%N0,%S1
+ vleig\t%v0,%h1,0
+ vlr\t%v0,%v1
+ vlvgg\t%v0,%1,0
+ vlgvg\t%0,%v1,0
+ vleg\t%v0,%1,0
+ vsteg\t%v1,%0,0"
[(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
- RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS")
+ RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS,VRX,VRX")
(set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
- floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,
- *,*")
+ floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*,
+ *,*,*,*,*,*,*")
(set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
z10,*,*,*,*,*,longdisp,*,longdisp,
- z10,z10,*,*,*,*")
+ z10,z10,*,*,*,*,vx,vx,vx,vx,vx,vx")
(set_attr "z10prop" "z10_fwd_A1,
z10_fwd_E1,
z10_fwd_E1,
*,
*,
*,
- *")
+ *,*,*,*,*,*,*")
])
(define_split
(define_insn "*movdi_31"
[(set (match_operand:DI 0 "nonimmediate_operand"
- "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
+ "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
(match_operand:DI 1 "general_operand"
- " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
+ " Q,S,d,d,dPT,d, *f, R, T,*f,*f,b"))]
"!TARGET_ZARCH"
"@
lm\t%0,%N0,%S1
#"
[(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
(set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
- (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
+ (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*,*,*,longdisp,*,longdisp,z10")])
; For a load from a symbol ref we can use one of the target registers
; together with larl to load the address.
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(match_operand:DI 1 "general_operand" ""))]
"!TARGET_ZARCH && reload_completed
+ && !s_operand (operands[0], DImode)
+ && !s_operand (operands[1], DImode)
&& s390_split_ok_p (operands[0], operands[1], DImode, 0)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(match_operand:DI 1 "general_operand" ""))]
"!TARGET_ZARCH && reload_completed
+ && !s_operand (operands[0], DImode)
+ && !s_operand (operands[1], DImode)
&& s390_split_ok_p (operands[0], operands[1], DImode, 1)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
(define_insn "*la_64"
[(set (match_operand:DI 0 "register_operand" "=d,d")
- (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
+ (match_operand:QI 1 "address_operand" "ZR,ZT"))]
"TARGET_64BIT"
"@
la\t%0,%a1
lay\t%0,%a1"
[(set_attr "op_type" "RX,RXY")
(set_attr "type" "la")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
(define_peephole2
(define_insn "*movsi_zarch"
[(set (match_operand:SI 0 "nonimmediate_operand"
- "=d,d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t")
+ "=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d,v,R")
(match_operand:SI 1 "general_operand"
- "K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,d,K,Q"))]
+ " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,R,v"))]
"TARGET_ZARCH"
"@
lhi\t%0,%h1
ly\t%0,%1
st\t%1,%0
sty\t%1,%0
+ ldr\t%0,%1
ler\t%0,%1
+ lde\t%0,%1
le\t%0,%1
ley\t%0,%1
ste\t%1,%0
stam\t%1,%1,%S0
strl\t%1,%0
mvhi\t%0,%1
- lam\t%0,%0,%S1"
+ lam\t%0,%0,%S1
+ vleif\t%v0,%h1,0
+ vlr\t%v0,%v1
+ vlvgf\t%v0,%1,0
+ vlgvf\t%0,%v1,0
+ vlef\t%v0,%1,0
+ vstef\t%v1,%0,0"
[(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
- RR,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS")
+ RR,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX")
(set_attr "type" "*,
*,
*,
floadsf,
floadsf,
floadsf,
+ floadsf,
+ floadsf,
fstoresf,
fstoresf,
*,
*,
larl,
*,
- *")
+ *,*,*,*,*,*,*")
(set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
- *,*,longdisp,*,longdisp,*,*,*,z10,z10,*")
+ vx,*,vx,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vx,vx,vx,vx,vx,vx")
(set_attr "z10prop" "z10_fwd_A1,
z10_fwd_E1,
z10_fwd_E1,
*,
*,
*,
+ *,
+ *,
z10_super_E1,
z10_super,
*,
z10_rec,
z10_super,
- *")])
+ *,*,*,*,*,*,*")])
(define_insn "*movsi_esa"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t")
- (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q"))]
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t")
+ (match_operand:SI 1 "general_operand" "K,d,R,d, *f, *f, R, R,*f,t,d,t,Q"))]
"!TARGET_ZARCH"
"@
lhi\t%0,%h1
lr\t%0,%1
l\t%0,%1
st\t%1,%0
+ ldr\t%0,%1
ler\t%0,%1
+ lde\t%0,%1
le\t%0,%1
ste\t%1,%0
ear\t%0,%1
sar\t%0,%1
stam\t%1,%1,%S0
lam\t%0,%0,%S1"
- [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS")
- (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*")
- (set_attr "z10prop" "z10_fwd_A1,
- z10_fr_E1,
- z10_fwd_A3,
- z10_rec,
- *,
- *,
- *,
- z10_super_E1,
- z10_super,
- *,
- *")
+ [(set_attr "op_type" "RI,RR,RX,RX,RR,RR,RXE,RX,RX,RRE,RRE,RS,RS")
+ (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*")
+ (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1,
+ z10_super,*,*")
+ (set_attr "cpu_facility" "*,*,*,*,vx,*,vx,*,*,*,*,*,*")
])
(define_peephole2
(define_insn "*la_31"
[(set (match_operand:SI 0 "register_operand" "=d,d")
- (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
+ (match_operand:QI 1 "address_operand" "ZR,ZT"))]
"!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
"@
la\t%0,%a1
lay\t%0,%a1"
[(set_attr "op_type" "RX,RXY")
(set_attr "type" "la")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
(define_peephole2
(define_insn "*la_31_and"
[(set (match_operand:SI 0 "register_operand" "=d,d")
- (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")
+ (and:SI (match_operand:QI 1 "address_operand" "ZR,ZT")
(const_int 2147483647)))]
"!TARGET_64BIT"
"@
lay\t%0,%a1"
[(set_attr "op_type" "RX,RXY")
(set_attr "type" "la")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
(define_insn_and_split "*la_31_and_cc"
(define_insn "force_la_31"
[(set (match_operand:SI 0 "register_operand" "=d,d")
- (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))
+ (match_operand:QI 1 "address_operand" "ZR,ZT"))
(use (const_int 0))]
"!TARGET_64BIT"
"@
lay\t%0,%a1"
[(set_attr "op_type" "RX")
(set_attr "type" "la")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
;
})
(define_insn "*movhi"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q")
- (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K"))]
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d,v,R")
+ (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,K,v,d,v,R,v"))]
""
"@
lr\t%0,%1
sth\t%1,%0
sthy\t%1,%0
sthrl\t%1,%0
- mvhhi\t%0,%1"
- [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL")
- (set_attr "type" "lr,*,*,*,larl,store,store,store,*")
- (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10")
+ mvhhi\t%0,%1
+ vleih\t%v0,%h1,0
+ vlr\t%v0,%v1
+ vlvgh\t%v0,%1,0
+ vlgvh\t%0,%v1,0
+ vleh\t%v0,%1,0
+ vsteh\t%v1,%0,0"
+ [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX")
+ (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*")
+ (set_attr "cpu_facility" "*,*,*,longdisp,z10,*,longdisp,z10,z10,vx,vx,vx,vx,vx,vx")
(set_attr "z10prop" "z10_fr_E1,
z10_fwd_A1,
z10_super_E1,
z10_rec,
z10_rec,
z10_rec,
- z10_super")])
+ z10_super,*,*,*,*,*,*")])
(define_peephole2
[(set (match_operand:HI 0 "register_operand" "")
})
(define_insn "*movqi"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
- (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q"))]
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d,v,R")
+ (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q,K,v,d,v,R,v"))]
""
"@
lr\t%0,%1
stcy\t%1,%0
mvi\t%S0,%b1
mviy\t%S0,%b1
- #"
- [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
- (set_attr "type" "lr,*,*,*,store,store,store,store,*")
+ #
+ vleib\t%v0,%b1,0
+ vlr\t%v0,%v1
+ vlvgb\t%v0,%1,0
+ vlgvb\t%0,%v1,0
+ vleb\t%v0,%1,0
+ vsteb\t%v1,%0,0"
+ [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX")
+ (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*")
+ (set_attr "cpu_facility" "*,*,*,longdisp,*,longdisp,*,longdisp,*,vx,vx,vx,vx,vx,vx")
(set_attr "z10prop" "z10_fr_E1,
z10_fwd_A1,
z10_super_E1,
z10_rec,
z10_super,
z10_super,
- *")])
+ *,*,*,*,*,*,*")])
(define_peephole2
[(set (match_operand:QI 0 "nonimmediate_operand" "")
ic\t%0,%1
icy\t%0,%1"
[(set_attr "op_type" "RX,RXY")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1")])
;
icm\t%0,3,%S1
icmy\t%0,3,%S1"
[(set_attr "op_type" "RS,RSY")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1")])
;
ear\t%0,%1"
[(set_attr "op_type" "RR,RX,RXY,RRE")
(set_attr "type" "lr,load,load,*")
+ (set_attr "cpu_facility" "*,*,longdisp,*")
(set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
;
"")
(define_insn "*mov<mode>_64"
- [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
- (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
+ [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o,d,S, d,o")
+ (match_operand:TD_TF 1 "general_operand" " G,f,o,f,S,d,dT,d"))]
"TARGET_ZARCH"
"@
lzxr\t%0
[(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
(match_operand:TD_TF 1 "general_operand" ""))]
"TARGET_ZARCH && reload_completed
+ && !s_operand (operands[0], <MODE>mode)
+ && !s_operand (operands[1], <MODE>mode)
&& s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
[(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
(match_operand:TD_TF 1 "general_operand" ""))]
"TARGET_ZARCH && reload_completed
+ && !s_operand (operands[0], <MODE>mode)
+ && !s_operand (operands[1], <MODE>mode)
&& s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
[(set (match_operand:TD_TF 0 "register_operand" "")
(match_operand:TD_TF 1 "memory_operand" ""))]
"TARGET_ZARCH && reload_completed
- && !FP_REG_P (operands[0])
+ && GENERAL_REG_P (operands[0])
&& !s_operand (operands[1], VOIDmode)"
[(set (match_dup 0) (match_dup 1))]
{
(define_insn "*mov<mode>_64dfp"
[(set (match_operand:DD_DF 0 "nonimmediate_operand"
- "=f,f,f,d,f,f,R,T,d,d, d,RT")
+ "=f,f,f,d,f,f,R,T,d,d,d,d,b,T,v,v,v,d,v,R")
(match_operand:DD_DF 1 "general_operand"
- " G,f,d,f,R,T,f,f,G,d,RT, d"))]
+ " G,f,d,f,R,T,f,f,G,d,b,T,d,d,v,G,d,v,R,v"))]
"TARGET_DFP"
"@
lzdr\t%0
stdy\t%1,%0
lghi\t%0,0
lgr\t%0,%1
+ lgrl\t%0,%1
lg\t%0,%1
- stg\t%1,%0"
- [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
+ stgrl\t%1,%0
+ stg\t%1,%0
+ vlr\t%v0,%v1
+ vleig\t%v0,0,0
+ vlvgg\t%v0,%1,0
+ vlgvg\t%0,%v1,0
+ vleg\t%0,%1,0
+ vsteg\t%1,%0,0"
+ [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRI,VRS,VRS,VRX,VRX")
(set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
- fstoredf,fstoredf,*,lr,load,store")
- (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
- (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
+ fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,*,load,store")
+ (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*,*")
+ (set_attr "cpu_facility" "z196,*,*,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vx,vx,vx,vx,vx,vx")])
(define_insn "*mov<mode>_64"
- [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d, d,RT")
- (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,RT, d"))]
+ [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,d,b,T")
+ (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,T,d,d"))]
"TARGET_ZARCH"
"@
lzdr\t%0
stdy\t%1,%0
lghi\t%0,0
lgr\t%0,%1
+ lgrl\t%0,%1
lg\t%0,%1
+ stgrl\t%1,%0
stg\t%1,%0"
- [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
+ [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY")
(set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
- fstore<mode>,fstore<mode>,*,lr,load,store")
- (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
- (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*")])
+ fstore<mode>,fstore<mode>,*,lr,load,load,store,store")
+ (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
+ (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*")])
(define_insn "*mov<mode>_31"
[(set (match_operand:DD_DF 0 "nonimmediate_operand"
- "=f,f,f,f,R,T,d,d,Q,S, d,o")
+ "=f,f,f,f,R,T,d,d,Q,S, d,o")
(match_operand:DD_DF 1 "general_operand"
- " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
+ " G,f,R,T,f,f,Q,S,d,d,dPT,d"))]
"!TARGET_ZARCH"
"@
lzdr\t%0
[(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
(set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
- (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
+ (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,longdisp,*,longdisp,*,*")])
(define_split
[(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
(match_operand:DD_DF 1 "general_operand" ""))]
"!TARGET_ZARCH && reload_completed
+ && !s_operand (operands[0], <MODE>mode)
+ && !s_operand (operands[1], <MODE>mode)
&& s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
[(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
(match_operand:DD_DF 1 "general_operand" ""))]
"!TARGET_ZARCH && reload_completed
+ && !s_operand (operands[0], <MODE>mode)
+ && !s_operand (operands[1], <MODE>mode)
&& s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
(define_insn "mov<mode>"
[(set (match_operand:SD_SF 0 "nonimmediate_operand"
- "=f,f,f,f,R,T,d,d,d,d,R,T")
+ "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,R")
(match_operand:SD_SF 1 "general_operand"
- " G,f,R,T,f,f,G,d,R,T,d,d"))]
+ " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,R,v"))]
""
"@
lzer\t%0
+ ldr\t%0,%1
ler\t%0,%1
+ lde\t%0,%1
le\t%0,%1
ley\t%0,%1
ste\t%1,%0
stey\t%1,%0
lhi\t%0,0
lr\t%0,%1
+ lrl\t%0,%1
l\t%0,%1
ly\t%0,%1
+ strl\t%1,%0
st\t%1,%0
- sty\t%1,%0"
- [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RR,RX,RXY,RX,RXY")
- (set_attr "type" "fsimpsf,fload<mode>,fload<mode>,fload<mode>,
- fstore<mode>,fstore<mode>,*,lr,load,load,store,store")
- (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
- (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
+ sty\t%1,%0
+ vlr\t%v0,%v1
+ vleif\t%v0,0,0
+ vlvgf\t%v0,%1,0
+ vlgvf\t%0,%v1,0
+ vlef\t%0,%1,0
+ vstef\t%1,%0,0"
+ [(set_attr "op_type" "RRE,RR,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX")
+ (set_attr "type" "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>,
+ fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store")
+ (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*")
+ (set_attr "cpu_facility" "z196,vx,*,vx,*,longdisp,*,longdisp,*,*,z10,*,longdisp,z10,*,longdisp,vx,vx,vx,vx,vx,vx")])
;
; movcc instruction pattern
sty\t%1,%0"
[(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
(set_attr "type" "lr,*,*,load,load,store,store")
+ (set_attr "cpu_facility" "*,*,*,*,longdisp,*,longdisp")
(set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
(set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
(define_insn "*load_multiple_di"
[(match_parallel 0 "load_multiple_operation"
[(set (match_operand:DI 1 "register_operand" "=r")
- (match_operand:DI 2 "s_operand" "QS"))])]
+ (match_operand:DI 2 "s_operand" "S"))])]
"reload_completed && TARGET_ZARCH"
{
int words = XVECLEN (operands[0], 0);
return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
}
[(set_attr "op_type" "RS,RSY")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "type" "lm")])
;
(define_insn "*store_multiple_di"
[(match_parallel 0 "store_multiple_operation"
- [(set (match_operand:DI 1 "s_operand" "=QS")
+ [(set (match_operand:DI 1 "s_operand" "=S")
(match_operand:DI 2 "register_operand" "r"))])]
"reload_completed && TARGET_ZARCH"
{
return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
}
[(set_attr "op_type" "RS,RSY")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "type" "stm")])
;;
;
(define_expand "strlen<mode>"
+ [(match_operand:P 0 "register_operand" "") ; result
+ (match_operand:BLK 1 "memory_operand" "") ; input string
+ (match_operand:SI 2 "immediate_operand" "") ; search character
+ (match_operand:SI 3 "immediate_operand" "")] ; known alignment
+ ""
+{
+ if (!TARGET_VX || operands[2] != const0_rtx)
+ emit_insn (gen_strlen_srst<mode> (operands[0], operands[1],
+ operands[2], operands[3]));
+ else
+ s390_expand_vec_strlen (operands[0], operands[1], operands[3]);
+
+ DONE;
+})
+
+(define_expand "strlen_srst<mode>"
[(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
(parallel
[(set (match_dup 4)
;
(define_expand "movstr"
+ [(match_operand 0 "register_operand" "")
+ (match_operand 1 "memory_operand" "")
+ (match_operand 2 "memory_operand" "")]
+ ""
+{
+ if (TARGET_64BIT)
+ emit_insn (gen_movstrdi (operands[0], operands[1], operands[2]));
+ else
+ emit_insn (gen_movstrsi (operands[0], operands[1], operands[2]));
+ DONE;
+})
+
+(define_expand "movstr<P:mode>"
[(set (reg:SI 0) (const_int 0))
(parallel
[(clobber (match_dup 3))
(set (match_operand:BLK 1 "memory_operand" "")
(match_operand:BLK 2 "memory_operand" ""))
- (set (match_operand 0 "register_operand" "")
- (unspec [(match_dup 1)
+ (set (match_operand:P 0 "register_operand" "")
+ (unspec:P [(match_dup 1)
(match_dup 2)
(reg:SI 0)] UNSPEC_MVST))
(clobber (reg:CC CC_REGNUM))])]
""
{
- rtx addr1 = gen_reg_rtx (Pmode);
- rtx addr2 = gen_reg_rtx (Pmode);
+ rtx addr1, addr2;
+
+ if (TARGET_VX && optimize_function_for_speed_p (cfun))
+ {
+ s390_expand_vec_movstr (operands[0], operands[1], operands[2]);
+ DONE;
+ }
+
+ addr1 = gen_reg_rtx (Pmode);
+ addr2 = gen_reg_rtx (Pmode);
emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
(set (mem:BLK (match_operand:P 1 "register_operand" "0"))
(mem:BLK (match_operand:P 3 "register_operand" "2")))
(set (match_operand:P 0 "register_operand" "=d")
- (unspec [(mem:BLK (match_dup 1))
+ (unspec:P [(mem:BLK (match_dup 1))
(mem:BLK (match_dup 3))
(reg:SI 0)] UNSPEC_MVST))
(clobber (reg:CC CC_REGNUM))]
operands[2] = GEN_INT (S390_TDC_INFINITY);
})
+; This extracts CC into a GPR properly shifted. The actual IPM
+; instruction will be issued by reload. The constraint of operand 1
+; forces reload to use a GPR. So reload will issue a movcc insn for
+; copying CC into a GPR first.
(define_insn_and_split "*cc_to_int"
- [(set (match_operand:SI 0 "register_operand" "=d")
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(unspec:SI [(match_operand 1 "register_operand" "0")]
UNSPEC_CC_TO_INT))]
"operands != NULL"
; Initialize a block of arbitrary length with (operands[2] % 256).
-(define_expand "setmem_long"
+(define_expand "setmem_long_<P:mode>"
[(parallel
[(clobber (match_dup 1))
(set (match_operand:BLK 0 "memory_operand" "")
- (match_operand 2 "shift_count_or_setmem_operand" ""))
- (use (match_operand 1 "general_operand" ""))
+ (unspec:BLK [(match_operand:P 2 "setmem_operand" "")
+ (match_dup 4)] UNSPEC_REPLICATE_BYTE))
(use (match_dup 3))
(clobber (reg:CC CC_REGNUM))])]
""
operands[0] = replace_equiv_address_nv (operands[0], addr0);
operands[1] = reg0;
operands[3] = reg1;
+ operands[4] = gen_lowpart (Pmode, operands[1]);
})
+; Patterns for 31 bit + Esa and 64 bit + Zarch.
+
(define_insn "*setmem_long"
[(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
(set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
- (match_operand 2 "shift_count_or_setmem_operand" "Y"))
- (use (match_dup 3))
+ (unspec:BLK [(match_operand:P 2 "setmem_operand" "Y")
+ (subreg:P (match_dup 3) <modesize>)]
+ UNSPEC_REPLICATE_BYTE))
(use (match_operand:<DBL> 1 "register_operand" "d"))
(clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT || !TARGET_ZARCH"
(define_insn "*setmem_long_and"
[(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
(set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
- (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
- (match_operand 4 "const_int_operand" "n")))
- (use (match_dup 3))
+ (unspec:BLK [(zero_extend:P (match_operand:QI 2 "setmem_operand" "Y"))
+ (subreg:P (match_dup 3) <modesize>)]
+ UNSPEC_REPLICATE_BYTE))
(use (match_operand:<DBL> 1 "register_operand" "d"))
(clobber (reg:CC CC_REGNUM))]
- "(TARGET_64BIT || !TARGET_ZARCH) &&
- (INTVAL (operands[4]) & 255) == 255"
+ "(TARGET_64BIT || !TARGET_ZARCH)"
"mvcle\t%0,%1,%Y2\;jo\t.-4"
[(set_attr "length" "8")
(set_attr "type" "vs")])
+; Variants for 31 bit + Zarch, necessary because of the odd in-register offsets
+; of the SImode subregs.
+
(define_insn "*setmem_long_31z"
[(clobber (match_operand:TI 0 "register_operand" "=d"))
(set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
- (match_operand 2 "shift_count_or_setmem_operand" "Y"))
- (use (match_dup 3))
+ (unspec:BLK [(match_operand:SI 2 "setmem_operand" "Y")
+ (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE))
(use (match_operand:TI 1 "register_operand" "d"))
(clobber (reg:CC CC_REGNUM))]
"!TARGET_64BIT && TARGET_ZARCH"
[(set_attr "length" "8")
(set_attr "type" "vs")])
+(define_insn "*setmem_long_and_31z"
+ [(clobber (match_operand:TI 0 "register_operand" "=d"))
+ (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
+ (unspec:BLK [(zero_extend:SI (match_operand:QI 2 "setmem_operand" "Y"))
+ (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE))
+ (use (match_operand:TI 1 "register_operand" "d"))
+ (clobber (reg:CC CC_REGNUM))]
+ "(!TARGET_64BIT && TARGET_ZARCH)"
+ "mvcle\t%0,%1,%Y2\;jo\t.-4"
+ [(set_attr "length" "8")
+ (set_attr "type" "vs")])
+
;
; cmpmemM instruction pattern(s).
;
icm\t%0,%2,%S1
icmy\t%0,%2,%S1"
[(set_attr "op_type" "RS,RSY")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1")])
(define_insn "*sethighpartdi_64"
[(set (match_operand:DI 0 "register_operand" "=d")
- (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
+ (unspec:DI [(match_operand:BLK 1 "s_operand" "S")
(match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH"
icm\t%0,%2,%S1
icmy\t%0,%2,%S1"
[(set_attr "op_type" "RS,RSY")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1")])
;
(clobber (reg:CC CC_REGNUM))])]
"TARGET_Z10"
{
+ if (! EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), 64))
+ FAIL;
/* Starting with zEC12 there is risbgn not clobbering CC. */
if (TARGET_ZEC12)
{
}
})
-(define_insn "*extzv<mode>_zEC12"
+(define_insn "*extzv<mode><clobbercc_or_nocc>"
[(set (match_operand:GPR 0 "register_operand" "=d")
(zero_extract:GPR
(match_operand:GPR 1 "register_operand" "d")
(match_operand 2 "const_int_operand" "") ; size
- (match_operand 3 "const_int_operand" "")))] ; start]
- "TARGET_ZEC12"
- "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
- [(set_attr "op_type" "RIE")])
+ (match_operand 3 "const_int_operand" ""))) ; start
+ ]
+ "<z10_or_zEC12_cond>
+ && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]),
+ GET_MODE_BITSIZE (<MODE>mode))"
+ "<risbg_n>\t%0,%1,64-%2,128+63,<bitoff_plus>%3+%2" ; dst, src, start, end, shift
+ [(set_attr "op_type" "RIE")
+ (set_attr "z10prop" "z10_super_E1")])
-(define_insn "*extzv<mode>_z10"
- [(set (match_operand:GPR 0 "register_operand" "=d")
- (zero_extract:GPR
- (match_operand:GPR 1 "register_operand" "d")
- (match_operand 2 "const_int_operand" "") ; size
- (match_operand 3 "const_int_operand" ""))) ; start
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_Z10"
- "risbg\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
+; 64 bit: (a & -16) | ((b >> 8) & 15)
+(define_insn "*extzvdi<clobbercc_or_nocc>_lshiftrt"
+ [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
+ (match_operand 1 "const_int_operand" "") ; size
+ (match_operand 2 "const_int_operand" "")) ; start
+ (lshiftrt:DI (match_operand:DI 3 "register_operand" "d")
+ (match_operand:DI 4 "nonzero_shift_count_operand" "")))]
+ "<z10_or_zEC12_cond>
+ && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64)
+ && 64 - UINTVAL (operands[4]) >= UINTVAL (operands[1])"
+ "<risbg_n>\t%0,%3,%2,%2+%1-1,128-%2-%1-%4"
+ [(set_attr "op_type" "RIE")
+ (set_attr "z10prop" "z10_super_E1")])
+
+; 32 bit: (a & -16) | ((b >> 8) & 15)
+(define_insn "*<risbg_n>_ior_and_sr_ze"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (ior:SI (and:SI
+ (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "const_int_operand" ""))
+ (subreg:SI
+ (zero_extract:DI
+ (match_operand:DI 3 "register_operand" "d")
+ (match_operand 4 "const_int_operand" "") ; size
+ (match_operand 5 "const_int_operand" "")) ; start
+ 4)))]
+ "<z10_or_zEC12_cond>
+ && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[4]), INTVAL (operands[5]), 64)
+ && UINTVAL (operands[2]) == (~(0ULL) << UINTVAL (operands[4]))"
+ "<risbg_n>\t%0,%3,64-%4,63,%4+%5"
+ [(set_attr "op_type" "RIE")
+ (set_attr "z10prop" "z10_super_E1")])
+
+; ((int)foo >> 10) & 1;
+(define_insn "*extract1bitdi<clobbercc_or_nocc>"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (ne:DI (zero_extract:DI
+ (match_operand:DI 1 "register_operand" "d")
+ (const_int 1) ; size
+ (match_operand 2 "const_int_operand" "")) ; start
+ (const_int 0)))]
+ "<z10_or_zEC12_cond>
+ && EXTRACT_ARGS_IN_RANGE (1, INTVAL (operands[2]), 64)"
+ "<risbg_n>\t%0,%1,64-1,128+63,%2+1" ; dst, src, start, end, shift
+ [(set_attr "op_type" "RIE")
+ (set_attr "z10prop" "z10_super_E1")])
+
+(define_insn "*<risbg_n>_and_subregdi_rotr"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (and:DI (subreg:DI
+ (rotate:SINT (match_operand:SINT 1 "register_operand" "d")
+ (match_operand:SINT 2 "const_int_operand" "")) 0)
+ (match_operand:DI 3 "contiguous_bitmask_operand" "")))]
+ "<z10_or_zEC12_cond>
+ && UINTVAL (operands[3]) < (1ULL << (UINTVAL (operands[2]) & 0x3f))"
+ "<risbg_n>\t%0,%1,%s3,128+%e3,<bitoff_plus>%2" ; dst, src, start, end, shift
+ [(set_attr "op_type" "RIE")
+ (set_attr "z10prop" "z10_super_E1")])
+
+(define_insn "*<risbg_n>_and_subregdi_rotl"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (and:DI (subreg:DI
+ (rotate:SINT (match_operand:SINT 1 "register_operand" "d")
+ (match_operand:SINT 2 "const_int_operand" "")) 0)
+ (match_operand:DI 3 "contiguous_bitmask_operand" "")))]
+ "<z10_or_zEC12_cond>
+ && !(UINTVAL (operands[3]) & ((1ULL << (UINTVAL (operands[2]) & 0x3f)) - 1))"
+ "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift
+ [(set_attr "op_type" "RIE")
+ (set_attr "z10prop" "z10_super_E1")])
+
+(define_insn "*<risbg_n>_di_and_rot"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (and:DI (rotate:DI (match_operand:DI 1 "register_operand" "d")
+ (match_operand:DI 2 "const_int_operand" ""))
+ (match_operand:DI 3 "contiguous_bitmask_operand" "")))]
+ "<z10_or_zEC12_cond>"
+ "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift
[(set_attr "op_type" "RIE")
(set_attr "z10prop" "z10_super_E1")])
(define_insn_and_split "*pre_z10_extzv<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
- (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
+ (zero_extract:GPR (match_operand:QI 1 "s_operand" "S")
(match_operand 2 "nonzero_shift_count_operand" "")
(const_int 0)))
(clobber (reg:CC CC_REGNUM))]
(define_insn_and_split "*pre_z10_extv<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
- (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
+ (sign_extract:GPR (match_operand:QI 1 "s_operand" "S")
(match_operand 2 "nonzero_shift_count_operand" "")
(const_int 0)))
(clobber (reg:CC CC_REGNUM))]
; The normal RTL expansion will never generate a zero_extract where
; the location operand isn't word mode. However, we do this in the
; back-end when generating atomic operations. See s390_two_part_insv.
-(define_insn "*insv<mode>_zEC12"
+(define_insn "*insv<mode><clobbercc_or_nocc>"
[(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
(match_operand 1 "const_int_operand" "I") ; size
(match_operand 2 "const_int_operand" "I")) ; pos
(match_operand:GPR 3 "nonimmediate_operand" "d"))]
- "TARGET_ZEC12
+ "<z10_or_zEC12_cond>
+ && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]),
+ GET_MODE_BITSIZE (<MODE>mode))
&& (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
- "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
- [(set_attr "op_type" "RIE")])
-
-(define_insn "*insv<mode>_z10"
- [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
- (match_operand 1 "const_int_operand" "I") ; size
- (match_operand 2 "const_int_operand" "I")) ; pos
- (match_operand:GPR 3 "nonimmediate_operand" "d"))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_Z10
- && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
- "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
+ "<risbg_n>\t%0,%3,<bitoff_plus>%2,<bitoff_plus>%2+%1-1,<bitsize>-%2-%1"
[(set_attr "op_type" "RIE")
(set_attr "z10prop" "z10_super_E1")])
; and op1 with a mask being 1 for the selected bits and 0 for the rest
; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
-(define_insn "*insv<mode>_zEC12_noshift"
- [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
- (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
+(define_insn "*insv<mode><clobbercc_or_nocc>_noshift"
+ [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d")
+ (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d,0")
(match_operand:GPR 2 "contiguous_bitmask_operand" ""))
- (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
+ (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0,d")
(match_operand:GPR 4 "const_int_operand" ""))))]
- "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
- "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0"
- [(set_attr "op_type" "RIE")])
+ "<z10_or_zEC12_cond> && INTVAL (operands[2]) == ~INTVAL (operands[4])"
+ "@
+ <risbg_n>\t%0,%1,%<bfstart>2,%<bfend>2,0
+ <risbg_n>\t%0,%3,%<bfstart>4,%<bfend>4,0"
+ [(set_attr "op_type" "RIE")
+ (set_attr "z10prop" "z10_super_E1")])
+
+(define_insn "*insv_z10_noshift_cc"
+ [(set (reg CC_REGNUM)
+ (compare
+ (ior:DI
+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0")
+ (match_operand:DI 2 "contiguous_bitmask_operand" ""))
+ (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d")
+ (match_operand:DI 4 "const_int_operand" "")))
+ (const_int 0)))
+ (set (match_operand:DI 0 "nonimmediate_operand" "=d,d")
+ (ior:DI (and:DI (match_dup 1) (match_dup 2))
+ (and:DI (match_dup 3) (match_dup 4))))]
+ "TARGET_Z10 && s390_match_ccmode (insn, CCSmode)
+ && INTVAL (operands[2]) == ~INTVAL (operands[4])"
+ "@
+ risbg\t%0,%1,%s2,%e2,0
+ risbg\t%0,%3,%s4,%e4,0"
+ [(set_attr "op_type" "RIE")
+ (set_attr "z10prop" "z10_super_E1")])
-(define_insn "*insv<mode>_z10_noshift"
+(define_insn "*insv_z10_noshift_cconly"
+ [(set
+ (reg CC_REGNUM)
+ (compare
+ (ior:DI
+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0")
+ (match_operand:DI 2 "contiguous_bitmask_operand" ""))
+ (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d")
+ (match_operand:DI 4 "const_int_operand" "")))
+ (const_int 0)))
+ (clobber (match_scratch:DI 0 "=d,d"))]
+ "TARGET_Z10 && s390_match_ccmode (insn, CCSmode)
+ && INTVAL (operands[2]) == ~INTVAL (operands[4])"
+ "@
+ risbg\t%0,%1,%s2,%e2,0
+ risbg\t%0,%3,%s4,%e4,0"
+ [(set_attr "op_type" "RIE")
+ (set_attr "z10prop" "z10_super_E1")])
+
+; Implement appending Y on the left of S bits of X
+; x = (y << s) | (x & ((1 << s) - 1))
+(define_insn "*insv<mode><clobbercc_or_nocc>_appendbitsleft"
[(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
- (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
- (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
- (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
- (match_operand:GPR 4 "const_int_operand" ""))))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
- "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
+ (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0")
+ (match_operand:GPR 2 "immediate_operand" ""))
+ (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d")
+ (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
+ "<z10_or_zEC12_cond>
+ && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1"
+ "<risbg_n>\t%0,%3,<bitoff>,64-%4-1,%4"
+ [(set_attr "op_type" "RIE")
+ (set_attr "z10prop" "z10_super_E1")])
+
+; a = ((i32)a & -16777216) | (((ui32)b) >> 8)
+(define_insn "*<risbg_n>_<mode>_ior_and_lshiftrt"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (ior:GPR (and:GPR
+ (match_operand:GPR 1 "register_operand" "0")
+ (match_operand:GPR 2 "const_int_operand" ""))
+ (lshiftrt:GPR
+ (match_operand:GPR 3 "register_operand" "d")
+ (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
+ "<z10_or_zEC12_cond> && UINTVAL (operands[2])
+ == (~(0ULL) << (GET_MODE_BITSIZE (<MODE>mode) - UINTVAL (operands[4])))"
+ "<risbg_n>\t%0,%3,<bitoff_plus>%4,63,64-%4"
[(set_attr "op_type" "RIE")
(set_attr "z10prop" "z10_super_E1")])
+; (ui32)(((ui64)x) >> 48) | ((i32)y & -65536);
+(define_insn "*<risbg_n>_sidi_ior_and_lshiftrt"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (ior:SI (and:SI
+ (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "const_int_operand" ""))
+ (subreg:SI
+ (lshiftrt:DI
+ (match_operand:DI 3 "register_operand" "d")
+ (match_operand:DI 4 "nonzero_shift_count_operand" "")) 4)))]
+ "<z10_or_zEC12_cond>
+ && UINTVAL (operands[2]) == ~(~(0ULL) >> UINTVAL (operands[4]))"
+ "<risbg_n>\t%0,%3,%4,63,64-%4"
+ [(set_attr "op_type" "RIE")
+ (set_attr "z10prop" "z10_super_E1")])
+
+; (ui32)(((ui64)x) >> 12) & -4
+(define_insn "*trunc_sidi_and_subreg_lshrt<clobbercc_or_nocc>"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (and:SI
+ (subreg:SI (lshiftrt:DI
+ (match_operand:DI 1 "register_operand" "d")
+ (match_operand:DI 2 "nonzero_shift_count_operand" "")) 4)
+ (match_operand:SI 3 "contiguous_bitmask_nowrap_operand" "")))]
+ "<z10_or_zEC12_cond>"
+ "<risbg_n>\t%0,%1,%t3,128+%f3,64-%2"
+ [(set_attr "op_type" "RIE")
+ (set_attr "z10prop" "z10_super_E1")])
+
+; z = (x << c) | (y >> d) with (x << c) and (y >> d) not overlapping after shifting
+; -> z = y >> d; z = (x << c) | (z & ((1 << c) - 1))
+; -> z = y >> d; z = risbg;
+
+(define_split
+ [(set (match_operand:GPR 0 "nonimmediate_operand" "")
+ (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
+ (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
+ (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "")
+ (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
+ "TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>"
+ [(set (match_dup 6)
+ (lshiftrt:GPR (match_dup 1) (match_dup 2)))
+ (set (match_dup 0)
+ (ior:GPR (and:GPR (match_dup 6) (match_dup 5))
+ (ashift:GPR (match_dup 3) (match_dup 4))))]
+{
+ operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
+ if (reg_overlap_mentioned_p (operands[0], operands[3]))
+ {
+ if (!can_create_pseudo_p ())
+ FAIL;
+ operands[6] = gen_reg_rtx (<MODE>mode);
+ }
+ else
+ operands[6] = operands[0];
+})
+
+(define_split
+ [(parallel
+ [(set (match_operand:GPR 0 "nonimmediate_operand" "")
+ (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
+ (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
+ (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "")
+ (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))
+ (clobber (reg:CC CC_REGNUM))])]
+ "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>"
+ [(set (match_dup 6)
+ (lshiftrt:GPR (match_dup 1) (match_dup 2)))
+ (parallel
+ [(set (match_dup 0)
+ (ior:GPR (and:GPR (match_dup 6) (match_dup 5))
+ (ashift:GPR (match_dup 3) (match_dup 4))))
+ (clobber (reg:CC CC_REGNUM))])]
+{
+ operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
+ if (reg_overlap_mentioned_p (operands[0], operands[3]))
+ {
+ if (!can_create_pseudo_p ())
+ FAIL;
+ operands[6] = gen_reg_rtx (<MODE>mode);
+ }
+ else
+ operands[6] = operands[0];
+})
+
+; rosbg, rxsbg
(define_insn "*r<noxa>sbg_<mode>_noshift"
[(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
(IXOR:GPR
"r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
[(set_attr "op_type" "RIE")])
+; rosbg, rxsbg
(define_insn "*r<noxa>sbg_di_rotl"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d")
(IXOR:DI
"r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
[(set_attr "op_type" "RIE")])
-(define_insn "*r<noxa>sbg_<mode>_srl"
+; rosbg, rxsbg
+(define_insn "*r<noxa>sbg_<mode>_srl_bitmask"
[(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
(IXOR:GPR
(and:GPR
(lshiftrt:GPR
(match_operand:GPR 1 "nonimmediate_operand" "d")
(match_operand:GPR 3 "nonzero_shift_count_operand" ""))
- (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
+ (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" ""))
(match_operand:GPR 4 "nonimmediate_operand" "0")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_Z10
"r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
[(set_attr "op_type" "RIE")])
-(define_insn "*r<noxa>sbg_<mode>_sll"
+; rosbg, rxsbg
+(define_insn "*r<noxa>sbg_<mode>_sll_bitmask"
[(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
(IXOR:GPR
(and:GPR
(ashift:GPR
(match_operand:GPR 1 "nonimmediate_operand" "d")
(match_operand:GPR 3 "nonzero_shift_count_operand" ""))
- (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
+ (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" ""))
(match_operand:GPR 4 "nonimmediate_operand" "0")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_Z10
"r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
[(set_attr "op_type" "RIE")])
+;; unsigned {int,long} a, b
+;; a = a | (b << const_int)
+;; a = a ^ (b << const_int)
+; rosbg, rxsbg
+(define_insn "*r<noxa>sbg_<mode>_sll"
+ [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
+ (IXOR:GPR
+ (ashift:GPR
+ (match_operand:GPR 1 "nonimmediate_operand" "d")
+ (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
+ (match_operand:GPR 3 "nonimmediate_operand" "0")))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z10"
+ "r<noxa>sbg\t%0,%1,<bitoff>,63-%2,%2"
+ [(set_attr "op_type" "RIE")])
+
+;; unsigned {int,long} a, b
+;; a = a | (b >> const_int)
+;; a = a ^ (b >> const_int)
+; rosbg, rxsbg
+(define_insn "*r<noxa>sbg_<mode>_srl"
+ [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
+ (IXOR:GPR
+ (lshiftrt:GPR
+ (match_operand:GPR 1 "nonimmediate_operand" "d")
+ (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
+ (match_operand:GPR 3 "nonimmediate_operand" "0")))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z10"
+ "r<noxa>sbg\t%0,%1,<bitoff_plus>%2,63,64-%2"
+ [(set_attr "op_type" "RIE")])
+
;; These two are generated by combine for s.bf &= val.
;; ??? For bitfields smaller than 32-bits, we wind up with SImode
;; shifts and ands, which results in some truly awful patterns
(match_operand:DI 3 "nonimmediate_operand" "d")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_Z10
+ && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64)
&& INTVAL (operands[1]) + INTVAL (operands[2]) == 64"
"rnsbg\t%0,%3,%2,63,0"
[(set_attr "op_type" "RIE")])
(match_operand:DI 4 "nonimmediate_operand" "d")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_Z10
+ && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64)
&& INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
"rnsbg\t%0,%4,%2,%2+%1-1,%3"
[(set_attr "op_type" "RIE")])
(match_operand 1 "const_int_operand" "n,n")
(const_int 0))
(match_operand:W 2 "register_operand" "d,d"))]
- "INTVAL (operands[1]) > 0
+ "EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64)
+ && INTVAL (operands[1]) > 0
&& INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
&& INTVAL (operands[1]) % BITS_PER_UNIT == 0"
{
: "stcmy\t%2,%1,%S0";
}
[(set_attr "op_type" "RS,RSY")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_super,z10_super")])
(define_insn "*insvdi_mem_reghigh"
- [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
+ [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+S")
(match_operand 1 "const_int_operand" "n")
(const_int 0))
(lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
(const_int 32)))]
"TARGET_ZARCH
+ && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64)
&& INTVAL (operands[1]) > 0
&& INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
&& INTVAL (operands[1]) % BITS_PER_UNIT == 0"
(match_operand 1 "const_int_operand" "n"))
(match_operand:DI 2 "const_int_operand" "n"))]
"TARGET_ZARCH
+ && EXTRACT_ARGS_IN_RANGE (16, INTVAL (operands[1]), 64)
&& INTVAL (operands[1]) >= 0
&& INTVAL (operands[1]) < BITS_PER_WORD
&& INTVAL (operands[1]) % 16 == 0"
(define_insn "*extendsidi2"
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
- (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
+ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))]
"TARGET_ZARCH"
"@
lgfr\t%0,%1
(define_insn "*extendhidi2_extimm"
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
- (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
+ (sign_extend:DI (match_operand:HI 1 "general_operand" "d,T,b")))]
"TARGET_ZARCH && TARGET_EXTIMM"
"@
lghr\t%0,%1
(define_insn "*extendhidi2"
[(set (match_operand:DI 0 "register_operand" "=d")
- (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
+ (sign_extend:DI (match_operand:HI 1 "memory_operand" "T")))]
"TARGET_ZARCH"
"lgh\t%0,%1"
[(set_attr "op_type" "RXY")
lh\t%0,%1
lhy\t%0,%1"
[(set_attr "op_type" "RX,RXY")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1")])
;
; lbr, lgbr, lb, lgb
(define_insn "*extendqi<mode>2_extimm"
[(set (match_operand:GPR 0 "register_operand" "=d,d")
- (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
+ (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,T")))]
"TARGET_EXTIMM"
"@
l<g>br\t%0,%1
; lb, lgb
(define_insn "*extendqi<mode>2"
[(set (match_operand:GPR 0 "register_operand" "=d")
- (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
+ (sign_extend:GPR (match_operand:QI 1 "memory_operand" "T")))]
"!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
"l<g>b\t%0,%1"
[(set_attr "op_type" "RXY")
(define_insn "*zero_extendsidi2"
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
- (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))]
"TARGET_ZARCH"
"@
llgfr\t%0,%1
(define_insn "*llgt_sidi"
[(set (match_operand:DI 0 "register_operand" "=d")
- (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
+ (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0)
(const_int 2147483647)))]
"TARGET_ZARCH"
"llgt\t%0,%1"
(define_insn_and_split "*llgt_sidi_split"
[(set (match_operand:DI 0 "register_operand" "=d")
- (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
+ (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0)
(const_int 2147483647)))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH"
(define_insn "*llgt_sisi"
[(set (match_operand:SI 0 "register_operand" "=d,d")
- (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,T")
(const_int 2147483647)))]
"TARGET_ZARCH"
"@
; llhrl, llghrl
(define_insn "*zero_extendhi<mode>2_z10"
[(set (match_operand:GPR 0 "register_operand" "=d,d,d")
- (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
+ (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,T,b")))]
"TARGET_Z10"
"@
ll<g>hr\t%0,%1
; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
(define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
[(set (match_operand:GPR 0 "register_operand" "=d,d")
- (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
+ (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,T")))]
"TARGET_EXTIMM"
"@
ll<g><hc>r\t%0,%1
; llgh, llgc
(define_insn "*zero_extend<HQI:mode><GPR:mode>2"
[(set (match_operand:GPR 0 "register_operand" "=d")
- (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
+ (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "T")))]
"TARGET_ZARCH && !TARGET_EXTIMM"
"llg<hc>\t%0,%1"
[(set_attr "op_type" "RXY")
(define_insn_and_split "*zero_extendhisi2_31"
[(set (match_operand:SI 0 "register_operand" "=&d")
- (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
+ (zero_extend:SI (match_operand:HI 1 "s_operand" "S")))
(clobber (reg:CC CC_REGNUM))]
"!TARGET_ZARCH"
"#"
(define_insn_and_split "*zero_extendqisi2_31"
[(set (match_operand:SI 0 "register_operand" "=&d")
- (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
+ (zero_extend:SI (match_operand:QI 1 "memory_operand" "T")))]
"!TARGET_ZARCH"
"#"
"&& reload_completed"
(define_insn "*zero_extendqihi2_64"
[(set (match_operand:HI 0 "register_operand" "=d")
- (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
+ (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))]
"TARGET_ZARCH && !TARGET_EXTIMM"
"llgc\t%0,%1"
[(set_attr "op_type" "RXY")
(define_insn_and_split "*zero_extendqihi2_31"
[(set (match_operand:HI 0 "register_operand" "=&d")
- (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
+ (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))]
"!TARGET_ZARCH"
"#"
"&& reload_completed"
[(parallel
[(set (match_operand:DI 0 "register_operand" "")
(unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
- (unspec:DI [(const_int 5)] UNSPEC_ROUND)
+ (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND)
(clobber (reg:CC CC_REGNUM))])]
"TARGET_HARD_DFP"
emit_insn (gen_extendddtd2 (temp, operands[1]));
temp = force_reg (TDmode, temp);
emit_cmp_and_jump_insns (temp,
- CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
+ const_double_from_real_value (cmp, TDmode),
LT, NULL_RTX, VOIDmode, 0, label1);
emit_insn (gen_subtd3 (temp, temp,
- CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
- emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
+ const_double_from_real_value (sub, TDmode)));
+ emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp,
+ GEN_INT (DFP_RND_TOWARD_MINF)));
emit_jump (label2);
emit_label (label1);
- emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
+ emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1],
+ GEN_INT (DFP_RND_TOWARD_0)));
emit_label (label2);
DONE;
}
[(parallel
[(set (match_operand:DI 0 "register_operand" "")
(unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
- (unspec:DI [(const_int 5)] UNSPEC_ROUND)
+ (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND)
(clobber (reg:CC CC_REGNUM))])]
"TARGET_HARD_DFP"
decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
emit_cmp_and_jump_insns (operands[1],
- CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
+ const_double_from_real_value (cmp, TDmode),
LT, NULL_RTX, VOIDmode, 0, label1);
emit_insn (gen_subtd3 (temp, operands[1],
- CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
- emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
+ const_double_from_real_value (sub, TDmode)));
+ emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp,
+ GEN_INT (DFP_RND_TOWARD_MINF)));
emit_jump (label2);
emit_label (label1);
- emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
+ emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1],
+ GEN_INT (DFP_RND_TOWARD_0)));
emit_label (label2);
DONE;
}
[(parallel
[(set (match_operand:GPR 0 "register_operand" "")
(unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
- (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
+ (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND)
(clobber (reg:CC CC_REGNUM))])]
"TARGET_HARD_FLOAT"
{
real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
emit_cmp_and_jump_insns (operands[1],
- CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode),
+ const_double_from_real_value (cmp, <BFP:MODE>mode),
LT, NULL_RTX, VOIDmode, 0, label1);
emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
- CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
+ const_double_from_real_value (sub, <BFP:MODE>mode)));
emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
- GEN_INT (7)));
+ GEN_INT (BFP_RND_TOWARD_MINF)));
emit_jump (label2);
emit_label (label1);
emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
- operands[1], GEN_INT (5)));
+ operands[1], GEN_INT (BFP_RND_TOWARD_0)));
emit_label (label2);
DONE;
}
[(parallel
[(set (match_operand:SI 0 "register_operand" "")
(unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
- (unspec:SI [(const_int 5)] UNSPEC_ROUND)
+ (unspec:SI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND)
(clobber (reg:CC CC_REGNUM))])]
"TARGET_Z196 && TARGET_HARD_DFP"
"")
; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
+(define_insn "*fixuns_truncdfdi2_z13"
+ [(set (match_operand:DI 0 "register_operand" "=d,v")
+ (unsigned_fix:DI (match_operand:DF 1 "register_operand" "f,v")))
+ (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND)
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_VX && TARGET_HARD_FLOAT"
+ "@
+ clgdbr\t%0,%h2,%1,0
+ wclgdb\t%v0,%v1,0,%h2"
+ [(set_attr "op_type" "RRF,VRR")
+ (set_attr "type" "ftoi")])
+
; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
; clfdtr, clfxtr, clgdtr, clgxtr
(define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
- [(set (match_operand:GPR 0 "register_operand" "=r")
- (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f")))
- (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f")))
+ (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
(clobber (reg:CC CC_REGNUM))]
- "TARGET_Z196"
+ "TARGET_Z196 && TARGET_HARD_FLOAT
+ && (!TARGET_VX || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)"
"cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
[(set_attr "op_type" "RRF")
(set_attr "type" "ftoi")])
"TARGET_HARD_FLOAT"
{
emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
- GEN_INT (5)));
+ GEN_INT (BFP_RND_TOWARD_0)));
DONE;
})
+(define_insn "*fix_truncdfdi2_bfp_z13"
+ [(set (match_operand:DI 0 "register_operand" "=d,v")
+ (fix:DI (match_operand:DF 1 "register_operand" "f,v")))
+ (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND)
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_VX && TARGET_HARD_FLOAT"
+ "@
+ cgdbr\t%0,%h2,%1
+ wcgdb\t%v0,%v1,0,%h2"
+ [(set_attr "op_type" "RRE,VRR")
+ (set_attr "type" "ftoi")])
+
; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr
-(define_insn "fix_trunc<BFP:mode><GPR:mode>2_bfp"
- [(set (match_operand:GPR 0 "register_operand" "=d")
- (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
- (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
+(define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
+ (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
(clobber (reg:CC CC_REGNUM))]
- "TARGET_HARD_FLOAT"
+ "TARGET_HARD_FLOAT
+ && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)"
"c<GPR:gf><BFP:xde>br\t%0,%h2,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "ftoi")])
-
+(define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp"
+ [(parallel
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (fix:GPR (match_operand:BFP 1 "register_operand" "f")))
+ (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
+ (clobber (reg:CC CC_REGNUM))])]
+ "TARGET_HARD_FLOAT")
;
; fix_trunc(td|dd)di2 instruction pattern(s).
;
{
operands[1] = force_reg (<MODE>mode, operands[1]);
emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
- GEN_INT (9)));
+ GEN_INT (DFP_RND_TOWARD_0)));
DONE;
})
(define_expand "fix_trunctf<mode>2"
[(parallel [(set (match_operand:GPR 0 "register_operand" "")
(fix:GPR (match_operand:TF 1 "register_operand" "")))
- (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
+ (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND)
(clobber (reg:CC CC_REGNUM))])]
"TARGET_HARD_FLOAT"
"")
; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
(define_insn "floatdi<mode>2"
- [(set (match_operand:FP 0 "register_operand" "=f")
- (float:FP (match_operand:DI 1 "register_operand" "d")))]
+ [(set (match_operand:FP 0 "register_operand" "=f,v")
+ (float:FP (match_operand:DI 1 "register_operand" "d,v")))]
"TARGET_ZARCH && TARGET_HARD_FLOAT"
- "c<xde>g<bt>r\t%0,%1"
- [(set_attr "op_type" "RRE")
- (set_attr "type" "itof<mode>" )])
+ "@
+ c<xde>g<bt>r\t%0,%1
+ wcdgb\t%v0,%v1,0,0"
+ [(set_attr "op_type" "RRE,VRR")
+ (set_attr "type" "itof<mode>" )
+ (set_attr "cpu_facility" "*,vx")
+ (set_attr "enabled" "*,<DFDI>")])
; cxfbr, cdfbr, cefbr
(define_insn "floatsi<mode>2"
; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
;
+(define_insn "*floatunsdidf2_z13"
+ [(set (match_operand:DF 0 "register_operand" "=f,v")
+ (unsigned_float:DF (match_operand:DI 1 "register_operand" "d,v")))]
+ "TARGET_VX && TARGET_HARD_FLOAT"
+ "@
+ cdlgbr\t%0,0,%1,0
+ wcdlgb\t%v0,%v1,0,0"
+ [(set_attr "op_type" "RRE,VRR")
+ (set_attr "type" "itofdf")])
+
; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
-(define_insn "floatuns<GPR:mode><FP:mode>2"
- [(set (match_operand:FP 0 "register_operand" "=f")
- (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))]
- "TARGET_Z196 && TARGET_HARD_FLOAT"
+(define_insn "*floatuns<GPR:mode><FP:mode>2"
+ [(set (match_operand:FP 0 "register_operand" "=f")
+ (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))]
+ "TARGET_Z196 && TARGET_HARD_FLOAT
+ && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)"
"c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
[(set_attr "op_type" "RRE")
- (set_attr "type" "itof<FP:mode>" )])
+ (set_attr "type" "itof<FP:mode>")])
+
+(define_expand "floatuns<GPR:mode><FP:mode>2"
+ [(set (match_operand:FP 0 "register_operand" "")
+ (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))]
+ "TARGET_Z196 && TARGET_HARD_FLOAT")
;
; truncdfsf2 instruction pattern(s).
;
(define_insn "truncdfsf2"
- [(set (match_operand:SF 0 "register_operand" "=f")
- (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
+ [(set (match_operand:SF 0 "register_operand" "=f,v")
+ (float_truncate:SF (match_operand:DF 1 "register_operand" "f,v")))]
"TARGET_HARD_FLOAT"
- "ledbr\t%0,%1"
- [(set_attr "op_type" "RRE")
- (set_attr "type" "ftruncdf")])
+ "@
+ ledbr\t%0,%1
+ wledb\t%v0,%v1,0,0" ; IEEE inexact exception not suppressed
+ ; According to BFP rounding mode
+ [(set_attr "op_type" "RRE,VRR")
+ (set_attr "type" "ftruncdf")
+ (set_attr "cpu_facility" "*,vx")])
;
; trunctf(df|sf)2 instruction pattern(s).
; trunctddd2 and truncddsd2 instruction pattern(s).
;
-(define_insn "trunctddd2"
+
+(define_expand "trunctddd2"
+ [(parallel
+ [(set (match_operand:DD 0 "register_operand" "")
+ (float_truncate:DD (match_operand:TD 1 "register_operand" "")))
+ (unspec:DI [(const_int DFP_RND_CURRENT)] UNSPEC_ROUND)
+ (clobber (scratch:TD))])]
+ "TARGET_HARD_DFP")
+
+(define_insn "*trunctddd2"
[(set (match_operand:DD 0 "register_operand" "=f")
(float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
- (clobber (match_scratch:TD 2 "=f"))]
+ (unspec:DI [(match_operand:DI 2 "const_mask_operand" "I")] UNSPEC_ROUND)
+ (clobber (match_scratch:TD 3 "=f"))]
"TARGET_HARD_DFP"
- "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
+ "ldxtr\t%3,%2,%1,0\;ldr\t%0,%3"
[(set_attr "length" "6")
(set_attr "type" "ftruncdd")])
(define_expand "trunctdsd2"
[(parallel
- [(set (match_dup 3)
+ [(set (match_dup 2)
(float_truncate:DD (match_operand:TD 1 "register_operand" "")))
- (clobber (match_scratch:TD 2 ""))])
+ (unspec:DI [(const_int DFP_RND_PREP_FOR_SHORT_PREC)] UNSPEC_ROUND)
+ (clobber (match_scratch:TD 3 ""))])
(set (match_operand:SD 0 "register_operand" "")
- (float_truncate:SD (match_dup 3)))]
+ (float_truncate:SD (match_dup 2)))]
"TARGET_HARD_DFP"
{
- operands[3] = gen_reg_rtx (DDmode);
+ operands[2] = gen_reg_rtx (DDmode);
})
;
; extend(sf|df)(df|tf)2 instruction pattern(s).
;
+(define_insn "*extendsfdf2_z13"
+ [(set (match_operand:DF 0 "register_operand" "=f,f,v")
+ (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R,v")))]
+ "TARGET_VX && TARGET_HARD_FLOAT"
+ "@
+ ldebr\t%0,%1
+ ldeb\t%0,%1
+ wldeb\t%v0,%v1"
+ [(set_attr "op_type" "RRE,RXE,VRR")
+ (set_attr "type" "fsimpdf, floaddf,fsimpdf")])
+
; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb
-(define_insn "extend<DSF:mode><BFP:mode>2"
- [(set (match_operand:BFP 0 "register_operand" "=f,f")
+(define_insn "*extend<DSF:mode><BFP:mode>2"
+ [(set (match_operand:BFP 0 "register_operand" "=f,f")
(float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))]
"TARGET_HARD_FLOAT
- && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)"
+ && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)
+ && (!TARGET_VX || <BFP:MODE>mode != DFmode || <DSF:MODE>mode != SFmode)"
"@
l<BFP:xde><DSF:xde>br\t%0,%1
l<BFP:xde><DSF:xde>b\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
+ [(set_attr "op_type" "RRE,RXE")
+ (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")])
+
+(define_expand "extend<DSF:mode><BFP:mode>2"
+ [(set (match_operand:BFP 0 "register_operand" "")
+ (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "")))]
+ "TARGET_HARD_FLOAT
+ && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)")
;
; extendddtd2 and extendsddd2 instruction pattern(s).
[(set (reg:DFP_ALL FPR0_REGNUM)
(float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
(use (reg:SI GPR0_REGNUM))
- (clobber (reg:CC CC_REGNUM))]
+ (clobber (reg:CC CC_REGNUM))
+ (clobber (reg:SI GPR1_REGNUM))]
"TARGET_HARD_DFP"
"pfpo")
[(set (reg:BFP FPR0_REGNUM)
(float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
(use (reg:SI GPR0_REGNUM))
- (clobber (reg:CC CC_REGNUM))]
+ (clobber (reg:CC CC_REGNUM))
+ (clobber (reg:SI GPR1_REGNUM))]
"TARGET_HARD_DFP"
"pfpo")
[(set (reg:DFP_ALL FPR0_REGNUM)
(float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
(use (reg:SI GPR0_REGNUM))
- (clobber (reg:CC CC_REGNUM))])
+ (clobber (reg:CC CC_REGNUM))
+ (clobber (reg:SI GPR1_REGNUM))])
(set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
(reg:DFP_ALL FPR0_REGNUM))]
"TARGET_HARD_DFP
(parallel
[(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
(use (reg:SI GPR0_REGNUM))
- (clobber (reg:CC CC_REGNUM))])
+ (clobber (reg:CC CC_REGNUM))
+ (clobber (reg:SI GPR1_REGNUM))])
(set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
"TARGET_HARD_DFP
&& GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
(define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
[(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
(use (reg:SI GPR0_REGNUM))
- (clobber (reg:CC CC_REGNUM))]
+ (clobber (reg:CC CC_REGNUM))
+ (clobber (reg:SI GPR1_REGNUM))]
"TARGET_HARD_DFP"
"pfpo")
(define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
[(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
(use (reg:SI GPR0_REGNUM))
- (clobber (reg:CC CC_REGNUM))]
+ (clobber (reg:CC CC_REGNUM))
+ (clobber (reg:SI GPR1_REGNUM))]
"TARGET_HARD_DFP"
"pfpo")
[(set (reg:DFP_ALL FPR0_REGNUM)
(float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
(use (reg:SI GPR0_REGNUM))
- (clobber (reg:CC CC_REGNUM))])
+ (clobber (reg:CC CC_REGNUM))
+ (clobber (reg:SI GPR1_REGNUM))])
(set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
(reg:DFP_ALL FPR0_REGNUM))]
"TARGET_HARD_DFP
(parallel
[(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
(use (reg:SI GPR0_REGNUM))
- (clobber (reg:CC CC_REGNUM))])
+ (clobber (reg:CC CC_REGNUM))
+ (clobber (reg:SI GPR1_REGNUM))])
(set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
"TARGET_HARD_DFP
&& GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
; addti3 instruction pattern(s).
;
-(define_insn_and_split "addti3"
- [(set (match_operand:TI 0 "register_operand" "=&d")
+(define_expand "addti3"
+ [(parallel
+ [(set (match_operand:TI 0 "register_operand" "")
+ (plus:TI (match_operand:TI 1 "nonimmediate_operand" "")
+ (match_operand:TI 2 "general_operand" "") ) )
+ (clobber (reg:CC CC_REGNUM))])]
+ "TARGET_ZARCH"
+{
+ /* For z13 we have vaq which doesn't set CC. */
+ if (TARGET_VX)
+ {
+ emit_insn (gen_rtx_SET (operands[0],
+ gen_rtx_PLUS (TImode,
+ copy_to_mode_reg (TImode, operands[1]),
+ copy_to_mode_reg (TImode, operands[2]))));
+ DONE;
+ }
+})
+
+(define_insn_and_split "*addti3"
+ [(set (match_operand:TI 0 "register_operand" "=&d")
(plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
- (match_operand:TI 2 "general_operand" "do") ) )
+ (match_operand:TI 2 "general_operand" "do") ) )
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH"
"#"
operands[5] = operand_subword (operands[2], 0, 0, TImode);
operands[6] = operand_subword (operands[0], 1, 0, TImode);
operands[7] = operand_subword (operands[1], 1, 0, TImode);
- operands[8] = operand_subword (operands[2], 1, 0, TImode);")
+ operands[8] = operand_subword (operands[2], 1, 0, TImode);"
+ [(set_attr "op_type" "*")
+ (set_attr "cpu_facility" "*")])
;
; adddi3 instruction pattern(s).
(define_insn "*adddi3_sign"
[(set (match_operand:DI 0 "register_operand" "=d,d")
- (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
+ (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
(match_operand:DI 1 "register_operand" "0,0")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH"
(define_insn "*adddi3_zero_cc"
[(set (reg CC_REGNUM)
- (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
+ (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
(match_operand:DI 1 "register_operand" "0,0"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d")
(define_insn "*adddi3_zero_cconly"
[(set (reg CC_REGNUM)
- (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
+ (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
(match_operand:DI 1 "register_operand" "0,0"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))]
(define_insn "*adddi3_zero"
[(set (match_operand:DI 0 "register_operand" "=d,d")
- (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
+ (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
(match_operand:DI 1 "register_operand" "0,0")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH"
ah\t%0,%2
ahy\t%0,%2"
[(set_attr "op_type" "RX,RXY")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "z196prop" "z196_cracked,z196_cracked")])
;
; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
(define_insn "*add<mode>3"
- [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS")
- (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0")
- (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) )
+ [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,S")
+ (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0,0")
+ (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T,C") ) )
(clobber (reg:CC CC_REGNUM))]
""
"@
a<y>\t%0,%2
a<g>si\t%0,%c2"
[(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
- (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10")
+ (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,longdisp,z10")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
z10_super_E1,z10_super_E1,z10_super_E1")])
al<y>\t%0,%2
al<g>si\t%0,%c2"
[(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
- (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
+ (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
z10_super_E1,z10_super_E1,z10_super_E1")])
al<g>\t%0,%2
al<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
- (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
(define_insn "*add<mode>3_carry2_cc"
[(set (reg CC_REGNUM)
- (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
- (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
+ (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
+ (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
(match_dup 2)))
- (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
+ (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S")
(plus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL1mode)"
"@
al<y>\t%0,%2
al<g>si\t%0,%c2"
[(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
- (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
+ (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
z10_super_E1,z10_super_E1,z10_super_E1")])
al<g>\t%0,%2
al<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
- (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
(define_insn "*add<mode>3_cc"
[(set (reg CC_REGNUM)
- (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
- (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
+ (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
+ (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
(const_int 0)))
- (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
+ (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S")
(plus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCLmode)"
"@
al<y>\t%0,%2
al<g>si\t%0,%c2"
[(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
- (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
+ (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
*,z10_super_E1,z10_super_E1,z10_super_E1")])
al<g>\t%0,%2
al<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
- (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
; alr, al, aly, algr, alg, alrk, algrk
al<g>\t%0,%2
al<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
- (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
; ahi, afi, aghi, agfi, asi, agsi
(define_insn "*add<mode>3_imm_cc"
[(set (reg CC_REGNUM)
(compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
- (match_operand:GPR 2 "const_int_operand" " K, K,Os, C"))
+ (match_operand:GPR 2 "const_int_operand" " K, K,Os,C"))
(const_int 0)))
- (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS")
+ (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d, S")
(plus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCAmode)
&& (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
;
; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
+; FIXME: wfadb does not clobber cc
(define_insn "add<mode>3"
- [(set (match_operand:FP 0 "register_operand" "=f, f")
- (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
- (match_operand:FP 2 "general_operand" " f,<Rf>")))
+ [(set (match_operand:FP 0 "register_operand" "=f,f,f,v")
+ (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v")
+ (match_operand:FP 2 "general_operand" "f,f,R,v")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT"
"@
- a<xde><bt>r\t%0,<op1>%2
- a<xde>b\t%0,%2"
- [(set_attr "op_type" "<RRer>,RXE")
- (set_attr "type" "fsimp<mode>")])
+ a<xde>tr\t%0,%1,%2
+ a<xde>br\t%0,%2
+ a<xde>b\t%0,%2
+ wfadb\t%v0,%v1,%v2"
+ [(set_attr "op_type" "RRF,RRE,RXE,VRR")
+ (set_attr "type" "fsimp<mode>")
+ (set_attr "cpu_facility" "*,*,*,vx")
+ (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
(define_insn "*add<mode>3_cc"
[(set (reg CC_REGNUM)
- (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
- (match_operand:FP 2 "general_operand" " f,<Rf>"))
+ (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0")
+ (match_operand:FP 2 "general_operand" "f,f,R"))
(match_operand:FP 3 "const0_operand" "")))
- (set (match_operand:FP 0 "register_operand" "=f,f")
+ (set (match_operand:FP 0 "register_operand" "=f,f,f")
(plus:FP (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
"@
- a<xde><bt>r\t%0,<op1>%2
+ a<xde>tr\t%0,%1,%2
+ a<xde>br\t%0,%2
a<xde>b\t%0,%2"
- [(set_attr "op_type" "<RRer>,RXE")
- (set_attr "type" "fsimp<mode>")])
+ [(set_attr "op_type" "RRF,RRE,RXE")
+ (set_attr "type" "fsimp<mode>")
+ (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")])
; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
(define_insn "*add<mode>3_cconly"
[(set (reg CC_REGNUM)
- (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
- (match_operand:FP 2 "general_operand" " f,<Rf>"))
+ (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0")
+ (match_operand:FP 2 "general_operand" "f,f,R"))
(match_operand:FP 3 "const0_operand" "")))
- (clobber (match_scratch:FP 0 "=f,f"))]
+ (clobber (match_scratch:FP 0 "=f,f,f"))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
"@
- a<xde><bt>r\t%0,<op1>%2
+ a<xde>tr\t%0,%1,%2
+ a<xde>br\t%0,%2
a<xde>b\t%0,%2"
- [(set_attr "op_type" "<RRer>,RXE")
- (set_attr "type" "fsimp<mode>")])
+ [(set_attr "op_type" "RRF,RRE,RXE")
+ (set_attr "type" "fsimp<mode>")
+ (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")])
;
; Pointer add instruction patterns
; subti3 instruction pattern(s).
;
-(define_insn_and_split "subti3"
- [(set (match_operand:TI 0 "register_operand" "=&d")
- (minus:TI (match_operand:TI 1 "register_operand" "0")
- (match_operand:TI 2 "general_operand" "do") ) )
+(define_expand "subti3"
+ [(parallel
+ [(set (match_operand:TI 0 "register_operand" "")
+ (minus:TI (match_operand:TI 1 "register_operand" "")
+ (match_operand:TI 2 "general_operand" "") ) )
+ (clobber (reg:CC CC_REGNUM))])]
+ "TARGET_ZARCH"
+{
+ /* For z13 we have vsq which doesn't set CC. */
+ if (TARGET_VX)
+ {
+ emit_insn (gen_rtx_SET (operands[0],
+ gen_rtx_MINUS (TImode,
+ operands[1],
+ copy_to_mode_reg (TImode, operands[2]))));
+ DONE;
+ }
+})
+
+(define_insn_and_split "*subti3"
+ [(set (match_operand:TI 0 "register_operand" "=&d")
+ (minus:TI (match_operand:TI 1 "register_operand" "0")
+ (match_operand:TI 2 "general_operand" "do") ) )
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH"
"#"
operands[5] = operand_subword (operands[2], 0, 0, TImode);
operands[6] = operand_subword (operands[0], 1, 0, TImode);
operands[7] = operand_subword (operands[1], 1, 0, TImode);
- operands[8] = operand_subword (operands[2], 1, 0, TImode);")
+ operands[8] = operand_subword (operands[2], 1, 0, TImode);"
+ [(set_attr "op_type" "*")
+ (set_attr "cpu_facility" "*")])
;
; subdi3 instruction pattern(s).
(define_insn "*subdi3_sign"
[(set (match_operand:DI 0 "register_operand" "=d,d")
(minus:DI (match_operand:DI 1 "register_operand" "0,0")
- (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
+ (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T"))))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH"
"@
(define_insn "*subdi3_zero_cc"
[(set (reg CC_REGNUM)
(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
- (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
+ (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d")
(minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
(define_insn "*subdi3_zero_cconly"
[(set (reg CC_REGNUM)
(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
- (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
+ (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))]
"s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
(define_insn "*subdi3_zero"
[(set (match_operand:DI 0 "register_operand" "=d,d")
(minus:DI (match_operand:DI 1 "register_operand" "0,0")
- (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
+ (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH"
"@
sh\t%0,%2
shy\t%0,%2"
[(set_attr "op_type" "RX,RXY")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "z196prop" "z196_cracked,z196_cracked")])
;
s<g>\t%0,%2
s<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
- (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
; slr, sl, sly, slgr, slg, slrk, slgrk
sl<g>\t%0,%2
sl<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
- (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
; slr, sl, sly, slgr, slg, slrk, slgrk
sl<g>\t%0,%2
sl<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
- (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
; slr, sl, sly, slgr, slg, slrk, slgrk
sl<g>\t%0,%2
sl<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
- (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
; slr, sl, sly, slgr, slg, slrk, slgrk
sl<g>\t%0,%2
sl<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
- (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
; slr, sl, sly, slgr, slg, slrk, slgrk
sl<g>\t%0,%2
sl<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
- (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
sl<g>\t%0,%2
sl<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
- (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
(define_insn "sub<mode>3"
- [(set (match_operand:FP 0 "register_operand" "=f, f")
- (minus:FP (match_operand:FP 1 "register_operand" "<f0>,0")
- (match_operand:FP 2 "general_operand" "f,<Rf>")))
+ [(set (match_operand:FP 0 "register_operand" "=f,f,f,v")
+ (minus:FP (match_operand:FP 1 "register_operand" "f,0,0,v")
+ (match_operand:FP 2 "general_operand" "f,f,R,v")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT"
"@
- s<xde><bt>r\t%0,<op1>%2
- s<xde>b\t%0,%2"
- [(set_attr "op_type" "<RRer>,RXE")
- (set_attr "type" "fsimp<mode>")])
+ s<xde>tr\t%0,%1,%2
+ s<xde>br\t%0,%2
+ s<xde>b\t%0,%2
+ wfsdb\t%v0,%v1,%v2"
+ [(set_attr "op_type" "RRF,RRE,RXE,VRR")
+ (set_attr "type" "fsimp<mode>")
+ (set_attr "cpu_facility" "*,*,*,vx")
+ (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
(define_insn "*sub<mode>3_cc"
[(set (reg CC_REGNUM)
- (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
- (match_operand:FP 2 "general_operand" "f,<Rf>"))
+ (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0")
+ (match_operand:FP 2 "general_operand" "f,f,R"))
(match_operand:FP 3 "const0_operand" "")))
- (set (match_operand:FP 0 "register_operand" "=f,f")
+ (set (match_operand:FP 0 "register_operand" "=f,f,f")
(minus:FP (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
"@
- s<xde><bt>r\t%0,<op1>%2
+ s<xde>tr\t%0,%1,%2
+ s<xde>br\t%0,%2
s<xde>b\t%0,%2"
- [(set_attr "op_type" "<RRer>,RXE")
- (set_attr "type" "fsimp<mode>")])
+ [(set_attr "op_type" "RRF,RRE,RXE")
+ (set_attr "type" "fsimp<mode>")
+ (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")])
; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
(define_insn "*sub<mode>3_cconly"
[(set (reg CC_REGNUM)
- (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
- (match_operand:FP 2 "general_operand" "f,<Rf>"))
+ (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0")
+ (match_operand:FP 2 "general_operand" "f,f,R"))
(match_operand:FP 3 "const0_operand" "")))
- (clobber (match_scratch:FP 0 "=f,f"))]
+ (clobber (match_scratch:FP 0 "=f,f,f"))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
"@
- s<xde><bt>r\t%0,<op1>%2
+ s<xde>tr\t%0,%1,%2
+ s<xde>br\t%0,%2
s<xde>b\t%0,%2"
- [(set_attr "op_type" "<RRer>,RXE")
- (set_attr "type" "fsimp<mode>")])
+ [(set_attr "op_type" "RRF,RRE,RXE")
+ (set_attr "type" "fsimp<mode>")
+ (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")])
;;
(compare
(plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
(match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
- (match_operand:GPR 2 "general_operand" "d,RT"))
+ (match_operand:GPR 2 "general_operand" "d,T"))
(match_dup 1)))
(set (match_operand:GPR 0 "register_operand" "=d,d")
(plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
(compare
(plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
(match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
- (match_operand:GPR 2 "general_operand" "d,RT"))
+ (match_operand:GPR 2 "general_operand" "d,T"))
(match_dup 1)))
(clobber (match_scratch:GPR 0 "=d,d"))]
"s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
(compare
(plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
(match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
- (match_operand:GPR 2 "general_operand" "d,RT"))
+ (match_operand:GPR 2 "general_operand" "d,T"))
(match_dup 2)))
(set (match_operand:GPR 0 "register_operand" "=d,d")
(plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
(compare
(plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
(match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
- (match_operand:GPR 2 "general_operand" "d,RT"))
+ (match_operand:GPR 2 "general_operand" "d,T"))
(match_dup 2)))
(clobber (match_scratch:GPR 0 "=d,d"))]
"s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
(compare
(plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
(match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
- (match_operand:GPR 2 "general_operand" "d,RT"))
+ (match_operand:GPR 2 "general_operand" "d,T"))
(const_int 0)))
(set (match_operand:GPR 0 "register_operand" "=d,d")
(plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
[(set (match_operand:GPR 0 "register_operand" "=d,d")
(plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
(match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
- (match_operand:GPR 2 "general_operand" "d,RT")))
+ (match_operand:GPR 2 "general_operand" "d,T")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_CPU_ZARCH"
"@
[(set (reg CC_REGNUM)
(compare
(minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
- (match_operand:GPR 2 "general_operand" "d,RT"))
+ (match_operand:GPR 2 "general_operand" "d,T"))
(match_operand:GPR 3 "s390_slb_comparison" ""))
(const_int 0)))
(set (match_operand:GPR 0 "register_operand" "=d,d")
(define_insn "*sub<mode>3_slb"
[(set (match_operand:GPR 0 "register_operand" "=d,d")
(minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
- (match_operand:GPR 2 "general_operand" "d,RT"))
+ (match_operand:GPR 2 "general_operand" "d,T"))
(match_operand:GPR 3 "s390_slb_comparison" "")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_CPU_ZARCH"
(match_operand:GPR 2 "nonimmediate_operand" "")
(match_operand:GPR 3 "nonimmediate_operand" "")))]
"TARGET_Z196"
- "operands[1] = s390_emit_compare (GET_CODE (operands[1]),
- XEXP (operands[1], 0), XEXP (operands[1], 1));")
+{
+ /* Emit the comparison insn in case we do not already have a comparison result. */
+ if (!s390_comparison (operands[1], VOIDmode))
+ operands[1] = s390_emit_compare (GET_CODE (operands[1]),
+ XEXP (operands[1], 0),
+ XEXP (operands[1], 1));
+})
-; locr, loc, stoc, locgr, locg, stocg
+; locr, loc, stoc, locgr, locg, stocg, lochi, locghi
(define_insn_and_split "*mov<mode>cc"
- [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d")
+ [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,S,S,&d")
(if_then_else:GPR
(match_operator 1 "s390_comparison"
- [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c")
+ [(match_operand 2 "cc_reg_operand" " c,c,c,c,c,c,c,c,c")
(match_operand 5 "const_int_operand" "")])
- (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS")
- (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))]
+ (match_operand:GPR 3 "loc_operand" " d,0,S,0,K,0,d,0,S")
+ (match_operand:GPR 4 "loc_operand" " 0,d,0,S,0,K,0,d,S")))]
"TARGET_Z196"
"@
loc<g>r%C1\t%0,%3
loc<g>r%D1\t%0,%4
loc<g>%C1\t%0,%3
loc<g>%D1\t%0,%4
+ loc<g>hi%C1\t%0,%h3
+ loc<g>hi%D1\t%0,%h4
stoc<g>%C1\t%3,%0
stoc<g>%D1\t%4,%0
#"
(match_dup 0)
(match_dup 4)))]
""
- [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")])
+ [(set_attr "op_type" "RRF,RRF,RSY,RSY,RIE,RIE,RSY,RSY,*")
+ (set_attr "cpu_facility" "*,*,*,*,z13,z13,*,*,*")])
;;
;;- Multiply instructions.
(define_insn "*muldi3_sign"
[(set (match_operand:DI 0 "register_operand" "=d,d")
- (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
+ (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
(match_operand:DI 1 "register_operand" "0,0")))]
"TARGET_ZARCH"
"@
(define_insn "muldi3"
[(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
(mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
- (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
+ (match_operand:DI 2 "general_operand" "d,K,T,Os")))]
"TARGET_ZARCH"
"@
msgr\t%0,%2
msfi\t%0,%2"
[(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
(set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
- (set_attr "cpu_facility" "*,*,*,*,z10")])
+ (set_attr "cpu_facility" "*,*,*,longdisp,z10")])
;
; mulsidi3 instruction pattern(s).
; mlr, ml, mlgr, mlg
(define_insn "umul<dwh><mode>3"
- [(set (match_operand:DW 0 "register_operand" "=d, d")
+ [(set (match_operand:DW 0 "register_operand" "=d,d")
(mult:DW (zero_extend:DW
- (match_operand:<DWH> 1 "register_operand" "%0, 0"))
+ (match_operand:<DWH> 1 "register_operand" "%0,0"))
(zero_extend:DW
- (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))]
+ (match_operand:<DWH> 2 "nonimmediate_operand" " d,T"))))]
"TARGET_CPU_ZARCH"
"@
ml<tg>r\t%0,%2
; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
(define_insn "mul<mode>3"
- [(set (match_operand:FP 0 "register_operand" "=f,f")
- (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
- (match_operand:FP 2 "general_operand" "f,<Rf>")))]
+ [(set (match_operand:FP 0 "register_operand" "=f,f,f,v")
+ (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v")
+ (match_operand:FP 2 "general_operand" "f,f,R,v")))]
"TARGET_HARD_FLOAT"
"@
- m<xdee><bt>r\t%0,<op1>%2
- m<xdee>b\t%0,%2"
- [(set_attr "op_type" "<RRer>,RXE")
- (set_attr "type" "fmul<mode>")])
+ m<xdee>tr\t%0,%1,%2
+ m<xdee>br\t%0,%2
+ m<xdee>b\t%0,%2
+ wfmdb\t%v0,%v1,%v2"
+ [(set_attr "op_type" "RRF,RRE,RXE,VRR")
+ (set_attr "type" "fmul<mode>")
+ (set_attr "cpu_facility" "*,*,*,vx")
+ (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
; madbr, maebr, maxb, madb, maeb
(define_insn "fma<mode>4"
- [(set (match_operand:DSF 0 "register_operand" "=f,f")
- (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
- (match_operand:DSF 2 "nonimmediate_operand" "f,R")
- (match_operand:DSF 3 "register_operand" "0,0")))]
+ [(set (match_operand:DSF 0 "register_operand" "=f,f,v")
+ (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v")
+ (match_operand:DSF 2 "nonimmediate_operand" "f,R,v")
+ (match_operand:DSF 3 "register_operand" "0,0,v")))]
"TARGET_HARD_FLOAT"
"@
ma<xde>br\t%0,%1,%2
- ma<xde>b\t%0,%1,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fmadd<mode>")])
+ ma<xde>b\t%0,%1,%2
+ wfmadb\t%v0,%v1,%v2,%v3"
+ [(set_attr "op_type" "RRE,RXE,VRR")
+ (set_attr "type" "fmadd<mode>")
+ (set_attr "cpu_facility" "*,*,vx")
+ (set_attr "enabled" "*,*,<DFDI>")])
; msxbr, msdbr, msebr, msxb, msdb, mseb
(define_insn "fms<mode>4"
- [(set (match_operand:DSF 0 "register_operand" "=f,f")
- (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f")
- (match_operand:DSF 2 "nonimmediate_operand" "f,R")
- (neg:DSF (match_operand:DSF 3 "register_operand" "0,0"))))]
+ [(set (match_operand:DSF 0 "register_operand" "=f,f,v")
+ (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v")
+ (match_operand:DSF 2 "nonimmediate_operand" "f,R,v")
+ (neg:DSF (match_operand:DSF 3 "register_operand" "0,0,v"))))]
"TARGET_HARD_FLOAT"
"@
ms<xde>br\t%0,%1,%2
- ms<xde>b\t%0,%1,%2"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fmadd<mode>")])
+ ms<xde>b\t%0,%1,%2
+ wfmsdb\t%v0,%v1,%v2,%v3"
+ [(set_attr "op_type" "RRE,RXE,VRR")
+ (set_attr "type" "fmadd<mode>")
+ (set_attr "cpu_facility" "*,*,vx")
+ (set_attr "enabled" "*,*,<DFDI>")])
;;
;;- Divide and modulo instructions.
(clobber (match_dup 4))]
"TARGET_ZARCH"
{
- rtx insn, div_equal, mod_equal;
+ rtx div_equal, mod_equal;
+ rtx_insn *insn;
div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
(ashift:TI
(zero_extend:TI
(mod:DI (match_operand:DI 1 "register_operand" "0,0")
- (match_operand:DI 2 "general_operand" "d,RT")))
+ (match_operand:DI 2 "general_operand" "d,T")))
(const_int 64))
(zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
"TARGET_ZARCH"
(zero_extend:TI
(mod:DI (match_operand:DI 1 "register_operand" "0,0")
(sign_extend:DI
- (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
+ (match_operand:SI 2 "nonimmediate_operand" "d,T"))))
(const_int 64))
(zero_extend:TI
(div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
(clobber (match_dup 4))]
"TARGET_ZARCH"
{
- rtx insn, div_equal, mod_equal, equal;
+ rtx div_equal, mod_equal, equal;
+ rtx_insn *insn;
div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
(truncate:DI
(umod:TI (match_operand:TI 1 "register_operand" "0,0")
(zero_extend:TI
- (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
+ (match_operand:DI 2 "nonimmediate_operand" "d,T")))))
(const_int 64))
(zero_extend:TI
(truncate:DI
(clobber (match_dup 4))]
"!TARGET_ZARCH"
{
- rtx insn, div_equal, mod_equal, equal;
+ rtx div_equal, mod_equal, equal;
+ rtx_insn *insn;
div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
(clobber (match_dup 4))]
"!TARGET_ZARCH && TARGET_CPU_ZARCH"
{
- rtx insn, div_equal, mod_equal, equal;
+ rtx div_equal, mod_equal, equal;
+ rtx_insn *insn;
div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
(truncate:SI
(umod:DI (match_operand:DI 1 "register_operand" "0,0")
(zero_extend:DI
- (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
+ (match_operand:SI 2 "nonimmediate_operand" "d,T")))))
(const_int 32))
(zero_extend:DI
(truncate:SI
(clobber (match_dup 3))]
"!TARGET_ZARCH && !TARGET_CPU_ZARCH"
{
- rtx insn, udiv_equal, umod_equal, equal;
+ rtx udiv_equal, umod_equal, equal;
+ rtx_insn *insn;
udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
(clobber (match_dup 3))]
"!TARGET_ZARCH && !TARGET_CPU_ZARCH"
{
- rtx insn, udiv_equal, umod_equal, equal;
+ rtx udiv_equal, umod_equal, equal;
+ rtx_insn *insn;
udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
(define_insn "div<mode>3"
- [(set (match_operand:FP 0 "register_operand" "=f,f")
- (div:FP (match_operand:FP 1 "register_operand" "<f0>,0")
- (match_operand:FP 2 "general_operand" "f,<Rf>")))]
+ [(set (match_operand:FP 0 "register_operand" "=f,f,f,v")
+ (div:FP (match_operand:FP 1 "register_operand" "f,0,0,v")
+ (match_operand:FP 2 "general_operand" "f,f,R,v")))]
"TARGET_HARD_FLOAT"
"@
- d<xde><bt>r\t%0,<op1>%2
- d<xde>b\t%0,%2"
- [(set_attr "op_type" "<RRer>,RXE")
- (set_attr "type" "fdiv<mode>")])
+ d<xde>tr\t%0,%1,%2
+ d<xde>br\t%0,%2
+ d<xde>b\t%0,%2
+ wfddb\t%v0,%v1,%v2"
+ [(set_attr "op_type" "RRF,RRE,RXE,VRR")
+ (set_attr "type" "fdiv<mode>")
+ (set_attr "cpu_facility" "*,*,*,vx")
+ (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")])
;;
(define_insn "*anddi3_cc"
[(set (reg CC_REGNUM)
(compare
- (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
- (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d")
+ (match_operand:DI 2 "general_operand" " d,d,T,NxxDw"))
(const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=d,d, d, d")
+ (set (match_operand:DI 0 "register_operand" "=d,d,d, d")
(and:DI (match_dup 1) (match_dup 2)))]
"TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
"@
(define_insn "*anddi3_cconly"
[(set (reg CC_REGNUM)
(compare
- (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
- (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d")
+ (match_operand:DI 2 "general_operand" " d,d,T,NxxDw"))
(const_int 0)))
- (clobber (match_scratch:DI 0 "=d,d, d, d"))]
+ (clobber (match_scratch:DI 0 "=d,d,d, d"))]
"TARGET_ZARCH
&& s390_match_ccmode(insn, CCTmode)
/* Do not steal TM patterns. */
(define_insn "*anddi3"
[(set (match_operand:DI 0 "nonimmediate_operand"
- "=d,d, d, d, d, d, d, d,d,d, d, d, AQ,Q")
+ "=d,d, d, d, d, d, d, d,d,d,d, d, AQ,Q")
(and:DI
(match_operand:DI 1 "nonimmediate_operand"
- "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, d, 0,0")
+ "%d,o, 0, 0, 0, 0, 0, 0,0,d,0, d, 0,0")
(match_operand:DI 2 "general_operand"
- "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q")))
+ "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,T,NxxDw,NxQDF,Q")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
"s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
;; These two are what combine generates for (ashift (zero_extract)).
-(define_insn "*extzv_<mode>_srl"
+(define_insn "*extzv_<mode>_srl<clobbercc_or_nocc>"
[(set (match_operand:GPR 0 "register_operand" "=d")
(and:GPR (lshiftrt:GPR
(match_operand:GPR 1 "register_operand" "d")
(match_operand:GPR 2 "nonzero_shift_count_operand" ""))
- (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_Z10
+ (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))]
+ "<z10_or_zEC12_cond>
/* Note that even for the SImode pattern, the rotate is always DImode. */
&& s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]),
INTVAL (operands[3]))"
- "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2"
+ "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2"
[(set_attr "op_type" "RIE")
(set_attr "z10prop" "z10_super_E1")])
-(define_insn "*extzv_<mode>_sll"
+(define_insn "*extzv_<mode>_sll<clobbercc_or_nocc>"
[(set (match_operand:GPR 0 "register_operand" "=d")
(and:GPR (ashift:GPR
(match_operand:GPR 1 "register_operand" "d")
(match_operand:GPR 2 "nonzero_shift_count_operand" ""))
- (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_Z10
+ (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))]
+ "<z10_or_zEC12_cond>
&& s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]),
INTVAL (operands[3]))"
- "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,%2"
+ "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,%2"
[(set_attr "op_type" "RIE")
(set_attr "z10prop" "z10_super_E1")])
ny\t%0,%2
risbg\t%0,%1,%t2,128+%f2,0"
[(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
- (set_attr "cpu_facility" "*,*,z196,*,*,z10")
+ (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
z10_super_E1,z10_super_E1,z10_super_E1")])
ny\t%0,%2
risbg\t%0,%1,%t2,128+%f2,0"
[(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
- (set_attr "cpu_facility" "*,*,z196,*,*,z10")
+ (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
z10_super_E1,z10_super_E1,z10_super_E1")])
(and:SI (match_operand:SI 1 "nonimmediate_operand"
"%d,o, 0, 0, 0,0,d,0,0, d, 0,0")
(match_operand:SI 2 "general_operand"
- " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q")))
+ " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSw,NxQSF,Q")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
#
#"
[(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
- (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*")
+ (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,longdisp,z10,*,*")
(set_attr "z10prop" "*,
*,
z10_super_E1,
niy\t%S0,%b2
#"
[(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
- (set_attr "cpu_facility" "*,z196,*,*,*,*")
+ (set_attr "cpu_facility" "*,z196,*,*,longdisp,*")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
(define_insn "*andqi3_esa"
[(set_attr "op_type" "RR,SI,SS")
(set_attr "z10prop" "z10_super_E1,z10_super,*")])
+;
+; And with complement
+;
+; c = ~b & a = (b & a) ^ a
+
+(define_insn_and_split "*andc_split_<mode>"
+ [(set (match_operand:GPR 0 "nonimmediate_operand" "")
+ (and:GPR (not:GPR (match_operand:GPR 1 "nonimmediate_operand" ""))
+ (match_operand:GPR 2 "general_operand" "")))
+ (clobber (reg:CC CC_REGNUM))]
+ "! reload_completed
+ && (GET_CODE (operands[0]) != MEM
+ /* Ensure that s390_logical_operator_ok_p will succeed even
+ on the split xor if (b & a) is stored into a pseudo. */
+ || rtx_equal_p (operands[0], operands[2]))"
+ "#"
+ "&& 1"
+ [
+ (parallel
+ [(set (match_dup 3) (and:GPR (match_dup 1) (match_dup 2)))
+ (clobber (reg:CC CC_REGNUM))])
+ (parallel
+ [(set (match_dup 0) (xor:GPR (match_dup 3) (match_dup 2)))
+ (clobber (reg:CC CC_REGNUM))])]
+{
+ if (reg_overlap_mentioned_p (operands[0], operands[2]))
+ operands[3] = gen_reg_rtx (<MODE>mode);
+ else
+ operands[3] = operands[0];
+})
+
;
; Block and (NC) patterns.
;
(define_insn "*iordi3_cc"
[(set (reg CC_REGNUM)
- (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
- (match_operand:DI 2 "general_operand" " d,d,RT"))
+ (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
+ (match_operand:DI 2 "general_operand" " d,d,T"))
(const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=d,d, d")
+ (set (match_operand:DI 0 "register_operand" "=d,d,d")
(ior:DI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@
(define_insn "*iordi3_cconly"
[(set (reg CC_REGNUM)
(compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
- (match_operand:DI 2 "general_operand" " d,d,RT"))
+ (match_operand:DI 2 "general_operand" " d,d,T"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
(define_insn "*iordi3"
[(set (match_operand:DI 0 "nonimmediate_operand"
- "=d, d, d, d, d, d,d,d, d, AQ,Q")
+ "=d, d, d, d, d, d,d,d,d, AQ,Q")
(ior:DI (match_operand:DI 1 "nonimmediate_operand"
- " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0")
+ " %0, 0, 0, 0, 0, 0,0,d,0, 0,0")
(match_operand:DI 2 "general_operand"
- "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
+ "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,T,NxQD0,Q")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
o\t%0,%2
oy\t%0,%2"
[(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
- (set_attr "cpu_facility" "*,*,z196,*,*")
+ (set_attr "cpu_facility" "*,*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
(define_insn "*iorsi3_cconly"
o\t%0,%2
oy\t%0,%2"
[(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
- (set_attr "cpu_facility" "*,*,z196,*,*")
+ (set_attr "cpu_facility" "*,*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
(define_insn "*iorsi3_zarch"
#
#"
[(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
- (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*")
+ (set_attr "cpu_facility" "*,*,*,*,z196,*,longdisp,*,*")
(set_attr "z10prop" "z10_super_E1,
z10_super_E1,
z10_super_E1,
oiy\t%S0,%b2
#"
[(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
- (set_attr "cpu_facility" "*,z196,*,*,*,*")
+ (set_attr "cpu_facility" "*,z196,*,*,longdisp,*")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
z10_super,z10_super,*")])
(define_insn "*xordi3_cc"
[(set (reg CC_REGNUM)
- (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
- (match_operand:DI 2 "general_operand" " d,d,RT"))
+ (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
+ (match_operand:DI 2 "general_operand" " d,d,T"))
(const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=d,d, d")
+ (set (match_operand:DI 0 "register_operand" "=d,d,d")
(xor:DI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@
(define_insn "*xordi3_cconly"
[(set (reg CC_REGNUM)
- (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
- (match_operand:DI 2 "general_operand" " d,d,RT"))
+ (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
+ (match_operand:DI 2 "general_operand" " d,d,T"))
(const_int 0)))
- (clobber (match_scratch:DI 0 "=d,d, d"))]
+ (clobber (match_scratch:DI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@
xgr\t%0,%2
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
(define_insn "*xordi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q")
- (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0")
- (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d,d, AQ,Q")
+ (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d,0, 0,0")
+ (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,T,NxQD0,Q")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
x\t%0,%2
xy\t%0,%2"
[(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
- (set_attr "cpu_facility" "*,*,z196,*,*")
+ (set_attr "cpu_facility" "*,*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
z10_super_E1,z10_super_E1")])
x\t%0,%2
xy\t%0,%2"
[(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
- (set_attr "cpu_facility" "*,*,z196,*,*")
+ (set_attr "cpu_facility" "*,*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
z10_super_E1,z10_super_E1")])
#
#"
[(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS")
- (set_attr "cpu_facility" "*,*,z196,*,*,*,*")
+ (set_attr "cpu_facility" "*,*,z196,*,longdisp,*,*")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
z10_super_E1,z10_super_E1,*,*")])
xiy\t%S0,%b2
#"
[(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS")
- (set_attr "cpu_facility" "*,*,z196,*,*,*")
+ (set_attr "cpu_facility" "*,*,z196,*,longdisp,*")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
(set_attr "type" "fsimp<mode>")])
; lcxbr, lcdbr, lcebr
+; FIXME: wflcdb does not clobber cc
(define_insn "*neg<mode>2"
- [(set (match_operand:BFP 0 "register_operand" "=f")
- (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
+ [(set (match_operand:BFP 0 "register_operand" "=f,v")
+ (neg:BFP (match_operand:BFP 1 "register_operand" "f,v")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT"
- "lc<xde>br\t%0,%1"
- [(set_attr "op_type" "RRE")
- (set_attr "type" "fsimp<mode>")])
+ "@
+ lc<xde>br\t%0,%1
+ wflcdb\t%0,%1"
+ [(set_attr "op_type" "RRE,VRR")
+ (set_attr "cpu_facility" "*,vx")
+ (set_attr "type" "fsimp<mode>,*")
+ (set_attr "enabled" "*,<DFDI>")])
;;
(set_attr "type" "fsimp<mode>")])
; lpxbr, lpdbr, lpebr
+; FIXME: wflpdb does not clobber cc
(define_insn "*abs<mode>2"
- [(set (match_operand:BFP 0 "register_operand" "=f")
- (abs:BFP (match_operand:BFP 1 "register_operand" "f")))
+ [(set (match_operand:BFP 0 "register_operand" "=f,v")
+ (abs:BFP (match_operand:BFP 1 "register_operand" "f,v")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT"
- "lp<xde>br\t%0,%1"
- [(set_attr "op_type" "RRE")
- (set_attr "type" "fsimp<mode>")])
+ "@
+ lp<xde>br\t%0,%1
+ wflpdb\t%0,%1"
+ [(set_attr "op_type" "RRE,VRR")
+ (set_attr "cpu_facility" "*,vx")
+ (set_attr "type" "fsimp<mode>,*")
+ (set_attr "enabled" "*,<DFDI>")])
;;
(set_attr "type" "fsimp<mode>")])
; lnxbr, lndbr, lnebr
+; FIXME: wflndb does not clobber cc
(define_insn "*negabs<mode>2"
- [(set (match_operand:BFP 0 "register_operand" "=f")
- (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))))
+ [(set (match_operand:BFP 0 "register_operand" "=f,v")
+ (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f,v"))))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT"
- "ln<xde>br\t%0,%1"
- [(set_attr "op_type" "RRE")
- (set_attr "type" "fsimp<mode>")])
+ "@
+ ln<xde>br\t%0,%1
+ wflndb\t%0,%1"
+ [(set_attr "op_type" "RRE,VRR")
+ (set_attr "cpu_facility" "*,vx")
+ (set_attr "type" "fsimp<mode>,*")
+ (set_attr "enabled" "*,<DFDI>")])
;;
;;- Square root instructions.
; sqxbr, sqdbr, sqebr, sqdb, sqeb
(define_insn "sqrt<mode>2"
- [(set (match_operand:BFP 0 "register_operand" "=f,f")
- (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>")))]
+ [(set (match_operand:BFP 0 "register_operand" "=f,f,v")
+ (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,R,v")))]
"TARGET_HARD_FLOAT"
"@
sq<xde>br\t%0,%1
- sq<xde>b\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsqrt<mode>")])
+ sq<xde>b\t%0,%1
+ wfsqdb\t%v0,%v1"
+ [(set_attr "op_type" "RRE,RXE,VRR")
+ (set_attr "type" "fsqrt<mode>")
+ (set_attr "cpu_facility" "*,*,vx")
+ (set_attr "enabled" "*,<DSF>,<DFDI>")])
;;
(clz:DI (match_operand:DI 1 "register_operand" "d")))]
"TARGET_EXTIMM && TARGET_ZARCH"
{
- rtx insn, clz_equal;
+ rtx_insn *insn;
+ rtx clz_equal;
rtx wide_reg = gen_reg_rtx (TImode);
- rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
+ rtx msb = gen_rtx_CONST_INT (DImode, HOST_WIDE_INT_1U << 63);
clz_equal = gen_rtx_CLZ (DImode, operands[1]);
(const_int 64))
(zero_extend:TI (clz:DI (match_dup 1)))))
(clobber (reg:CC CC_REGNUM))]
- "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
- == (unsigned HOST_WIDE_INT) 1 << 63
+ "UINTVAL (operands[2]) == HOST_WIDE_INT_1U << 63
&& TARGET_EXTIMM && TARGET_ZARCH"
"flogr\t%0,%1"
[(set_attr "op_type" "RRE")])
; rotl(di|si)3 instruction pattern(s).
;
-; rll, rllg
-(define_insn "rotl<mode>3"
- [(set (match_operand:GPR 0 "register_operand" "=d")
- (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
- (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
+(define_expand "rotl<mode>3"
+ [(set (match_operand:GPR 0 "register_operand" "")
+ (rotate:GPR (match_operand:GPR 1 "register_operand" "")
+ (match_operand:SI 2 "nonmemory_operand" "")))]
"TARGET_CPU_ZARCH"
- "rll<g>\t%0,%1,%Y2"
- [(set_attr "op_type" "RSE")
- (set_attr "atype" "reg")
- (set_attr "z10prop" "z10_super_E1")])
+ "")
; rll, rllg
-(define_insn "*rotl<mode>3_and"
- [(set (match_operand:GPR 0 "register_operand" "=d")
- (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
- (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
- (match_operand:SI 3 "const_int_operand" "n"))))]
- "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
- "rll<g>\t%0,%1,%Y2"
+(define_insn "*rotl<mode>3<addr_style_op><masked_op>"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:SI 2 "nonmemory_operand" "an")))]
+ "TARGET_CPU_ZARCH"
+ "rll<g>\t%0,%1,<addr_style_op_ops>"
[(set_attr "op_type" "RSE")
(set_attr "atype" "reg")
- (set_attr "z10prop" "z10_super_E1")])
+ (set_attr "z10prop" "z10_super_E1")])
;;
(define_expand "<shift><mode>3"
[(set (match_operand:DSI 0 "register_operand" "")
(SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
- (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
+ (match_operand:SI 2 "nonmemory_operand" "")))]
""
"")
+; ESA 64 bit register pair shift with reg or imm shift count
; sldl, srdl
-(define_insn "*<shift>di3_31"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
+(define_insn "*<shift>di3_31<addr_style_op><masked_op>"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
+ (match_operand:SI 2 "nonmemory_operand" "an")))]
"!TARGET_ZARCH"
- "s<lr>dl\t%0,%Y2"
+ "s<lr>dl\t%0,<addr_style_op_ops>"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")
(set_attr "z196prop" "z196_cracked")])
+
+; 64 bit register shift with reg or imm shift count
; sll, srl, sllg, srlg, sllk, srlk
-(define_insn "*<shift><mode>3"
- [(set (match_operand:GPR 0 "register_operand" "=d,d")
- (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
- (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))]
+(define_insn "*<shift><mode>3<addr_style_op><masked_op>"
+ [(set (match_operand:GPR 0 "register_operand" "=d, d")
+ (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>, d")
+ (match_operand:SI 2 "nonmemory_operand" "an,an")))]
""
"@
- s<lr>l<g>\t%0,<1>%Y2
- s<lr>l<gk>\t%0,%1,%Y2"
- [(set_attr "op_type" "RS<E>,RSY")
- (set_attr "atype" "reg,reg")
- (set_attr "cpu_facility" "*,z196")
- (set_attr "z10prop" "z10_super_E1,*")])
-
-; sldl, srdl
-(define_insn "*<shift>di3_31_and"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
- (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
- (match_operand:SI 3 "const_int_operand" "n"))))]
- "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
- "s<lr>dl\t%0,%Y2"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "reg")])
-
-; sll, srl, sllg, srlg, sllk, srlk
-(define_insn "*<shift><mode>3_and"
- [(set (match_operand:GPR 0 "register_operand" "=d,d")
- (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
- (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
- (match_operand:SI 3 "const_int_operand" "n,n"))))]
- "(INTVAL (operands[3]) & 63) == 63"
- "@
- s<lr>l<g>\t%0,<1>%Y2
- s<lr>l<gk>\t%0,%1,%Y2"
+ s<lr>l<g>\t%0,<1><addr_style_op_ops>
+ s<lr>l<gk>\t%0,%1,<addr_style_op_ops>"
[(set_attr "op_type" "RS<E>,RSY")
(set_attr "atype" "reg,reg")
(set_attr "cpu_facility" "*,z196")
- (set_attr "z10prop" "z10_super_E1,*")])
+ (set_attr "z10prop" "z10_super_E1,*")])
;
; ashr(di|si)3 instruction pattern(s).
[(parallel
[(set (match_operand:DSI 0 "register_operand" "")
(ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
- (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
+ (match_operand:SI 2 "nonmemory_operand" "")))
(clobber (reg:CC CC_REGNUM))])]
""
"")
-(define_insn "*ashrdi3_cc_31"
- [(set (reg CC_REGNUM)
- (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
- (const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=d")
- (ashiftrt:DI (match_dup 1) (match_dup 2)))]
- "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
- "srda\t%0,%Y2"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "reg")])
-
-(define_insn "*ashrdi3_cconly_31"
- [(set (reg CC_REGNUM)
- (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
- (const_int 0)))
- (clobber (match_scratch:DI 0 "=d"))]
- "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
- "srda\t%0,%Y2"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "reg")])
-
-(define_insn "*ashrdi3_31"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
+; FIXME: The number of alternatives is doubled here to match the fix
+; number of 2 in the subst pattern for the (clobber (match_scratch...
+; The right fix should be to support match_scratch in the output
+; pattern of a define_subst.
+(define_insn "*ashrdi3_31<addr_style_op_cc><masked_op_cc><setcc><cconly>"
+ [(set (match_operand:DI 0 "register_operand" "=d, d")
+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "0, 0")
+ (match_operand:SI 2 "nonmemory_operand" "an,an")))
(clobber (reg:CC CC_REGNUM))]
"!TARGET_ZARCH"
- "srda\t%0,%Y2"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "reg")])
-
-; sra, srag, srak
-(define_insn "*ashr<mode>3_cc"
- [(set (reg CC_REGNUM)
- (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
- (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
- (const_int 0)))
- (set (match_operand:GPR 0 "register_operand" "=d,d")
- (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
- "s390_match_ccmode(insn, CCSmode)"
"@
- sra<g>\t%0,<1>%Y2
- sra<gk>\t%0,%1,%Y2"
- [(set_attr "op_type" "RS<E>,RSY")
- (set_attr "atype" "reg,reg")
- (set_attr "cpu_facility" "*,z196")
- (set_attr "z10prop" "z10_super_E1,*")])
+ srda\t%0,<addr_style_op_cc_ops>
+ srda\t%0,<addr_style_op_cc_ops>"
+ [(set_attr "op_type" "RS")
+ (set_attr "atype" "reg")])
-; sra, srag, srak
-(define_insn "*ashr<mode>3_cconly"
- [(set (reg CC_REGNUM)
- (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
- (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
- (const_int 0)))
- (clobber (match_scratch:GPR 0 "=d,d"))]
- "s390_match_ccmode(insn, CCSmode)"
- "@
- sra<g>\t%0,<1>%Y2
- sra<gk>\t%0,%1,%Y2"
- [(set_attr "op_type" "RS<E>,RSY")
- (set_attr "atype" "reg,reg")
- (set_attr "cpu_facility" "*,z196")
- (set_attr "z10prop" "z10_super_E1,*")])
; sra, srag
-(define_insn "*ashr<mode>3"
- [(set (match_operand:GPR 0 "register_operand" "=d,d")
- (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
- (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))
+(define_insn "*ashr<mode>3<addr_style_op_cc><masked_op_cc><setcc><cconly>"
+ [(set (match_operand:GPR 0 "register_operand" "=d, d")
+ (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>, d")
+ (match_operand:SI 2 "nonmemory_operand" "an,an")))
(clobber (reg:CC CC_REGNUM))]
""
"@
- sra<g>\t%0,<1>%Y2
- sra<gk>\t%0,%1,%Y2"
- [(set_attr "op_type" "RS<E>,RSY")
- (set_attr "atype" "reg,reg")
- (set_attr "cpu_facility" "*,z196")
- (set_attr "z10prop" "z10_super_E1,*")])
-
-
-; shift pattern with implicit ANDs
-
-(define_insn "*ashrdi3_cc_31_and"
- [(set (reg CC_REGNUM)
- (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
- (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
- (match_operand:SI 3 "const_int_operand" "n")))
- (const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=d")
- (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
- "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
- && (INTVAL (operands[3]) & 63) == 63"
- "srda\t%0,%Y2"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "reg")])
-
-(define_insn "*ashrdi3_cconly_31_and"
- [(set (reg CC_REGNUM)
- (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
- (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
- (match_operand:SI 3 "const_int_operand" "n")))
- (const_int 0)))
- (clobber (match_scratch:DI 0 "=d"))]
- "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
- && (INTVAL (operands[3]) & 63) == 63"
- "srda\t%0,%Y2"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "reg")])
-
-(define_insn "*ashrdi3_31_and"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
- (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
- (match_operand:SI 3 "const_int_operand" "n"))))
- (clobber (reg:CC CC_REGNUM))]
- "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
- "srda\t%0,%Y2"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "reg")])
-
-; sra, srag, srak
-(define_insn "*ashr<mode>3_cc_and"
- [(set (reg CC_REGNUM)
- (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
- (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
- (match_operand:SI 3 "const_int_operand" "n,n")))
- (const_int 0)))
- (set (match_operand:GPR 0 "register_operand" "=d,d")
- (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
- "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
- "@
- sra<g>\t%0,<1>%Y2
- sra<gk>\t%0,%1,%Y2"
- [(set_attr "op_type" "RS<E>,RSY")
- (set_attr "atype" "reg,reg")
- (set_attr "cpu_facility" "*,z196")
- (set_attr "z10prop" "z10_super_E1,*")])
-
-; sra, srag, srak
-(define_insn "*ashr<mode>3_cconly_and"
- [(set (reg CC_REGNUM)
- (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
- (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
- (match_operand:SI 3 "const_int_operand" "n,n")))
- (const_int 0)))
- (clobber (match_scratch:GPR 0 "=d,d"))]
- "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
- "@
- sra<g>\t%0,<1>%Y2
- sra<gk>\t%0,%1,%Y2"
- [(set_attr "op_type" "RS<E>,RSY")
- (set_attr "atype" "reg,reg")
- (set_attr "cpu_facility" "*,z196")
- (set_attr "z10prop" "z10_super_E1,*")])
-
-; sra, srag, srak
-(define_insn "*ashr<mode>3_and"
- [(set (match_operand:GPR 0 "register_operand" "=d,d")
- (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
- (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
- (match_operand:SI 3 "const_int_operand" "n,n"))))
- (clobber (reg:CC CC_REGNUM))]
- "(INTVAL (operands[3]) & 63) == 63"
- "@
- sra<g>\t%0,<1>%Y2
- sra<gk>\t%0,%1,%Y2"
+ sra<g>\t%0,<1><addr_style_op_cc_ops>
+ sra<gk>\t%0,%1,<addr_style_op_cc_ops>"
[(set_attr "op_type" "RS<E>,RSY")
- (set_attr "atype" "reg,reg")
+ (set_attr "atype" "reg")
(set_attr "cpu_facility" "*,z196")
(set_attr "z10prop" "z10_super_E1,*")])
; clrt, clgrt, clfit, clgit, clt, clgt
(define_insn "*cmp_and_trap_unsigned_int<mode>"
[(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
- [(match_operand:GPR 1 "register_operand" "d,d, d")
- (match_operand:GPR 2 "general_operand" "d,D,RT")])
+ [(match_operand:GPR 1 "register_operand" "d,d,d")
+ (match_operand:GPR 2 "general_operand" "d,D,T")])
(const_int 0))]
"TARGET_Z10"
"@
; lat, lgat
(define_insn "*load_and_trap<mode>"
- [(trap_if (eq (match_operand:GPR 0 "memory_operand" "RT")
+ [(trap_if (eq (match_operand:GPR 0 "memory_operand" "T")
(const_int 0))
(const_int 0))
(set (match_operand:GPR 1 "register_operand" "=d")
(if_then_else
(ne (match_operand:SI 1 "register_operand" "d")
(const_int 1))
- (match_operand 0 "address_operand" "ZQZR")
+ (match_operand 0 "address_operand" "ZR")
(pc)))
(set (match_operand:SI 2 "register_operand" "=1")
(plus:SI (match_dup 1) (const_int -1)))
;
(define_insn "indirect_jump"
- [(set (pc) (match_operand 0 "address_operand" "ZQZR"))]
+ [(set (pc) (match_operand 0 "address_operand" "ZR"))]
""
{
if (get_attr_op_type (insn) == OP_TYPE_RR)
;
(define_insn "casesi_jump"
- [(set (pc) (match_operand 0 "address_operand" "ZQZR"))
+ [(set (pc) (match_operand 0 "address_operand" "ZR"))
(use (label_ref (match_operand 1 "" "")))]
""
{
(set_attr "z196prop" "z196_cracked")])
(define_insn "*basr"
- [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
+ [(call (mem:QI (match_operand 0 "address_operand" "ZR"))
(match_operand 1 "const_int_operand" "n"))
(clobber (match_operand 2 "register_operand" "=r"))]
"!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
(define_insn "*basr_r"
[(set (match_operand 0 "" "")
- (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
+ (call (mem:QI (match_operand 1 "address_operand" "ZR"))
(match_operand 2 "const_int_operand" "n")))
(clobber (match_operand 3 "register_operand" "=r"))]
"!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
(define_insn "*tls_load_64"
[(set (match_operand:DI 0 "register_operand" "=d")
- (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
+ (unspec:DI [(match_operand:DI 1 "memory_operand" "T")
(match_operand:DI 2 "" "")]
UNSPEC_TLS_LOAD))]
"TARGET_64BIT"
ly\t%0,%1%J2"
[(set_attr "op_type" "RX,RXY")
(set_attr "type" "load")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
(define_insn "*bras_tls"
(define_insn "*basr_tls"
[(set (match_operand 0 "" "")
- (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
+ (call (mem:QI (match_operand 1 "address_operand" "ZR"))
(match_operand 2 "const_int_operand" "n")))
(clobber (match_operand 3 "register_operand" "=r"))
(use (match_operand 4 "" ""))]
ld\t%0,%1
ldy\t%0,%1"
[(set_attr "op_type" "RS,RSY,RS,RSY")
+ (set_attr "cpu_facility" "*,longdisp,*,longdisp")
(set_attr "type" "lm,lm,floaddf,floaddf")])
(define_insn "atomic_loadti_1"
[(set (match_operand:TI 0 "register_operand" "=r")
- (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")]
+ (unspec:TI [(match_operand:TI 1 "memory_operand" "T")]
UNSPEC_MOVA))]
"TARGET_ZARCH"
"lpq\t%0,%1"
std %1,%0
stdy %1,%0"
[(set_attr "op_type" "RS,RSY,RS,RSY")
+ (set_attr "cpu_facility" "*,longdisp,*,longdisp")
(set_attr "type" "stm,stm,fstoredf,fstoredf")])
(define_insn "atomic_storeti_1"
- [(set (match_operand:TI 0 "memory_operand" "=RT")
+ [(set (match_operand:TI 0 "memory_operand" "=T")
(unspec:TI [(match_operand:TI 1 "register_operand" "r")]
UNSPEC_MOVA))]
"TARGET_ZARCH"
; cdsg, csg
(define_insn "*atomic_compare_and_swap<mode>_1"
[(set (match_operand:TDI 0 "register_operand" "=r")
- (match_operand:TDI 1 "memory_operand" "+QS"))
+ (match_operand:TDI 1 "memory_operand" "+S"))
(set (match_dup 1)
(unspec_volatile:TDI
[(match_dup 1)
cds\t%0,%3,%S1
cdsy\t%0,%3,%S1"
[(set_attr "op_type" "RS,RSY")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "type" "sem")])
; cs, csy
cs\t%0,%3,%S1
csy\t%0,%3,%S1"
[(set_attr "op_type" "RS,RSY")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "type" "sem")])
;
; lan, lang, lao, laog, lax, laxg, laa, laag
(define_insn "atomic_fetch_<atomic><mode>_iaf"
[(set (match_operand:GPR 0 "register_operand" "=d")
- (match_operand:GPR 1 "memory_operand" "+QS"))
+ (match_operand:GPR 1 "memory_operand" "+S"))
(set (match_dup 1)
(unspec_volatile:GPR
[(ATOMIC_Z196:GPR (match_dup 1)
(define_insn "nop_2_byte"
[(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)]
""
- "nopr\t%%r7"
+ "nopr\t%%r0"
[(set_attr "op_type" "RR")])
(define_insn "nop_4_byte"
(define_insn "pool_section_start"
[(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
""
- ".section\t.rodata"
+{
+ switch_to_section (targetm.asm_out.function_rodata_section
+ (current_function_decl));
+ return "";
+}
[(set_attr "length" "0")])
(define_insn "pool_section_end"
[(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
""
- ".previous"
+{
+ switch_to_section (current_function_section ());
+ return "";
+}
[(set_attr "length" "0")])
(define_insn "main_base_31_small"
[(set_attr "length" "0")])
+(define_insn "stack_restore_from_fpr"
+ [(set (reg:DI STACK_REGNUM)
+ (match_operand:DI 0 "register_operand" "f"))
+ (clobber (mem:BLK (scratch)))]
+ "TARGET_Z10"
+ "lgdr\t%%r15,%0"
+ [(set_attr "op_type" "RRE")])
+
;
; Data prefetch patterns
;
(define_insn "prefetch"
- [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X")
- (match_operand:SI 1 "const_int_operand" " n,n")
- (match_operand:SI 2 "const_int_operand" " n,n"))]
+ [(prefetch (match_operand 0 "address_operand" "ZT,X")
+ (match_operand:SI 1 "const_int_operand" " n,n")
+ (match_operand:SI 2 "const_int_operand" " n,n"))]
"TARGET_Z10"
{
switch (which_alternative)
case 1:
if (larl_operand (operands[0], Pmode))
return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
+ /* fallthrough */
default:
/* This might be reached for symbolic operands with an odd
; Byte swap instructions
;
+; FIXME: There is also mvcin but we cannot use it since src and target
+; may overlap.
+; lrvr, lrv, strv, lrvgr, lrvg, strvg
(define_insn "bswap<mode>2"
- [(set (match_operand:GPR 0 "register_operand" "=d, d")
- (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))]
+ [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,T")
+ (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,T,d")))]
"TARGET_CPU_ZARCH"
"@
lrv<g>r\t%0,%1
- lrv<g>\t%0,%1"
- [(set_attr "type" "*,load")
- (set_attr "op_type" "RRE,RXY")
+ lrv<g>\t%0,%1
+ strv<g>\t%1,%0"
+ [(set_attr "type" "*,load,store")
+ (set_attr "op_type" "RRE,RXY,RXY")
+ (set_attr "z10prop" "z10_super")])
+
+(define_insn "bswaphi2"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,T")
+ (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,T,d")))]
+ "TARGET_CPU_ZARCH"
+ "@
+ #
+ lrvh\t%0,%1
+ strvh\t%1,%0"
+ [(set_attr "type" "*,load,store")
+ (set_attr "op_type" "RRE,RXY,RXY")
(set_attr "z10prop" "z10_super")])
+(define_split
+ [(set (match_operand:HI 0 "register_operand" "")
+ (bswap:HI (match_operand:HI 1 "register_operand" "")))]
+ "TARGET_CPU_ZARCH"
+ [(set (match_dup 2) (bswap:SI (match_dup 3)))
+ (set (match_dup 2) (lshiftrt:SI (match_dup 2) (const_int 16)))]
+{
+ operands[2] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
+ operands[3] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
+})
+
;
; Population count instruction
DONE;
})
+; Clobber VRs since they don't get restored
+(define_insn "tbegin_1_z13"
+ [(set (reg:CCRAW CC_REGNUM)
+ (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
+ UNSPECV_TBEGIN))
+ (set (match_operand:BLK 1 "memory_operand" "=Q")
+ (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))
+ (clobber (reg:TI 16)) (clobber (reg:TI 38))
+ (clobber (reg:TI 17)) (clobber (reg:TI 39))
+ (clobber (reg:TI 18)) (clobber (reg:TI 40))
+ (clobber (reg:TI 19)) (clobber (reg:TI 41))
+ (clobber (reg:TI 20)) (clobber (reg:TI 42))
+ (clobber (reg:TI 21)) (clobber (reg:TI 43))
+ (clobber (reg:TI 22)) (clobber (reg:TI 44))
+ (clobber (reg:TI 23)) (clobber (reg:TI 45))
+ (clobber (reg:TI 24)) (clobber (reg:TI 46))
+ (clobber (reg:TI 25)) (clobber (reg:TI 47))
+ (clobber (reg:TI 26)) (clobber (reg:TI 48))
+ (clobber (reg:TI 27)) (clobber (reg:TI 49))
+ (clobber (reg:TI 28)) (clobber (reg:TI 50))
+ (clobber (reg:TI 29)) (clobber (reg:TI 51))
+ (clobber (reg:TI 30)) (clobber (reg:TI 52))
+ (clobber (reg:TI 31)) (clobber (reg:TI 53))]
+; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is
+; not supposed to be used for immediates (see genpreds.c).
+ "TARGET_VX && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff"
+ "tbegin\t%1,%x0"
+ [(set_attr "op_type" "SIL")])
+
(define_insn "tbegin_1"
[(set (reg:CCRAW CC_REGNUM)
(unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")]
; Transaction abort
(define_expand "tabort"
- [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "")]
+ [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "")]
UNSPECV_TABORT)]
"TARGET_HTM && operands != NULL"
{
if (CONST_INT_P (operands[0])
&& INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255)
{
- error ("Invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC
+ error ("invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC
". Values in range 0 through 255 are reserved.",
INTVAL (operands[0]));
FAIL;
})
(define_insn "*tabort_1"
- [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "Y")]
+ [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "aJ")]
UNSPECV_TABORT)]
"TARGET_HTM && operands != NULL"
"tabort\t%Y0"
[(set_attr "op_type" "S")])
+(define_insn "*tabort_1_plus"
+ [(unspec_volatile [(plus:SI (match_operand:SI 0 "register_operand" "a")
+ (match_operand:SI 1 "const_int_operand" "J"))]
+ UNSPECV_TABORT)]
+ "TARGET_HTM && operands != NULL
+ && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'J', \"J\")"
+ "tabort\t%1(%0)"
+ [(set_attr "op_type" "S")])
+
; Transaction extract nesting depth
(define_insn "etnd"
; Non-transactional store
(define_insn "ntstg"
- [(set (match_operand:DI 0 "memory_operand" "=RT")
+ [(set (match_operand:DI 0 "memory_operand" "=T")
(unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")]
UNSPECV_NTSTG))]
"TARGET_HTM"
; Set and get floating point control register
-(define_insn "s390_sfpc"
+(define_insn "sfpc"
[(unspec_volatile [(match_operand:SI 0 "register_operand" "d")]
UNSPECV_SFPC)]
"TARGET_HARD_FLOAT"
"sfpc\t%0")
-(define_insn "s390_efpc"
+(define_insn "efpc"
[(set (match_operand:SI 0 "register_operand" "=d")
(unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))]
"TARGET_HARD_FLOAT"
"efpc\t%0")
+
+
+; Load count to block boundary
+
+(define_insn "lcbb"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (unspec:SI [(match_operand 1 "address_operand" "ZR")
+ (match_operand:SI 2 "immediate_operand" "C")] UNSPEC_LCBB))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z13"
+ "lcbb\t%0,%a1,%b2"
+ [(set_attr "op_type" "VRX")])
+
+; Handle -fsplit-stack.
+
+(define_expand "split_stack_prologue"
+ [(const_int 0)]
+ ""
+{
+ s390_expand_split_stack_prologue ();
+ DONE;
+})
+
+;; If there are operand 0 bytes available on the stack, jump to
+;; operand 1.
+
+(define_expand "split_stack_space_check"
+ [(set (pc) (if_then_else
+ (ltu (minus (reg 15)
+ (match_operand 0 "register_operand"))
+ (unspec [(const_int 0)] UNSPEC_STACK_CHECK))
+ (label_ref (match_operand 1))
+ (pc)))]
+ ""
+{
+ /* Offset from thread pointer to __private_ss. */
+ int psso = TARGET_64BIT ? 0x38 : 0x20;
+ rtx tp = s390_get_thread_pointer ();
+ rtx guard = gen_rtx_MEM (Pmode, plus_constant (Pmode, tp, psso));
+ rtx reg = gen_reg_rtx (Pmode);
+ rtx cc;
+ if (TARGET_64BIT)
+ emit_insn (gen_subdi3 (reg, stack_pointer_rtx, operands[0]));
+ else
+ emit_insn (gen_subsi3 (reg, stack_pointer_rtx, operands[0]));
+ cc = s390_emit_compare (GT, reg, guard);
+ s390_emit_jump (operands[1], cc);
+
+ DONE;
+})
+
+;; __morestack parameter block for split stack prologue. Parameters are:
+;; parameter block label, label to be called by __morestack, frame size,
+;; stack parameter size.
+
+(define_insn "split_stack_data"
+ [(unspec_volatile [(match_operand 0 "" "X")
+ (match_operand 1 "" "X")
+ (match_operand 2 "const_int_operand" "X")
+ (match_operand 3 "const_int_operand" "X")]
+ UNSPECV_SPLIT_STACK_DATA)]
+ "TARGET_CPU_ZARCH"
+{
+ switch_to_section (targetm.asm_out.function_rodata_section
+ (current_function_decl));
+
+ if (TARGET_64BIT)
+ output_asm_insn (".align\t8", operands);
+ else
+ output_asm_insn (".align\t4", operands);
+ (*targetm.asm_out.internal_label) (asm_out_file, "L",
+ CODE_LABEL_NUMBER (operands[0]));
+ if (TARGET_64BIT)
+ {
+ output_asm_insn (".quad\t%2", operands);
+ output_asm_insn (".quad\t%3", operands);
+ output_asm_insn (".quad\t%1-%0", operands);
+ }
+ else
+ {
+ output_asm_insn (".long\t%2", operands);
+ output_asm_insn (".long\t%3", operands);
+ output_asm_insn (".long\t%1-%0", operands);
+ }
+
+ switch_to_section (current_function_section ());
+ return "";
+}
+ [(set_attr "length" "0")])
+
+
+;; A jg with minimal fuss for use in split stack prologue.
+
+(define_expand "split_stack_call"
+ [(match_operand 0 "bras_sym_operand" "X")
+ (match_operand 1 "" "")]
+ "TARGET_CPU_ZARCH"
+{
+ if (TARGET_64BIT)
+ emit_jump_insn (gen_split_stack_call_di (operands[0], operands[1]));
+ else
+ emit_jump_insn (gen_split_stack_call_si (operands[0], operands[1]));
+ DONE;
+})
+
+(define_insn "split_stack_call_<mode>"
+ [(set (pc) (label_ref (match_operand 1 "" "")))
+ (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X")
+ (reg:P 1)]
+ UNSPECV_SPLIT_STACK_CALL))]
+ "TARGET_CPU_ZARCH"
+ "jg\t%0"
+ [(set_attr "op_type" "RIL")
+ (set_attr "type" "branch")])
+
+;; Also a conditional one.
+
+(define_expand "split_stack_cond_call"
+ [(match_operand 0 "bras_sym_operand" "X")
+ (match_operand 1 "" "")
+ (match_operand 2 "" "")]
+ "TARGET_CPU_ZARCH"
+{
+ if (TARGET_64BIT)
+ emit_jump_insn (gen_split_stack_cond_call_di (operands[0], operands[1], operands[2]));
+ else
+ emit_jump_insn (gen_split_stack_cond_call_si (operands[0], operands[1], operands[2]));
+ DONE;
+})
+
+(define_insn "split_stack_cond_call_<mode>"
+ [(set (pc)
+ (if_then_else
+ (match_operand 1 "" "")
+ (label_ref (match_operand 2 "" ""))
+ (pc)))
+ (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X")
+ (reg:P 1)]
+ UNSPECV_SPLIT_STACK_CALL))]
+ "TARGET_CPU_ZARCH"
+ "jg%C1\t%0"
+ [(set_attr "op_type" "RIL")
+ (set_attr "type" "branch")])
+
+(define_insn "osc_break"
+ [(unspec_volatile [(const_int 0)] UNSPECV_OSC_BREAK)]
+ ""
+ "bcr\t7,%%r0"
+ [(set_attr "op_type" "RR")])