;;- Machine description for GNU compiler -- S/390 / zSeries version.
;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
-;; 2009 Free Software Foundation, Inc.
+;; 2009, 2010 Free Software Foundation, Inc.
;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
;; Ulrich Weigand (uweigand@de.ibm.com) and
;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
(UNSPEC_SP_SET 700)
(UNSPEC_SP_TEST 701)
- ; Copy sign instructions
- (UNSPEC_COPYSIGN 800)
-
; Test Data Class (TDC)
- (UNSPEC_TDC_INSN 900)
+ (UNSPEC_TDC_INSN 800)
+
+ ; Population Count
+ (UNSPEC_POPCNT 900)
+ (UNSPEC_COPYSIGN 901)
])
;;
; Atomic Support
(UNSPECV_CAS 700)
+ (UNSPECV_ATOMIC_OP 701)
])
;;
floadtf,floaddf,floadsf,fstoredf,fstoresf,
fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf,
ftoi,fsqrttf,fsqrtdf,fsqrtsf,
+ fmadddf,fmaddsf,
ftrunctf,ftruncdf, ftruncsd, ftruncdd,
itoftf, itofdf, itofsf, itofdd, itoftd,
fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd,
;; reg: Instruction does not use the agen unit
(define_attr "atype" "agen,reg"
- (if_then_else (eq_attr "op_type" "E,RR,RI,RRE")
+ (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR")
(const_string "reg")
(const_string "agen")))
z10_c"
(const_string "none"))
+;; Properties concerning Z196 decoding
+;; z196_alone: must group alone
+;; z196_end: ends a group
+;; z196_cracked: instruction is cracked or expanded
+(define_attr "z196prop" "none,
+ z196_alone, z196_ends,
+ z196_cracked"
+ (const_string "none"))
;; Length in bytes.
;; distinguish between g5 and g6, but there are differences between the two
;; CPUs could in theory be modeled.
-(define_attr "cpu" "g5,g6,z900,z990,z9_109,z10"
+(define_attr "cpu" "g5,g6,z900,z990,z9_109,z10,z196"
(const (symbol_ref "s390_tune_attr")))
-(define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10"
+(define_attr "cpu_facility" "standard,ieee,zarch,longdisp,extimm,dfp,z10,z196"
(const_string "standard"))
(define_attr "enabled" ""
(and (eq_attr "cpu_facility" "z10")
(ne (symbol_ref "TARGET_Z10") (const_int 0)))
+ (const_int 1)
+
+ (and (eq_attr "cpu_facility" "z196")
+ (ne (symbol_ref "TARGET_Z196") (const_int 0)))
(const_int 1)]
(const_int 0)))
;; Pipeline description for z10
(include "2097.md")
+;; Pipeline description for z196
+(include "2817.md")
+
;; Predicates
(include "predicates.md")
;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
;; from the same template.
-(define_mode_iterator GPR [(DI "TARGET_64BIT") SI])
+(define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
(define_mode_iterator DSI [DI SI])
;; These mode iterators allow :P to be used for patterns that operate on
;; pointer-sized quantities. Exactly one of the two alternatives will match.
-(define_mode_iterator DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")])
(define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
+;; These macros refer to the actual word_mode of the configuration. This is equal
+;; to Pmode except on 31-bit machines in zarch mode.
+(define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
+(define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
+
;; This mode iterator allows the QI and HI patterns to be defined from
;; the same template.
(define_mode_iterator HQI [HI QI])
;; This mode iterator allows the integer patterns to be defined from the
;; same template.
-(define_mode_iterator INT [(DI "TARGET_64BIT") SI HI QI])
+(define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
(define_mode_iterator INTALL [TI DI SI HI QI])
;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
;; This iterator and attribute allow to combine most atomic operations.
(define_code_iterator ATOMIC [and ior xor plus minus mult])
+(define_code_iterator ATOMIC_Z196 [and ior xor plus])
(define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
(plus "add") (minus "sub") (mult "nand")])
+(define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")])
;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in
;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode.
;; variant for long displacements.
(define_mode_attr y [(DI "g") (SI "y")])
-;; In DP templates, a string like "cds<g>" will expand to "cdsg" in TImode
+;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode
;; and "cds" in DImode.
(define_mode_attr tg [(TI "g") (DI "")])
;; and "cfdbr" in SImode.
(define_mode_attr gf [(DI "g") (SI "f")])
+;; In GPR templates, a string like sll<gk> will expand to sllg for DI
+;; and sllk for SI. This way it is possible to merge the new z196 SI
+;; 3 operands shift instructions into the existing patterns.
+(define_mode_attr gk [(DI "g") (SI "k")])
+
;; ICM mask required to load MODE value into the lowest subreg
;; of a SImode register.
(define_mode_attr icm_lo [(HI "3") (QI "1")])
(match_operand:DI 1 "immediate_operand"
"N0HD0,N1HD0,N2HD0,N3HD0"))
(match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
- "TARGET_64BIT
+ "TARGET_ZARCH
&& s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true))
&& s390_single_part (operands[1], DImode, HImode, 0) >= 0"
"@
(match_operand:DI 1 "const0_operand" "")))
(set (match_operand:DI 2 "register_operand" "=d,d")
(sign_extend:DI (match_dup 0)))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
+ "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH"
"ltgfr\t%2,%0
ltgf\t%2,%0"
[(set_attr "op_type" "RRE,RXY")
(match_operand:DI 1 "const0_operand" "")))
(set (match_operand:DI 2 "register_operand" "=d")
(match_dup 0))]
- "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM"
+ "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM"
"ltgr\t%2,%0"
[(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_fr_E1")])
[(set (reg CC_REGNUM)
(compare (match_operand:DI 0 "register_operand" "d")
(match_operand:DI 1 "const0_operand" "")))]
- "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
+ "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH"
"srda\t%0,0"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
[(set (reg CC_REGNUM)
(compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
(match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
- "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
+ "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
"@
cgr\t%0,%1
cghi\t%0,%h1
(compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
"d,RT,b"))
(match_operand:DI 0 "register_operand" "d, d,d")))]
- "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
+ "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
"@
cgfr\t%0,%1
cgf\t%0,%1
chrl\t%0,%1"
[(set_attr "op_type" "RX,RXY,RIL")
(set_attr "cpu_facility" "*,*,z10")
- (set_attr "type" "*,*,larl")])
+ (set_attr "type" "*,*,larl")
+ (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
(define_insn "*cmphi_ccs_z10"
[(set (reg CC_REGNUM)
(match_operand:HI 1 "immediate_operand" "K")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_Z10"
"chhsi\t%0,%1"
- [(set_attr "op_type" "SIL")])
+ [(set_attr "op_type" "SIL")
+ (set_attr "z196prop" "z196_cracked")])
(define_insn "*cmpdi_ccs_signhi_rl"
[(set (reg CC_REGNUM)
(compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
"d,RT,b"))
(match_operand:DI 0 "register_operand" "d, d,d")))]
- "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
+ "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
"@
clgfr\t%0,%1
clgf\t%0,%1
"d, d,d,Q, d, Q,BQ")
(match_operand:DI 1 "general_operand"
"d,Op,b,D,RT,BQ,Q")))]
- "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
+ "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
"@
clgr\t%0,%1
clgfi\t%0,%1
(label_ref (match_operand 3 "" ""))
(pc)))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_Z10"
+ "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
{
if (get_attr_length (insn) == 6)
return which_alternative ?
(label_ref (match_operand 3 "" ""))
(pc)))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_Z10"
+ "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
{
if (get_attr_length (insn) == 6)
return which_alternative ?
(pc)
(label_ref (match_operand 3 "" ""))))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_Z10"
+ "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
{
if (get_attr_length (insn) == 6)
return which_alternative ?
(pc)
(label_ref (match_operand 3 "" ""))))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_Z10"
+ "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH"
{
if (get_attr_length (insn) == 6)
return which_alternative ?
(define_insn "movti"
[(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o")
(match_operand:TI 1 "general_operand" "QS,d,dPRT,d"))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
lmg\t%0,%N0,%S1
stmg\t%1,%N1,%S0
(define_split
[(set (match_operand:TI 0 "nonimmediate_operand" "")
(match_operand:TI 1 "general_operand" ""))]
- "TARGET_64BIT && reload_completed
+ "TARGET_ZARCH && reload_completed
&& s390_split_ok_p (operands[0], operands[1], TImode, 0)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
(define_split
[(set (match_operand:TI 0 "nonimmediate_operand" "")
(match_operand:TI 1 "general_operand" ""))]
- "TARGET_64BIT && reload_completed
+ "TARGET_ZARCH && reload_completed
&& s390_split_ok_p (operands[0], operands[1], TImode, 1)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
(define_split
[(set (match_operand:TI 0 "register_operand" "")
(match_operand:TI 1 "memory_operand" ""))]
- "TARGET_64BIT && reload_completed
+ "TARGET_ZARCH && reload_completed
&& !s_operand (operands[1], VOIDmode)"
[(set (match_dup 0) (match_dup 1))]
{
rtx addr = operand_subword (operands[0], 1, 0, TImode);
+ addr = gen_lowpart (Pmode, addr);
s390_load_address (addr, XEXP (operands[1], 0));
operands[1] = replace_equiv_address (operands[1], addr);
})
(match_operand:DI 1 "general_operand"
"K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT,
d,*f,R,T,*f,*f,d,K,t,d,t,Q"))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
lghi\t%0,%h1
llihh\t%0,%i1
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "register_operand" ""))]
- "TARGET_64BIT && ACCESS_REG_P (operands[1])"
+ "TARGET_ZARCH && ACCESS_REG_P (operands[1])"
[(set (match_dup 2) (match_dup 3))
(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
(set (strict_low_part (match_dup 2)) (match_dup 4))]
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "register_operand" ""))]
- "TARGET_64BIT && ACCESS_REG_P (operands[0])
+ "TARGET_ZARCH && ACCESS_REG_P (operands[0])
&& dead_or_set_p (insn, operands[1])"
[(set (match_dup 3) (match_dup 2))
(set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "register_operand" ""))]
- "TARGET_64BIT && ACCESS_REG_P (operands[0])
+ "TARGET_ZARCH && ACCESS_REG_P (operands[0])
&& !dead_or_set_p (insn, operands[1])"
[(set (match_dup 3) (match_dup 2))
(set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
"=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
(match_operand:DI 1 "general_operand"
" Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
- "!TARGET_64BIT"
+ "!TARGET_ZARCH"
"@
lm\t%0,%N0,%S1
lmy\t%0,%N0,%S1
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "memory_operand" ""))]
- "!TARGET_64BIT && reload_completed && TARGET_Z10
+ "!TARGET_ZARCH && reload_completed && TARGET_Z10
&& larl_operand (XEXP (operands[1], 0), SImode)"
[(set (match_dup 2) (match_dup 3))
(set (match_dup 0) (match_dup 1))]
(define_split
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(match_operand:DI 1 "general_operand" ""))]
- "!TARGET_64BIT && reload_completed
+ "!TARGET_ZARCH && reload_completed
&& s390_split_ok_p (operands[0], operands[1], DImode, 0)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
(define_split
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(match_operand:DI 1 "general_operand" ""))]
- "!TARGET_64BIT && reload_completed
+ "!TARGET_ZARCH && reload_completed
&& s390_split_ok_p (operands[0], operands[1], DImode, 1)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
(define_split
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "memory_operand" ""))]
- "!TARGET_64BIT && reload_completed
+ "!TARGET_ZARCH && reload_completed
&& !FP_REG_P (operands[0])
&& !s_operand (operands[1], VOIDmode)"
[(set (match_dup 0) (match_dup 1))]
(define_peephole2
[(set (match_operand:DI 0 "register_operand" "")
(mem:DI (match_operand 1 "address_operand" "")))]
- "TARGET_64BIT
+ "TARGET_ZARCH
&& !FP_REG_P (operands[0])
&& GET_CODE (operands[1]) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (operands[1])
&& register_operand (operands[0], VOIDmode)
&& GET_CODE (operands[1]) == MEM)
{
- rtx tmp = gen_reg_rtx (word_mode);
- rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
+ rtx tmp = gen_reg_rtx (DImode);
+ rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
operands[1] = gen_lowpart (QImode, tmp);
}
})
(define_insn "*movqi"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S")
- (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n"))]
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
+ (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q"))]
""
"@
lr\t%0,%1
stc\t%1,%0
stcy\t%1,%0
mvi\t%S0,%b1
- mviy\t%S0,%b1"
- [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY")
- (set_attr "type" "lr,*,*,*,store,store,store,store")
+ mviy\t%S0,%b1
+ #"
+ [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
+ (set_attr "type" "lr,*,*,*,store,store,store,store,*")
(set_attr "z10prop" "z10_fr_E1,
z10_fwd_A1,
z10_super_E1,
z10_rec,
z10_rec,
z10_super,
- z10_super")])
+ z10_super,
+ *")])
(define_peephole2
[(set (match_operand:QI 0 "nonimmediate_operand" "")
(define_insn "movstrictsi"
[(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
(match_operand:SI 1 "general_operand" "d,R,T,t"))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
lr\t%0,%1
l\t%0,%1
(define_insn "*mov<mode>_64"
[(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
(match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
lzxr\t%0
lxr\t%0,%1
stmg\t%1,%N1,%S0
#
#"
- [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
- (set_attr "type" "fhex,fsimptf,*,*,lm,stm,*,*")])
+ [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
+ (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*")
+ (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")])
(define_insn "*mov<mode>_31"
[(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
(match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
- "!TARGET_64BIT"
+ "!TARGET_ZARCH"
"@
lzxr\t%0
lxr\t%0,%1
#
#"
- [(set_attr "op_type" "RRE,RRE,*,*")
- (set_attr "type" "fhex,fsimptf,*,*")])
+ [(set_attr "op_type" "RRE,RRE,*,*")
+ (set_attr "type" "fsimptf,fsimptf,*,*")
+ (set_attr "cpu_facility" "z196,*,*,*")])
; TFmode in GPRs splitters
(define_split
[(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
(match_operand:TD_TF 1 "general_operand" ""))]
- "TARGET_64BIT && reload_completed
+ "TARGET_ZARCH && reload_completed
&& s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
(define_split
[(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
(match_operand:TD_TF 1 "general_operand" ""))]
- "TARGET_64BIT && reload_completed
+ "TARGET_ZARCH && reload_completed
&& s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
(define_split
[(set (match_operand:TD_TF 0 "register_operand" "")
(match_operand:TD_TF 1 "memory_operand" ""))]
- "TARGET_64BIT && reload_completed
+ "TARGET_ZARCH && reload_completed
&& !FP_REG_P (operands[0])
&& !s_operand (operands[1], VOIDmode)"
[(set (match_dup 0) (match_dup 1))]
(define_insn "*mov<mode>_64dfp"
[(set (match_operand:DD_DF 0 "nonimmediate_operand"
- "=f,f,f,d,f,f,R,T,d, d,RT")
+ "=f,f,f,d,f,f,R,T,d,d, d,RT")
(match_operand:DD_DF 1 "general_operand"
- " G,f,d,f,R,T,f,f,d,RT, d"))]
- "TARGET_64BIT && TARGET_DFP"
+ " G,f,d,f,R,T,f,f,G,d,RT, d"))]
+ "TARGET_DFP"
"@
lzdr\t%0
ldr\t%0,%1
ldy\t%0,%1
std\t%1,%0
stdy\t%1,%0
+ lghi\t%0,0
lgr\t%0,%1
lg\t%0,%1
stg\t%1,%0"
- [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY")
- (set_attr "type" "fhex,floaddf,floaddf,floaddf,floaddf,floaddf,
- fstoredf,fstoredf,lr,load,store")
- (set_attr "z10prop" "*,
- *,
- *,
- *,
- *,
- *,
- *,
- *,
- z10_fr_E1,
- z10_fwd_A3,
- z10_rec")
-])
+ [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
+ (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
+ fstoredf,fstoredf,*,lr,load,store")
+ (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
+ (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
(define_insn "*mov<mode>_64"
- [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d, d,RT")
- (match_operand:DD_DF 1 "general_operand" "G,f,R,T,f,f,d,RT, d"))]
- "TARGET_64BIT"
+ [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d, d,RT")
+ (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,RT, d"))]
+ "TARGET_ZARCH"
"@
lzdr\t%0
ldr\t%0,%1
ldy\t%0,%1
std\t%1,%0
stdy\t%1,%0
+ lghi\t%0,0
lgr\t%0,%1
lg\t%0,%1
stg\t%1,%0"
- [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY")
- (set_attr "type" "fhex,fload<mode>,fload<mode>,fload<mode>,
- fstore<mode>,fstore<mode>,lr,load,store")
- (set_attr "z10prop" "*,
- *,
- *,
- *,
- *,
- *,
- z10_fr_E1,
- z10_fwd_A3,
- z10_rec")])
+ [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RXY,RXY")
+ (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
+ fstore<mode>,fstore<mode>,*,lr,load,store")
+ (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec")
+ (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*")])
(define_insn "*mov<mode>_31"
[(set (match_operand:DD_DF 0 "nonimmediate_operand"
"=f,f,f,f,R,T,d,d,Q,S, d,o")
(match_operand:DD_DF 1 "general_operand"
" G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
- "!TARGET_64BIT"
+ "!TARGET_ZARCH"
"@
lzdr\t%0
ldr\t%0,%1
#
#"
[(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
- (set_attr "type" "fhex,fload<mode>,fload<mode>,fload<mode>,
- fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")])
+ (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
+ fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
+ (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
(define_split
[(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
(match_operand:DD_DF 1 "general_operand" ""))]
- "!TARGET_64BIT && reload_completed
+ "!TARGET_ZARCH && reload_completed
&& s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
(define_split
[(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
(match_operand:DD_DF 1 "general_operand" ""))]
- "!TARGET_64BIT && reload_completed
+ "!TARGET_ZARCH && reload_completed
&& s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
(define_split
[(set (match_operand:DD_DF 0 "register_operand" "")
(match_operand:DD_DF 1 "memory_operand" ""))]
- "!TARGET_64BIT && reload_completed
+ "!TARGET_ZARCH && reload_completed
&& !FP_REG_P (operands[0])
&& !s_operand (operands[1], VOIDmode)"
[(set (match_dup 0) (match_dup 1))]
(define_insn "mov<mode>"
[(set (match_operand:SD_SF 0 "nonimmediate_operand"
- "=f,f,f,f,R,T,d,d,d,R,T")
+ "=f,f,f,f,R,T,d,d,d,d,R,T")
(match_operand:SD_SF 1 "general_operand"
- " G,f,R,T,f,f,d,R,T,d,d"))]
+ " G,f,R,T,f,f,G,d,R,T,d,d"))]
""
"@
lzer\t%0
ley\t%0,%1
ste\t%1,%0
stey\t%1,%0
+ lhi\t%0,0
lr\t%0,%1
l\t%0,%1
ly\t%0,%1
st\t%1,%0
sty\t%1,%0"
- [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY")
- (set_attr "type" "fhex,fload<mode>,fload<mode>,fload<mode>,
- fstore<mode>,fstore<mode>,lr,load,load,store,store")
- (set_attr "z10prop" "*,
- *,
- *,
- *,
- *,
- *,
- z10_fr_E1,
- z10_fwd_A3,
- z10_fwd_A3,
- z10_rec,
- z10_rec")])
+ [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RR,RX,RXY,RX,RXY")
+ (set_attr "type" "fsimpsf,fload<mode>,fload<mode>,fload<mode>,
+ fstore<mode>,fstore<mode>,*,lr,load,load,store,store")
+ (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
+ (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
;
; movcc instruction pattern
ly\t%1,%0"
[(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
(set_attr "type" "lr,*,*,store,store,load,load")
- (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3")])
+ (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3")
+ (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
;
; Block move (MVC) patterns.
"mvc\t%O0(%2,%R0),%S1"
[(set_attr "op_type" "SS")])
+; This splitter converts a QI to QI mode copy into a BLK mode copy in
+; order to have it implemented with mvc.
+
+(define_split
+ [(set (match_operand:QI 0 "memory_operand" "")
+ (match_operand:QI 1 "memory_operand" ""))]
+ "reload_completed"
+ [(parallel
+ [(set (match_dup 0) (match_dup 1))
+ (use (const_int 1))])]
+{
+ operands[0] = adjust_address (operands[0], BLKmode, 0);
+ operands[1] = adjust_address (operands[1], BLKmode, 0);
+})
+
+
(define_peephole2
[(parallel
[(set (match_operand:BLK 0 "memory_operand" "")
count = INTVAL (operands[2]);
regno = REGNO (operands[0]);
mode = GET_MODE (operands[0]);
- if (mode != SImode && mode != word_mode)
+ if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
FAIL;
operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
[(match_parallel 0 "load_multiple_operation"
[(set (match_operand:DI 1 "register_operand" "=r")
(match_operand:DI 2 "s_operand" "QS"))])]
- "reload_completed && word_mode == DImode"
+ "reload_completed && TARGET_ZARCH"
{
int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
count = INTVAL (operands[2]);
regno = REGNO (operands[1]);
mode = GET_MODE (operands[1]);
- if (mode != SImode && mode != word_mode)
+ if (mode != SImode && (!TARGET_ZARCH || mode != DImode))
FAIL;
operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
[(match_parallel 0 "store_multiple_operation"
[(set (match_operand:DI 1 "s_operand" "=QS")
(match_operand:DI 2 "register_operand" "r"))])]
- "reload_completed && word_mode == DImode"
+ "reload_completed && TARGET_ZARCH"
{
int words = XVECLEN (operands[0], 0);
operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
(clobber (reg:CC CC_REGNUM))])]
""
{
- enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
- rtx reg0 = gen_reg_rtx (dword_mode);
- rtx reg1 = gen_reg_rtx (dword_mode);
- rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
- rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
+ enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
+ enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
+ rtx reg0 = gen_reg_rtx (dreg_mode);
+ rtx reg1 = gen_reg_rtx (dreg_mode);
+ rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
+ rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
rtx len0 = gen_lowpart (Pmode, reg0);
rtx len1 = gen_lowpart (Pmode, reg1);
(use (match_dup 2))
(use (match_dup 3))
(clobber (reg:CC CC_REGNUM))]
- ""
+ "TARGET_64BIT || !TARGET_ZARCH"
+ "mvcle\t%0,%1,0\;jo\t.-4"
+ [(set_attr "length" "8")
+ (set_attr "type" "vs")])
+
+(define_insn "*movmem_long_31z"
+ [(clobber (match_operand:TI 0 "register_operand" "=d"))
+ (clobber (match_operand:TI 1 "register_operand" "=d"))
+ (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
+ (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))
+ (use (match_dup 2))
+ (use (match_dup 3))
+ (clobber (reg:CC CC_REGNUM))]
+ "!TARGET_64BIT && TARGET_ZARCH"
"mvcle\t%0,%1,0\;jo\t.-4"
[(set_attr "length" "8")
(set_attr "type" "vs")])
(clobber (reg:CC CC_REGNUM))])]
""
{
- enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
- rtx reg0 = gen_reg_rtx (dword_mode);
- rtx reg1 = gen_reg_rtx (dword_mode);
- rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
+ enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
+ enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
+ rtx reg0 = gen_reg_rtx (dreg_mode);
+ rtx reg1 = gen_reg_rtx (dreg_mode);
+ rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
rtx len0 = gen_lowpart (Pmode, reg0);
emit_clobber (reg0);
(use (match_dup 3))
(use (match_operand:<DBL> 1 "register_operand" "d"))
(clobber (reg:CC CC_REGNUM))]
- ""
+ "TARGET_64BIT || !TARGET_ZARCH"
"mvcle\t%0,%1,%Y2\;jo\t.-4"
[(set_attr "length" "8")
(set_attr "type" "vs")])
(use (match_dup 3))
(use (match_operand:<DBL> 1 "register_operand" "d"))
(clobber (reg:CC CC_REGNUM))]
- "(INTVAL (operands[4]) & 255) == 255"
+ "(TARGET_64BIT || !TARGET_ZARCH) &&
+ (INTVAL (operands[4]) & 255) == 255"
+ "mvcle\t%0,%1,%Y2\;jo\t.-4"
+ [(set_attr "length" "8")
+ (set_attr "type" "vs")])
+
+(define_insn "*setmem_long_31z"
+ [(clobber (match_operand:TI 0 "register_operand" "=d"))
+ (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
+ (match_operand 2 "shift_count_or_setmem_operand" "Y"))
+ (use (match_dup 3))
+ (use (match_operand:TI 1 "register_operand" "d"))
+ (clobber (reg:CC CC_REGNUM))]
+ "!TARGET_64BIT && TARGET_ZARCH"
"mvcle\t%0,%1,%Y2\;jo\t.-4"
[(set_attr "length" "8")
(set_attr "type" "vs")])
+
;
; cmpmemM instruction pattern(s).
;
(use (match_dup 3))])]
""
{
- enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
- rtx reg0 = gen_reg_rtx (dword_mode);
- rtx reg1 = gen_reg_rtx (dword_mode);
- rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
- rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
+ enum machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode;
+ enum machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode;
+ rtx reg0 = gen_reg_rtx (dreg_mode);
+ rtx reg1 = gen_reg_rtx (dreg_mode);
+ rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0));
+ rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1));
rtx len0 = gen_lowpart (Pmode, reg0);
rtx len1 = gen_lowpart (Pmode, reg1);
(mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))))
(use (match_dup 2))
(use (match_dup 3))]
- ""
+ "TARGET_64BIT || !TARGET_ZARCH"
"clcle\t%0,%1,0\;jo\t.-4"
[(set_attr "length" "8")
(set_attr "type" "vs")])
+(define_insn "*cmpmem_long_31z"
+ [(clobber (match_operand:TI 0 "register_operand" "=d"))
+ (clobber (match_operand:TI 1 "register_operand" "=d"))
+ (set (reg:CCU CC_REGNUM)
+ (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4))
+ (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))))
+ (use (match_dup 2))
+ (use (match_dup 3))]
+ "!TARGET_64BIT && TARGET_ZARCH"
+ "clcle\t%0,%1,0\;jo\t.-4"
+ [(set_attr "op_type" "NN")
+ (set_attr "type" "vs")
+ (set_attr "length" "8")])
+
; Convert CCUmode condition code to integer.
; Result is zero if EQ, positive if LTU, negative if GTU.
(sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
UNSPEC_CCU_TO_INT)))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"#"
"&& reload_completed"
[(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
(sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CCU_TO_INT)))]
- "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
+ "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH"
"#"
"&& reload_completed"
[(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
(unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
(match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"icmh\t%0,%2,%S1"
[(set_attr "op_type" "RSY")
(set_attr "z10prop" "z10_super")])
(unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S")
(match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM))
(clobber (reg:CC CC_REGNUM))]
- "!TARGET_64BIT"
+ "!TARGET_ZARCH"
"@
icm\t%0,%2,%S1
icmy\t%0,%2,%S1"
[(set_attr "op_type" "RIE")])
(define_insn "*insv<mode>_mem_reg"
- [(set (zero_extract:P (match_operand:QI 0 "memory_operand" "+Q,S")
+ [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S")
(match_operand 1 "const_int_operand" "n,n")
(const_int 0))
- (match_operand:P 2 "register_operand" "d,d"))]
+ (match_operand:W 2 "register_operand" "d,d"))]
"INTVAL (operands[1]) > 0
&& INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
&& INTVAL (operands[1]) % BITS_PER_UNIT == 0"
(const_int 0))
(lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
(const_int 32)))]
- "TARGET_64BIT
+ "TARGET_ZARCH
&& INTVAL (operands[1]) > 0
&& INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
&& INTVAL (operands[1]) % BITS_PER_UNIT == 0"
[(set_attr "op_type" "RSY")
(set_attr "z10prop" "z10_super")])
-(define_insn "*insv<mode>_reg_imm"
- [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
- (const_int 16)
- (match_operand 1 "const_int_operand" "n"))
- (match_operand:P 2 "const_int_operand" "n"))]
+(define_insn "*insvdi_reg_imm"
+ [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
+ (const_int 16)
+ (match_operand 1 "const_int_operand" "n"))
+ (match_operand:DI 2 "const_int_operand" "n"))]
"TARGET_ZARCH
&& INTVAL (operands[1]) >= 0
&& INTVAL (operands[1]) < BITS_PER_WORD
(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
""
{
- if (!TARGET_64BIT)
+ if (!TARGET_ZARCH)
{
emit_clobber (operands[0]);
emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
(define_insn "*extendsidi2"
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
lgfr\t%0,%1
lgf\t%0,%1
(sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))]
""
{
- if (<DSI:MODE>mode == DImode && !TARGET_64BIT)
+ if (<DSI:MODE>mode == DImode && !TARGET_ZARCH)
{
rtx tmp = gen_reg_rtx (SImode);
emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1]));
(define_insn "*extendhidi2_extimm"
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
(sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
- "TARGET_64BIT && TARGET_EXTIMM"
+ "TARGET_ZARCH && TARGET_EXTIMM"
"@
lghr\t%0,%1
lgh\t%0,%1
(define_insn "*extendhidi2"
[(set (match_operand:DI 0 "register_operand" "=d")
(sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"lgh\t%0,%1"
[(set_attr "op_type" "RXY")
(set_attr "z10prop" "z10_super_E1")])
(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
""
{
- if (!TARGET_64BIT)
+ if (!TARGET_ZARCH)
{
emit_clobber (operands[0]);
emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
(define_insn "*zero_extendsidi2"
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
llgfr\t%0,%1
llgf\t%0,%1
[(set (match_operand:DI 0 "register_operand" "=d")
(and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
(const_int 2147483647)))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"llgt\t%0,%1"
[(set_attr "op_type" "RXE")
(set_attr "z10prop" "z10_super_E1")])
(and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
(const_int 2147483647)))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"#"
"&& reload_completed"
[(set (match_dup 0)
[(set (match_operand:DI 0 "register_operand" "=d,d")
(and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
(const_int 2147483647)))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
llgtr\t%0,%1
llgt\t%0,%N1"
(set_attr "z10prop" "z10_super_E1,z10_super_E1")])
(define_split
- [(set (match_operand:GPR 0 "register_operand" "")
- (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "")
+ [(set (match_operand:DSI 0 "register_operand" "")
+ (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "")
(const_int 2147483647)))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && reload_completed"
[(set (match_dup 0)
- (and:GPR (match_dup 1)
+ (and:DSI (match_dup 1)
(const_int 2147483647)))]
"")
(zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))]
""
{
- if (!TARGET_64BIT)
+ if (!TARGET_ZARCH)
{
rtx tmp = gen_reg_rtx (SImode);
emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1]));
[(parallel
[(set (match_operand:DI 0 "register_operand" "")
(unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
- (clobber (match_scratch:TD 2 "=f"))])]
+ (unspec:DI [(const_int 5)] UNSPEC_ROUND)
+ (clobber (reg:CC CC_REGNUM))])]
"TARGET_HARD_DFP"
{
- rtx label1 = gen_label_rtx ();
- rtx label2 = gen_label_rtx ();
- rtx temp = gen_reg_rtx (TDmode);
- REAL_VALUE_TYPE cmp, sub;
-
- decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
- decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
-
- /* 2^63 can't be represented as 64bit DFP number with full precision. The
- solution is doing the check and the subtraction in TD mode and using a
- TD -> DI convert afterwards. */
- emit_insn (gen_extendddtd2 (temp, operands[1]));
- temp = force_reg (TDmode, temp);
- emit_cmp_and_jump_insns (temp,
- CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
- LT, NULL_RTX, VOIDmode, 0, label1);
- emit_insn (gen_subtd3 (temp, temp,
- CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
- emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
- emit_jump (label2);
-
- emit_label (label1);
- emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
- emit_label (label2);
- DONE;
+ if (!TARGET_Z196)
+ {
+ rtx label1 = gen_label_rtx ();
+ rtx label2 = gen_label_rtx ();
+ rtx temp = gen_reg_rtx (TDmode);
+ REAL_VALUE_TYPE cmp, sub;
+
+ decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
+ decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
+
+ /* 2^63 can't be represented as 64bit DFP number with full precision. The
+ solution is doing the check and the subtraction in TD mode and using a
+ TD -> DI convert afterwards. */
+ emit_insn (gen_extendddtd2 (temp, operands[1]));
+ temp = force_reg (TDmode, temp);
+ emit_cmp_and_jump_insns (temp,
+ CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
+ LT, NULL_RTX, VOIDmode, 0, label1);
+ emit_insn (gen_subtd3 (temp, temp,
+ CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
+ emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
+ emit_jump (label2);
+
+ emit_label (label1);
+ emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
+ emit_label (label2);
+ DONE;
+ }
})
(define_expand "fixuns_trunctddi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))]
+ [(parallel
+ [(set (match_operand:DI 0 "register_operand" "")
+ (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
+ (unspec:DI [(const_int 5)] UNSPEC_ROUND)
+ (clobber (reg:CC CC_REGNUM))])]
+
"TARGET_HARD_DFP"
{
- rtx label1 = gen_label_rtx ();
- rtx label2 = gen_label_rtx ();
- rtx temp = gen_reg_rtx (TDmode);
- REAL_VALUE_TYPE cmp, sub;
-
- operands[1] = force_reg (TDmode, operands[1]);
- decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
- decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
-
- emit_cmp_and_jump_insns (operands[1],
- CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
- LT, NULL_RTX, VOIDmode, 0, label1);
- emit_insn (gen_subtd3 (temp, operands[1],
- CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
- emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
- emit_jump (label2);
-
- emit_label (label1);
- emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
- emit_label (label2);
- DONE;
+ if (!TARGET_Z196)
+ {
+ rtx label1 = gen_label_rtx ();
+ rtx label2 = gen_label_rtx ();
+ rtx temp = gen_reg_rtx (TDmode);
+ REAL_VALUE_TYPE cmp, sub;
+
+ operands[1] = force_reg (TDmode, operands[1]);
+ decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
+ decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
+
+ emit_cmp_and_jump_insns (operands[1],
+ CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode),
+ LT, NULL_RTX, VOIDmode, 0, label1);
+ emit_insn (gen_subtd3 (temp, operands[1],
+ CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode)));
+ emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
+ emit_jump (label2);
+
+ emit_label (label1);
+ emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
+ emit_label (label2);
+ DONE;
+ }
})
;
-; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2
+; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2
; instruction pattern(s).
;
(define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
- [(set (match_operand:GPR 0 "register_operand" "")
- (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))]
+ [(parallel
+ [(set (match_operand:GPR 0 "register_operand" "")
+ (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
+ (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
+ (clobber (reg:CC CC_REGNUM))])]
"TARGET_HARD_FLOAT"
{
- rtx label1 = gen_label_rtx ();
- rtx label2 = gen_label_rtx ();
- rtx temp = gen_reg_rtx (<BFP:MODE>mode);
- REAL_VALUE_TYPE cmp, sub;
-
- operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
- real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:MODE>mode);
- real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:MODE>mode);
-
- emit_cmp_and_jump_insns (operands[1],
- CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode),
- LT, NULL_RTX, VOIDmode, 0, label1);
- emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
- CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
- emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
- GEN_INT (7)));
- emit_jump (label2);
-
- emit_label (label1);
- emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
- operands[1], GEN_INT (5)));
- emit_label (label2);
- DONE;
+ if (!TARGET_Z196)
+ {
+ rtx label1 = gen_label_rtx ();
+ rtx label2 = gen_label_rtx ();
+ rtx temp = gen_reg_rtx (<BFP:MODE>mode);
+ REAL_VALUE_TYPE cmp, sub;
+
+ operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
+ real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1, <BFP:MODE>mode);
+ real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode), <BFP:MODE>mode);
+
+ emit_cmp_and_jump_insns (operands[1],
+ CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode),
+ LT, NULL_RTX, VOIDmode, 0, label1);
+ emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
+ CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode)));
+ emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
+ GEN_INT (7)));
+ emit_jump (label2);
+
+ emit_label (label1);
+ emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
+ operands[1], GEN_INT (5)));
+ emit_label (label2);
+ DONE;
+ }
})
+; fixuns_trunc(td|dd)si2 expander
+(define_expand "fixuns_trunc<mode>si2"
+ [(parallel
+ [(set (match_operand:SI 0 "register_operand" "")
+ (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
+ (unspec:SI [(const_int 5)] UNSPEC_ROUND)
+ (clobber (reg:CC CC_REGNUM))])]
+ "TARGET_Z196 && TARGET_HARD_FLOAT"
+ "")
+
+; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
+
+; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
+; clfdtr, clfxtr, clgdtr, clgxtr
+(define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
+ [(set (match_operand:GPR 0 "register_operand" "=r")
+ (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f")))
+ (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z196"
+ "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
+ [(set_attr "op_type" "RRF")
+ (set_attr "type" "ftoi")])
+
(define_expand "fix_trunc<DSF:mode><GPR:mode>2"
[(set (match_operand:GPR 0 "register_operand" "")
(fix:GPR (match_operand:DSF 1 "register_operand" "")))]
(define_expand "fix_trunc<mode>di2"
[(set (match_operand:DI 0 "register_operand" "")
(fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))]
- "TARGET_64BIT && TARGET_HARD_DFP"
+ "TARGET_ZARCH && TARGET_HARD_DFP"
{
operands[1] = force_reg (<MODE>mode, operands[1]);
emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
(fix:DI (match_operand:DFP 1 "register_operand" "f")))
(unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT && TARGET_HARD_DFP"
+ "TARGET_ZARCH && TARGET_HARD_DFP"
"cg<DFP:xde>tr\t%0,%h2,%1"
[(set_attr "op_type" "RRF")
(set_attr "type" "ftoidfp")])
(define_insn "floatdi<mode>2"
[(set (match_operand:FP 0 "register_operand" "=f")
(float:FP (match_operand:DI 1 "register_operand" "d")))]
- "TARGET_64BIT && TARGET_HARD_FLOAT"
+ "TARGET_ZARCH && TARGET_HARD_FLOAT"
"c<xde>g<bt>r\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "type" "itof<mode>" )])
[(set_attr "op_type" "RRE")
(set_attr "type" "itof<mode>" )])
+; cxftr, cdftr
+(define_insn "floatsi<mode>2"
+ [(set (match_operand:DFP 0 "register_operand" "=f")
+ (float:DFP (match_operand:SI 1 "register_operand" "d")))]
+ "TARGET_Z196 && TARGET_HARD_FLOAT"
+ "c<xde>ftr\t%0,0,%1,0"
+ [(set_attr "op_type" "RRE")
+ (set_attr "type" "itof<mode>" )])
+
+;
+; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s).
+;
+
+; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr
+; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr
+(define_insn "floatuns<GPR:mode><FP:mode>2"
+ [(set (match_operand:FP 0 "register_operand" "=f")
+ (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))]
+ "TARGET_Z196 && TARGET_HARD_FLOAT"
+ "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0"
+ [(set_attr "op_type" "RRE")
+ (set_attr "type" "itof<FP:mode>" )])
;
; truncdfsf2 instruction pattern(s).
(plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
(match_operand:TI 2 "general_operand" "do") ) )
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"#"
"&& reload_completed"
[(parallel
(plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
(match_operand:DI 1 "register_operand" "0,0")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
agfr\t%0,%2
agf\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
+ [(set_attr "op_type" "RRE,RXY")
+ (set_attr "z196prop" "z196_cracked,z196_cracked")])
(define_insn "*adddi3_zero_cc"
[(set (reg CC_REGNUM)
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d")
(plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
- "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
+ "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
"@
algfr\t%0,%2
algf\t%0,%2"
(match_operand:DI 1 "register_operand" "0,0"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))]
- "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
+ "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
"@
algfr\t%0,%2
algf\t%0,%2"
(plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
(match_operand:DI 1 "register_operand" "0,0")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
algfr\t%0,%2
algf\t%0,%2"
(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
(match_operand:DI 2 "general_operand" "do") ) )
(clobber (reg:CC CC_REGNUM))]
- "!TARGET_64BIT && TARGET_CPU_ZARCH"
+ "!TARGET_ZARCH && TARGET_CPU_ZARCH"
"#"
"&& reload_completed"
[(parallel
"@
ah\t%0,%2
ahy\t%0,%2"
- [(set_attr "op_type" "RX,RXY")])
+ [(set_attr "op_type" "RX,RXY")
+ (set_attr "z196prop" "z196_cracked,z196_cracked")])
;
; add(di|si)3 instruction pattern(s).
;
-; ar, ahi, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
+; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
(define_insn "*add<mode>3"
- [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,QS")
- (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0,0")
- (match_operand:GPR 2 "general_operand" "d,K,Op,On,R,T,C") ) )
+ [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS")
+ (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0")
+ (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) )
(clobber (reg:CC CC_REGNUM))]
""
"@
a<g>r\t%0,%2
+ a<g>rk\t%0,%1,%2
a<g>hi\t%0,%h2
+ a<g>hik\t%0,%1,%h2
al<g>fi\t%0,%2
sl<g>fi\t%0,%n2
a<g>\t%0,%2
a<y>\t%0,%2
a<g>si\t%0,%c2"
- [(set_attr "op_type" "RR<E>,RI,RIL,RIL,RX<Y>,RXY,SIY")
- (set_attr "cpu_facility" "*,*,extimm,extimm,*,*,z10")
- (set_attr "z10prop" "z10_super_E1,
- z10_super_E1,
- z10_super_E1,
- z10_super_E1,
- z10_super_E1,
- z10_super_E1,
- z10_super_E1")])
+ [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
+ (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10")
+ (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
+ z10_super_E1,z10_super_E1,z10_super_E1")])
-; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
+; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik
(define_insn "*add<mode>3_carry1_cc"
[(set (reg CC_REGNUM)
- (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
- (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
+ (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
+ (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
(match_dup 1)))
- (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d")
+ (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d")
(plus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL1mode)"
"@
al<g>r\t%0,%2
+ al<g>rk\t%0,%1,%2
al<g>fi\t%0,%2
sl<g>fi\t%0,%n2
+ al<g>hsik\t%0,%1,%h2
al<g>\t%0,%2
al<y>\t%0,%2
al<g>si\t%0,%c2"
- [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
- (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
- (set_attr "z10prop" "z10_super_E1,
- z10_super_E1,
- z10_super_E1,
- z10_super_E1,
- z10_super_E1,
- z10_super_E1")])
+ [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
+ (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
+ (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
+ z10_super_E1,z10_super_E1,z10_super_E1")])
-; alr, al, aly, algr, alg
+; alr, al, aly, algr, alg, alrk, algrk
(define_insn "*add<mode>3_carry1_cconly"
[(set (reg CC_REGNUM)
- (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:GPR 2 "general_operand" "d,R,T"))
+ (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
+ (match_operand:GPR 2 "general_operand" "d,d,R,T"))
(match_dup 1)))
- (clobber (match_scratch:GPR 0 "=d,d,d"))]
+ (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
"s390_match_ccmode (insn, CCL1mode)"
"@
al<g>r\t%0,%2
+ al<g>rk\t%0,%1,%2
al<g>\t%0,%2
al<y>\t%0,%2"
- [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
- (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
+ [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
+ (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
-; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
+; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
(define_insn "*add<mode>3_carry2_cc"
[(set (reg CC_REGNUM)
- (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
- (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
+ (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
+ (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
(match_dup 2)))
- (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS")
+ (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
(plus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL1mode)"
"@
al<g>r\t%0,%2
+ al<g>rk\t%0,%1,%2
al<g>fi\t%0,%2
sl<g>fi\t%0,%n2
+ al<g>hsik\t%0,%1,%h2
al<g>\t%0,%2
al<y>\t%0,%2
al<g>si\t%0,%c2"
- [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
- (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
- (set_attr "z10prop" "z10_super_E1,
- z10_super_E1,
- z10_super_E1,
- z10_super_E1,
- z10_super_E1,
- z10_super_E1")])
+ [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
+ (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
+ (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
+ z10_super_E1,z10_super_E1,z10_super_E1")])
-; alr, al, aly, algr, alg
+; alr, al, aly, algr, alg, alrk, algrk
(define_insn "*add<mode>3_carry2_cconly"
[(set (reg CC_REGNUM)
- (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:GPR 2 "general_operand" "d,R,T"))
+ (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
+ (match_operand:GPR 2 "general_operand" "d,d,R,T"))
(match_dup 2)))
- (clobber (match_scratch:GPR 0 "=d,d,d"))]
+ (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
"s390_match_ccmode (insn, CCL1mode)"
"@
al<g>r\t%0,%2
+ al<g>rk\t%0,%1,%2
al<g>\t%0,%2
al<y>\t%0,%2"
- [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
- (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
+ [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
+ (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
-; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi
+; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
(define_insn "*add<mode>3_cc"
[(set (reg CC_REGNUM)
- (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0,0,0,0")
- (match_operand:GPR 2 "general_operand" "d,Op,On,R,T,C"))
+ (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
+ (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
(const_int 0)))
- (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,RS")
+ (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
(plus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCLmode)"
"@
al<g>r\t%0,%2
+ al<g>rk\t%0,%1,%2
al<g>fi\t%0,%2
sl<g>fi\t%0,%n2
+ al<g>hsik\t%0,%1,%h2
al<g>\t%0,%2
al<y>\t%0,%2
al<g>si\t%0,%c2"
- [(set_attr "op_type" "RR<E>,RIL,RIL,RX<Y>,RXY,SIY")
- (set_attr "cpu_facility" "*,extimm,extimm,*,*,z10")
- (set_attr "z10prop" "z10_super_E1,
- z10_super_E1,
- z10_super_E1,
- z10_super_E1,
- z10_super_E1,
- z10_super_E1")])
+ [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
+ (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
+ (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
+ *,z10_super_E1,z10_super_E1,z10_super_E1")])
-; alr, al, aly, algr, alg
+; alr, al, aly, algr, alg, alrk, algrk
(define_insn "*add<mode>3_cconly"
[(set (reg CC_REGNUM)
- (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
- (match_operand:GPR 2 "general_operand" "d,R,T"))
+ (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
+ (match_operand:GPR 2 "general_operand" "d,d,R,T"))
(const_int 0)))
- (clobber (match_scratch:GPR 0 "=d,d,d"))]
+ (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
"s390_match_ccmode (insn, CCLmode)"
"@
al<g>r\t%0,%2
+ al<g>rk\t%0,%1,%2
al<g>\t%0,%2
al<y>\t%0,%2"
- [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
- (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
+ [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
+ (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
-; alr, al, aly, algr, alg
+; alr, al, aly, algr, alg, alrk, algrk
(define_insn "*add<mode>3_cconly2"
[(set (reg CC_REGNUM)
- (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,0,0")
- (neg:GPR (match_operand:GPR 2 "general_operand" "d,R,T"))))
- (clobber (match_scratch:GPR 0 "=d,d,d"))]
+ (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0")
+ (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T"))))
+ (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
"s390_match_ccmode(insn, CCLmode)"
"@
al<g>r\t%0,%2
+ al<g>rk\t%0,%1,%2
al<g>\t%0,%2
al<y>\t%0,%2"
- [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
- (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
+ [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
+ (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
; ahi, afi, aghi, agfi, asi, agsi
(define_insn "*add<mode>3_imm_cc"
[(set (reg CC_REGNUM)
- (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0,0")
- (match_operand:GPR 2 "const_int_operand" "K,Os,C"))
+ (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
+ (match_operand:GPR 2 "const_int_operand" " K, K,Os, C"))
(const_int 0)))
- (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,QS")
+ (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS")
(plus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCAmode)
&& (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
&& INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << (GET_MODE_BITSIZE(<MODE>mode) - 1))"
"@
a<g>hi\t%0,%h2
+ a<g>hik\t%0,%1,%h2
a<g>fi\t%0,%2
a<g>si\t%0,%c2"
- [(set_attr "op_type" "RI,RIL,SIY")
- (set_attr "cpu_facility" "*,extimm,z10")
- (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
+ [(set_attr "op_type" "RI,RIE,RIL,SIY")
+ (set_attr "cpu_facility" "*,z196,extimm,z10")
+ (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
;
; add(tf|df|sf|td|dd)3 instruction pattern(s).
(minus:TI (match_operand:TI 1 "register_operand" "0")
(match_operand:TI 2 "general_operand" "do") ) )
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"#"
"&& reload_completed"
[(parallel
(minus:DI (match_operand:DI 1 "register_operand" "0,0")
(sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
sgfr\t%0,%2
sgf\t%0,%2"
[(set_attr "op_type" "RRE,RXY")
- (set_attr "z10prop" "z10_c,*")])
+ (set_attr "z10prop" "z10_c,*")
+ (set_attr "z196prop" "z196_cracked")])
(define_insn "*subdi3_zero_cc"
[(set (reg CC_REGNUM)
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d")
(minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
- "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
+ "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
"@
slgfr\t%0,%2
slgf\t%0,%2"
(zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))]
- "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
+ "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
"@
slgfr\t%0,%2
slgf\t%0,%2"
(minus:DI (match_operand:DI 1 "register_operand" "0,0")
(zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
slgfr\t%0,%2
slgf\t%0,%2"
(minus:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:DI 2 "general_operand" "do") ) )
(clobber (reg:CC CC_REGNUM))]
- "!TARGET_64BIT && TARGET_CPU_ZARCH"
+ "!TARGET_ZARCH && TARGET_CPU_ZARCH"
"#"
"&& reload_completed"
[(parallel
"@
sh\t%0,%2
shy\t%0,%2"
- [(set_attr "op_type" "RX,RXY")])
+ [(set_attr "op_type" "RX,RXY")
+ (set_attr "z196prop" "z196_cracked,z196_cracked")])
;
; sub(di|si)3 instruction pattern(s).
;
-; sr, s, sy, sgr, sg
+; sr, s, sy, sgr, sg, srk, sgrk
(define_insn "*sub<mode>3"
- [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
- (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
- (match_operand:GPR 2 "general_operand" "d,R,T") ) )
+ [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
+ (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
+ (match_operand:GPR 2 "general_operand" "d,d,R,T") ) )
(clobber (reg:CC CC_REGNUM))]
""
"@
s<g>r\t%0,%2
+ s<g>rk\t%0,%1,%2
s<g>\t%0,%2
s<y>\t%0,%2"
- [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
- (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
+ [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
+ (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
-; slr, sl, sly, slgr, slg
+; slr, sl, sly, slgr, slg, slrk, slgrk
(define_insn "*sub<mode>3_borrow_cc"
[(set (reg CC_REGNUM)
- (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
- (match_operand:GPR 2 "general_operand" "d,R,T"))
+ (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
+ (match_operand:GPR 2 "general_operand" "d,d,R,T"))
(match_dup 1)))
- (set (match_operand:GPR 0 "register_operand" "=d,d,d")
+ (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
(minus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL2mode)"
"@
sl<g>r\t%0,%2
+ sl<g>rk\t%0,%1,%2
sl<g>\t%0,%2
sl<y>\t%0,%2"
- [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
- (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
+ [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
+ (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
-; slr, sl, sly, slgr, slg
+; slr, sl, sly, slgr, slg, slrk, slgrk
(define_insn "*sub<mode>3_borrow_cconly"
[(set (reg CC_REGNUM)
- (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
- (match_operand:GPR 2 "general_operand" "d,R,T"))
+ (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
+ (match_operand:GPR 2 "general_operand" "d,d,R,T"))
(match_dup 1)))
- (clobber (match_scratch:GPR 0 "=d,d,d"))]
+ (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
"s390_match_ccmode (insn, CCL2mode)"
"@
sl<g>r\t%0,%2
+ sl<g>rk\t%0,%1,%2
sl<g>\t%0,%2
sl<y>\t%0,%2"
- [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
- (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
+ [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
+ (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
-; slr, sl, sly, slgr, slg
+; slr, sl, sly, slgr, slg, slrk, slgrk
(define_insn "*sub<mode>3_cc"
[(set (reg CC_REGNUM)
- (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
- (match_operand:GPR 2 "general_operand" "d,R,T"))
+ (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
+ (match_operand:GPR 2 "general_operand" "d,d,R,T"))
(const_int 0)))
- (set (match_operand:GPR 0 "register_operand" "=d,d,d")
+ (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
(minus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCLmode)"
"@
sl<g>r\t%0,%2
+ sl<g>rk\t%0,%1,%2
sl<g>\t%0,%2
sl<y>\t%0,%2"
- [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
- (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
+ [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
+ (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
-; slr, sl, sly, slgr, slg
+; slr, sl, sly, slgr, slg, slrk, slgrk
(define_insn "*sub<mode>3_cc2"
[(set (reg CC_REGNUM)
- (compare (match_operand:GPR 1 "register_operand" "0,0,0")
- (match_operand:GPR 2 "general_operand" "d,R,T")))
- (set (match_operand:GPR 0 "register_operand" "=d,d,d")
+ (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
+ (match_operand:GPR 2 "general_operand" "d,d,R,T")))
+ (set (match_operand:GPR 0 "register_operand" "=d,d,d,d")
(minus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL3mode)"
"@
sl<g>r\t%0,%2
+ sl<g>rk\t%0,%1,%2
sl<g>\t%0,%2
sl<y>\t%0,%2"
- [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
- (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
+ [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
+ (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
-; slr, sl, sly, slgr, slg
+; slr, sl, sly, slgr, slg, slrk, slgrk
(define_insn "*sub<mode>3_cconly"
[(set (reg CC_REGNUM)
- (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,0,0")
- (match_operand:GPR 2 "general_operand" "d,R,T"))
+ (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0")
+ (match_operand:GPR 2 "general_operand" "d,d,R,T"))
(const_int 0)))
- (clobber (match_scratch:GPR 0 "=d,d,d"))]
+ (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
"s390_match_ccmode (insn, CCLmode)"
"@
sl<g>r\t%0,%2
+ sl<g>rk\t%0,%1,%2
sl<g>\t%0,%2
sl<y>\t%0,%2"
- [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
- (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
+ [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
+ (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
-; slr, sl, sly, slgr, slg
+; slr, sl, sly, slgr, slg, slrk, slgrk
(define_insn "*sub<mode>3_cconly2"
[(set (reg CC_REGNUM)
- (compare (match_operand:GPR 1 "register_operand" "0,0,0")
- (match_operand:GPR 2 "general_operand" "d,R,T")))
- (clobber (match_scratch:GPR 0 "=d,d,d"))]
+ (compare (match_operand:GPR 1 "register_operand" "0,d,0,0")
+ (match_operand:GPR 2 "general_operand" "d,d,R,T")))
+ (clobber (match_scratch:GPR 0 "=d,d,d,d"))]
"s390_match_ccmode (insn, CCL3mode)"
"@
sl<g>r\t%0,%2
+ sl<g>rk\t%0,%1,%2
sl<g>\t%0,%2
sl<y>\t%0,%2"
- [(set_attr "op_type" "RR<E>,RX<Y>,RXY")
- (set_attr "z10prop" "z10_super_c_E1,z10_super_E1,z10_super_E1")])
+ [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
+ (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
;
"@
alc<g>r\t%0,%2
alc<g>\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
+ [(set_attr "op_type" "RRE,RXY")
+ (set_attr "z196prop" "z196_alone,z196_alone")])
; alcr, alc, alcgr, alcg
(define_insn "*add<mode>3_alc_carry1_cconly"
"@
alc<g>r\t%0,%2
alc<g>\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")])
+ [(set_attr "op_type" "RRE,RXY")
+ (set_attr "z196prop" "z196_alone,z196_alone")])
; op1 + op2 + c < op2
(clobber (reg:CC CC_REGNUM))])])
+;;
+;; - Conditional move instructions (introduced with z196)
+;;
+
+(define_expand "mov<mode>cc"
+ [(set (match_operand:GPR 0 "nonimmediate_operand" "")
+ (if_then_else:GPR (match_operand 1 "comparison_operator" "")
+ (match_operand:GPR 2 "nonimmediate_operand" "")
+ (match_operand:GPR 3 "nonimmediate_operand" "")))]
+ "TARGET_Z196"
+ "operands[1] = s390_emit_compare (GET_CODE (operands[1]),
+ XEXP (operands[1], 0), XEXP (operands[1], 1));")
+
+; locr, loc, stoc, locgr, lgoc, stgoc
+(define_insn_and_split "*mov<mode>cc"
+ [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d")
+ (if_then_else:GPR
+ (match_operator 1 "s390_comparison"
+ [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c")
+ (const_int 0)])
+ (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS")
+ (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))]
+ "TARGET_Z196"
+ "@
+ loc<g>r%C1\t%0,%3
+ loc<g>r%D1\t%0,%4
+ loc<g>%C1\t%0,%3
+ loc<g>%D1\t%0,%4
+ stoc<g>%C1\t%3,%0
+ stoc<g>%D1\t%4,%0
+ #"
+ "&& reload_completed
+ && MEM_P (operands[3]) && MEM_P (operands[4])"
+ [(set (match_dup 0)
+ (if_then_else:GPR
+ (match_op_dup 1 [(match_dup 2) (const_int 0)])
+ (match_dup 3)
+ (match_dup 0)))
+ (set (match_dup 0)
+ (if_then_else:GPR
+ (match_op_dup 1 [(match_dup 2) (const_int 0)])
+ (match_dup 0)
+ (match_dup 4)))]
+ ""
+ [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")])
+
;;
;;- Multiply instructions.
;;
[(set (match_operand:DI 0 "register_operand" "=d,d")
(mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
(match_operand:DI 1 "register_operand" "0,0")))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
msgfr\t%0,%2
msgf\t%0,%2"
[(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
(mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
(match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
msgr\t%0,%2
mghi\t%0,%h2
(match_operand:SI 1 "register_operand" "%0,0,0"))
(sign_extend:DI
(match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))]
- "!TARGET_64BIT"
+ "!TARGET_ZARCH"
"@
mr\t%0,%2
m\t%0,%2
(match_operand:SI 1 "register_operand" "%0,0"))
(zero_extend:DI
(match_operand:SI 2 "nonimmediate_operand" "d,RT"))))]
- "!TARGET_64BIT && TARGET_CPU_ZARCH"
+ "!TARGET_ZARCH && TARGET_CPU_ZARCH"
"@
mlr\t%0,%2
ml\t%0,%2"
ma<xde>br\t%0,%1,%2
ma<xde>b\t%0,%1,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fmul<mode>")])
+ (set_attr "type" "fmadd<mode>")])
; msxbr, msdbr, msebr, msxb, msdb, mseb
(define_insn "*fmsub<mode>"
ms<xde>br\t%0,%1,%2
ms<xde>b\t%0,%1,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fmul<mode>")])
+ (set_attr "type" "fmadd<mode>")])
;;
;;- Divide and modulo instructions.
(set (match_operand:DI 3 "general_operand" "")
(mod:DI (match_dup 1) (match_dup 2)))])
(clobber (match_dup 4))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
{
rtx insn, div_equal, mod_equal;
(match_operand:DI 2 "general_operand" "d,RT")))
(const_int 64))
(zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
dsgr\t%0,%2
dsg\t%0,%2"
(const_int 64))
(zero_extend:TI
(div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
dsgfr\t%0,%2
dsgf\t%0,%2"
(set (match_operand:DI 3 "general_operand" "")
(umod:DI (match_dup 1) (match_dup 2)))])
(clobber (match_dup 4))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
{
rtx insn, div_equal, mod_equal, equal;
(zero_extend:TI
(truncate:DI
(udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
dlgr\t%0,%2
dlg\t%0,%2"
(set (match_operand:SI 3 "general_operand" "")
(mod:SI (match_dup 1) (match_dup 2)))])
(clobber (match_dup 4))]
- "!TARGET_64BIT"
+ "!TARGET_ZARCH"
{
rtx insn, div_equal, mod_equal, equal;
(zero_extend:DI
(truncate:SI
(div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
- "!TARGET_64BIT"
+ "!TARGET_ZARCH"
"@
dr\t%0,%2
d\t%0,%2"
(set (match_operand:SI 3 "general_operand" "")
(umod:SI (match_dup 1) (match_dup 2)))])
(clobber (match_dup 4))]
- "!TARGET_64BIT && TARGET_CPU_ZARCH"
+ "!TARGET_ZARCH && TARGET_CPU_ZARCH"
{
rtx insn, div_equal, mod_equal, equal;
(zero_extend:DI
(truncate:SI
(udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
- "!TARGET_64BIT && TARGET_CPU_ZARCH"
+ "!TARGET_ZARCH && TARGET_CPU_ZARCH"
"@
dlr\t%0,%2
dl\t%0,%2"
(udiv:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))
(clobber (match_dup 3))]
- "!TARGET_64BIT && !TARGET_CPU_ZARCH"
+ "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
{
rtx insn, udiv_equal, umod_equal, equal;
(umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
(match_operand:SI 2 "nonimmediate_operand" "")))
(clobber (match_dup 3))]
- "!TARGET_64BIT && !TARGET_CPU_ZARCH"
+ "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
{
rtx insn, udiv_equal, umod_equal, equal;
(define_insn "*anddi3_cc"
[(set (reg CC_REGNUM)
- (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
- (match_operand:DI 2 "general_operand" "d,RT"))
+ (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
+ (match_operand:DI 2 "general_operand" " d,d,RT"))
(const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=d,d")
+ (set (match_operand:DI 0 "register_operand" "=d,d, d")
(and:DI (match_dup 1) (match_dup 2)))]
- "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
+ "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@
ngr\t%0,%2
+ ngrk\t%0,%1,%2
ng\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")
- (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
+ [(set_attr "op_type" "RRE,RRF,RXY")
+ (set_attr "cpu_facility" "*,z196,*")
+ (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
(define_insn "*anddi3_cconly"
[(set (reg CC_REGNUM)
- (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
- (match_operand:DI 2 "general_operand" "d,RT"))
+ (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
+ (match_operand:DI 2 "general_operand" " d,d,RT"))
(const_int 0)))
- (clobber (match_scratch:DI 0 "=d,d"))]
- "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
+ (clobber (match_scratch:DI 0 "=d,d, d"))]
+ "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH
/* Do not steal TM patterns. */
&& s390_single_part (operands[2], DImode, HImode, 0) < 0"
"@
ngr\t%0,%2
+ ngrk\t%0,%1,%2
ng\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")
- (set_attr "z10prop" "z10_super_E1, z10_super_E1")])
+ [(set_attr "op_type" "RRE,RRF,RXY")
+ (set_attr "cpu_facility" "*,z196,*")
+ (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
(define_insn "*anddi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q")
+ [(set (match_operand:DI 0 "nonimmediate_operand"
+ "=d,d, d, d, d, d, d, d,d,d, d, AQ,Q")
(and:DI (match_operand:DI 1 "nonimmediate_operand"
- "%d,o,0,0,0,0,0,0,0,0,0,0")
+ "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, 0,0")
(match_operand:DI 2 "general_operand"
- "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,RT,NxQDF,Q")))
+ "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxQDF,Q")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
+ "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
#
#
nihf\t%0,%m2
nilf\t%0,%m2
ngr\t%0,%2
+ ngrk\t%0,%1,%2
ng\t%0,%2
#
#"
- [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")
- (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,*,*,*")
+ [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
+ (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,*,*")
(set_attr "z10prop" "*,
*,
z10_super_E1,
z10_super_E1,
z10_super_E1,
z10_super_E1,
+ *,
z10_super_E1,
*,
*")])
(define_insn "*andsi3_cc"
[(set (reg CC_REGNUM)
- (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
- (match_operand:SI 2 "general_operand" "Os,d,R,T"))
+ (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
+ (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
(const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
+ (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
(and:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode)"
"@
nilf\t%0,%o2
nr\t%0,%2
+ nrk\t%0,%1,%2
n\t%0,%2
ny\t%0,%2"
- [(set_attr "op_type" "RIL,RR,RX,RXY")
- (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
+ [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
+ (set_attr "cpu_facility" "*,*,z196,*,*")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
(define_insn "*andsi3_cconly"
[(set (reg CC_REGNUM)
- (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
- (match_operand:SI 2 "general_operand" "Os,d,R,T"))
+ (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
+ (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
(const_int 0)))
- (clobber (match_scratch:SI 0 "=d,d,d,d"))]
+ (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
"s390_match_ccmode(insn, CCTmode)
/* Do not steal TM patterns. */
&& s390_single_part (operands[2], SImode, HImode, 0) < 0"
"@
nilf\t%0,%o2
nr\t%0,%2
+ nrk\t%0,%1,%2
n\t%0,%2
ny\t%0,%2"
- [(set_attr "op_type" "RIL,RR,RX,RXY")
- (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
+ [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
+ (set_attr "cpu_facility" "*,*,z196,*,*")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
+ z10_super_E1,z10_super_E1")])
(define_insn "*andsi3_zarch"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
+ [(set (match_operand:SI 0 "nonimmediate_operand"
+ "=d,d, d, d, d,d,d,d,d, AQ,Q")
(and:SI (match_operand:SI 1 "nonimmediate_operand"
- "%d,o,0,0,0,0,0,0,0,0")
+ "%d,o, 0, 0, 0,0,d,0,0, 0,0")
(match_operand:SI 2 "general_operand"
- "M,M,N0HSF,N1HSF,Os,d,R,T,NxQSF,Q")))
+ " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxQSF,Q")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
nill\t%0,%j2
nilf\t%0,%o2
nr\t%0,%2
+ nrk\t%0,%1,%2
n\t%0,%2
ny\t%0,%2
#
#"
- [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")
+ [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
+ (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,*,*")
(set_attr "z10prop" "*,
*,
z10_super_E1,
z10_super_E1,
z10_super_E1,
z10_super_E1,
+ *,
z10_super_E1,
z10_super_E1,
*,
*")])
(define_insn "*andsi3_esa"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
- (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
- (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q")
+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0")
+ (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q")))
(clobber (reg:CC CC_REGNUM))]
"!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
;
(define_insn "*andhi3_zarch"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
- (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
- (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
+ (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
+ (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
nr\t%0,%2
+ nrk\t%0,%1,%2
nill\t%0,%x2
#
#"
- [(set_attr "op_type" "RR,RI,SI,SS")
- (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")
+ [(set_attr "op_type" "RR,RRF,RI,SI,SS")
+ (set_attr "cpu_facility" "*,z196,*,*,*")
+ (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")
])
(define_insn "*andhi3_esa"
;
(define_insn "*andqi3_zarch"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
- (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
- (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
+ (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
+ (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
nr\t%0,%2
+ nrk\t%0,%1,%2
nill\t%0,%b2
ni\t%S0,%b2
niy\t%S0,%b2
#"
- [(set_attr "op_type" "RR,RI,SI,SIY,SS")
- (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
+ [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
+ (set_attr "cpu_facility" "*,z196,*,*,*,*")
+ (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
(define_insn "*andqi3_esa"
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
(clobber (reg:CC CC_REGNUM))]
"INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
"nc\t%O0(%2,%R0),%S1"
- [(set_attr "op_type" "SS")])
+ [(set_attr "op_type" "SS")
+ (set_attr "z196prop" "z196_cracked")])
(define_split
[(set (match_operand 0 "memory_operand" "")
(define_insn "*iordi3_cc"
[(set (reg CC_REGNUM)
- (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
- (match_operand:DI 2 "general_operand" "d,RT"))
+ (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
+ (match_operand:DI 2 "general_operand" " d,d,RT"))
(const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=d,d")
+ (set (match_operand:DI 0 "register_operand" "=d,d, d")
(ior:DI (match_dup 1) (match_dup 2)))]
- "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
+ "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@
ogr\t%0,%2
+ ogrk\t%0,%1,%2
og\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")
- (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
+ [(set_attr "op_type" "RRE,RRF,RXY")
+ (set_attr "cpu_facility" "*,z196,*")
+ (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
(define_insn "*iordi3_cconly"
[(set (reg CC_REGNUM)
- (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
- (match_operand:DI 2 "general_operand" "d,RT"))
+ (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
+ (match_operand:DI 2 "general_operand" " d,d,RT"))
(const_int 0)))
- (clobber (match_scratch:DI 0 "=d,d"))]
- "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
+ (clobber (match_scratch:DI 0 "=d,d,d"))]
+ "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@
ogr\t%0,%2
+ ogrk\t%0,%1,%2
og\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")
- (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
+ [(set_attr "op_type" "RRE,RRF,RXY")
+ (set_attr "cpu_facility" "*,z196,*")
+ (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
(define_insn "*iordi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
- (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0")
+ [(set (match_operand:DI 0 "nonimmediate_operand"
+ "=d, d, d, d, d, d,d,d, d, AQ,Q")
+ (ior:DI (match_operand:DI 1 "nonimmediate_operand"
+ " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0")
(match_operand:DI 2 "general_operand"
- "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,RT,NxQD0,Q")))
+ "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
+ "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
oihh\t%0,%i2
oihl\t%0,%i2
oihf\t%0,%k2
oilf\t%0,%k2
ogr\t%0,%2
+ ogrk\t%0,%1,%2
og\t%0,%2
#
#"
- [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")
- (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,*,*,*")
+ [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS")
+ (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*")
(set_attr "z10prop" "z10_super_E1,
z10_super_E1,
z10_super_E1,
z10_super_E1,
z10_super_E1,
z10_super_E1,
+ *,
z10_super_E1,
*,
*")])
(define_insn "*iorsi3_cc"
[(set (reg CC_REGNUM)
- (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
- (match_operand:SI 2 "general_operand" "Os,d,R,T"))
+ (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
+ (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
(const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
+ (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
(ior:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode)"
"@
oilf\t%0,%o2
or\t%0,%2
+ ork\t%0,%1,%2
o\t%0,%2
oy\t%0,%2"
- [(set_attr "op_type" "RIL,RR,RX,RXY")
- (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
+ [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
+ (set_attr "cpu_facility" "*,*,z196,*,*")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
(define_insn "*iorsi3_cconly"
[(set (reg CC_REGNUM)
- (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
- (match_operand:SI 2 "general_operand" "Os,d,R,T"))
+ (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
+ (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
(const_int 0)))
- (clobber (match_scratch:SI 0 "=d,d,d,d"))]
+ (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
"s390_match_ccmode(insn, CCTmode)"
"@
oilf\t%0,%o2
or\t%0,%2
+ ork\t%0,%1,%2
o\t%0,%2
oy\t%0,%2"
- [(set_attr "op_type" "RIL,RR,RX,RXY")
- (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
+ [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
+ (set_attr "cpu_facility" "*,*,z196,*,*")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
(define_insn "*iorsi3_zarch"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
- (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
- (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,R,T,NxQS0,Q")))
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q")
+ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0")
+ (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
oill\t%0,%i2
oilf\t%0,%o2
or\t%0,%2
+ ork\t%0,%1,%2
o\t%0,%2
oy\t%0,%2
#
#"
- [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS")
+ [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
+ (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*")
(set_attr "z10prop" "z10_super_E1,
z10_super_E1,
z10_super_E1,
z10_super_E1,
+ *,
z10_super_E1,
z10_super_E1,
*,
;
(define_insn "*iorhi3_zarch"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
- (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
- (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
+ (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0")
+ (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
or\t%0,%2
+ ork\t%0,%1,%2
oill\t%0,%x2
#
#"
- [(set_attr "op_type" "RR,RI,SI,SS")
- (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
+ [(set_attr "op_type" "RR,RRF,RI,SI,SS")
+ (set_attr "cpu_facility" "*,z196,*,*,*")
+ (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")])
(define_insn "*iorhi3_esa"
[(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
;
(define_insn "*iorqi3_zarch"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
- (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
- (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
+ (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
+ (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
or\t%0,%2
+ ork\t%0,%1,%2
oill\t%0,%b2
oi\t%S0,%b2
oiy\t%S0,%b2
#"
- [(set_attr "op_type" "RR,RI,SI,SIY,SS")
- (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
+ [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
+ (set_attr "cpu_facility" "*,z196,*,*,*,*")
+ (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
+ z10_super,z10_super,*")])
(define_insn "*iorqi3_esa"
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
(clobber (reg:CC CC_REGNUM))]
"INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
"oc\t%O0(%2,%R0),%S1"
- [(set_attr "op_type" "SS")])
+ [(set_attr "op_type" "SS")
+ (set_attr "z196prop" "z196_cracked")])
(define_split
[(set (match_operand 0 "memory_operand" "")
(define_insn "*xordi3_cc"
[(set (reg CC_REGNUM)
- (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
- (match_operand:DI 2 "general_operand" "d,RT"))
+ (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
+ (match_operand:DI 2 "general_operand" " d,d,RT"))
(const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=d,d")
+ (set (match_operand:DI 0 "register_operand" "=d,d, d")
(xor:DI (match_dup 1) (match_dup 2)))]
- "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
+ "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@
xgr\t%0,%2
+ xgrk\t%0,%1,%2
xg\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")
- (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
+ [(set_attr "op_type" "RRE,RRF,RXY")
+ (set_attr "cpu_facility" "*,z196,*")
+ (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
(define_insn "*xordi3_cconly"
[(set (reg CC_REGNUM)
- (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
- (match_operand:DI 2 "general_operand" "d,RT"))
+ (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
+ (match_operand:DI 2 "general_operand" " d,d,RT"))
(const_int 0)))
- (clobber (match_scratch:DI 0 "=d,d"))]
- "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
+ (clobber (match_scratch:DI 0 "=d,d, d"))]
+ "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@
xgr\t%0,%2
+ xgrk\t%0,%1,%2
xg\t%0,%2"
- [(set_attr "op_type" "RRE,RXY")
- (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
+ [(set_attr "op_type" "RRE,RRF,RXY")
+ (set_attr "cpu_facility" "*,z196,*")
+ (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
(define_insn "*xordi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
- (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
- (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,RT,NxQD0,Q")))
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q")
+ (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0")
+ (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
+ "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
xihf\t%0,%k2
xilf\t%0,%k2
xgr\t%0,%2
+ xgrk\t%0,%1,%2
xg\t%0,%2
#
#"
- [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS")
- (set_attr "cpu_facility" "extimm,extimm,*,*,*,*")
- (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")])
+ [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS")
+ (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,
+ *,z10_super_E1,*,*")])
(define_split
[(set (match_operand:DI 0 "s_operand" "")
(define_insn "*xorsi3_cc"
[(set (reg CC_REGNUM)
- (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
- (match_operand:SI 2 "general_operand" "Os,d,R,T"))
+ (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
+ (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
(const_int 0)))
- (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
+ (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
(xor:SI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode)"
"@
xilf\t%0,%o2
xr\t%0,%2
+ xrk\t%0,%1,%2
x\t%0,%2
xy\t%0,%2"
- [(set_attr "op_type" "RIL,RR,RX,RXY")
- (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
+ [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
+ (set_attr "cpu_facility" "*,*,z196,*,*")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
+ z10_super_E1,z10_super_E1")])
(define_insn "*xorsi3_cconly"
[(set (reg CC_REGNUM)
- (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
- (match_operand:SI 2 "general_operand" "Os,d,R,T"))
+ (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0")
+ (match_operand:SI 2 "general_operand" "Os,d,d,R,T"))
(const_int 0)))
- (clobber (match_scratch:SI 0 "=d,d,d,d"))]
+ (clobber (match_scratch:SI 0 "=d,d,d,d,d"))]
"s390_match_ccmode(insn, CCTmode)"
"@
xilf\t%0,%o2
xr\t%0,%2
+ xrk\t%0,%1,%2
x\t%0,%2
xy\t%0,%2"
- [(set_attr "op_type" "RIL,RR,RX,RXY")
- (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
+ [(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
+ (set_attr "cpu_facility" "*,*,z196,*,*")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
+ z10_super_E1,z10_super_E1")])
(define_insn "*xorsi3"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q")
- (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
- (match_operand:SI 2 "general_operand" "Os,d,R,T,NxQS0,Q")))
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q")
+ (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0")
+ (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q")))
(clobber (reg:CC CC_REGNUM))]
"s390_logical_operator_ok_p (operands)"
"@
xilf\t%0,%o2
xr\t%0,%2
+ xrk\t%0,%1,%2
x\t%0,%2
xy\t%0,%2
#
#"
- [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS")
- (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1,*,*")])
+ [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS")
+ (set_attr "cpu_facility" "*,*,z196,*,*,*,*")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
+ z10_super_E1,z10_super_E1,*,*")])
(define_split
[(set (match_operand:SI 0 "s_operand" "")
;
(define_insn "*xorhi3"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
- (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
- (match_operand:HI 2 "general_operand" "Os,d,NxQH0,Q")))
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q")
+ (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0")
+ (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q")))
(clobber (reg:CC CC_REGNUM))]
"s390_logical_operator_ok_p (operands)"
"@
xilf\t%0,%x2
xr\t%0,%2
+ xrk\t%0,%1,%2
#
#"
- [(set_attr "op_type" "RIL,RR,SI,SS")
- (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")])
+ [(set_attr "op_type" "RIL,RR,RRF,SI,SS")
+ (set_attr "cpu_facility" "*,*,z196,*,*")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")])
(define_split
[(set (match_operand:HI 0 "s_operand" "")
;
(define_insn "*xorqi3"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
- (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
- (match_operand:QI 2 "general_operand" "Os,d,n,n,Q")))
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q")
+ (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0")
+ (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q")))
(clobber (reg:CC CC_REGNUM))]
"s390_logical_operator_ok_p (operands)"
"@
xilf\t%0,%b2
xr\t%0,%2
+ xrk\t%0,%1,%2
xi\t%S0,%b2
xiy\t%S0,%b2
#"
- [(set_attr "op_type" "RIL,RR,SI,SIY,SS")
- (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super,z10_super,*")])
+ [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS")
+ (set_attr "cpu_facility" "*,*,z196,*,*,*")
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
;
(clobber (reg:CC CC_REGNUM))]
"INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
"xc\t%O0(%1,%R0),%S0"
- [(set_attr "op_type" "SS")])
+ [(set_attr "op_type" "SS")
+ (set_attr "z196prop" "z196_cracked")])
(define_peephole2
[(parallel
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (sign_extend:DI (match_dup 1))))]
- "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
+ "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
"lcgfr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_c")])
[(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"lcgfr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_c")])
[(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (match_operand:DI 1 "register_operand" "d")))
(clobber (reg:CC CC_REGNUM))]
- "!TARGET_64BIT"
+ "!TARGET_ZARCH"
"#"
"&& reload_completed"
[(parallel
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
(abs:DI (sign_extend:DI (match_dup 1))))]
- "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
+ "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
"lpgfr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_c")])
[(set (match_operand:DI 0 "register_operand" "=d")
(abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"lpgfr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_c")])
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
- "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
+ "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)"
"lngfr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_c")])
(neg:DI (abs:DI (sign_extend:DI
(match_operand:SI 1 "register_operand" "d")))))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"lngfr\t%0,%1"
[(set_attr "op_type" "RRE")
(set_attr "z10prop" "z10_c")])
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimp<mode>")])
-;;
-;;- Copy sign instructions
-;;
-
-; cpsdr
-(define_insn "copysign<mode>3"
- [(set (match_operand:FP 0 "register_operand" "=f")
- (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
- (match_operand:FP 2 "register_operand" "f")]
- UNSPEC_COPYSIGN))]
- "TARGET_DFP"
- "cpsdr\t%0,%2,%1"
- [(set_attr "op_type" "RRF")
- (set_attr "type" "fsimp<mode>")])
-
;;
;;- Square root instructions.
;;
(define_expand "clzdi2"
[(set (match_operand:DI 0 "register_operand" "=d")
(clz:DI (match_operand:DI 1 "register_operand" "d")))]
- "TARGET_EXTIMM && TARGET_64BIT"
+ "TARGET_EXTIMM && TARGET_ZARCH"
{
rtx insn, clz_equal;
rtx wide_reg = gen_reg_rtx (TImode);
(clobber (reg:CC CC_REGNUM))]
"(unsigned HOST_WIDE_INT) INTVAL (operands[2])
== (unsigned HOST_WIDE_INT) 1 << 63
- && TARGET_EXTIMM && TARGET_64BIT"
+ && TARGET_EXTIMM && TARGET_ZARCH"
"flogr\t%0,%1"
[(set_attr "op_type" "RRE")])
;
; (ashl|lshr)(di|si)3 instruction pattern(s).
-;
+; Left shifts and logical right shifts
(define_expand "<shift><mode>3"
[(set (match_operand:DSI 0 "register_operand" "")
[(set (match_operand:DI 0 "register_operand" "=d")
(SHIFT:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
- "!TARGET_64BIT"
+ "!TARGET_ZARCH"
"s<lr>dl\t%0,%Y2"
[(set_attr "op_type" "RS")
- (set_attr "atype" "reg")])
+ (set_attr "atype" "reg")
+ (set_attr "z196prop" "z196_cracked")])
-; sll, srl, sllg, srlg
+; sll, srl, sllg, srlg, sllk, srlk
(define_insn "*<shift><mode>3"
- [(set (match_operand:GPR 0 "register_operand" "=d")
- (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
- (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
+ [(set (match_operand:GPR 0 "register_operand" "=d,d")
+ (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
+ (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))]
""
- "s<lr>l<g>\t%0,<1>%Y2"
- [(set_attr "op_type" "RS<E>")
- (set_attr "atype" "reg")
- (set_attr "z10prop" "z10_super_E1")])
+ "@
+ s<lr>l<g>\t%0,<1>%Y2
+ s<lr>l<gk>\t%0,%1,%Y2"
+ [(set_attr "op_type" "RS<E>,RSY")
+ (set_attr "atype" "reg,reg")
+ (set_attr "cpu_facility" "*,z196")
+ (set_attr "z10prop" "z10_super_E1,*")])
; sldl, srdl
(define_insn "*<shift>di3_31_and"
(SHIFT:DI (match_operand:DI 1 "register_operand" "0")
(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
(match_operand:SI 3 "const_int_operand" "n"))))]
- "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
+ "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
"s<lr>dl\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
-; sll, srl, sllg, srlg
+; sll, srl, sllg, srlg, sllk, srlk
(define_insn "*<shift><mode>3_and"
- [(set (match_operand:GPR 0 "register_operand" "=d")
- (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>")
- (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
- (match_operand:SI 3 "const_int_operand" "n"))))]
+ [(set (match_operand:GPR 0 "register_operand" "=d,d")
+ (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
+ (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
+ (match_operand:SI 3 "const_int_operand" "n,n"))))]
"(INTVAL (operands[3]) & 63) == 63"
- "s<lr>l<g>\t%0,<1>%Y2"
- [(set_attr "op_type" "RS<E>")
- (set_attr "atype" "reg")
- (set_attr "z10prop" "z10_super_E1")])
+ "@
+ s<lr>l<g>\t%0,<1>%Y2
+ s<lr>l<gk>\t%0,%1,%Y2"
+ [(set_attr "op_type" "RS<E>,RSY")
+ (set_attr "atype" "reg,reg")
+ (set_attr "cpu_facility" "*,z196")
+ (set_attr "z10prop" "z10_super_E1,*")])
;
; ashr(di|si)3 instruction pattern(s).
-;
+; Arithmetic right shifts
(define_expand "ashr<mode>3"
[(parallel
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
(ashiftrt:DI (match_dup 1) (match_dup 2)))]
- "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
+ "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
"srda\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
(match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d"))]
- "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
+ "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
"srda\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
(ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
(clobber (reg:CC CC_REGNUM))]
- "!TARGET_64BIT"
+ "!TARGET_ZARCH"
"srda\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
-; sra, srag
+; sra, srag, srak
(define_insn "*ashr<mode>3_cc"
[(set (reg CC_REGNUM)
- (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
- (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
+ (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
+ (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
(const_int 0)))
- (set (match_operand:GPR 0 "register_operand" "=d")
+ (set (match_operand:GPR 0 "register_operand" "=d,d")
(ashiftrt:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCSmode)"
- "sra<g>\t%0,<1>%Y2"
- [(set_attr "op_type" "RS<E>")
- (set_attr "atype" "reg")
- (set_attr "z10prop" "z10_super_E1")])
+ "@
+ sra<g>\t%0,<1>%Y2
+ sra<gk>\t%0,%1,%Y2"
+ [(set_attr "op_type" "RS<E>,RSY")
+ (set_attr "atype" "reg,reg")
+ (set_attr "cpu_facility" "*,z196")
+ (set_attr "z10prop" "z10_super_E1,*")])
-; sra, srag
+; sra, srag, srak
(define_insn "*ashr<mode>3_cconly"
[(set (reg CC_REGNUM)
- (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
- (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
+ (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
+ (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
(const_int 0)))
- (clobber (match_scratch:GPR 0 "=d"))]
+ (clobber (match_scratch:GPR 0 "=d,d"))]
"s390_match_ccmode(insn, CCSmode)"
- "sra<g>\t%0,<1>%Y2"
- [(set_attr "op_type" "RS<E>")
- (set_attr "atype" "reg")
- (set_attr "z10prop" "z10_super_E1")])
+ "@
+ sra<g>\t%0,<1>%Y2
+ sra<gk>\t%0,%1,%Y2"
+ [(set_attr "op_type" "RS<E>,RSY")
+ (set_attr "atype" "reg,reg")
+ (set_attr "cpu_facility" "*,z196")
+ (set_attr "z10prop" "z10_super_E1,*")])
; sra, srag
(define_insn "*ashr<mode>3"
- [(set (match_operand:GPR 0 "register_operand" "=d")
- (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
- (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
+ [(set (match_operand:GPR 0 "register_operand" "=d,d")
+ (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
+ (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))
(clobber (reg:CC CC_REGNUM))]
""
- "sra<g>\t%0,<1>%Y2"
- [(set_attr "op_type" "RS<E>")
- (set_attr "atype" "reg")
- (set_attr "z10prop" "z10_super_E1")])
+ "@
+ sra<g>\t%0,<1>%Y2
+ sra<gk>\t%0,%1,%Y2"
+ [(set_attr "op_type" "RS<E>,RSY")
+ (set_attr "atype" "reg,reg")
+ (set_attr "cpu_facility" "*,z196")
+ (set_attr "z10prop" "z10_super_E1,*")])
; shift pattern with implicit ANDs
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d")
(ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
- "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
+ "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
&& (INTVAL (operands[3]) & 63) == 63"
"srda\t%0,%Y2"
[(set_attr "op_type" "RS")
(match_operand:SI 3 "const_int_operand" "n")))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d"))]
- "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)
+ "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
&& (INTVAL (operands[3]) & 63) == 63"
"srda\t%0,%Y2"
[(set_attr "op_type" "RS")
(and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
(match_operand:SI 3 "const_int_operand" "n"))))
(clobber (reg:CC CC_REGNUM))]
- "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63"
+ "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
"srda\t%0,%Y2"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")])
-; sra, srag
+; sra, srag, srak
(define_insn "*ashr<mode>3_cc_and"
[(set (reg CC_REGNUM)
- (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
- (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
- (match_operand:SI 3 "const_int_operand" "n")))
+ (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
+ (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
+ (match_operand:SI 3 "const_int_operand" "n,n")))
(const_int 0)))
- (set (match_operand:GPR 0 "register_operand" "=d")
+ (set (match_operand:GPR 0 "register_operand" "=d,d")
(ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
"s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
- "sra<g>\t%0,<1>%Y2"
- [(set_attr "op_type" "RS<E>")
- (set_attr "atype" "reg")
- (set_attr "z10prop" "z10_super_E1")])
+ "@
+ sra<g>\t%0,<1>%Y2
+ sra<gk>\t%0,%1,%Y2"
+ [(set_attr "op_type" "RS<E>,RSY")
+ (set_attr "atype" "reg,reg")
+ (set_attr "cpu_facility" "*,z196")
+ (set_attr "z10prop" "z10_super_E1,*")])
-; sra, srag
+; sra, srag, srak
(define_insn "*ashr<mode>3_cconly_and"
[(set (reg CC_REGNUM)
- (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
- (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
- (match_operand:SI 3 "const_int_operand" "n")))
+ (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
+ (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
+ (match_operand:SI 3 "const_int_operand" "n,n")))
(const_int 0)))
- (clobber (match_scratch:GPR 0 "=d"))]
+ (clobber (match_scratch:GPR 0 "=d,d"))]
"s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
- "sra<g>\t%0,<1>%Y2"
- [(set_attr "op_type" "RS<E>")
- (set_attr "atype" "reg")
- (set_attr "z10prop" "z10_super_E1")])
+ "@
+ sra<g>\t%0,<1>%Y2
+ sra<gk>\t%0,%1,%Y2"
+ [(set_attr "op_type" "RS<E>,RSY")
+ (set_attr "atype" "reg,reg")
+ (set_attr "cpu_facility" "*,z196")
+ (set_attr "z10prop" "z10_super_E1,*")])
-; sra, srag
+; sra, srag, srak
(define_insn "*ashr<mode>3_and"
- [(set (match_operand:GPR 0 "register_operand" "=d")
- (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>")
- (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
- (match_operand:SI 3 "const_int_operand" "n"))))
+ [(set (match_operand:GPR 0 "register_operand" "=d,d")
+ (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
+ (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
+ (match_operand:SI 3 "const_int_operand" "n,n"))))
(clobber (reg:CC CC_REGNUM))]
"(INTVAL (operands[3]) & 63) == 63"
- "sra<g>\t%0,<1>%Y2"
- [(set_attr "op_type" "RS<E>")
- (set_attr "atype" "reg")
- (set_attr "z10prop" "z10_super_E1")])
+ "@
+ sra<g>\t%0,<1>%Y2
+ sra<gk>\t%0,%1,%Y2"
+ [(set_attr "op_type" "RS<E>,RSY")
+ (set_attr "atype" "reg,reg")
+ (set_attr "z10prop" "z10_super_E1,*")])
;;
(subreg:DI (match_dup 2) 0)))
(clobber (match_scratch:DI 4 "=X,&1,&?d"))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
{
if (which_alternative != 0)
return "#";
(subreg:SI (match_dup 2) 4)))
(clobber (match_scratch:SI 4 "=X,&1,&?d"))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
{
if (which_alternative != 0)
return "#";
(subreg:SI (match_dup 2) 0)))
(clobber (match_scratch:SI 4 "=X,&1,&?d"))
(clobber (reg:CC CC_REGNUM))]
- "!TARGET_64BIT && TARGET_CPU_ZARCH"
+ "!TARGET_ZARCH && TARGET_CPU_ZARCH"
{
if (which_alternative != 0)
return "#";
emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
- else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
+ else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
else
FAIL;
(const_string "RR") (const_string "RX")))
(set_attr "type" "branch")
(set_attr "atype" "agen")
- (set_attr "z10prop" "z10_c")])
+ (set_attr "z10prop" "z10_c")
+ (set_attr "z196prop" "z196_cracked")])
(define_insn_and_split "doloop_di"
[(set (pc)
(plus:DI (match_dup 1) (const_int -1)))
(clobber (match_scratch:DI 3 "=X,&1,&?d"))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
{
if (which_alternative != 0)
return "#";
&& GET_MODE (operands[2]) == Pmode"
"bras\t%2,%0"
[(set_attr "op_type" "RI")
- (set_attr "type" "jsr")])
+ (set_attr "type" "jsr")
+ (set_attr "z196prop" "z196_cracked")])
(define_insn "*brasl"
[(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
&& GET_MODE (operands[2]) == Pmode"
"brasl\t%2,%0"
[(set_attr "op_type" "RIL")
- (set_attr "type" "jsr")])
+ (set_attr "type" "jsr")
+ (set_attr "z196prop" "z196_cracked")])
(define_insn "*basr"
[(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
(set_attr "type" "jsr")
- (set_attr "atype" "agen")])
+ (set_attr "atype" "agen")
+ (set_attr "z196prop" "z196_cracked")])
;
; call_value instruction pattern(s).
&& GET_MODE (operands[3]) == Pmode"
"bras\t%3,%1"
[(set_attr "op_type" "RI")
- (set_attr "type" "jsr")])
+ (set_attr "type" "jsr")
+ (set_attr "z196prop" "z196_cracked")])
(define_insn "*brasl_r"
[(set (match_operand 0 "" "")
&& GET_MODE (operands[3]) == Pmode"
"brasl\t%3,%1"
[(set_attr "op_type" "RIL")
- (set_attr "type" "jsr")])
+ (set_attr "type" "jsr")
+ (set_attr "z196prop" "z196_cracked")])
(define_insn "*basr_r"
[(set (match_operand 0 "" "")
(if_then_else (match_operand 1 "register_operand" "")
(const_string "RR") (const_string "RX")))
(set_attr "type" "jsr")
- (set_attr "atype" "agen")])
+ (set_attr "atype" "agen")
+ (set_attr "z196prop" "z196_cracked")])
;;
;;- Thread-local storage support.
&& GET_MODE (operands[3]) == Pmode"
"bras\t%3,%1%J4"
[(set_attr "op_type" "RI")
- (set_attr "type" "jsr")])
+ (set_attr "type" "jsr")
+ (set_attr "z196prop" "z196_cracked")])
(define_insn "*brasl_tls"
[(set (match_operand 0 "" "")
&& GET_MODE (operands[3]) == Pmode"
"brasl\t%3,%1%J4"
[(set_attr "op_type" "RIL")
- (set_attr "type" "jsr")])
+ (set_attr "type" "jsr")
+ (set_attr "z196prop" "z196_cracked")])
(define_insn "*basr_tls"
[(set (match_operand 0 "" "")
(if_then_else (match_operand 1 "register_operand" "")
(const_string "RR") (const_string "RX")))
(set_attr "type" "jsr")
- (set_attr "atype" "agen")])
+ (set_attr "atype" "agen")
+ (set_attr "z196prop" "z196_cracked")])
;;
;;- Atomic operations
; cds, cdsg
(define_insn "*sync_compare_and_swap<mode>"
- [(set (match_operand:DP 0 "register_operand" "=r")
- (match_operand:DP 1 "memory_operand" "+Q"))
+ [(set (match_operand:DW 0 "register_operand" "=r")
+ (match_operand:DW 1 "memory_operand" "+Q"))
(set (match_dup 1)
- (unspec_volatile:DP
+ (unspec_volatile:DW
[(match_dup 1)
- (match_operand:DP 2 "register_operand" "0")
- (match_operand:DP 3 "register_operand" "r")]
+ (match_operand:DW 2 "register_operand" "0")
+ (match_operand:DW 3 "register_operand" "r")]
UNSPECV_CAS))
(set (reg:CCZ1 CC_REGNUM)
(compare:CCZ1 (match_dup 1) (match_dup 2)))]
"s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
operands[2], false); DONE;")
+; z196 load and add, xor, or and and instructions
+
+; lan, lang, lao, laog, lax, laxg, laa, laag
+(define_insn "sync_<atomic><mode>"
+ [(parallel
+ [(set (match_operand:GPR 0 "memory_operand" "+QS")
+ (unspec_volatile:GPR
+ [(ATOMIC_Z196:GPR (match_dup 0)
+ (match_operand:GPR 1 "general_operand" "d"))]
+ UNSPECV_ATOMIC_OP))
+ (clobber (match_scratch:GPR 2 "=d"))
+ (clobber (reg:CC CC_REGNUM))])]
+ "TARGET_Z196"
+ "la<noxa><g>\t%2,%1,%0")
+
+; lan, lang, lao, laog, lax, laxg, laa, laag
+(define_insn "sync_old_<atomic><mode>"
+ [(parallel
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (match_operand:GPR 1 "memory_operand" "+QS"))
+ (set (match_dup 1)
+ (unspec_volatile
+ [(ATOMIC_Z196:GPR (match_dup 1)
+ (match_operand:GPR 2 "general_operand" "d"))]
+ UNSPECV_ATOMIC_OP))
+ (clobber (reg:CC CC_REGNUM))])]
+ "TARGET_Z196"
+ "la<noxa><g>\t%0,%2,%1")
+
+
(define_expand "sync_<atomic><mode>"
[(set (match_operand:HQI 0 "memory_operand")
(ATOMIC:HQI (match_dup 0)
(match_operand 1 "register_operand" "")]
""
{
- enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
/* Copy the backchain to the first word, sp to the second and the
literal pool base to the third. */
+ rtx save_bc = adjust_address (operands[0], Pmode, 0);
+ rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode));
+ rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode));
+
if (TARGET_BACKCHAIN)
- {
- rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
- emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
- }
+ emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ()));
- emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
- emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
+ emit_move_insn (save_sp, operands[1]);
+ emit_move_insn (save_bp, base);
DONE;
})
(match_operand 1 "memory_operand" "")]
""
{
- enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
rtx temp = NULL_RTX;
/* Restore the backchain from the first word, sp from the second and the
literal pool base from the third. */
+ rtx save_bc = adjust_address (operands[1], Pmode, 0);
+ rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode));
+ rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode));
+
if (TARGET_BACKCHAIN)
- temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
+ temp = force_reg (Pmode, save_bc);
- emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
- emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
+ emit_move_insn (base, save_bp);
+ emit_move_insn (operands[0], save_sp);
if (temp)
emit_move_insn (s390_back_chain_rtx (), temp);
"!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
"basr\t%0,0"
[(set_attr "op_type" "RR")
- (set_attr "type" "la")])
+ (set_attr "type" "la")
+ (set_attr "z196prop" "z196_cracked")])
(define_insn "main_base_31_large"
[(set (match_operand 0 "register_operand" "=a")
(set (pc) (label_ref (match_operand 2 "" "")))]
"!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
"bras\t%0,%2"
- [(set_attr "op_type" "RI")])
+ [(set_attr "op_type" "RI")
+ (set_attr "z196prop" "z196_cracked")])
(define_insn "main_base_64"
[(set (match_operand 0 "register_operand" "=a")
"!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
"basr\t%0,0\;la\t%0,%1-.(%0)"
[(set_attr "length" "6")
- (set_attr "type" "la")])
+ (set_attr "type" "la")
+ (set_attr "z196prop" "z196_cracked")])
(define_insn "reload_base_64"
[(set (match_operand 0 "register_operand" "=a")
}
[(set_attr "type" "load,larl")
(set_attr "op_type" "RXY,RIL")
- (set_attr "z10prop" "z10_super")])
+ (set_attr "z10prop" "z10_super")
+ (set_attr "z196prop" "z196_alone")])
;
[(set_attr "type" "*,load")
(set_attr "op_type" "RRE,RXY")
(set_attr "z10prop" "z10_super")])
+
+
+;
+; Population count instruction
+;
+
+; The S/390 popcount instruction counts the bits of op1 in 8 byte
+; portions and stores the result in the corresponding bytes in op0.
+(define_insn "*popcount<mode>"
+ [(set (match_operand:INT 0 "register_operand" "=d")
+ (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z196"
+ "popcnt\t%0,%1"
+ [(set_attr "op_type" "RRE")])
+
+(define_expand "popcountdi2"
+ [; popcnt op0, op1
+ (parallel [(set (match_operand:DI 0 "register_operand" "")
+ (unspec:DI [(match_operand:DI 1 "register_operand")]
+ UNSPEC_POPCNT))
+ (clobber (reg:CC CC_REGNUM))])
+ ; sllg op2, op0, 32
+ (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32)))
+ ; agr op0, op2
+ (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
+ (clobber (reg:CC CC_REGNUM))])
+ ; sllg op2, op0, 16
+ (set (match_operand:DI 2 "register_operand" "")
+ (ashift:DI (match_dup 0) (const_int 16)))
+ ; agr op0, op2
+ (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
+ (clobber (reg:CC CC_REGNUM))])
+ ; sllg op2, op0, 8
+ (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8)))
+ ; agr op0, op2
+ (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))
+ (clobber (reg:CC CC_REGNUM))])
+ ; srlg op0, op0, 56
+ (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))]
+ "TARGET_Z196 && TARGET_64BIT"
+ "operands[2] = gen_reg_rtx (DImode);")
+
+(define_expand "popcountsi2"
+ [; popcnt op0, op1
+ (parallel [(set (match_operand:SI 0 "register_operand" "")
+ (unspec:SI [(match_operand:SI 1 "register_operand")]
+ UNSPEC_POPCNT))
+ (clobber (reg:CC CC_REGNUM))])
+ ; sllk op2, op0, 16
+ (set (match_operand:SI 2 "register_operand" "")
+ (ashift:SI (match_dup 0) (const_int 16)))
+ ; ar op0, op2
+ (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
+ (clobber (reg:CC CC_REGNUM))])
+ ; sllk op2, op0, 8
+ (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8)))
+ ; ar op0, op2
+ (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
+ (clobber (reg:CC CC_REGNUM))])
+ ; srl op0, op0, 24
+ (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))]
+ "TARGET_Z196"
+ "operands[2] = gen_reg_rtx (SImode);")
+
+(define_expand "popcounthi2"
+ [; popcnt op0, op1
+ (parallel [(set (match_operand:HI 0 "register_operand" "")
+ (unspec:HI [(match_operand:HI 1 "register_operand")]
+ UNSPEC_POPCNT))
+ (clobber (reg:CC CC_REGNUM))])
+ ; sllk op2, op0, 8
+ (set (match_operand:SI 2 "register_operand" "")
+ (ashift:SI (match_dup 0) (const_int 8)))
+ ; ar op0, op2
+ (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))
+ (clobber (reg:CC CC_REGNUM))])
+ ; srl op0, op0, 8
+ (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))]
+ "TARGET_Z196"
+ "operands[2] = gen_reg_rtx (SImode);")
+
+(define_expand "popcountqi2"
+ [; popcnt op0, op1
+ (parallel [(set (match_operand:QI 0 "register_operand" "")
+ (unspec:QI [(match_operand:QI 1 "register_operand")]
+ UNSPEC_POPCNT))
+ (clobber (reg:CC CC_REGNUM))])]
+ "TARGET_Z196"
+ "")
+
+;;
+;;- Copy sign instructions
+;;
+
+(define_insn "copysign<mode>3"
+ [(set (match_operand:FP 0 "register_operand" "=f")
+ (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>")
+ (match_operand:FP 2 "register_operand" "f")]
+ UNSPEC_COPYSIGN))]
+ "TARGET_Z196"
+ "cpsdr\t%0,%2,%1"
+ [(set_attr "op_type" "RRF")
+ (set_attr "type" "fsimp<mode>")])
projects / gcc.git / blobdiff