;;- Machine description for GNU compiler -- S/390 / zSeries version.
-;; Copyright (C) 1999-2015 Free Software Foundation, Inc.
+;; Copyright (C) 1999-2019 Free Software Foundation, Inc.
;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
;; Ulrich Weigand (uweigand@de.ibm.com) and
;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
; Copy CC as is into the lower 2 bits of an integer register
UNSPEC_CC_TO_INT
+ ; The right hand side of an setmem
+ UNSPEC_REPLICATE_BYTE
+
; GOT/PLT and lt-relative accesses
UNSPEC_LTREL_OFFSET
- UNSPEC_LTREL_BASE
UNSPEC_POOL_OFFSET
UNSPEC_GOTENT
UNSPEC_GOT
UNSPEC_LTREF
UNSPEC_INSN
UNSPEC_EXECUTE
+ UNSPEC_EXECUTE_JUMP
; Atomic Support
UNSPEC_MB
UNSPEC_SP_SET
UNSPEC_SP_TEST
+ ; Split stack support
+ UNSPEC_STACK_CHECK
+
; Test Data Class (TDC)
UNSPEC_TDC_INSN
UNSPEC_VEC_INSERT_AND_ZERO
UNSPEC_VEC_LOAD_BNDRY
UNSPEC_VEC_LOAD_LEN
+ UNSPEC_VEC_LOAD_LEN_R
UNSPEC_VEC_MERGEH
UNSPEC_VEC_MERGEL
UNSPEC_VEC_PACK
UNSPEC_VEC_PERMI
UNSPEC_VEC_EXTEND
UNSPEC_VEC_STORE_LEN
+ UNSPEC_VEC_STORE_LEN_R
+ UNSPEC_VEC_VBPERM
UNSPEC_VEC_UNPACKH
UNSPEC_VEC_UNPACKH_L
UNSPEC_VEC_UNPACKL
UNSPEC_VEC_UNPACKL_L
UNSPEC_VEC_ADDC
- UNSPEC_VEC_ADDC_U128
UNSPEC_VEC_ADDE_U128
UNSPEC_VEC_ADDEC_U128
UNSPEC_VEC_AVG
UNSPEC_VEC_SRL
UNSPEC_VEC_SRLB
- UNSPEC_VEC_SUB_U128
UNSPEC_VEC_SUBC
- UNSPEC_VEC_SUBC_U128
UNSPEC_VEC_SUBE_U128
UNSPEC_VEC_SUBEC_U128
UNSPEC_VEC_VCGDB
UNSPEC_VEC_VCLGDB
- UNSPEC_VEC_VFIDB
+ UNSPEC_VEC_VFI
+
+ UNSPEC_VEC_VFLL ; vector fp load lengthened
+ UNSPEC_VEC_VFLR ; vector fp load rounded
+
+ UNSPEC_VEC_VFTCI
+ UNSPEC_VEC_VFTCICC
- UNSPEC_VEC_VLDEB
- UNSPEC_VEC_VLEDB
+ UNSPEC_VEC_MSUM
- UNSPEC_VEC_VFTCIDB
- UNSPEC_VEC_VFTCIDBCC
+ UNSPEC_VEC_VFMIN
+ UNSPEC_VEC_VFMAX
])
;;
UNSPECV_CAS
UNSPECV_ATOMIC_OP
+ ; Non-branch nops used for compare-and-branch adjustments on z10
+ UNSPECV_NOP_LR_0
+ UNSPECV_NOP_LR_1
+
; Hotpatching (unremovable NOPs)
UNSPECV_NOP_2_BYTE
UNSPECV_NOP_4_BYTE
; Set and get floating point control register
UNSPECV_SFPC
UNSPECV_EFPC
+
+ ; Split stack support
+ UNSPECV_SPLIT_STACK_CALL
+ UNSPECV_SPLIT_STACK_DATA
+
+ UNSPECV_OSC_BREAK
])
;;
[
; Sibling call register.
(SIBCALL_REGNUM 1)
+ ; A call-clobbered reg which can be used in indirect branch thunks
+ (INDIRECT_BRANCH_THUNK_REGNUM 1)
; Literal pool base register.
(BASE_REGNUM 13)
; Return address register.
(RETURN_REGNUM 14)
+ ; Stack pointer register.
+ (STACK_REGNUM 15)
; Condition code register.
(CC_REGNUM 33)
; Thread local storage pointer register.
[
; General purpose registers
(GPR0_REGNUM 0)
+ (GPR1_REGNUM 1)
+ (GPR2_REGNUM 2)
+ (GPR6_REGNUM 6)
; Floating point registers.
(FPR0_REGNUM 16)
(FPR1_REGNUM 20)
(VR31_REGNUM 53)
])
+; Rounding modes for binary floating point numbers
+(define_constants
+ [(BFP_RND_CURRENT 0)
+ (BFP_RND_NEAREST_TIE_AWAY_FROM_0 1)
+ (BFP_RND_PREP_FOR_SHORT_PREC 3)
+ (BFP_RND_NEAREST_TIE_TO_EVEN 4)
+ (BFP_RND_TOWARD_0 5)
+ (BFP_RND_TOWARD_INF 6)
+ (BFP_RND_TOWARD_MINF 7)])
+
+; Rounding modes for decimal floating point numbers
+; 1-7 were introduced with the floating point extension facility
+; available with z196
+; With these rounding modes (1-7) a quantum exception might occur
+; which is suppressed for the other modes.
+(define_constants
+ [(DFP_RND_CURRENT 0)
+ (DFP_RND_NEAREST_TIE_AWAY_FROM_0_QUANTEXC 1)
+ (DFP_RND_CURRENT_QUANTEXC 2)
+ (DFP_RND_PREP_FOR_SHORT_PREC_QUANTEXC 3)
+ (DFP_RND_NEAREST_TIE_TO_EVEN_QUANTEXC 4)
+ (DFP_RND_TOWARD_0_QUANTEXC 5)
+ (DFP_RND_TOWARD_INF_QUANTEXC 6)
+ (DFP_RND_TOWARD_MINF_QUANTEXC 7)
+ (DFP_RND_NEAREST_TIE_TO_EVEN 8)
+ (DFP_RND_TOWARD_0 9)
+ (DFP_RND_TOWARD_INF 10)
+ (DFP_RND_TOWARD_MINF 11)
+ (DFP_RND_NEAREST_TIE_AWAY_FROM_0 12)
+ (DFP_RND_NEAREST_TIE_TO_0 13)
+ (DFP_RND_AWAY_FROM_0 14)
+ (DFP_RND_PREP_FOR_SHORT_PREC 15)])
+
;;
;; PFPO GPR0 argument format
;;
; Bitposition of operand types
(PFPO_OP0_TYPE_SHIFT 16)
(PFPO_OP1_TYPE_SHIFT 8)
+ ; Decide whether current DFP or BFD rounding mode should be used
+ ; for the conversion.
+ (PFPO_RND_MODE_DFP 0)
+ (PFPO_RND_MODE_BFP 1)
])
+;; PPA constants
+
+; Immediate values which can be used as the third operand to the
+; perform processor assist instruction
+
+(define_constants
+ [(PPA_TX_ABORT 1)
+ (PPA_OOO_BARRIER 15)])
+
; Immediate operands for tbegin and tbeginc
(define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c
(define_constants [(TBEGINC_MASK 65288)]) ; 0xff08
;; Used to determine defaults for length and other attribute values.
(define_attr "op_type"
- "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX"
+ "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX,VSI"
(const_string "NN"))
;; Instruction type attribute used for scheduling.
;; reg: Instruction does not use the agen unit
(define_attr "atype" "agen,reg"
- (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR")
+ (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF")
(const_string "reg")
(const_string "agen")))
z196_cracked"
(const_string "none"))
-(define_attr "mnemonic" "bcr_flush,unknown" (const_string "unknown"))
+; mnemonics which only get defined through if_then_else currently
+; don't get added to the list values automatically and hence need to
+; be listed here.
+(define_attr "mnemonic" "b,bas,basr,bc,bcr_flush,unknown" (const_string "unknown"))
;; Length in bytes.
(define_attr "length" ""
- (cond [(eq_attr "op_type" "E,RR") (const_int 2)
- (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)]
+ (cond [(eq_attr "op_type" "E,RR") (const_int 2)
+ (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF") (const_int 4)]
(const_int 6)))
;; Processor type. This attribute must exactly match the processor_type
-;; enumeration in s390.h. The current machine description does not
-;; distinguish between g5 and g6, but there are differences between the two
-;; CPUs could in theory be modeled.
+;; enumeration in s390.h.
-(define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13"
+(define_attr "cpu" "z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13,z14"
(const (symbol_ref "s390_tune_attr")))
(define_attr "cpu_facility"
- "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vec"
+ "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vx,z13,z14,vxe,arch13,vxe2"
(const_string "standard"))
(define_attr "enabled" ""
(match_test "TARGET_DFP"))
(const_int 1)
- (and (eq_attr "cpu_facility" "cpu_zarch")
- (match_test "TARGET_CPU_ZARCH"))
+ (eq_attr "cpu_facility" "cpu_zarch")
(const_int 1)
(and (eq_attr "cpu_facility" "z10")
(match_test "TARGET_ZEC12"))
(const_int 1)
- (and (eq_attr "cpu_facility" "vec")
+ (and (eq_attr "cpu_facility" "vx")
(match_test "TARGET_VX"))
- (const_int 1)]
+ (const_int 1)
+
+ (and (eq_attr "cpu_facility" "z13")
+ (match_test "TARGET_Z13"))
+ (const_int 1)
+
+ (and (eq_attr "cpu_facility" "z14")
+ (match_test "TARGET_Z14"))
+ (const_int 1)
+
+ (and (eq_attr "cpu_facility" "vxe")
+ (match_test "TARGET_VXE"))
+ (const_int 1)
+
+ (and (eq_attr "cpu_facility" "arch13")
+ (match_test "TARGET_ARCH13"))
+ (const_int 1)
+
+ (and (eq_attr "cpu_facility" "vxe2")
+ (match_test "TARGET_VXE2"))
+ (const_int 1)
+ ]
(const_int 0)))
-;; Pipeline description for z900. For lack of anything better,
-;; this description is also used for the g5 and g6.
+;; Whether an instruction supports relative long addressing.
+;; Currently this corresponds to RIL-b and RIL-c instruction formats,
+;; but having a separate attribute, as opposed to reusing op_type,
+;; provides additional flexibility.
+
+(define_attr "relative_long" "no,yes" (const_string "no"))
+
+;; Pipeline description for z900.
(include "2064.md")
;; Pipeline description for z990, z9-109 and z9-ec.
;; Pipeline description for zEC12
(include "2827.md")
+;; Pipeline description for z13
+(include "2964.md")
+
+;; Pipeline description for z14
+(include "3906.md")
+
;; Predicates
(include "predicates.md")
;; same template.
(define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI])
(define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI])
+(define_mode_iterator SINT [SI HI QI])
;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from
;; the same template.
;; This iterator allows r[ox]sbg to be defined with the same template
(define_code_iterator IXOR [ior xor])
+;; This is used for merging the nand/nor and and/or with complement patterns
+(define_code_iterator ANDOR [and ior])
+(define_code_attr bitops_name [(and "and") (ior "or")])
+(define_code_attr inv_bitops_name [(and "or") (ior "and")])
+(define_code_attr inv_no [(and "o") (ior "n")])
+
;; This iterator is used to expand the patterns for the nearest
;; integer functions.
(define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC
;; fp register operands. The following attributes allow to merge the bfp and
;; dfp variants in a single insn definition.
-;; This attribute is used to set op_type accordingly.
-(define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR")
- (DD "RRR") (SD "RRR")])
-
-;; This attribute is used in the operand constraint list in order to have the
-;; first and the second operand match for bfp modes.
-(define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")])
-
-;; This attribute is used to merge the scalar vector instructions into
-;; the FP patterns. For non-supported modes (all but DF) it expands
-;; to constraints which are supposed to be matched by an earlier
-;; variant.
-(define_mode_attr v0 [(TF "0") (DF "v") (SF "0") (TD "0") (DD "0") (DD "0") (TI "0") (DI "v") (SI "0")])
-(define_mode_attr vf [(TF "f") (DF "v") (SF "f") (TD "f") (DD "f") (DD "f") (TI "f") (DI "v") (SI "f")])
-(define_mode_attr vd [(TF "d") (DF "v") (SF "d") (TD "d") (DD "d") (DD "d") (TI "d") (DI "v") (SI "d")])
-
-;; This attribute is used in the operand list of the instruction to have an
-;; additional operand for the dfp instructions.
-(define_mode_attr op1 [(TF "") (DF "") (SF "")
- (TD "%1,") (DD "%1,") (SD "%1,")])
-
+;; These mode attributes are supposed to be used in the `enabled' insn
+;; attribute to disable certain alternatives for certain modes.
+(define_mode_attr nBFP [(TF "0") (DF "0") (SF "0") (TD "*") (DD "*") (DD "*")])
+(define_mode_attr nDFP [(TF "*") (DF "*") (SF "*") (TD "0") (DD "0") (DD "0")])
+(define_mode_attr DSF [(TF "0") (DF "*") (SF "*") (TD "0") (DD "0") (SD "0")])
+(define_mode_attr DFDI [(TF "0") (DF "*") (SF "0")
+ (TD "0") (DD "0") (DD "0")
+ (TI "0") (DI "*") (SI "0")])
+(define_mode_attr DF [(TF "0") (DF "*") (SF "0")
+ (TD "0") (DD "0") (DD "0")
+ (TI "0") (DI "0") (SI "0")])
+(define_mode_attr SF [(TF "0") (DF "0") (SF "*")
+ (TD "0") (DD "0") (DD "0")
+ (TI "0") (DI "0") (SI "0")])
;; This attribute is used in the operand constraint list
;; for instructions dealing with the sign bit of 32 or 64bit fp values.
;; target operand uses the same fp register.
(define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")])
-;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise.
-;; This is used to disable the memory alternative in TFmode patterns.
-(define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")])
-
;; This attribute adds b for bfp instructions and t for dfp instructions and is used
;; within instruction mnemonics.
(define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")])
;; In place of GET_MODE_BITSIZE (<MODE>mode)
(define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
+;; 64 - bitsize
+(define_mode_attr bitoff [(DI "0") (SI "32") (HI "48") (QI "56")])
+(define_mode_attr bitoff_plus [(DI "") (SI "32+") (HI "48+") (QI "56+")])
+
+;; In place of GET_MODE_SIZE (<MODE>mode)
+(define_mode_attr modesize [(DI "8") (SI "4")])
;; Allow return and simple_return to be defined from a single template.
(define_code_iterator ANY_RETURN [return simple_return])
; Used with VFCMP to expand part of the mnemonic
; For fp we have a mismatch: eq in the insn name - e in asm
(define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")])
-(define_mode_attr insn_cmp [(CCVEQ "eq") (CCVH "h") (CCVHU "hl") (CCVFH "h") (CCVFHE "he")])
+(define_mode_attr insn_cmp [(CCVEQ "eq") (CCVIH "h") (CCVIHU "hl") (CCVFH "h") (CCVFHE "he")])
+;; Subst pattern definitions
+(include "subst.md")
(include "vector.md")
tm\t%S0,%b1
tmy\t%S0,%b1"
[(set_attr "op_type" "SI,SIY")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_super,z10_super")])
(define_insn "*tmdi_reg"
(compare
(ashiftrt:DI
(ashift:DI
- (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0)
+ (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,T") 0)
(const_int 32)) (const_int 32))
(match_operand:DI 1 "const0_operand" "")))
(set (match_operand:DI 2 "register_operand" "=d,d")
; ltr, lt, ltgr, ltg
(define_insn "*tst<mode>_extimm"
[(set (reg CC_REGNUM)
- (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
+ (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T")
(match_operand:GPR 1 "const0_operand" "")))
(set (match_operand:GPR 2 "register_operand" "=d,d")
(match_dup 0))]
[(set_attr "op_type" "RR<E>,RXY")
(set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
+; Peephole to combine a load-and-test from volatile memory which combine does
+; not do.
+(define_peephole2
+ [(set (match_operand:GPR 0 "register_operand")
+ (match_operand:GPR 2 "memory_operand"))
+ (set (reg CC_REGNUM)
+ (compare (match_dup 0) (match_operand:GPR 1 "const0_operand")))]
+ "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM
+ && GENERAL_REG_P (operands[0])
+ && satisfies_constraint_T (operands[2])
+ && !contains_constant_pool_address_p (operands[2])"
+ [(parallel
+ [(set (reg:CCS CC_REGNUM)
+ (compare:CCS (match_dup 2) (match_dup 1)))
+ (set (match_dup 0) (match_dup 2))])])
+
; ltr, lt, ltgr, ltg
(define_insn "*tst<mode>_cconly_extimm"
[(set (reg CC_REGNUM)
- (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT")
+ (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T")
(match_operand:GPR 1 "const0_operand" "")))
(clobber (match_scratch:GPR 2 "=X,d"))]
"s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM"
icm\t%2,15,%S0
icmy\t%2,15,%S0"
[(set_attr "op_type" "RR,RS,RSY")
+ (set_attr "cpu_facility" "*,*,longdisp")
(set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
(define_insn "*tstsi_cconly"
icm\t%2,15,%S0
icmy\t%2,15,%S0"
[(set_attr "op_type" "RR,RS,RSY")
+ (set_attr "cpu_facility" "*,*,longdisp")
(set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")])
(define_insn "*tstdi_cconly_31"
icmy\t%2,<icm_lo>,%S0
tml\t%0,<max_uint>"
[(set_attr "op_type" "RS,RSY,RI")
+ (set_attr "cpu_facility" "*,longdisp,*")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
(define_insn "*tsthiCCT_cconly"
icmy\t%2,3,%S0
tml\t%0,65535"
[(set_attr "op_type" "RS,RSY,RI")
+ (set_attr "cpu_facility" "*,longdisp,*")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")])
(define_insn "*tstqiCCT_cconly"
cliy\t%S0,0
tml\t%0,255"
[(set_attr "op_type" "SI,SIY,RI")
+ (set_attr "cpu_facility" "*,longdisp,*")
(set_attr "z10prop" "z10_super,z10_super,z10_super")])
(define_insn "*tst<mode>"
icm\t%2,<icm_lo>,%S0
icmy\t%2,<icm_lo>,%S0"
[(set_attr "op_type" "RS,RSY")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1")])
(define_insn "*tst<mode>_cconly"
icm\t%2,<icm_lo>,%S0
icmy\t%2,<icm_lo>,%S0"
[(set_attr "op_type" "RS,RSY")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1")])
(define_insn "*cmpdi_cct"
[(set (reg CC_REGNUM)
(compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q")
- (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))]
+ (match_operand:DI 1 "general_operand" "d,K,Os,T,BQ")))]
"s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH"
"@
cgr\t%0,%1
cy\t%0,%1
#"
[(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")
+ (set_attr "cpu_facility" "*,*,*,*,longdisp,*")
(set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")])
; Compare (signed) instructions
(define_insn "*cmpdi_ccs_sign"
[(set (reg CC_REGNUM)
(compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"
- "d,RT,b"))
+ "d,T,b"))
(match_operand:DI 0 "register_operand" "d, d,d")))]
"s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH"
"@
cgfrl\t%0,%1"
[(set_attr "op_type" "RRE,RXY,RIL")
(set_attr "z10prop" "z10_c,*,*")
- (set_attr "type" "*,*,larl")])
+ (set_attr "type" "*,*,larl")
+ (set_attr "relative_long" "*,*,yes")])
chy\t%0,%1
chrl\t%0,%1"
[(set_attr "op_type" "RX,RXY,RIL")
- (set_attr "cpu_facility" "*,*,z10")
+ (set_attr "cpu_facility" "*,longdisp,z10")
(set_attr "type" "*,*,larl")
- (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")])
+ (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")
+ (set_attr "relative_long" "*,*,yes")])
(define_insn "*cmphi_ccs_z10"
[(set (reg CC_REGNUM)
(define_insn "*cmpdi_ccs_signhi_rl"
[(set (reg CC_REGNUM)
- (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b"))
+ (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "T,b"))
(match_operand:GPR 0 "register_operand" "d,d")))]
"s390_match_ccmode(insn, CCSRmode) && TARGET_Z10"
"@
cgh\t%0,%1
cghrl\t%0,%1"
[(set_attr "op_type" "RXY,RIL")
- (set_attr "type" "*,larl")])
+ (set_attr "type" "*,larl")
+ (set_attr "relative_long" "*,yes")])
; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl
(define_insn "*cmp<mode>_ccs"
c<y>\t%0,%1
c<g>rl\t%0,%1"
[(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL")
- (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10")
+ (set_attr "cpu_facility" "*,*,z10,extimm,*,longdisp,z10")
(set_attr "type" "*,*,*,*,*,*,larl")
- (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")])
+ (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")
+ (set_attr "relative_long" "*,*,*,*,*,*,yes")])
; Compare (unsigned) instructions
"clhrl\t%0,%1"
[(set_attr "op_type" "RIL")
(set_attr "type" "larl")
- (set_attr "z10prop" "z10_super")])
+ (set_attr "z10prop" "z10_super")
+ (set_attr "relative_long" "yes")])
; clhrl, clghrl
(define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
"cl<g>hrl\t%0,%1"
[(set_attr "op_type" "RIL")
(set_attr "type" "larl")
- (set_attr "z10prop" "z10_super")])
+ (set_attr "z10prop" "z10_super")
+ (set_attr "relative_long" "yes")])
(define_insn "*cmpdi_ccu_zero"
[(set (reg CC_REGNUM)
(compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand"
- "d,RT,b"))
- (match_operand:DI 0 "register_operand" "d, d,d")))]
+ "d,T,b"))
+ (match_operand:DI 0 "register_operand" "d,d,d")))]
"s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH"
"@
clgfr\t%0,%1
[(set_attr "op_type" "RRE,RXY,RIL")
(set_attr "cpu_facility" "*,*,z10")
(set_attr "type" "*,*,larl")
- (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")])
+ (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")
+ (set_attr "relative_long" "*,*,yes")])
(define_insn "*cmpdi_ccu"
[(set (reg CC_REGNUM)
(compare (match_operand:DI 0 "nonimmediate_operand"
- "d, d,d,Q, d, Q,BQ")
+ "d, d,d,Q,d, Q,BQ")
(match_operand:DI 1 "general_operand"
- "d,Op,b,D,RT,BQ,Q")))]
+ "d,Op,b,D,T,BQ,Q")))]
"s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH"
"@
clgr\t%0,%1
[(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS")
(set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*")
(set_attr "type" "*,*,larl,*,*,*,*")
- (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")])
+ (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")
+ (set_attr "relative_long" "*,*,yes,*,*,*,*")])
(define_insn "*cmpsi_ccu"
[(set (reg CC_REGNUM)
#
#"
[(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS")
- (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*")
+ (set_attr "cpu_facility" "*,extimm,z10,z10,*,longdisp,*,*")
(set_attr "type" "*,*,larl,*,*,*,*,*")
- (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")])
+ (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")
+ (set_attr "relative_long" "*,*,yes,*,*,*,*,*")])
(define_insn "*cmphi_ccu"
[(set (reg CC_REGNUM)
#
#"
[(set_attr "op_type" "RS,RSY,SIL,SS,SS")
- (set_attr "cpu_facility" "*,*,z10,*,*")
+ (set_attr "cpu_facility" "*,longdisp,z10,*,*")
(set_attr "z10prop" "*,*,z10_super,*,*")])
(define_insn "*cmpqi_ccu"
#
#"
[(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")
+ (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*")
(set_attr "z10prop" "*,*,z10_super,z10_super,*,*")])
; (TF|DF|SF|TD|DD|SD) instructions
+
+; FIXME: load and test instructions turn SNaN into QNaN what is not
+; acceptable if the target will be used afterwards. On the other hand
+; they are quite convenient for implementing comparisons with 0.0. So
+; try to enable them via splitter/peephole if the value isn't needed anymore.
+; See testcases: load-and-test-fp-1.c and load-and-test-fp-2.c
+
; ltxbr, ltdbr, ltebr, ltxtr, ltdtr
(define_insn "*cmp<mode>_ccs_0"
[(set (reg CC_REGNUM)
- (compare (match_operand:FP 0 "register_operand" "f")
- (match_operand:FP 1 "const0_operand" "")))]
+ (compare (match_operand:FP 0 "register_operand" "f")
+ (match_operand:FP 1 "const0_operand" "")))
+ (clobber (match_operand:FP 2 "register_operand" "=0"))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
"lt<xde><bt>r\t%0,%0"
[(set_attr "op_type" "RRE")
(set_attr "type" "fsimp<mode>")])
-; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb
+; VX: TFmode in FPR pairs: use cxbr instead of wfcxb
+; cxtr, cdtr, cxbr, cdbr, cebr, cdb, ceb, wfcsb, wfcdb
(define_insn "*cmp<mode>_ccs"
[(set (reg CC_REGNUM)
- (compare (match_operand:FP 0 "register_operand" "f,f")
- (match_operand:FP 1 "general_operand" "f,<Rf>")))]
+ (compare (match_operand:FP 0 "register_operand" "f,f,v,v")
+ (match_operand:FP 1 "general_operand" "f,R,v,v")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT"
"@
c<xde><bt>r\t%0,%1
- c<xde>b\t%0,%1"
- [(set_attr "op_type" "RRE,RXE")
- (set_attr "type" "fsimp<mode>")])
-
-; wfcedbs, wfchdbs, wfchedbs
-(define_insn "*vec_cmp<insn_cmp>df_cconly"
- [(set (reg:VFCMP CC_REGNUM)
- (compare:VFCMP (match_operand:DF 0 "register_operand" "v")
- (match_operand:DF 1 "register_operand" "v")))
- (clobber (match_scratch:V2DI 2 "=v"))]
- "TARGET_Z13 && TARGET_HARD_FLOAT"
- "wfc<asm_fcmp>dbs\t%v2,%v0,%v1"
- [(set_attr "op_type" "VRR")])
+ c<xde>b\t%0,%1
+ wfcdb\t%0,%1
+ wfcsb\t%0,%1"
+ [(set_attr "op_type" "RRE,RXE,VRR,VRR")
+ (set_attr "cpu_facility" "*,*,vx,vxe")
+ (set_attr "enabled" "*,<DSF>,<DF>,<SF>")])
; Compare and Branch instructions
; movti instruction pattern(s).
;
+
+; Separate out the register pair alternative since constraints (P) are
+; not able to deal with const_wide_int's. But predicates do.
+(define_insn "*movti_bigconst"
+ [(set (match_operand:TI 0 "register_operand" "=d")
+ (match_operand:TI 1 "reload_const_wide_int_operand" ""))]
+ "TARGET_ZARCH"
+ "#")
+
; FIXME: More constants are possible by enabling jxx, jyy constraints
; for TImode (use double-int for the calculations)
(define_insn "movti"
- [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,v, v, v,v,d, v,QR, d,o")
- (match_operand:TI 1 "general_operand" "QS, d,v,j00,jm1,d,v,QR, v,dPRT,d"))]
+ [(set (match_operand:TI 0 "nonimmediate_operand" "=d,S,v, v, v,v,d,v,R,d, d, d, d, d,o")
+ (match_operand:TI 1 "general_operand" " S,d,v,j00,jm1,d,v,R,v,K,NxHD0,Os,NxSD0,dT,d"))]
"TARGET_ZARCH"
"@
lmg\t%0,%N0,%S1
vone\t%v0
vlvgp\t%v0,%1,%N1
#
- vl\t%v0,%1
- vst\t%v1,%0
+ vl\t%v0,%1%A1
+ vst\t%v1,%0%A0
+ #
+ #
+ #
+ #
#
#"
- [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*")
- (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*")
- (set_attr "cpu_facility" "*,*,vec,vec,vec,vec,vec,vec,vec,*,*")])
+ [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*,*,*,*,*")
+ (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*,*,*,*,*")
+ (set_attr "cpu_facility" "*,*,vx,vx,vx,vx,vx,vx,vx,*,*,*,extimm,*,*")])
(define_split
[(set (match_operand:TI 0 "nonimmediate_operand" "")
(match_operand:TI 1 "general_operand" ""))]
"TARGET_ZARCH && reload_completed
+ && !s_operand (operands[0], TImode)
+ && !s_operand (operands[1], TImode)
&& s390_split_ok_p (operands[0], operands[1], TImode, 0)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
[(set (match_operand:TI 0 "nonimmediate_operand" "")
(match_operand:TI 1 "general_operand" ""))]
"TARGET_ZARCH && reload_completed
+ && !s_operand (operands[0], TImode)
+ && !s_operand (operands[1], TImode)
&& s390_split_ok_p (operands[0], operands[1], TImode, 1)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
emit_symbolic_move (operands);
})
-(define_insn "*movdi_larl"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (match_operand:DI 1 "larl_operand" "X"))]
- "TARGET_64BIT
- && !FP_REG_P (operands[0])"
- "larl\t%0,%1"
- [(set_attr "op_type" "RIL")
- (set_attr "type" "larl")
- (set_attr "z10prop" "z10_super_A1")])
-
(define_insn "*movdi_64"
[(set (match_operand:DI 0 "nonimmediate_operand"
- "=d, d, d, d, d, d, d, d,f,d,d,d,d, d,RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d, v,QR")
+ "=d, d, d, d, d, d, d, d,f,d,d,d,d,d,T,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d,v,R,d")
(match_operand:DI 1 "general_operand"
- " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT, d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,QR, v"))]
+ " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,T,d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,R,v,ZL"))]
"TARGET_ZARCH"
"@
lghi\t%0,%h1
vlvgg\t%v0,%1,0
vlgvg\t%0,%v1,0
vleg\t%v0,%1,0
- vsteg\t%v1,%0,0"
+ vsteg\t%v1,%0,0
+ larl\t%0,%1"
[(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY,
- RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS,VRX,VRX")
+ RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS,
+ VRX,VRX,RIL")
(set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store,
floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*,
- *,*,*,*,*,*,*")
+ *,*,*,*,*,*,*,larl")
(set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp,
z10,*,*,*,*,*,longdisp,*,longdisp,
- z10,z10,*,*,*,*,vec,vec,vec,vec,vec,vec")
+ z10,z10,*,*,*,*,vx,vx,vx,vx,vx,vx,*")
(set_attr "z10prop" "z10_fwd_A1,
z10_fwd_E1,
z10_fwd_E1,
*,
*,
*,
- *,*,*,*,*,*,*")
+ *,*,*,*,*,*,*,
+ z10_super_A1")
+ (set_attr "relative_long" "*,*,*,*,*,*,*,*,*,*,
+ *,yes,*,*,*,*,*,*,*,*,
+ yes,*,*,*,*,*,*,*,*,*,
+ *,*,yes")
])
(define_split
(define_insn "*movdi_31"
[(set (match_operand:DI 0 "nonimmediate_operand"
- "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
+ "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d")
(match_operand:DI 1 "general_operand"
- " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))]
+ " Q,S,d,d,dPT,d, *f, R, T,*f,*f,b"))]
"!TARGET_ZARCH"
"@
lm\t%0,%N0,%S1
#"
[(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*")
(set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")
- (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")])
+ (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*,*,*,longdisp,*,longdisp,z10")])
; For a load from a symbol ref we can use one of the target registers
; together with larl to load the address.
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(match_operand:DI 1 "general_operand" ""))]
"!TARGET_ZARCH && reload_completed
+ && !s_operand (operands[0], DImode)
+ && !s_operand (operands[1], DImode)
&& s390_split_ok_p (operands[0], operands[1], DImode, 0)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(match_operand:DI 1 "general_operand" ""))]
"!TARGET_ZARCH && reload_completed
+ && !s_operand (operands[0], DImode)
+ && !s_operand (operands[1], DImode)
&& s390_split_ok_p (operands[0], operands[1], DImode, 1)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
(define_insn "*la_64"
[(set (match_operand:DI 0 "register_operand" "=d,d")
- (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
+ (match_operand:QI 1 "address_operand" "ZR,ZT"))]
"TARGET_64BIT"
"@
la\t%0,%a1
lay\t%0,%a1"
[(set_attr "op_type" "RX,RXY")
(set_attr "type" "la")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
(define_peephole2
(define_insn "*movsi_larl"
[(set (match_operand:SI 0 "register_operand" "=d")
(match_operand:SI 1 "larl_operand" "X"))]
- "!TARGET_64BIT && TARGET_CPU_ZARCH
+ "!TARGET_64BIT
&& !FP_REG_P (operands[0])"
"larl\t%0,%1"
[(set_attr "op_type" "RIL")
(set_attr "type" "larl")
- (set_attr "z10prop" "z10_fwd_A1")])
+ (set_attr "z10prop" "z10_fwd_A1")
+ (set_attr "relative_long" "yes")])
(define_insn "*movsi_zarch"
[(set (match_operand:SI 0 "nonimmediate_operand"
- "=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d, v,QR")
+ "=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d,v,R")
(match_operand:SI 1 "general_operand"
- " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,QR, v"))]
+ " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,R,v"))]
"TARGET_ZARCH"
"@
lhi\t%0,%h1
ly\t%0,%1
st\t%1,%0
sty\t%1,%0
- lder\t%0,%1
+ ldr\t%0,%1
ler\t%0,%1
lde\t%0,%1
le\t%0,%1
vlef\t%v0,%1,0
vstef\t%v1,%0,0"
[(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY,
- RRE,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX")
+ RR,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX")
(set_attr "type" "*,
*,
*,
*,
*,*,*,*,*,*,*")
(set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp,
- vec,*,vec,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vec,vec,vec,vec,vec,vec")
+ vx,*,vx,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vx,vx,vx,vx,vx,vx")
(set_attr "z10prop" "z10_fwd_A1,
z10_fwd_E1,
z10_fwd_E1,
*,
z10_rec,
z10_super,
- *,*,*,*,*,*,*")])
+ *,*,*,*,*,*,*")
+ (set_attr "relative_long" "*,*,*,*,*,yes,*,*,*,*,
+ *,*,*,*,*,*,*,*,*,*,
+ *,yes,*,*,*,*,*,*,*,*")])
(define_insn "*movsi_esa"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t")
lr\t%0,%1
l\t%0,%1
st\t%1,%0
- lder\t%0,%1
+ ldr\t%0,%1
ler\t%0,%1
lde\t%0,%1
le\t%0,%1
sar\t%0,%1
stam\t%1,%1,%S0
lam\t%0,%0,%S1"
- [(set_attr "op_type" "RI,RR,RX,RX,RRE,RR,RXE,RX,RX,RRE,RRE,RS,RS")
+ [(set_attr "op_type" "RI,RR,RX,RX,RR,RR,RXE,RX,RX,RRE,RRE,RS,RS")
(set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*")
(set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1,
z10_super,*,*")
- (set_attr "cpu_facility" "*,*,*,*,vec,*,vec,*,*,*,*,*,*")
+ (set_attr "cpu_facility" "*,*,*,*,vx,*,vx,*,*,*,*,*,*")
])
(define_peephole2
(define_insn "*la_31"
[(set (match_operand:SI 0 "register_operand" "=d,d")
- (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))]
+ (match_operand:QI 1 "address_operand" "ZR,ZT"))]
"!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
"@
la\t%0,%a1
lay\t%0,%a1"
[(set_attr "op_type" "RX,RXY")
(set_attr "type" "la")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
(define_peephole2
(define_insn "*la_31_and"
[(set (match_operand:SI 0 "register_operand" "=d,d")
- (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")
+ (and:SI (match_operand:QI 1 "address_operand" "ZR,ZT")
(const_int 2147483647)))]
"!TARGET_64BIT"
"@
lay\t%0,%a1"
[(set_attr "op_type" "RX,RXY")
(set_attr "type" "la")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
(define_insn_and_split "*la_31_and_cc"
(define_insn "force_la_31"
[(set (match_operand:SI 0 "register_operand" "=d,d")
- (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))
+ (match_operand:QI 1 "address_operand" "ZR,ZT"))
(use (const_int 0))]
"!TARGET_64BIT"
"@
lay\t%0,%a1"
[(set_attr "op_type" "RX")
(set_attr "type" "la")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")])
;
})
(define_insn "*movhi"
- [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d, v,QR")
- (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,K,v,d,v,QR, v"))]
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d,v,R")
+ (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,K,v,d,v,R,v"))]
""
"@
lr\t%0,%1
vsteh\t%v1,%0,0"
[(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX")
(set_attr "type" "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*")
- (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10,vec,vec,vec,vec,vec,vec")
+ (set_attr "cpu_facility" "*,*,*,longdisp,z10,*,longdisp,z10,z10,vx,vx,vx,vx,vx,vx")
(set_attr "z10prop" "z10_fr_E1,
z10_fwd_A1,
z10_super_E1,
z10_rec,
z10_rec,
z10_rec,
- z10_super,*,*,*,*,*,*")])
+ z10_super,*,*,*,*,*,*")
+ (set_attr "relative_long" "*,*,*,*,yes,*,*,yes,*,*,*,*,*,*,*")])
(define_peephole2
[(set (match_operand:HI 0 "register_operand" "")
})
(define_insn "*movqi"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d, v,QR")
- (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q,K,v,d,v,QR, v"))]
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d,v,R")
+ (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q,K,v,d,v,R,v"))]
""
"@
lr\t%0,%1
vsteb\t%v1,%0,0"
[(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX")
(set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*")
- (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,vec,vec,vec,vec,vec,vec")
+ (set_attr "cpu_facility" "*,*,*,longdisp,*,longdisp,*,longdisp,*,vx,vx,vx,vx,vx,vx")
(set_attr "z10prop" "z10_fr_E1,
z10_fwd_A1,
z10_super_E1,
ic\t%0,%1
icy\t%0,%1"
[(set_attr "op_type" "RX,RXY")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1")])
;
icm\t%0,3,%S1
icmy\t%0,3,%S1"
[(set_attr "op_type" "RS,RSY")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1")])
;
ear\t%0,%1"
[(set_attr "op_type" "RR,RX,RXY,RRE")
(set_attr "type" "lr,load,load,*")
+ (set_attr "cpu_facility" "*,*,longdisp,*")
(set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")])
;
"")
(define_insn "*mov<mode>_64"
- [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
- (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
+ [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o,d,S, d,o")
+ (match_operand:TD_TF 1 "general_operand" " G,f,o,f,S,d,dT,d"))]
"TARGET_ZARCH"
"@
lzxr\t%0
[(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
(match_operand:TD_TF 1 "general_operand" ""))]
"TARGET_ZARCH && reload_completed
+ && !s_operand (operands[0], <MODE>mode)
+ && !s_operand (operands[1], <MODE>mode)
&& s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
[(set (match_operand:TD_TF 0 "nonimmediate_operand" "")
(match_operand:TD_TF 1 "general_operand" ""))]
"TARGET_ZARCH && reload_completed
+ && !s_operand (operands[0], <MODE>mode)
+ && !s_operand (operands[1], <MODE>mode)
&& s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
(define_insn "*mov<mode>_64dfp"
[(set (match_operand:DD_DF 0 "nonimmediate_operand"
- "=f,f,f,d,f,f,R,T,d,d,d, d,b,RT,v,v,d,v,QR")
+ "=f,f,f,d,f,f,R,T,d,d,d,d,b,T,v,v,v,d,v,R")
(match_operand:DD_DF 1 "general_operand"
- " G,f,d,f,R,T,f,f,G,d,b,RT,d, d,v,d,v,QR,v"))]
+ " G,f,d,f,R,T,f,f,G,d,b,T,d,d,v,G,d,v,R,v"))]
"TARGET_DFP"
"@
lzdr\t%0
stgrl\t%1,%0
stg\t%1,%0
vlr\t%v0,%v1
+ vleig\t%v0,0,0
vlvgg\t%v0,%1,0
vlgvg\t%0,%v1,0
vleg\t%0,%1,0
vsteg\t%1,%0,0"
- [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRS,VRS,VRX,VRX")
+ [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRI,VRS,VRS,VRX,VRX")
(set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf,
- fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,load,store")
- (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*")
- (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,z10,*,z10,*,vec,vec,vec,vec,vec")])
+ fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,*,load,store")
+ (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*,*")
+ (set_attr "cpu_facility" "z196,*,*,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vx,vx,vx,vx,vx,vx")
+ (set_attr "relative_long" "*,*,*,*,*,*,*,*,*,*,yes,*,yes,*,*,*,*,*,*,*")])
(define_insn "*mov<mode>_64"
- [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d, d,b,RT,v,v,QR")
- (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,RT,d, d,v,QR,v"))]
+ [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,d,b,T")
+ (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,T,d,d"))]
"TARGET_ZARCH"
"@
lzdr\t%0
lgrl\t%0,%1
lg\t%0,%1
stgrl\t%1,%0
- stg\t%1,%0
- vlr\t%v0,%v1
- vleg\t%v0,%1,0
- vsteg\t%v1,%0,0"
- [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRX,VRX")
+ stg\t%1,%0"
+ [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY")
(set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
- fstore<mode>,fstore<mode>,*,lr,load,load,store,store,*,load,store")
- (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*")
- (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,z10,*,z10,*,vec,vec,vec")])
+ fstore<mode>,fstore<mode>,*,lr,load,load,store,store")
+ (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
+ (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*")
+ (set_attr "relative_long" "*,*,*,*,*,*,*,*,yes,*,*,*")])
(define_insn "*mov<mode>_31"
[(set (match_operand:DD_DF 0 "nonimmediate_operand"
- "=f,f,f,f,R,T,d,d,Q,S, d,o")
+ "=f,f,f,f,R,T,d,d,Q,S, d,o")
(match_operand:DD_DF 1 "general_operand"
- " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
+ " G,f,R,T,f,f,Q,S,d,d,dPT,d"))]
"!TARGET_ZARCH"
"@
lzdr\t%0
[(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
(set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>,
fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")
- (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")])
+ (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,longdisp,*,longdisp,*,*")])
(define_split
[(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
(match_operand:DD_DF 1 "general_operand" ""))]
"!TARGET_ZARCH && reload_completed
+ && !s_operand (operands[0], <MODE>mode)
+ && !s_operand (operands[1], <MODE>mode)
&& s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
[(set (match_operand:DD_DF 0 "nonimmediate_operand" "")
(match_operand:DD_DF 1 "general_operand" ""))]
"!TARGET_ZARCH && reload_completed
+ && !s_operand (operands[0], <MODE>mode)
+ && !s_operand (operands[1], <MODE>mode)
&& s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))]
(define_insn "mov<mode>"
[(set (match_operand:SD_SF 0 "nonimmediate_operand"
- "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,QR")
+ "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,R")
(match_operand:SD_SF 1 "general_operand"
- " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,QR,v"))]
+ " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,R,v"))]
""
"@
lzer\t%0
- lder\t%0,%1
+ ldr\t%0,%1
ler\t%0,%1
lde\t%0,%1
le\t%0,%1
st\t%1,%0
sty\t%1,%0
vlr\t%v0,%v1
- vleif\t%v0,0
+ vleif\t%v0,0,0
vlvgf\t%v0,%1,0
vlgvf\t%0,%v1,0
- vleg\t%0,%1,0
- vsteg\t%1,%0,0"
- [(set_attr "op_type" "RRE,RRE,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX")
+ vlef\t%0,%1,0
+ vstef\t%1,%0,0"
+ [(set_attr "op_type" "RRE,RR,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX")
(set_attr "type" "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>,
fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store")
(set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*")
- (set_attr "cpu_facility" "z196,vec,*,vec,*,*,*,*,*,*,z10,*,*,z10,*,*,vec,vec,vec,vec,vec,vec")])
+ (set_attr "cpu_facility" "z196,vx,*,vx,*,longdisp,*,longdisp,*,*,z10,*,longdisp,z10,*,longdisp,vx,vx,vx,vx,vx,vx")
+ (set_attr "relative_long" "*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*,*,*,*,*")])
;
; movcc instruction pattern
sty\t%1,%0"
[(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
(set_attr "type" "lr,*,*,load,load,store,store")
+ (set_attr "cpu_facility" "*,*,*,*,longdisp,*,longdisp")
(set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")
(set_attr "z196prop" "*,*,z196_ends,*,*,*,*")])
[(set (match_operand:BLK 3 "memory_operand" "")
(match_operand:BLK 4 "memory_operand" ""))
(use (match_operand 5 "const_int_operand" ""))])]
- "s390_offset_p (operands[0], operands[3], operands[2])
+ "((INTVAL (operands[2]) > 16 && INTVAL (operands[5]) > 16)
+ || (INTVAL (operands[2]) + INTVAL (operands[5]) <= 16))
+ && s390_offset_p (operands[0], operands[3], operands[2])
&& s390_offset_p (operands[1], operands[4], operands[2])
&& !s390_overlap_p (operands[0], operands[1],
INTVAL (operands[2]) + INTVAL (operands[5]))
operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
+(define_peephole2
+ [(parallel
+ [(set (match_operand:BLK 0 "plus16_Q_operand" "")
+ (match_operand:BLK 1 "plus16_Q_operand" ""))
+ (use (match_operand 2 "const_int_operand" ""))])]
+ "INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32"
+ [(parallel
+ [(set (match_dup 0) (match_dup 1))
+ (use (const_int 16))])
+ (parallel
+ [(set (match_dup 3) (match_dup 4))
+ (use (match_dup 5))])]
+ "operands[3] = change_address (operands[0], VOIDmode,
+ plus_constant (Pmode, XEXP (operands[0], 0), 16));
+ operands[4] = change_address (operands[1], VOIDmode,
+ plus_constant (Pmode, XEXP (operands[1], 0), 16));
+ operands[5] = GEN_INT (INTVAL (operands[2]) - 16);")
+
;
; load_multiple pattern(s).
(define_insn "*load_multiple_di"
[(match_parallel 0 "load_multiple_operation"
[(set (match_operand:DI 1 "register_operand" "=r")
- (match_operand:DI 2 "s_operand" "QS"))])]
+ (match_operand:DI 2 "s_operand" "S"))])]
"reload_completed && TARGET_ZARCH"
{
int words = XVECLEN (operands[0], 0);
return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
}
[(set_attr "op_type" "RS,RSY")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "type" "lm")])
;
(define_insn "*store_multiple_di"
[(match_parallel 0 "store_multiple_operation"
- [(set (match_operand:DI 1 "s_operand" "=QS")
+ [(set (match_operand:DI 1 "s_operand" "=S")
(match_operand:DI 2 "register_operand" "r"))])]
"reload_completed && TARGET_ZARCH"
{
return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
}
[(set_attr "op_type" "RS,RSY")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "type" "stm")])
;;
&& GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
"exrl\t%1,%3"
[(set_attr "op_type" "RIL")
- (set_attr "type" "cs")])
+ (set_attr "type" "cs")
+ (set_attr "relative_long" "yes")])
(define_insn "*execute"
[(match_parallel 0 "execute_operation"
;
(define_expand "movstr"
+ [(match_operand 0 "register_operand" "")
+ (match_operand 1 "memory_operand" "")
+ (match_operand 2 "memory_operand" "")]
+ ""
+{
+ if (TARGET_64BIT)
+ emit_insn (gen_movstrdi (operands[0], operands[1], operands[2]));
+ else
+ emit_insn (gen_movstrsi (operands[0], operands[1], operands[2]));
+ DONE;
+})
+
+(define_expand "movstr<P:mode>"
[(set (reg:SI 0) (const_int 0))
(parallel
[(clobber (match_dup 3))
(set (match_operand:BLK 1 "memory_operand" "")
(match_operand:BLK 2 "memory_operand" ""))
- (set (match_operand 0 "register_operand" "")
- (unspec [(match_dup 1)
+ (set (match_operand:P 0 "register_operand" "")
+ (unspec:P [(match_dup 1)
(match_dup 2)
(reg:SI 0)] UNSPEC_MVST))
(clobber (reg:CC CC_REGNUM))])]
""
{
- rtx addr1 = gen_reg_rtx (Pmode);
- rtx addr2 = gen_reg_rtx (Pmode);
+ rtx addr1, addr2;
+
+ if (TARGET_VX && optimize_function_for_speed_p (cfun))
+ {
+ s390_expand_vec_movstr (operands[0], operands[1], operands[2]);
+ DONE;
+ }
+
+ addr1 = gen_reg_rtx (Pmode);
+ addr2 = gen_reg_rtx (Pmode);
emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX));
(set (mem:BLK (match_operand:P 1 "register_operand" "0"))
(mem:BLK (match_operand:P 3 "register_operand" "2")))
(set (match_operand:P 0 "register_operand" "=d")
- (unspec [(mem:BLK (match_dup 1))
+ (unspec:P [(mem:BLK (match_dup 1))
(mem:BLK (match_dup 3))
(reg:SI 0)] UNSPEC_MVST))
(clobber (reg:CC CC_REGNUM))]
(use (match_operand 2 "register_operand" ""))
(use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
(clobber (match_operand 3 "register_operand" ""))]
- "reload_completed && TARGET_CPU_ZARCH"
+ "reload_completed"
[(set (match_dup 3) (label_ref (match_dup 4)))
(parallel
[(unspec [(match_dup 2) (mem:BLK (match_dup 3))
(use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
(clobber (match_operand 2 "register_operand" ""))
(clobber (reg:CC CC_REGNUM))]
- "reload_completed && TARGET_CPU_ZARCH"
+ "reload_completed"
[(set (match_dup 2) (label_ref (match_dup 3)))
(parallel
[(unspec [(match_dup 1) (mem:BLK (match_dup 2))
; Initialize a block of arbitrary length with (operands[2] % 256).
-(define_expand "setmem_long"
+(define_expand "setmem_long_<P:mode>"
[(parallel
[(clobber (match_dup 1))
(set (match_operand:BLK 0 "memory_operand" "")
- (match_operand 2 "shift_count_or_setmem_operand" ""))
- (use (match_operand 1 "general_operand" ""))
+ (unspec:BLK [(match_operand:P 2 "setmem_operand" "")
+ (match_dup 4)] UNSPEC_REPLICATE_BYTE))
(use (match_dup 3))
(clobber (reg:CC CC_REGNUM))])]
""
operands[0] = replace_equiv_address_nv (operands[0], addr0);
operands[1] = reg0;
operands[3] = reg1;
+ operands[4] = gen_lowpart (Pmode, operands[1]);
})
+; Patterns for 31 bit + Esa and 64 bit + Zarch.
+
(define_insn "*setmem_long"
[(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
(set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
- (match_operand 2 "shift_count_or_setmem_operand" "Y"))
- (use (match_dup 3))
+ (unspec:BLK [(match_operand:P 2 "setmem_operand" "Y")
+ (subreg:P (match_dup 3) <modesize>)]
+ UNSPEC_REPLICATE_BYTE))
(use (match_operand:<DBL> 1 "register_operand" "d"))
(clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT || !TARGET_ZARCH"
(define_insn "*setmem_long_and"
[(clobber (match_operand:<DBL> 0 "register_operand" "=d"))
(set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0))
- (and (match_operand 2 "shift_count_or_setmem_operand" "Y")
- (match_operand 4 "const_int_operand" "n")))
- (use (match_dup 3))
+ (unspec:BLK [(zero_extend:P (match_operand:QI 2 "setmem_operand" "Y"))
+ (subreg:P (match_dup 3) <modesize>)]
+ UNSPEC_REPLICATE_BYTE))
(use (match_operand:<DBL> 1 "register_operand" "d"))
(clobber (reg:CC CC_REGNUM))]
- "(TARGET_64BIT || !TARGET_ZARCH) &&
- (INTVAL (operands[4]) & 255) == 255"
+ "(TARGET_64BIT || !TARGET_ZARCH)"
"mvcle\t%0,%1,%Y2\;jo\t.-4"
[(set_attr "length" "8")
(set_attr "type" "vs")])
+; Variants for 31 bit + Zarch, necessary because of the odd in-register offsets
+; of the SImode subregs.
+
(define_insn "*setmem_long_31z"
[(clobber (match_operand:TI 0 "register_operand" "=d"))
(set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
- (match_operand 2 "shift_count_or_setmem_operand" "Y"))
- (use (match_dup 3))
+ (unspec:BLK [(match_operand:SI 2 "setmem_operand" "Y")
+ (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE))
(use (match_operand:TI 1 "register_operand" "d"))
(clobber (reg:CC CC_REGNUM))]
"!TARGET_64BIT && TARGET_ZARCH"
[(set_attr "length" "8")
(set_attr "type" "vs")])
+(define_insn "*setmem_long_and_31z"
+ [(clobber (match_operand:TI 0 "register_operand" "=d"))
+ (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4))
+ (unspec:BLK [(zero_extend:SI (match_operand:QI 2 "setmem_operand" "Y"))
+ (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE))
+ (use (match_operand:TI 1 "register_operand" "d"))
+ (clobber (reg:CC CC_REGNUM))]
+ "(!TARGET_64BIT && TARGET_ZARCH)"
+ "mvcle\t%0,%1,%Y2\;jo\t.-4"
+ [(set_attr "length" "8")
+ (set_attr "type" "vs")])
+
;
; cmpmemM instruction pattern(s).
;
(use (match_operand 2 "register_operand" ""))
(use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
(clobber (match_operand 3 "register_operand" ""))]
- "reload_completed && TARGET_CPU_ZARCH"
+ "reload_completed"
[(set (match_dup 3) (label_ref (match_dup 4)))
(parallel
[(unspec [(match_dup 2) (mem:BLK (match_dup 3))
icm\t%0,%2,%S1
icmy\t%0,%2,%S1"
[(set_attr "op_type" "RS,RSY")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1")])
(define_insn "*sethighpartdi_64"
[(set (match_operand:DI 0 "register_operand" "=d")
- (unspec:DI [(match_operand:BLK 1 "s_operand" "QS")
+ (unspec:DI [(match_operand:BLK 1 "s_operand" "S")
(match_operand 2 "const_int_operand" "n")] UNSPEC_ICM))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH"
icm\t%0,%2,%S1
icmy\t%0,%2,%S1"
[(set_attr "op_type" "RS,RSY")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1")])
;
(clobber (reg:CC CC_REGNUM))])]
"TARGET_Z10"
{
+ if (! EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), 64))
+ FAIL;
/* Starting with zEC12 there is risbgn not clobbering CC. */
if (TARGET_ZEC12)
{
}
})
-(define_insn "*extzv<mode>_zEC12"
+(define_insn "*extzv<mode><clobbercc_or_nocc>"
[(set (match_operand:GPR 0 "register_operand" "=d")
(zero_extract:GPR
(match_operand:GPR 1 "register_operand" "d")
(match_operand 2 "const_int_operand" "") ; size
- (match_operand 3 "const_int_operand" "")))] ; start]
- "TARGET_ZEC12"
- "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
- [(set_attr "op_type" "RIE")])
+ (match_operand 3 "const_int_operand" ""))) ; start
+ ]
+ "<z10_or_zEC12_cond>
+ && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]),
+ GET_MODE_BITSIZE (<MODE>mode))"
+ "<risbg_n>\t%0,%1,64-%2,128+63,<bitoff_plus>%3+%2" ; dst, src, start, end, shift
+ [(set_attr "op_type" "RIE")
+ (set_attr "z10prop" "z10_super_E1")])
-(define_insn "*extzv<mode>_z10"
- [(set (match_operand:GPR 0 "register_operand" "=d")
- (zero_extract:GPR
- (match_operand:GPR 1 "register_operand" "d")
- (match_operand 2 "const_int_operand" "") ; size
- (match_operand 3 "const_int_operand" ""))) ; start
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_Z10"
- "risbg\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
+; 64 bit: (a & -16) | ((b >> 8) & 15)
+(define_insn "*extzvdi<clobbercc_or_nocc>_lshiftrt"
+ [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
+ (match_operand 1 "const_int_operand" "") ; size
+ (match_operand 2 "const_int_operand" "")) ; start
+ (lshiftrt:DI (match_operand:DI 3 "register_operand" "d")
+ (match_operand:DI 4 "nonzero_shift_count_operand" "")))]
+ "<z10_or_zEC12_cond>
+ && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64)
+ && 64 - UINTVAL (operands[4]) >= UINTVAL (operands[1])"
+ "<risbg_n>\t%0,%3,%2,%2+%1-1,128-%2-%1-%4"
+ [(set_attr "op_type" "RIE")
+ (set_attr "z10prop" "z10_super_E1")])
+
+; 32 bit: (a & -16) | ((b >> 8) & 15)
+(define_insn "*<risbg_n>_ior_and_sr_ze"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (ior:SI (and:SI
+ (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "const_int_operand" ""))
+ (subreg:SI
+ (zero_extract:DI
+ (match_operand:DI 3 "register_operand" "d")
+ (match_operand 4 "const_int_operand" "") ; size
+ (match_operand 5 "const_int_operand" "")) ; start
+ 4)))]
+ "<z10_or_zEC12_cond>
+ && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[4]), INTVAL (operands[5]), 64)
+ && UINTVAL (operands[2]) == (HOST_WIDE_INT_M1U << UINTVAL (operands[4]))"
+ "<risbg_n>\t%0,%3,64-%4,63,%4+%5"
+ [(set_attr "op_type" "RIE")
+ (set_attr "z10prop" "z10_super_E1")])
+
+; ((int)foo >> 10) & 1;
+(define_insn "*extract1bitdi<clobbercc_or_nocc>"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (ne:DI (zero_extract:DI
+ (match_operand:DI 1 "register_operand" "d")
+ (const_int 1) ; size
+ (match_operand 2 "const_int_operand" "")) ; start
+ (const_int 0)))]
+ "<z10_or_zEC12_cond>
+ && EXTRACT_ARGS_IN_RANGE (1, INTVAL (operands[2]), 64)"
+ "<risbg_n>\t%0,%1,64-1,128+63,%2+1" ; dst, src, start, end, shift
+ [(set_attr "op_type" "RIE")
+ (set_attr "z10prop" "z10_super_E1")])
+
+(define_insn "*<risbg_n>_and_subregdi_rotr"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (and:DI (subreg:DI
+ (rotate:SINT (match_operand:SINT 1 "register_operand" "d")
+ (match_operand:SINT 2 "const_int_operand" "")) 0)
+ (match_operand:DI 3 "contiguous_bitmask_operand" "")))]
+ "<z10_or_zEC12_cond>
+ && (UINTVAL (operands[3])
+ < (HOST_WIDE_INT_1U << (UINTVAL (operands[2]) & 0x3f)))"
+ "<risbg_n>\t%0,%1,%s3,128+%e3,<bitoff_plus>%2" ; dst, src, start, end, shift
+ [(set_attr "op_type" "RIE")
+ (set_attr "z10prop" "z10_super_E1")])
+
+(define_insn "*<risbg_n>_and_subregdi_rotl"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (and:DI (subreg:DI
+ (rotate:SINT (match_operand:SINT 1 "register_operand" "d")
+ (match_operand:SINT 2 "const_int_operand" "")) 0)
+ (match_operand:DI 3 "contiguous_bitmask_operand" "")))]
+ "<z10_or_zEC12_cond>
+ && !(UINTVAL (operands[3])
+ & ((HOST_WIDE_INT_1U << (UINTVAL (operands[2]) & 0x3f)) - 1))"
+ "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift
+ [(set_attr "op_type" "RIE")
+ (set_attr "z10prop" "z10_super_E1")])
+
+(define_insn "*<risbg_n>_di_and_rot"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (and:DI (rotate:DI (match_operand:DI 1 "register_operand" "d")
+ (match_operand:DI 2 "const_int_operand" ""))
+ (match_operand:DI 3 "contiguous_bitmask_operand" "")))]
+ "<z10_or_zEC12_cond>"
+ "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift
[(set_attr "op_type" "RIE")
(set_attr "z10prop" "z10_super_E1")])
(define_insn_and_split "*pre_z10_extzv<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
- (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS")
+ (zero_extract:GPR (match_operand:QI 1 "s_operand" "S")
(match_operand 2 "nonzero_shift_count_operand" "")
(const_int 0)))
(clobber (reg:CC CC_REGNUM))]
{
int bitsize = INTVAL (operands[2]);
int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
- int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
+ unsigned HOST_WIDE_INT mask
+ = ((HOST_WIDE_INT_1U << size) - 1) << (GET_MODE_SIZE (SImode) - size);
operands[1] = adjust_address (operands[1], BLKmode, 0);
set_mem_size (operands[1], size);
(define_insn_and_split "*pre_z10_extv<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
- (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS")
+ (sign_extract:GPR (match_operand:QI 1 "s_operand" "S")
(match_operand 2 "nonzero_shift_count_operand" "")
(const_int 0)))
(clobber (reg:CC CC_REGNUM))]
{
int bitsize = INTVAL (operands[2]);
int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */
- int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size);
+ unsigned HOST_WIDE_INT mask
+ = ((HOST_WIDE_INT_1U << size) - 1) << (GET_MODE_SIZE (SImode) - size);
operands[1] = adjust_address (operands[1], BLKmode, 0);
set_mem_size (operands[1], size);
; The normal RTL expansion will never generate a zero_extract where
; the location operand isn't word mode. However, we do this in the
; back-end when generating atomic operations. See s390_two_part_insv.
-(define_insn "*insv<mode>_zEC12"
+(define_insn "*insv<mode><clobbercc_or_nocc>"
[(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
(match_operand 1 "const_int_operand" "I") ; size
(match_operand 2 "const_int_operand" "I")) ; pos
(match_operand:GPR 3 "nonimmediate_operand" "d"))]
- "TARGET_ZEC12
- && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
- "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
- [(set_attr "op_type" "RIE")])
-
-(define_insn "*insv<mode>_z10"
- [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
- (match_operand 1 "const_int_operand" "I") ; size
- (match_operand 2 "const_int_operand" "I")) ; pos
- (match_operand:GPR 3 "nonimmediate_operand" "d"))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_Z10
+ "<z10_or_zEC12_cond>
+ && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]),
+ GET_MODE_BITSIZE (<MODE>mode))
&& (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
- "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
+ "<risbg_n>\t%0,%3,<bitoff_plus>%2,<bitoff_plus>%2+%1-1,<bitsize>-%2-%1"
[(set_attr "op_type" "RIE")
(set_attr "z10prop" "z10_super_E1")])
; and op1 with a mask being 1 for the selected bits and 0 for the rest
; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest
-(define_insn "*insv<mode>_zEC12_noshift"
- [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
- (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
+(define_insn "*insv<mode><clobbercc_or_nocc>_noshift"
+ [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d")
+ (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d,0")
(match_operand:GPR 2 "contiguous_bitmask_operand" ""))
- (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
+ (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0,d")
(match_operand:GPR 4 "const_int_operand" ""))))]
- "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
- "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0"
- [(set_attr "op_type" "RIE")])
+ "<z10_or_zEC12_cond> && INTVAL (operands[2]) == ~INTVAL (operands[4])"
+ "@
+ <risbg_n>\t%0,%1,%<bfstart>2,%<bfend>2,0
+ <risbg_n>\t%0,%3,%<bfstart>4,%<bfend>4,0"
+ [(set_attr "op_type" "RIE")
+ (set_attr "z10prop" "z10_super_E1")])
-(define_insn "*insv<mode>_z10_noshift"
- [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
- (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d")
- (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
- (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0")
- (match_operand:GPR 4 "const_int_operand" ""))))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])"
- "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
+(define_insn "*insv_z10_noshift_cc"
+ [(set (reg CC_REGNUM)
+ (compare
+ (ior:DI
+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0")
+ (match_operand:DI 2 "contiguous_bitmask_operand" ""))
+ (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d")
+ (match_operand:DI 4 "const_int_operand" "")))
+ (const_int 0)))
+ (set (match_operand:DI 0 "nonimmediate_operand" "=d,d")
+ (ior:DI (and:DI (match_dup 1) (match_dup 2))
+ (and:DI (match_dup 3) (match_dup 4))))]
+ "TARGET_Z10 && s390_match_ccmode (insn, CCSmode)
+ && INTVAL (operands[2]) == ~INTVAL (operands[4])"
+ "@
+ risbg\t%0,%1,%s2,%e2,0
+ risbg\t%0,%3,%s4,%e4,0"
+ [(set_attr "op_type" "RIE")
+ (set_attr "z10prop" "z10_super_E1")])
+
+(define_insn "*insv_z10_noshift_cconly"
+ [(set
+ (reg CC_REGNUM)
+ (compare
+ (ior:DI
+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0")
+ (match_operand:DI 2 "contiguous_bitmask_operand" ""))
+ (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d")
+ (match_operand:DI 4 "const_int_operand" "")))
+ (const_int 0)))
+ (clobber (match_scratch:DI 0 "=d,d"))]
+ "TARGET_Z10 && s390_match_ccmode (insn, CCSmode)
+ && INTVAL (operands[2]) == ~INTVAL (operands[4])"
+ "@
+ risbg\t%0,%1,%s2,%e2,0
+ risbg\t%0,%3,%s4,%e4,0"
[(set_attr "op_type" "RIE")
(set_attr "z10prop" "z10_super_E1")])
; Implement appending Y on the left of S bits of X
; x = (y << s) | (x & ((1 << s) - 1))
-(define_insn "*insv<mode>_zEC12_appendbitsleft"
+(define_insn "*insv<mode><clobbercc_or_nocc>_appendbitsleft"
[(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
(ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0")
(match_operand:GPR 2 "immediate_operand" ""))
(ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d")
(match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
- "TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1"
- "risbgn\t%0,%3,64-<bitsize>,64-%4-1,%4"
+ "<z10_or_zEC12_cond>
+ && UINTVAL (operands[2]) == (HOST_WIDE_INT_1U << UINTVAL (operands[4])) - 1"
+ "<risbg_n>\t%0,%3,<bitoff>,64-%4-1,%4"
[(set_attr "op_type" "RIE")
(set_attr "z10prop" "z10_super_E1")])
-(define_insn "*insv<mode>_z10_appendbitsleft"
- [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
- (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0")
- (match_operand:GPR 2 "immediate_operand" ""))
- (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d")
- (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1"
- "risbg\t%0,%3,64-<bitsize>,64-%4-1,%4"
+; a = ((i32)a & -16777216) | (((ui32)b) >> 8)
+(define_insn "*<risbg_n>_<mode>_ior_and_lshiftrt"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (ior:GPR (and:GPR
+ (match_operand:GPR 1 "register_operand" "0")
+ (match_operand:GPR 2 "const_int_operand" ""))
+ (lshiftrt:GPR
+ (match_operand:GPR 3 "register_operand" "d")
+ (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
+ "<z10_or_zEC12_cond> && UINTVAL (operands[2])
+ == (HOST_WIDE_INT_M1U
+ << (GET_MODE_BITSIZE (<MODE>mode) - UINTVAL (operands[4])))"
+ "<risbg_n>\t%0,%3,<bitoff_plus>%4,63,64-%4"
+ [(set_attr "op_type" "RIE")
+ (set_attr "z10prop" "z10_super_E1")])
+
+; (ui32)(((ui64)x) >> 48) | ((i32)y & -65536);
+(define_insn "*<risbg_n>_sidi_ior_and_lshiftrt"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (ior:SI (and:SI
+ (match_operand:SI 1 "register_operand" "0")
+ (match_operand:SI 2 "const_int_operand" ""))
+ (subreg:SI
+ (lshiftrt:DI
+ (match_operand:DI 3 "register_operand" "d")
+ (match_operand:DI 4 "nonzero_shift_count_operand" "")) 4)))]
+ "<z10_or_zEC12_cond>
+ && UINTVAL (operands[2]) == ~(HOST_WIDE_INT_M1U >> UINTVAL (operands[4]))"
+ "<risbg_n>\t%0,%3,%4,63,64-%4"
+ [(set_attr "op_type" "RIE")
+ (set_attr "z10prop" "z10_super_E1")])
+
+; (ui32)(((ui64)x) >> 12) & -4
+(define_insn "*trunc_sidi_and_subreg_lshrt<clobbercc_or_nocc>"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (and:SI
+ (subreg:SI (lshiftrt:DI
+ (match_operand:DI 1 "register_operand" "d")
+ (match_operand:DI 2 "nonzero_shift_count_operand" "")) 4)
+ (match_operand:SI 3 "contiguous_bitmask_nowrap_operand" "")))]
+ "<z10_or_zEC12_cond>"
+ "<risbg_n>\t%0,%1,%t3,128+%f3,64-%2"
[(set_attr "op_type" "RIE")
(set_attr "z10prop" "z10_super_E1")])
(ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "")
(match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
"TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>"
- [(set (match_dup 0)
+ [(set (match_dup 6)
(lshiftrt:GPR (match_dup 1) (match_dup 2)))
(set (match_dup 0)
- (ior:GPR (and:GPR (match_dup 0) (match_dup 5))
+ (ior:GPR (and:GPR (match_dup 6) (match_dup 5))
(ashift:GPR (match_dup 3) (match_dup 4))))]
{
- operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
+ operands[5] = GEN_INT ((HOST_WIDE_INT_1U << UINTVAL (operands[4])) - 1);
+ if (reg_overlap_mentioned_p (operands[0], operands[3]))
+ {
+ if (!can_create_pseudo_p ())
+ FAIL;
+ operands[6] = gen_reg_rtx (<MODE>mode);
+ }
+ else
+ operands[6] = operands[0];
})
(define_split
(match_operand:GPR 4 "nonzero_shift_count_operand" ""))))
(clobber (reg:CC CC_REGNUM))])]
"TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>"
- [(set (match_dup 0)
+ [(set (match_dup 6)
(lshiftrt:GPR (match_dup 1) (match_dup 2)))
(parallel
[(set (match_dup 0)
- (ior:GPR (and:GPR (match_dup 0) (match_dup 5))
+ (ior:GPR (and:GPR (match_dup 6) (match_dup 5))
(ashift:GPR (match_dup 3) (match_dup 4))))
(clobber (reg:CC CC_REGNUM))])]
{
- operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1);
+ operands[5] = GEN_INT ((HOST_WIDE_INT_1U << UINTVAL (operands[4])) - 1);
+ if (reg_overlap_mentioned_p (operands[0], operands[3]))
+ {
+ if (!can_create_pseudo_p ())
+ FAIL;
+ operands[6] = gen_reg_rtx (<MODE>mode);
+ }
+ else
+ operands[6] = operands[0];
})
+; rosbg, rxsbg
(define_insn "*r<noxa>sbg_<mode>_noshift"
[(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
(IXOR:GPR
"r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0"
[(set_attr "op_type" "RIE")])
+; rosbg, rxsbg
(define_insn "*r<noxa>sbg_di_rotl"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d")
(IXOR:DI
(match_operand:DI 4 "nonimmediate_operand" "0")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_Z10"
- "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3"
+ "r<noxa>sbg\t%0,%1,%s2,%e2,%b3"
[(set_attr "op_type" "RIE")])
-(define_insn "*r<noxa>sbg_<mode>_srl"
+; rosbg, rxsbg
+(define_insn "*r<noxa>sbg_<mode>_srl_bitmask"
[(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
(IXOR:GPR
(and:GPR
(lshiftrt:GPR
(match_operand:GPR 1 "nonimmediate_operand" "d")
(match_operand:GPR 3 "nonzero_shift_count_operand" ""))
- (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
+ (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" ""))
(match_operand:GPR 4 "nonimmediate_operand" "0")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_Z10
&& s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]),
INTVAL (operands[2]))"
- "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3"
+ {
+ operands[3] = GEN_INT (64 - INTVAL (operands[3]));
+ return "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3";
+ }
[(set_attr "op_type" "RIE")])
-(define_insn "*r<noxa>sbg_<mode>_sll"
+; rosbg, rxsbg
+(define_insn "*r<noxa>sbg_<mode>_sll_bitmask"
[(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
(IXOR:GPR
(and:GPR
(ashift:GPR
(match_operand:GPR 1 "nonimmediate_operand" "d")
(match_operand:GPR 3 "nonzero_shift_count_operand" ""))
- (match_operand:GPR 2 "contiguous_bitmask_operand" ""))
+ (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" ""))
(match_operand:GPR 4 "nonimmediate_operand" "0")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_Z10
"r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"
[(set_attr "op_type" "RIE")])
+;; unsigned {int,long} a, b
+;; a = a | (b << const_int)
+;; a = a ^ (b << const_int)
+; rosbg, rxsbg
+(define_insn "*r<noxa>sbg_<mode>_sll"
+ [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
+ (IXOR:GPR
+ (ashift:GPR
+ (match_operand:GPR 1 "nonimmediate_operand" "d")
+ (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
+ (match_operand:GPR 3 "nonimmediate_operand" "0")))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z10"
+ {
+ operands[3] = GEN_INT (63 - INTVAL (operands[2]));
+ return "r<noxa>sbg\t%0,%1,<bitoff>,%3,%2";
+ }
+ [(set_attr "op_type" "RIE")])
+
+;; unsigned {int,long} a, b
+;; a = a | (b >> const_int)
+;; a = a ^ (b >> const_int)
+; rosbg, rxsbg
+(define_insn "*r<noxa>sbg_<mode>_srl"
+ [(set (match_operand:GPR 0 "nonimmediate_operand" "=d")
+ (IXOR:GPR
+ (lshiftrt:GPR
+ (match_operand:GPR 1 "nonimmediate_operand" "d")
+ (match_operand:GPR 2 "nonzero_shift_count_operand" ""))
+ (match_operand:GPR 3 "nonimmediate_operand" "0")))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z10"
+ {
+ operands[3] = GEN_INT (64 - INTVAL (operands[2]));
+ operands[2] = GEN_INT (<bitoff_plus> INTVAL (operands[2]));
+ return "r<noxa>sbg\t%0,%1,%2,63,%3";
+ }
+ [(set_attr "op_type" "RIE")])
+
+; rosbg, rxsbg
+(define_insn "*r<noxa>sbg_sidi_srl"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
+ (IXOR:SI
+ (subreg:SI
+ (zero_extract:DI
+ (match_operand:DI 1 "nonimmediate_operand" "d")
+ (const_int 32)
+ (match_operand:DI 2 "immediate_operand" ""))
+ 4)
+ (match_operand:SI 3 "nonimmediate_operand" "0")))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z10"
+ {
+ operands[2] = GEN_INT (32 + INTVAL (operands[2]));
+ return "r<noxa>sbg\t%0,%1,32,63,%2";
+ }
+ [(set_attr "op_type" "RIE")])
+
;; These two are generated by combine for s.bf &= val.
;; ??? For bitfields smaller than 32-bits, we wind up with SImode
;; shifts and ands, which results in some truly awful patterns
(match_operand:DI 3 "nonimmediate_operand" "d")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_Z10
+ && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64)
&& INTVAL (operands[1]) + INTVAL (operands[2]) == 64"
"rnsbg\t%0,%3,%2,63,0"
[(set_attr "op_type" "RIE")])
(match_operand:DI 4 "nonimmediate_operand" "d")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_Z10
+ && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64)
&& INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])"
"rnsbg\t%0,%4,%2,%2+%1-1,%3"
[(set_attr "op_type" "RIE")])
(match_operand 1 "const_int_operand" "n,n")
(const_int 0))
(match_operand:W 2 "register_operand" "d,d"))]
- "INTVAL (operands[1]) > 0
+ "EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64)
+ && INTVAL (operands[1]) > 0
&& INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
&& INTVAL (operands[1]) % BITS_PER_UNIT == 0"
{
int size = INTVAL (operands[1]) / BITS_PER_UNIT;
- operands[1] = GEN_INT ((1ul << size) - 1);
+ operands[1] = GEN_INT ((HOST_WIDE_INT_1U << size) - 1);
return (which_alternative == 0) ? "stcm\t%2,%1,%S0"
: "stcmy\t%2,%1,%S0";
}
[(set_attr "op_type" "RS,RSY")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_super,z10_super")])
(define_insn "*insvdi_mem_reghigh"
- [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS")
+ [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+S")
(match_operand 1 "const_int_operand" "n")
(const_int 0))
(lshiftrt:DI (match_operand:DI 2 "register_operand" "d")
(const_int 32)))]
"TARGET_ZARCH
+ && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64)
&& INTVAL (operands[1]) > 0
&& INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode)
&& INTVAL (operands[1]) % BITS_PER_UNIT == 0"
{
int size = INTVAL (operands[1]) / BITS_PER_UNIT;
- operands[1] = GEN_INT ((1ul << size) - 1);
+ operands[1] = GEN_INT ((HOST_WIDE_INT_1U << size) - 1);
return "stcmh\t%2,%1,%S0";
}
[(set_attr "op_type" "RSY")
(match_operand 1 "const_int_operand" "n"))
(match_operand:DI 2 "const_int_operand" "n"))]
"TARGET_ZARCH
+ && EXTRACT_ARGS_IN_RANGE (16, INTVAL (operands[1]), 64)
&& INTVAL (operands[1]) >= 0
&& INTVAL (operands[1]) < BITS_PER_WORD
&& INTVAL (operands[1]) % 16 == 0"
(define_insn "*extendsidi2"
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
- (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
+ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))]
"TARGET_ZARCH"
"@
lgfr\t%0,%1
[(set_attr "op_type" "RRE,RXY,RIL")
(set_attr "type" "*,*,larl")
(set_attr "cpu_facility" "*,*,z10")
- (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")
+ (set_attr "relative_long" "*,*,yes")])
;
; extend(hi|qi)(si|di)2 instruction pattern(s).
(define_insn "*extendhidi2_extimm"
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
- (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))]
+ (sign_extend:DI (match_operand:HI 1 "general_operand" "d,T,b")))]
"TARGET_ZARCH && TARGET_EXTIMM"
"@
lghr\t%0,%1
[(set_attr "op_type" "RRE,RXY,RIL")
(set_attr "type" "*,*,larl")
(set_attr "cpu_facility" "extimm,extimm,z10")
- (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")])
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")
+ (set_attr "relative_long" "*,*,yes")])
(define_insn "*extendhidi2"
[(set (match_operand:DI 0 "register_operand" "=d")
- (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))]
+ (sign_extend:DI (match_operand:HI 1 "memory_operand" "T")))]
"TARGET_ZARCH"
"lgh\t%0,%1"
[(set_attr "op_type" "RXY")
[(set_attr "op_type" "RRE,RX,RXY,RIL")
(set_attr "type" "*,*,*,larl")
(set_attr "cpu_facility" "extimm,extimm,extimm,z10")
- (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")])
+ (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")
+ (set_attr "relative_long" "*,*,*,yes")])
(define_insn "*extendhisi2"
[(set (match_operand:SI 0 "register_operand" "=d,d")
lh\t%0,%1
lhy\t%0,%1"
[(set_attr "op_type" "RX,RXY")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1")])
;
; lbr, lgbr, lb, lgb
(define_insn "*extendqi<mode>2_extimm"
[(set (match_operand:GPR 0 "register_operand" "=d,d")
- (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))]
+ (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,T")))]
"TARGET_EXTIMM"
"@
l<g>br\t%0,%1
; lb, lgb
(define_insn "*extendqi<mode>2"
[(set (match_operand:GPR 0 "register_operand" "=d")
- (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))]
+ (sign_extend:GPR (match_operand:QI 1 "memory_operand" "T")))]
"!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT"
"l<g>b\t%0,%1"
[(set_attr "op_type" "RXY")
(define_insn "*zero_extendsidi2"
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
- (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))]
+ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))]
"TARGET_ZARCH"
"@
llgfr\t%0,%1
[(set_attr "op_type" "RRE,RXY,RIL")
(set_attr "type" "*,*,larl")
(set_attr "cpu_facility" "*,*,z10")
- (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")])
+ (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")
+ (set_attr "relative_long" "*,*,yes")])
;
; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
(define_insn "*llgt_sidi"
[(set (match_operand:DI 0 "register_operand" "=d")
- (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
+ (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0)
(const_int 2147483647)))]
"TARGET_ZARCH"
"llgt\t%0,%1"
(define_insn_and_split "*llgt_sidi_split"
[(set (match_operand:DI 0 "register_operand" "=d")
- (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0)
+ (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0)
(const_int 2147483647)))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH"
(define_insn "*llgt_sisi"
[(set (match_operand:SI 0 "register_operand" "=d,d")
- (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT")
+ (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,T")
(const_int 2147483647)))]
"TARGET_ZARCH"
"@
; llhrl, llghrl
(define_insn "*zero_extendhi<mode>2_z10"
[(set (match_operand:GPR 0 "register_operand" "=d,d,d")
- (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))]
+ (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,T,b")))]
"TARGET_Z10"
"@
ll<g>hr\t%0,%1
[(set_attr "op_type" "RXY,RRE,RIL")
(set_attr "type" "*,*,larl")
(set_attr "cpu_facility" "*,*,z10")
- (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
+ (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")
+ (set_attr "relative_long" "*,*,yes")])
; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
(define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
[(set (match_operand:GPR 0 "register_operand" "=d,d")
- (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))]
+ (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,T")))]
"TARGET_EXTIMM"
"@
ll<g><hc>r\t%0,%1
; llgh, llgc
(define_insn "*zero_extend<HQI:mode><GPR:mode>2"
[(set (match_operand:GPR 0 "register_operand" "=d")
- (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))]
+ (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "T")))]
"TARGET_ZARCH && !TARGET_EXTIMM"
"llg<hc>\t%0,%1"
[(set_attr "op_type" "RXY")
(define_insn_and_split "*zero_extendhisi2_31"
[(set (match_operand:SI 0 "register_operand" "=&d")
- (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
+ (zero_extend:SI (match_operand:HI 1 "s_operand" "S")))
(clobber (reg:CC CC_REGNUM))]
"!TARGET_ZARCH"
"#"
(define_insn_and_split "*zero_extendqisi2_31"
[(set (match_operand:SI 0 "register_operand" "=&d")
- (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))]
+ (zero_extend:SI (match_operand:QI 1 "memory_operand" "T")))]
"!TARGET_ZARCH"
"#"
"&& reload_completed"
(define_insn "*zero_extendqihi2_64"
[(set (match_operand:HI 0 "register_operand" "=d")
- (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
+ (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))]
"TARGET_ZARCH && !TARGET_EXTIMM"
"llgc\t%0,%1"
[(set_attr "op_type" "RXY")
(define_insn_and_split "*zero_extendqihi2_31"
[(set (match_operand:HI 0 "register_operand" "=&d")
- (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))]
+ (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))]
"!TARGET_ZARCH"
"#"
"&& reload_completed"
"operands[2] = gen_lowpart (QImode, operands[0]);")
;
-; fixuns_trunc(dd|td)di2 instruction pattern(s).
+; fixuns_trunc(dd|td|sf|df|tf)(si|di)2 expander
;
-(define_expand "fixuns_truncdddi2"
+; This is the only entry point for fixuns_trunc. It multiplexes the
+; expansion to either the *_emu expanders below for pre z196 machines
+; or emits the default pattern otherwise.
+(define_expand "fixuns_trunc<FP:mode><GPR:mode>2"
[(parallel
- [(set (match_operand:DI 0 "register_operand" "")
- (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
- (unspec:DI [(const_int 5)] UNSPEC_ROUND)
+ [(set (match_operand:GPR 0 "register_operand" "")
+ (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "")))
+ (unspec:GPR [(match_dup 2)] UNSPEC_ROUND)
(clobber (reg:CC CC_REGNUM))])]
-
- "TARGET_HARD_DFP"
+ "TARGET_HARD_FLOAT"
{
if (!TARGET_Z196)
{
- rtx_code_label *label1 = gen_label_rtx ();
- rtx_code_label *label2 = gen_label_rtx ();
- rtx temp = gen_reg_rtx (TDmode);
- REAL_VALUE_TYPE cmp, sub;
-
- decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
- decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
-
- /* 2^63 can't be represented as 64bit DFP number with full precision. The
- solution is doing the check and the subtraction in TD mode and using a
- TD -> DI convert afterwards. */
- emit_insn (gen_extendddtd2 (temp, operands[1]));
- temp = force_reg (TDmode, temp);
- emit_cmp_and_jump_insns (temp,
- const_double_from_real_value (cmp, TDmode),
- LT, NULL_RTX, VOIDmode, 0, label1);
- emit_insn (gen_subtd3 (temp, temp,
- const_double_from_real_value (sub, TDmode)));
- emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
- emit_jump (label2);
-
- emit_label (label1);
- emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9)));
- emit_label (label2);
+ /* We don't provide emulation for TD|DD->SI. */
+ if (GET_MODE_CLASS (<FP:MODE>mode) == MODE_DECIMAL_FLOAT
+ && <GPR:MODE>mode == SImode)
+ FAIL;
+ emit_insn (gen_fixuns_trunc<FP:mode><GPR:mode>2_emu (operands[0],
+ operands[1]));
DONE;
}
-})
-
-(define_expand "fixuns_trunctddi2"
- [(parallel
- [(set (match_operand:DI 0 "register_operand" "")
- (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
- (unspec:DI [(const_int 5)] UNSPEC_ROUND)
- (clobber (reg:CC CC_REGNUM))])]
- "TARGET_HARD_DFP"
-{
- if (!TARGET_Z196)
- {
- rtx_code_label *label1 = gen_label_rtx ();
- rtx_code_label *label2 = gen_label_rtx ();
- rtx temp = gen_reg_rtx (TDmode);
- REAL_VALUE_TYPE cmp, sub;
-
- operands[1] = force_reg (TDmode, operands[1]);
- decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
- decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
-
- emit_cmp_and_jump_insns (operands[1],
- const_double_from_real_value (cmp, TDmode),
- LT, NULL_RTX, VOIDmode, 0, label1);
- emit_insn (gen_subtd3 (temp, operands[1],
- const_double_from_real_value (sub, TDmode)));
- emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11)));
- emit_jump (label2);
-
- emit_label (label1);
- emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9)));
- emit_label (label2);
- DONE;
- }
+ if (GET_MODE_CLASS (<FP:MODE>mode) == MODE_DECIMAL_FLOAT)
+ operands[2] = GEN_INT (DFP_RND_TOWARD_0);
+ else
+ operands[2] = GEN_INT (BFP_RND_TOWARD_0);
})
-;
-; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2
-; instruction pattern(s).
-;
+; (sf|df|tf)->unsigned (si|di)
-(define_expand "fixuns_trunc<BFP:mode><GPR:mode>2"
+; Emulate the unsigned conversion with the signed version for pre z196
+; machines.
+(define_expand "fixuns_trunc<BFP:mode><GPR:mode>2_emu"
[(parallel
[(set (match_operand:GPR 0 "register_operand" "")
(unsigned_fix:GPR (match_operand:BFP 1 "register_operand" "")))
- (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
+ (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND)
(clobber (reg:CC CC_REGNUM))])]
- "TARGET_HARD_FLOAT"
-{
- if (!TARGET_Z196)
- {
- rtx_code_label *label1 = gen_label_rtx ();
- rtx_code_label *label2 = gen_label_rtx ();
- rtx temp = gen_reg_rtx (<BFP:MODE>mode);
- REAL_VALUE_TYPE cmp, sub;
-
- operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
- real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode);
- real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
-
- emit_cmp_and_jump_insns (operands[1],
- const_double_from_real_value (cmp, <BFP:MODE>mode),
- LT, NULL_RTX, VOIDmode, 0, label1);
- emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
- const_double_from_real_value (sub, <BFP:MODE>mode)));
- emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
- GEN_INT (7)));
- emit_jump (label2);
-
- emit_label (label1);
- emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
- operands[1], GEN_INT (5)));
- emit_label (label2);
- DONE;
- }
+ "!TARGET_Z196 && TARGET_HARD_FLOAT"
+{
+ rtx_code_label *label1 = gen_label_rtx ();
+ rtx_code_label *label2 = gen_label_rtx ();
+ rtx temp = gen_reg_rtx (<BFP:MODE>mode);
+ REAL_VALUE_TYPE cmp, sub;
+
+ operands[1] = force_reg (<BFP:MODE>mode, operands[1]);
+ real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode);
+ real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode);
+
+ emit_cmp_and_jump_insns (operands[1],
+ const_double_from_real_value (cmp, <BFP:MODE>mode),
+ LT, NULL_RTX, VOIDmode, 0, label1);
+ emit_insn (gen_sub<BFP:mode>3 (temp, operands[1],
+ const_double_from_real_value (sub, <BFP:MODE>mode)));
+ emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp,
+ GEN_INT (BFP_RND_TOWARD_MINF)));
+ emit_jump (label2);
+
+ emit_label (label1);
+ emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0],
+ operands[1],
+ GEN_INT (BFP_RND_TOWARD_0)));
+ emit_label (label2);
+ DONE;
})
-; fixuns_trunc(td|dd)si2 expander
-(define_expand "fixuns_trunc<mode>si2"
+; dd->unsigned di
+
+; Emulate the unsigned conversion with the signed version for pre z196
+; machines.
+(define_expand "fixuns_truncdddi2_emu"
[(parallel
- [(set (match_operand:SI 0 "register_operand" "")
- (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
- (unspec:SI [(const_int 5)] UNSPEC_ROUND)
+ [(set (match_operand:DI 0 "register_operand" "")
+ (unsigned_fix:DI (match_operand:DD 1 "register_operand" "")))
+ (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND)
(clobber (reg:CC CC_REGNUM))])]
- "TARGET_Z196 && TARGET_HARD_DFP"
- "")
-
-; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
-(define_insn "*fixuns_truncdfdi2_z13"
+ "!TARGET_Z196 && TARGET_HARD_DFP"
+{
+ rtx_code_label *label1 = gen_label_rtx ();
+ rtx_code_label *label2 = gen_label_rtx ();
+ rtx temp = gen_reg_rtx (TDmode);
+ REAL_VALUE_TYPE cmp, sub;
+
+ decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
+ decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
+
+ /* 2^63 can't be represented as 64bit DFP number with full precision. The
+ solution is doing the check and the subtraction in TD mode and using a
+ TD -> DI convert afterwards. */
+ emit_insn (gen_extendddtd2 (temp, operands[1]));
+ temp = force_reg (TDmode, temp);
+ emit_cmp_and_jump_insns (temp,
+ const_double_from_real_value (cmp, TDmode),
+ LT, NULL_RTX, VOIDmode, 0, label1);
+ emit_insn (gen_subtd3 (temp, temp,
+ const_double_from_real_value (sub, TDmode)));
+ emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp,
+ GEN_INT (DFP_RND_TOWARD_MINF)));
+ emit_jump (label2);
+
+ emit_label (label1);
+ emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1],
+ GEN_INT (DFP_RND_TOWARD_0)));
+ emit_label (label2);
+ DONE;
+})
+
+; td->unsigned di
+
+; Emulate the unsigned conversion with the signed version for pre z196
+; machines.
+(define_expand "fixuns_trunctddi2_emu"
+ [(parallel
+ [(set (match_operand:DI 0 "register_operand" "")
+ (unsigned_fix:DI (match_operand:TD 1 "register_operand" "")))
+ (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND)
+ (clobber (reg:CC CC_REGNUM))])]
+
+ "!TARGET_Z196 && TARGET_HARD_DFP"
+{
+ rtx_code_label *label1 = gen_label_rtx ();
+ rtx_code_label *label2 = gen_label_rtx ();
+ rtx temp = gen_reg_rtx (TDmode);
+ REAL_VALUE_TYPE cmp, sub;
+
+ operands[1] = force_reg (TDmode, operands[1]);
+ decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */
+ decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */
+
+ emit_cmp_and_jump_insns (operands[1],
+ const_double_from_real_value (cmp, TDmode),
+ LT, NULL_RTX, VOIDmode, 0, label1);
+ emit_insn (gen_subtd3 (temp, operands[1],
+ const_double_from_real_value (sub, TDmode)));
+ emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp,
+ GEN_INT (DFP_RND_TOWARD_MINF)));
+ emit_jump (label2);
+
+ emit_label (label1);
+ emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1],
+ GEN_INT (DFP_RND_TOWARD_0)));
+ emit_label (label2);
+ DONE;
+})
+
+; Just a dummy to make the code in the first expander a bit easier.
+(define_expand "fixuns_trunc<mode>si2_emu"
+ [(parallel
+ [(set (match_operand:SI 0 "register_operand" "")
+ (unsigned_fix:SI (match_operand:DFP 1 "register_operand" "")))
+ (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND)
+ (clobber (reg:CC CC_REGNUM))])]
+
+ "!TARGET_Z196 && TARGET_HARD_DFP"
+ {
+ FAIL;
+ })
+
+
+; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns.
+
+; df -> unsigned di
+(define_insn "*fixuns_truncdfdi2_vx"
[(set (match_operand:DI 0 "register_operand" "=d,v")
(unsigned_fix:DI (match_operand:DF 1 "register_operand" "f,v")))
(unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND)
(clobber (reg:CC CC_REGNUM))]
- "TARGET_Z13 && TARGET_HARD_FLOAT"
- "@
- clgdbr\t%0,%h2,%1,0
- wclgdb\t%v0,%v1,0,%h2"
- [(set_attr "op_type" "RRF,VRR")
- (set_attr "type" "ftoi")])
+ "TARGET_VX && TARGET_HARD_FLOAT"
+ "@
+ clgdbr\t%0,%h2,%1,0
+ wclgdb\t%v0,%v1,0,%h2"
+ [(set_attr "op_type" "RRF,VRR")
+ (set_attr "type" "ftoi")])
+; (dd|td|sf|df|tf)->unsigned (di|si)
; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr
; clfdtr, clfxtr, clgdtr, clgxtr
(define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196"
(unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND)
(clobber (reg:CC CC_REGNUM))]
"TARGET_Z196 && TARGET_HARD_FLOAT
- && (!TARGET_Z13 || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)"
+ && (!TARGET_VX || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)"
"cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0"
[(set_attr "op_type" "RRF")
(set_attr "type" "ftoi")])
"TARGET_HARD_FLOAT"
{
emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1],
- GEN_INT (5)));
+ GEN_INT (BFP_RND_TOWARD_0)));
DONE;
})
(fix:DI (match_operand:DF 1 "register_operand" "f,v")))
(unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND)
(clobber (reg:CC CC_REGNUM))]
- "TARGET_Z13 && TARGET_HARD_FLOAT"
+ "TARGET_VX && TARGET_HARD_FLOAT"
"@
cgdbr\t%0,%h2,%1
wcgdb\t%v0,%v1,0,%h2"
{
operands[1] = force_reg (<MODE>mode, operands[1]);
emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1],
- GEN_INT (9)));
+ GEN_INT (DFP_RND_TOWARD_0)));
DONE;
})
(define_expand "fix_trunctf<mode>2"
[(parallel [(set (match_operand:GPR 0 "register_operand" "")
(fix:GPR (match_operand:TF 1 "register_operand" "")))
- (unspec:GPR [(const_int 5)] UNSPEC_ROUND)
+ (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND)
(clobber (reg:CC CC_REGNUM))])]
"TARGET_HARD_FLOAT"
"")
; cxgbr, cdgbr, cegbr, cxgtr, cdgtr
(define_insn "floatdi<mode>2"
- [(set (match_operand:FP 0 "register_operand" "=f,<vf>")
- (float:FP (match_operand:DI 1 "register_operand" "d,<vd>")))]
+ [(set (match_operand:FP 0 "register_operand" "=f,v")
+ (float:FP (match_operand:DI 1 "register_operand" "d,v")))]
"TARGET_ZARCH && TARGET_HARD_FLOAT"
"@
c<xde>g<bt>r\t%0,%1
wcdgb\t%v0,%v1,0,0"
[(set_attr "op_type" "RRE,VRR")
(set_attr "type" "itof<mode>" )
- (set_attr "cpu_facility" "*,vec")])
+ (set_attr "cpu_facility" "*,vx")
+ (set_attr "enabled" "*,<DFDI>")])
; cxfbr, cdfbr, cefbr
(define_insn "floatsi<mode>2"
(define_insn "*floatunsdidf2_z13"
[(set (match_operand:DF 0 "register_operand" "=f,v")
(unsigned_float:DF (match_operand:DI 1 "register_operand" "d,v")))]
- "TARGET_Z13 && TARGET_HARD_FLOAT"
+ "TARGET_VX && TARGET_HARD_FLOAT"
"@
cdlgbr\t%0,0,%1,0
wcdlgb\t%v0,%v1,0,0"
; According to BFP rounding mode
[(set_attr "op_type" "RRE,VRR")
(set_attr "type" "ftruncdf")
- (set_attr "cpu_facility" "*,vec")])
+ (set_attr "cpu_facility" "*,vx")])
;
; trunctf(df|sf)2 instruction pattern(s).
; trunctddd2 and truncddsd2 instruction pattern(s).
;
-(define_insn "trunctddd2"
+
+(define_expand "trunctddd2"
+ [(parallel
+ [(set (match_operand:DD 0 "register_operand" "")
+ (float_truncate:DD (match_operand:TD 1 "register_operand" "")))
+ (unspec:DI [(const_int DFP_RND_CURRENT)] UNSPEC_ROUND)
+ (clobber (scratch:TD))])]
+ "TARGET_HARD_DFP")
+
+(define_insn "*trunctddd2"
[(set (match_operand:DD 0 "register_operand" "=f")
(float_truncate:DD (match_operand:TD 1 "register_operand" "f")))
- (clobber (match_scratch:TD 2 "=f"))]
+ (unspec:DI [(match_operand:DI 2 "const_mask_operand" "I")] UNSPEC_ROUND)
+ (clobber (match_scratch:TD 3 "=f"))]
"TARGET_HARD_DFP"
- "ldxtr\t%2,0,%1,0\;ldr\t%0,%2"
+ "ldxtr\t%3,%2,%1,0\;ldr\t%0,%3"
[(set_attr "length" "6")
(set_attr "type" "ftruncdd")])
(define_expand "trunctdsd2"
[(parallel
- [(set (match_dup 3)
+ [(set (match_dup 2)
(float_truncate:DD (match_operand:TD 1 "register_operand" "")))
- (clobber (match_scratch:TD 2 ""))])
+ (unspec:DI [(const_int DFP_RND_PREP_FOR_SHORT_PREC)] UNSPEC_ROUND)
+ (clobber (match_scratch:TD 3 ""))])
(set (match_operand:SD 0 "register_operand" "")
- (float_truncate:SD (match_dup 3)))]
+ (float_truncate:SD (match_dup 2)))]
"TARGET_HARD_DFP"
{
- operands[3] = gen_reg_rtx (DDmode);
+ operands[2] = gen_reg_rtx (DDmode);
})
;
; extend(sf|df)(df|tf)2 instruction pattern(s).
;
+; wflls
(define_insn "*extendsfdf2_z13"
[(set (match_operand:DF 0 "register_operand" "=f,f,v")
(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R,v")))]
- "TARGET_Z13 && TARGET_HARD_FLOAT"
+ "TARGET_VX && TARGET_HARD_FLOAT"
"@
ldebr\t%0,%1
ldeb\t%0,%1
[(set (reg:DFP_ALL FPR0_REGNUM)
(float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
(use (reg:SI GPR0_REGNUM))
- (clobber (reg:CC CC_REGNUM))]
+ (clobber (reg:CC CC_REGNUM))
+ (clobber (reg:SI GPR1_REGNUM))]
"TARGET_HARD_DFP"
"pfpo")
[(set (reg:BFP FPR0_REGNUM)
(float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
(use (reg:SI GPR0_REGNUM))
- (clobber (reg:CC CC_REGNUM))]
+ (clobber (reg:CC CC_REGNUM))
+ (clobber (reg:SI GPR1_REGNUM))]
"TARGET_HARD_DFP"
"pfpo")
[(set (reg:DFP_ALL FPR0_REGNUM)
(float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM)))
(use (reg:SI GPR0_REGNUM))
- (clobber (reg:CC CC_REGNUM))])
+ (clobber (reg:CC CC_REGNUM))
+ (clobber (reg:SI GPR1_REGNUM))])
(set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
(reg:DFP_ALL FPR0_REGNUM))]
"TARGET_HARD_DFP
{
HOST_WIDE_INT flags;
+ /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the
+ rounding mode of the target format needs to be used. */
+
flags = (PFPO_CONVERT |
PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
- PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
+ PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT |
+ PFPO_RND_MODE_DFP);
operands[2] = GEN_INT (flags);
})
(parallel
[(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM)))
(use (reg:SI GPR0_REGNUM))
- (clobber (reg:CC CC_REGNUM))])
+ (clobber (reg:CC CC_REGNUM))
+ (clobber (reg:SI GPR1_REGNUM))])
(set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
"TARGET_HARD_DFP
&& GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)"
{
HOST_WIDE_INT flags;
+ /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the
+ rounding mode of the target format needs to be used. */
+
flags = (PFPO_CONVERT |
PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
- PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
+ PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT |
+ PFPO_RND_MODE_BFP);
operands[2] = GEN_INT (flags);
})
(define_insn "*extend<BFP:mode><DFP_ALL:mode>2"
[(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
(use (reg:SI GPR0_REGNUM))
- (clobber (reg:CC CC_REGNUM))]
+ (clobber (reg:CC CC_REGNUM))
+ (clobber (reg:SI GPR1_REGNUM))]
"TARGET_HARD_DFP"
"pfpo")
(define_insn "*extend<DFP_ALL:mode><BFP:mode>2"
[(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
(use (reg:SI GPR0_REGNUM))
- (clobber (reg:CC CC_REGNUM))]
+ (clobber (reg:CC CC_REGNUM))
+ (clobber (reg:SI GPR1_REGNUM))]
"TARGET_HARD_DFP"
"pfpo")
[(set (reg:DFP_ALL FPR0_REGNUM)
(float_extend:DFP_ALL (reg:BFP FPR4_REGNUM)))
(use (reg:SI GPR0_REGNUM))
- (clobber (reg:CC CC_REGNUM))])
+ (clobber (reg:CC CC_REGNUM))
+ (clobber (reg:SI GPR1_REGNUM))])
(set (match_operand:DFP_ALL 0 "nonimmediate_operand" "")
(reg:DFP_ALL FPR0_REGNUM))]
"TARGET_HARD_DFP
{
HOST_WIDE_INT flags;
+ /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the
+ rounding mode of the target format needs to be used. */
+
flags = (PFPO_CONVERT |
PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT |
- PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT);
+ PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT |
+ PFPO_RND_MODE_DFP);
operands[2] = GEN_INT (flags);
})
(parallel
[(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM)))
(use (reg:SI GPR0_REGNUM))
- (clobber (reg:CC CC_REGNUM))])
+ (clobber (reg:CC CC_REGNUM))
+ (clobber (reg:SI GPR1_REGNUM))])
(set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))]
"TARGET_HARD_DFP
&& GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)"
{
HOST_WIDE_INT flags;
+ /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the
+ rounding mode of the target format needs to be used. */
+
flags = (PFPO_CONVERT |
PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT |
- PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT);
+ PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT |
+ PFPO_RND_MODE_BFP);
operands[2] = GEN_INT (flags);
})
(define_insn "*adddi3_sign"
[(set (match_operand:DI 0 "register_operand" "=d,d")
- (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
+ (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
(match_operand:DI 1 "register_operand" "0,0")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH"
(define_insn "*adddi3_zero_cc"
[(set (reg CC_REGNUM)
- (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
+ (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
(match_operand:DI 1 "register_operand" "0,0"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d")
(define_insn "*adddi3_zero_cconly"
[(set (reg CC_REGNUM)
- (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
+ (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
(match_operand:DI 1 "register_operand" "0,0"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))]
(define_insn "*adddi3_zero"
[(set (match_operand:DI 0 "register_operand" "=d,d")
- (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
+ (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
(match_operand:DI 1 "register_operand" "0,0")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH"
(plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
(match_operand:DI 2 "general_operand" "do") ) )
(clobber (reg:CC CC_REGNUM))]
- "!TARGET_ZARCH && TARGET_CPU_ZARCH"
+ "!TARGET_ZARCH"
"#"
"&& reload_completed"
[(parallel
operands[7] = operand_subword (operands[1], 1, 0, DImode);
operands[8] = operand_subword (operands[2], 1, 0, DImode);")
-(define_insn_and_split "*adddi3_31"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
- (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
- (match_operand:DI 2 "general_operand" "do") ) )
- (clobber (reg:CC CC_REGNUM))]
- "!TARGET_CPU_ZARCH"
- "#"
- "&& reload_completed"
- [(parallel
- [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
- (clobber (reg:CC CC_REGNUM))])
- (parallel
- [(set (reg:CCL1 CC_REGNUM)
- (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
- (match_dup 7)))
- (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
- (set (pc)
- (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0))
- (pc)
- (label_ref (match_dup 9))))
- (parallel
- [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
- (clobber (reg:CC CC_REGNUM))])
- (match_dup 9)]
- "operands[3] = operand_subword (operands[0], 0, 0, DImode);
- operands[4] = operand_subword (operands[1], 0, 0, DImode);
- operands[5] = operand_subword (operands[2], 0, 0, DImode);
- operands[6] = operand_subword (operands[0], 1, 0, DImode);
- operands[7] = operand_subword (operands[1], 1, 0, DImode);
- operands[8] = operand_subword (operands[2], 1, 0, DImode);
- operands[9] = gen_label_rtx ();")
-
;
; addsi3 instruction pattern(s).
;
ah\t%0,%2
ahy\t%0,%2"
[(set_attr "op_type" "RX,RXY")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "z196prop" "z196_cracked,z196_cracked")])
;
; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi
(define_insn "*add<mode>3"
- [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS")
- (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0")
- (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) )
+ [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,S")
+ (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0,0")
+ (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T,C") ) )
(clobber (reg:CC CC_REGNUM))]
""
"@
a<y>\t%0,%2
a<g>si\t%0,%c2"
[(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY")
- (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10")
+ (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,longdisp,z10")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1,
z10_super_E1,z10_super_E1,z10_super_E1")])
al<y>\t%0,%2
al<g>si\t%0,%c2"
[(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
- (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
+ (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
z10_super_E1,z10_super_E1,z10_super_E1")])
al<g>\t%0,%2
al<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
- (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
(define_insn "*add<mode>3_carry2_cc"
[(set (reg CC_REGNUM)
- (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
- (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
+ (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
+ (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
(match_dup 2)))
- (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
+ (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S")
(plus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCL1mode)"
"@
al<y>\t%0,%2
al<g>si\t%0,%c2"
[(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
- (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
+ (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*,
z10_super_E1,z10_super_E1,z10_super_E1")])
al<g>\t%0,%2
al<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
- (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik
(define_insn "*add<mode>3_cc"
[(set (reg CC_REGNUM)
- (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0")
- (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C"))
+ (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0")
+ (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C"))
(const_int 0)))
- (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS")
+ (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S")
(plus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCLmode)"
"@
al<y>\t%0,%2
al<g>si\t%0,%c2"
[(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY")
- (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10")
+ (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,
*,z10_super_E1,z10_super_E1,z10_super_E1")])
al<g>\t%0,%2
al<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
- (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
; alr, al, aly, algr, alg, alrk, algrk
al<g>\t%0,%2
al<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
- (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
; ahi, afi, aghi, agfi, asi, agsi
(define_insn "*add<mode>3_imm_cc"
[(set (reg CC_REGNUM)
(compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0")
- (match_operand:GPR 2 "const_int_operand" " K, K,Os, C"))
+ (match_operand:GPR 2 "const_int_operand" " K, K,Os,C"))
(const_int 0)))
- (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS")
+ (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d, S")
(plus:GPR (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCAmode)
&& (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")
(set_attr "cpu_facility" "*,z196,extimm,z10")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")])
+(define_insn "*adddi3_sign"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (plus:DI (sign_extend:DI (match_operand:HI 2 "memory_operand" "T"))
+ (match_operand:DI 1 "register_operand" "0")))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z14"
+ "agh\t%0,%2"
+ [(set_attr "op_type" "RXY")])
+
;
; add(tf|df|sf|td|dd)3 instruction pattern(s).
;
; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
; FIXME: wfadb does not clobber cc
(define_insn "add<mode>3"
- [(set (match_operand:FP 0 "register_operand" "=f, f,<vf>")
- (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>, 0,<v0>")
- (match_operand:FP 2 "general_operand" "f,<Rf>,<vf>")))
+ [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v")
+ (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v,v")
+ (match_operand:FP 2 "general_operand" "f,f,R,v,v")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT"
"@
- a<xde><bt>r\t%0,<op1>%2
+ a<xde>tr\t%0,%1,%2
+ a<xde>br\t%0,%2
a<xde>b\t%0,%2
- wfadb\t%v0,%v1,%v2"
- [(set_attr "op_type" "<RRer>,RXE,VRR")
+ wfadb\t%v0,%v1,%v2
+ wfasb\t%v0,%v1,%v2"
+ [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR")
(set_attr "type" "fsimp<mode>")
- (set_attr "cpu_facility" "*,*,vec")])
+ (set_attr "cpu_facility" "*,*,*,vx,vxe")
+ (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")])
; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
(define_insn "*add<mode>3_cc"
[(set (reg CC_REGNUM)
- (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
- (match_operand:FP 2 "general_operand" " f,<Rf>"))
+ (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0")
+ (match_operand:FP 2 "general_operand" "f,f,R"))
(match_operand:FP 3 "const0_operand" "")))
- (set (match_operand:FP 0 "register_operand" "=f,f")
+ (set (match_operand:FP 0 "register_operand" "=f,f,f")
(plus:FP (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
"@
- a<xde><bt>r\t%0,<op1>%2
+ a<xde>tr\t%0,%1,%2
+ a<xde>br\t%0,%2
a<xde>b\t%0,%2"
- [(set_attr "op_type" "<RRer>,RXE")
- (set_attr "type" "fsimp<mode>")])
+ [(set_attr "op_type" "RRF,RRE,RXE")
+ (set_attr "type" "fsimp<mode>")
+ (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")])
; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr
(define_insn "*add<mode>3_cconly"
[(set (reg CC_REGNUM)
- (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0")
- (match_operand:FP 2 "general_operand" " f,<Rf>"))
+ (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0")
+ (match_operand:FP 2 "general_operand" "f,f,R"))
(match_operand:FP 3 "const0_operand" "")))
- (clobber (match_scratch:FP 0 "=f,f"))]
+ (clobber (match_scratch:FP 0 "=f,f,f"))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
"@
- a<xde><bt>r\t%0,<op1>%2
+ a<xde>tr\t%0,%1,%2
+ a<xde>br\t%0,%2
a<xde>b\t%0,%2"
- [(set_attr "op_type" "<RRer>,RXE")
- (set_attr "type" "fsimp<mode>")])
+ [(set_attr "op_type" "RRF,RRE,RXE")
+ (set_attr "type" "fsimp<mode>")
+ (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")])
;
; Pointer add instruction patterns
(clobber (reg:CC CC_REGNUM))])]
"TARGET_ZARCH"
{
- /* For z13 we have vaq which doesn't set CC. */
+ /* For z13 we have vsq which doesn't set CC. */
if (TARGET_VX)
{
emit_insn (gen_rtx_SET (operands[0],
(define_insn "*subdi3_sign"
[(set (match_operand:DI 0 "register_operand" "=d,d")
(minus:DI (match_operand:DI 1 "register_operand" "0,0")
- (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
+ (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T"))))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH"
"@
(define_insn "*subdi3_zero_cc"
[(set (reg CC_REGNUM)
(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
- (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
+ (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=d,d")
(minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
(define_insn "*subdi3_zero_cconly"
[(set (reg CC_REGNUM)
(compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
- (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))
+ (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d,d"))]
"s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH"
(define_insn "*subdi3_zero"
[(set (match_operand:DI 0 "register_operand" "=d,d")
(minus:DI (match_operand:DI 1 "register_operand" "0,0")
- (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))))
+ (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH"
"@
(minus:DI (match_operand:DI 1 "register_operand" "0")
(match_operand:DI 2 "general_operand" "do") ) )
(clobber (reg:CC CC_REGNUM))]
- "!TARGET_ZARCH && TARGET_CPU_ZARCH"
+ "!TARGET_ZARCH"
"#"
"&& reload_completed"
[(parallel
operands[7] = operand_subword (operands[1], 1, 0, DImode);
operands[8] = operand_subword (operands[2], 1, 0, DImode);")
-(define_insn_and_split "*subdi3_31"
- [(set (match_operand:DI 0 "register_operand" "=&d")
- (minus:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:DI 2 "general_operand" "do") ) )
- (clobber (reg:CC CC_REGNUM))]
- "!TARGET_CPU_ZARCH"
- "#"
- "&& reload_completed"
- [(parallel
- [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
- (clobber (reg:CC CC_REGNUM))])
- (parallel
- [(set (reg:CCL2 CC_REGNUM)
- (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
- (match_dup 7)))
- (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
- (set (pc)
- (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0))
- (pc)
- (label_ref (match_dup 9))))
- (parallel
- [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
- (clobber (reg:CC CC_REGNUM))])
- (match_dup 9)]
- "operands[3] = operand_subword (operands[0], 0, 0, DImode);
- operands[4] = operand_subword (operands[1], 0, 0, DImode);
- operands[5] = operand_subword (operands[2], 0, 0, DImode);
- operands[6] = operand_subword (operands[0], 1, 0, DImode);
- operands[7] = operand_subword (operands[1], 1, 0, DImode);
- operands[8] = operand_subword (operands[2], 1, 0, DImode);
- operands[9] = gen_label_rtx ();")
-
;
; subsi3 instruction pattern(s).
;
sh\t%0,%2
shy\t%0,%2"
[(set_attr "op_type" "RX,RXY")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "z196prop" "z196_cracked,z196_cracked")])
;
s<g>\t%0,%2
s<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
- (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
; slr, sl, sly, slgr, slg, slrk, slgrk
sl<g>\t%0,%2
sl<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
- (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
; slr, sl, sly, slgr, slg, slrk, slgrk
sl<g>\t%0,%2
sl<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
- (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
; slr, sl, sly, slgr, slg, slrk, slgrk
sl<g>\t%0,%2
sl<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
- (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
; slr, sl, sly, slgr, slg, slrk, slgrk
sl<g>\t%0,%2
sl<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
- (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
; slr, sl, sly, slgr, slg, slrk, slgrk
sl<g>\t%0,%2
sl<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
- (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
sl<g>\t%0,%2
sl<y>\t%0,%2"
[(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY")
- (set_attr "cpu_facility" "*,z196,*,*")
+ (set_attr "cpu_facility" "*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")])
+(define_insn "*subdi3_sign"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (minus:DI (match_operand:DI 1 "register_operand" "0")
+ (sign_extend:DI (match_operand:HI 2 "memory_operand" "T"))))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_Z14"
+ "sgh\t%0,%2"
+ [(set_attr "op_type" "RXY")])
+
;
; sub(tf|df|sf|td|dd)3 instruction pattern(s).
;
+; FIXME: (clobber (match_scratch:CC 3 "=c,c,c,X,X")) does not work - why?
; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
(define_insn "sub<mode>3"
- [(set (match_operand:FP 0 "register_operand" "=f, f,<vf>")
- (minus:FP (match_operand:FP 1 "register_operand" "<f0>, 0,<v0>")
- (match_operand:FP 2 "general_operand" "f,<Rf>,<vf>")))
+ [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v")
+ (minus:FP (match_operand:FP 1 "register_operand" "f,0,0,v,v")
+ (match_operand:FP 2 "general_operand" "f,f,R,v,v")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT"
"@
- s<xde><bt>r\t%0,<op1>%2
+ s<xde>tr\t%0,%1,%2
+ s<xde>br\t%0,%2
s<xde>b\t%0,%2
- wfsdb\t%v0,%v1,%v2"
- [(set_attr "op_type" "<RRer>,RXE,VRR")
+ wfsdb\t%v0,%v1,%v2
+ wfssb\t%v0,%v1,%v2"
+ [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR")
(set_attr "type" "fsimp<mode>")
- (set_attr "cpu_facility" "*,*,vec")])
+ (set_attr "cpu_facility" "*,*,*,vx,vxe")
+ (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")])
; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
(define_insn "*sub<mode>3_cc"
[(set (reg CC_REGNUM)
- (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
- (match_operand:FP 2 "general_operand" "f,<Rf>"))
+ (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0")
+ (match_operand:FP 2 "general_operand" "f,f,R"))
(match_operand:FP 3 "const0_operand" "")))
- (set (match_operand:FP 0 "register_operand" "=f,f")
+ (set (match_operand:FP 0 "register_operand" "=f,f,f")
(minus:FP (match_dup 1) (match_dup 2)))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
"@
- s<xde><bt>r\t%0,<op1>%2
+ s<xde>tr\t%0,%1,%2
+ s<xde>br\t%0,%2
s<xde>b\t%0,%2"
- [(set_attr "op_type" "<RRer>,RXE")
- (set_attr "type" "fsimp<mode>")])
+ [(set_attr "op_type" "RRF,RRE,RXE")
+ (set_attr "type" "fsimp<mode>")
+ (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")])
; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr
(define_insn "*sub<mode>3_cconly"
[(set (reg CC_REGNUM)
- (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0")
- (match_operand:FP 2 "general_operand" "f,<Rf>"))
+ (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0")
+ (match_operand:FP 2 "general_operand" "f,f,R"))
(match_operand:FP 3 "const0_operand" "")))
- (clobber (match_scratch:FP 0 "=f,f"))]
+ (clobber (match_scratch:FP 0 "=f,f,f"))]
"s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT"
"@
- s<xde><bt>r\t%0,<op1>%2
+ s<xde>tr\t%0,%1,%2
+ s<xde>br\t%0,%2
s<xde>b\t%0,%2"
- [(set_attr "op_type" "<RRer>,RXE")
- (set_attr "type" "fsimp<mode>")])
+ [(set_attr "op_type" "RRF,RRE,RXE")
+ (set_attr "type" "fsimp<mode>")
+ (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")])
;;
(compare
(plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
(match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
- (match_operand:GPR 2 "general_operand" "d,RT"))
+ (match_operand:GPR 2 "general_operand" "d,T"))
(match_dup 1)))
(set (match_operand:GPR 0 "register_operand" "=d,d")
(plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
- "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
+ "s390_match_ccmode (insn, CCL1mode)"
"@
alc<g>r\t%0,%2
alc<g>\t%0,%2"
(compare
(plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
(match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
- (match_operand:GPR 2 "general_operand" "d,RT"))
+ (match_operand:GPR 2 "general_operand" "d,T"))
(match_dup 1)))
(clobber (match_scratch:GPR 0 "=d,d"))]
- "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
+ "s390_match_ccmode (insn, CCL1mode)"
"@
alc<g>r\t%0,%2
alc<g>\t%0,%2"
(compare
(plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
(match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
- (match_operand:GPR 2 "general_operand" "d,RT"))
+ (match_operand:GPR 2 "general_operand" "d,T"))
(match_dup 2)))
(set (match_operand:GPR 0 "register_operand" "=d,d")
(plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
- "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
+ "s390_match_ccmode (insn, CCL1mode)"
"@
alc<g>r\t%0,%2
alc<g>\t%0,%2"
(compare
(plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
(match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
- (match_operand:GPR 2 "general_operand" "d,RT"))
+ (match_operand:GPR 2 "general_operand" "d,T"))
(match_dup 2)))
(clobber (match_scratch:GPR 0 "=d,d"))]
- "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH"
+ "s390_match_ccmode (insn, CCL1mode)"
"@
alc<g>r\t%0,%2
alc<g>\t%0,%2"
(compare
(plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
(match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
- (match_operand:GPR 2 "general_operand" "d,RT"))
+ (match_operand:GPR 2 "general_operand" "d,T"))
(const_int 0)))
(set (match_operand:GPR 0 "register_operand" "=d,d")
(plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))]
- "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
+ "s390_match_ccmode (insn, CCLmode)"
"@
alc<g>r\t%0,%2
alc<g>\t%0,%2"
[(set (match_operand:GPR 0 "register_operand" "=d,d")
(plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "")
(match_operand:GPR 1 "nonimmediate_operand" "%0,0"))
- (match_operand:GPR 2 "general_operand" "d,RT")))
+ (match_operand:GPR 2 "general_operand" "d,T")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_CPU_ZARCH"
+ ""
"@
alc<g>r\t%0,%2
alc<g>\t%0,%2"
[(set (reg CC_REGNUM)
(compare
(minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
- (match_operand:GPR 2 "general_operand" "d,RT"))
+ (match_operand:GPR 2 "general_operand" "d,T"))
(match_operand:GPR 3 "s390_slb_comparison" ""))
(const_int 0)))
(set (match_operand:GPR 0 "register_operand" "=d,d")
(minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))]
- "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
+ "s390_match_ccmode (insn, CCLmode)"
"@
slb<g>r\t%0,%2
slb<g>\t%0,%2"
(define_insn "*sub<mode>3_slb"
[(set (match_operand:GPR 0 "register_operand" "=d,d")
(minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0")
- (match_operand:GPR 2 "general_operand" "d,RT"))
+ (match_operand:GPR 2 "general_operand" "d,T"))
(match_operand:GPR 3 "s390_slb_comparison" "")))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_CPU_ZARCH"
+ ""
"@
slb<g>r\t%0,%2
slb<g>\t%0,%2"
(match_operand 1 "comparison_operator" "")
(match_operand:GPR 2 "register_operand" "")
(match_operand:GPR 3 "const_int_operand" "")]
- "TARGET_CPU_ZARCH"
+ ""
"if (!s390_expand_addcc (GET_CODE (operands[1]),
XEXP (operands[1], 0), XEXP (operands[1], 1),
operands[0], operands[2],
[(set (match_operand:GPR 0 "register_operand" "=&d")
(match_operand:GPR 1 "s390_alc_comparison" ""))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_CPU_ZARCH"
+ ""
"#"
"&& reload_completed"
[(set (match_dup 0) (const_int 0))
[(set (match_operand:GPR 0 "register_operand" "=&d")
(match_operand:GPR 1 "s390_slb_comparison" ""))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_CPU_ZARCH"
+ ""
"#"
"&& reload_completed"
[(set (match_dup 0) (const_int 0))
(match_operator:SI 1 "s390_scond_operator"
[(match_operand:GPR 2 "register_operand" "")
(match_operand:GPR 3 "general_operand" "")]))]
- "TARGET_CPU_ZARCH"
+ ""
"if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3],
operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
[(parallel
[(set (match_operand:SI 0 "register_operand" "")
(match_operator:SI 1 "s390_eqne_operator"
- [(match_operand:CCZ1 2 "register_operand")
+ [(match_operand 2 "cc_reg_operand")
(match_operand 3 "const0_operand")]))
(clobber (reg:CC CC_REGNUM))])]
""
- "emit_insn (gen_sne (operands[0], operands[2]));
- if (GET_CODE (operands[1]) == EQ)
- emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
+ "machine_mode mode = GET_MODE (operands[2]);
+ if (TARGET_Z196)
+ {
+ rtx cond, ite;
+
+ if (GET_CODE (operands[1]) == NE)
+ cond = gen_rtx_NE (VOIDmode, operands[2], const0_rtx);
+ else
+ cond = gen_rtx_EQ (VOIDmode, operands[2], const0_rtx);
+ ite = gen_rtx_IF_THEN_ELSE (SImode, cond, const1_rtx, const0_rtx);
+ emit_insn (gen_rtx_SET (operands[0], ite));
+ }
+ else
+ {
+ if (mode != CCZ1mode)
+ FAIL;
+ emit_insn (gen_sne (operands[0], operands[2]));
+ if (GET_CODE (operands[1]) == EQ)
+ emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx));
+ }
DONE;")
(define_insn_and_split "sne"
(define_expand "mov<mode>cc"
[(set (match_operand:GPR 0 "nonimmediate_operand" "")
(if_then_else:GPR (match_operand 1 "comparison_operator" "")
- (match_operand:GPR 2 "nonimmediate_operand" "")
- (match_operand:GPR 3 "nonimmediate_operand" "")))]
+ (match_operand:GPR 2 "loc_operand" "")
+ (match_operand:GPR 3 "loc_operand" "")))]
"TARGET_Z196"
{
+ if (!TARGET_Z13 && CONSTANT_P (operands[2]))
+ operands[2] = force_reg (<MODE>mode, operands[2]);
+
+ if (!TARGET_Z13 && CONSTANT_P (operands[3]))
+ operands[3] = force_reg (<MODE>mode, operands[3]);
+
/* Emit the comparison insn in case we do not already have a comparison result. */
if (!s390_comparison (operands[1], VOIDmode))
operands[1] = s390_emit_compare (GET_CODE (operands[1]),
XEXP (operands[1], 1));
})
-; locr, loc, stoc, locgr, locg, stocg
-(define_insn_and_split "*mov<mode>cc"
- [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d")
+;;
+;; - We do not have instructions for QImode or HImode but still
+;; enable load on condition/if conversion for them.
+(define_expand "mov<mode>cc"
+ [(set (match_operand:HQI 0 "nonimmediate_operand" "")
+ (if_then_else:HQI (match_operand 1 "comparison_operator" "")
+ (match_operand:HQI 2 "loc_operand" "")
+ (match_operand:HQI 3 "loc_operand" "")))]
+ "TARGET_Z196"
+{
+ /* Emit the comparison insn in case we do not already have a comparison
+ result. */
+ if (!s390_comparison (operands[1], VOIDmode))
+ operands[1] = s390_emit_compare (GET_CODE (operands[1]),
+ XEXP (operands[1], 0),
+ XEXP (operands[1], 1));
+
+ rtx then = operands[2];
+ rtx els = operands[3];
+
+ if ((!TARGET_Z13 && CONSTANT_P (then)) || MEM_P (then))
+ then = force_reg (<MODE>mode, then);
+ if ((!TARGET_Z13 && CONSTANT_P (els)) || MEM_P (els))
+ els = force_reg (<MODE>mode, els);
+
+ if (!CONSTANT_P (then))
+ then = simplify_gen_subreg (E_SImode, then, <MODE>mode, 0);
+ if (!CONSTANT_P (els))
+ els = simplify_gen_subreg (E_SImode, els, <MODE>mode, 0);
+
+ rtx tmp_target = gen_reg_rtx (E_SImode);
+ emit_insn (gen_movsicc (tmp_target, operands[1], then, els));
+ emit_move_insn (operands[0], gen_lowpart (<MODE>mode, tmp_target));
+ DONE;
+})
+
+
+
+; locr, loc, stoc, locgr, locg, stocg, lochi, locghi
+(define_insn "*mov<mode>cc"
+ [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,S,S")
(if_then_else:GPR
(match_operator 1 "s390_comparison"
- [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c")
+ [(match_operand 2 "cc_reg_operand" " c,c,c,c,c,c,c,c")
(match_operand 5 "const_int_operand" "")])
- (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS")
- (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))]
+ (match_operand:GPR 3 "loc_operand" " d,0,S,0,K,0,d,0")
+ (match_operand:GPR 4 "loc_operand" " 0,d,0,S,0,K,0,d")))]
"TARGET_Z196"
"@
loc<g>r%C1\t%0,%3
loc<g>r%D1\t%0,%4
loc<g>%C1\t%0,%3
loc<g>%D1\t%0,%4
+ loc<g>hi%C1\t%0,%h3
+ loc<g>hi%D1\t%0,%h4
stoc<g>%C1\t%3,%0
- stoc<g>%D1\t%4,%0
- #"
- "&& reload_completed
- && MEM_P (operands[3]) && MEM_P (operands[4])"
- [(set (match_dup 0)
- (if_then_else:GPR
- (match_op_dup 1 [(match_dup 2) (const_int 0)])
- (match_dup 3)
- (match_dup 0)))
- (set (match_dup 0)
- (if_then_else:GPR
- (match_op_dup 1 [(match_dup 2) (const_int 0)])
- (match_dup 0)
- (match_dup 4)))]
- ""
- [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")])
+ stoc<g>%D1\t%4,%0"
+ [(set_attr "op_type" "RRF,RRF,RSY,RSY,RIE,RIE,RSY,RSY")
+ (set_attr "cpu_facility" "*,*,*,*,z13,z13,*,*")])
;;
;;- Multiply instructions.
; muldi3 instruction pattern(s).
;
+(define_expand "muldi3"
+ [(parallel
+ [(set (match_operand:DI 0 "register_operand")
+ (mult:DI (match_operand:DI 1 "nonimmediate_operand")
+ (match_operand:DI 2 "general_operand")))
+ (clobber (reg:CC CC_REGNUM))])]
+ "TARGET_ZARCH")
+
(define_insn "*muldi3_sign"
[(set (match_operand:DI 0 "register_operand" "=d,d")
- (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))
+ (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T"))
(match_operand:DI 1 "register_operand" "0,0")))]
"TARGET_ZARCH"
"@
[(set_attr "op_type" "RRE,RXY")
(set_attr "type" "imuldi")])
-(define_insn "muldi3"
- [(set (match_operand:DI 0 "register_operand" "=d,d,d,d")
- (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
- (match_operand:DI 2 "general_operand" "d,K,RT,Os")))]
+(define_insn "*muldi3"
+ [(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d")
+ (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0,0,0")
+ (match_operand:DI 2 "general_operand" "d,d,K,T,Os")))
+ (clobber (match_scratch:CC 3 "=X,c,X,X,X"))]
"TARGET_ZARCH"
"@
msgr\t%0,%2
+ msgrkc\t%0,%1,%2
mghi\t%0,%h2
msg\t%0,%2
msgfi\t%0,%2"
- [(set_attr "op_type" "RRE,RI,RXY,RIL")
+ [(set_attr "op_type" "RRE,RRF,RI,RXY,RIL")
(set_attr "type" "imuldi")
- (set_attr "cpu_facility" "*,*,*,z10")])
+ (set_attr "cpu_facility" "*,z14,*,*,z10")])
+
+(define_insn "mulditi3"
+ [(set (match_operand:TI 0 "register_operand" "=d,d")
+ (mult:TI (sign_extend:TI
+ (match_operand:DI 1 "register_operand" "%d,0"))
+ (sign_extend:TI
+ (match_operand:DI 2 "nonimmediate_operand" " d,T"))))]
+ "TARGET_Z14"
+ "@
+ mgrk\t%0,%1,%2
+ mg\t%0,%2"
+ [(set_attr "op_type" "RRF,RXY")])
+
+; Combine likes op1 and op2 to be swapped sometimes.
+(define_insn "mulditi3_2"
+ [(set (match_operand:TI 0 "register_operand" "=d,d")
+ (mult:TI (sign_extend:TI
+ (match_operand:DI 1 "nonimmediate_operand" "%d,T"))
+ (sign_extend:TI
+ (match_operand:DI 2 "register_operand" " d,0"))))]
+ "TARGET_Z14"
+ "@
+ mgrk\t%0,%1,%2
+ mg\t%0,%1"
+ [(set_attr "op_type" "RRF,RXY")])
+
+(define_insn "*muldi3_sign"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (mult:DI (sign_extend:DI (match_operand:HI 2 "memory_operand" "T"))
+ (match_operand:DI 1 "register_operand" "0")))]
+ "TARGET_Z14"
+ "mgh\t%0,%2"
+ [(set_attr "op_type" "RXY")])
+
;
; mulsi3 instruction pattern(s).
;
+(define_expand "mulsi3"
+ [(parallel
+ [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d,d")
+ (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
+ (match_operand:SI 2 "general_operand" "d,d,K,R,T,Os")))
+ (clobber (reg:CC CC_REGNUM))])]
+ "")
+
(define_insn "*mulsi3_sign"
[(set (match_operand:SI 0 "register_operand" "=d,d")
(mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
(set_attr "type" "imulhi")
(set_attr "cpu_facility" "*,z10")])
-(define_insn "mulsi3"
- [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d")
- (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
- (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))]
+(define_insn "*mulsi3"
+ [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d,d")
+ (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,d,0,0,0,0")
+ (match_operand:SI 2 "general_operand" "d,d,K,R,T,Os")))
+ (clobber (match_scratch:CC 3 "=X,c,X,X,X,X"))]
""
"@
msr\t%0,%2
+ msrkc\t%0,%1,%2
mhi\t%0,%h2
ms\t%0,%2
msy\t%0,%2
msfi\t%0,%2"
- [(set_attr "op_type" "RRE,RI,RX,RXY,RIL")
- (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi")
- (set_attr "cpu_facility" "*,*,*,*,z10")])
+ [(set_attr "op_type" "RRE,RRF,RI,RX,RXY,RIL")
+ (set_attr "type" "imulsi,*,imulhi,imulsi,imulsi,imulsi")
+ (set_attr "cpu_facility" "*,z14,*,*,longdisp,z10")])
;
; mulsidi3 instruction pattern(s).
; mlr, ml, mlgr, mlg
(define_insn "umul<dwh><mode>3"
- [(set (match_operand:DW 0 "register_operand" "=d, d")
+ [(set (match_operand:DW 0 "register_operand" "=d,d")
(mult:DW (zero_extend:DW
- (match_operand:<DWH> 1 "register_operand" "%0, 0"))
+ (match_operand:<DWH> 1 "register_operand" "%0,0"))
(zero_extend:DW
- (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))]
- "TARGET_CPU_ZARCH"
+ (match_operand:<DWH> 2 "nonimmediate_operand" " d,T"))))]
+ ""
"@
ml<tg>r\t%0,%2
ml<tg>\t%0,%2"
; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr
(define_insn "mul<mode>3"
- [(set (match_operand:FP 0 "register_operand" "=f, f,<vf>")
- (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>, 0,<v0>")
- (match_operand:FP 2 "general_operand" "f,<Rf>,<vf>")))]
+ [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v")
+ (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v,v")
+ (match_operand:FP 2 "general_operand" "f,f,R,v,v")))]
"TARGET_HARD_FLOAT"
"@
- m<xdee><bt>r\t%0,<op1>%2
+ m<xdee>tr\t%0,%1,%2
+ m<xdee>br\t%0,%2
m<xdee>b\t%0,%2
- wfmdb\t%v0,%v1,%v2"
- [(set_attr "op_type" "<RRer>,RXE,VRR")
+ wfmdb\t%v0,%v1,%v2
+ wfmsb\t%v0,%v1,%v2"
+ [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR")
(set_attr "type" "fmul<mode>")
- (set_attr "cpu_facility" "*,*,vec")])
+ (set_attr "cpu_facility" "*,*,*,vx,vxe")
+ (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")])
; madbr, maebr, maxb, madb, maeb
(define_insn "fma<mode>4"
- [(set (match_operand:DSF 0 "register_operand" "=f,f,<vf>")
- (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,<vf>")
- (match_operand:DSF 2 "nonimmediate_operand" "f,R,<vf>")
- (match_operand:DSF 3 "register_operand" "0,0,<v0>")))]
+ [(set (match_operand:DSF 0 "register_operand" "=f,f,v,v")
+ (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v,v")
+ (match_operand:DSF 2 "nonimmediate_operand" "f,R,v,v")
+ (match_operand:DSF 3 "register_operand" "0,0,v,v")))]
"TARGET_HARD_FLOAT"
"@
ma<xde>br\t%0,%1,%2
ma<xde>b\t%0,%1,%2
- wfmadb\t%v0,%v1,%v2,%v3"
- [(set_attr "op_type" "RRE,RXE,VRR")
+ wfmadb\t%v0,%v1,%v2,%v3
+ wfmasb\t%v0,%v1,%v2,%v3"
+ [(set_attr "op_type" "RRE,RXE,VRR,VRR")
(set_attr "type" "fmadd<mode>")
- (set_attr "cpu_facility" "*,*,vec")])
+ (set_attr "cpu_facility" "*,*,vx,vxe")
+ (set_attr "enabled" "*,*,<DF>,<SF>")])
; msxbr, msdbr, msebr, msxb, msdb, mseb
(define_insn "fms<mode>4"
- [(set (match_operand:DSF 0 "register_operand" "=f,f,<vf>")
- (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,<vf>")
- (match_operand:DSF 2 "nonimmediate_operand" "f,R,<vf>")
- (neg:DSF (match_operand:DSF 3 "register_operand" "0,0,<v0>"))))]
+ [(set (match_operand:DSF 0 "register_operand" "=f,f,v,v")
+ (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v,v")
+ (match_operand:DSF 2 "nonimmediate_operand" "f,R,v,v")
+ (neg:DSF (match_operand:DSF 3 "register_operand" "0,0,v,v"))))]
"TARGET_HARD_FLOAT"
"@
ms<xde>br\t%0,%1,%2
ms<xde>b\t%0,%1,%2
- wfmsdb\t%v0,%v1,%v2,%v3"
- [(set_attr "op_type" "RRE,RXE,VRR")
+ wfmsdb\t%v0,%v1,%v2,%v3
+ wfmssb\t%v0,%v1,%v2,%v3"
+ [(set_attr "op_type" "RRE,RXE,VRR,VRR")
(set_attr "type" "fmadd<mode>")
- (set_attr "cpu_facility" "*,*,vec")])
+ (set_attr "cpu_facility" "*,*,vx,vxe")
+ (set_attr "enabled" "*,*,<DF>,<SF>")])
;;
;;- Divide and modulo instructions.
(clobber (match_dup 4))]
"TARGET_ZARCH"
{
- rtx insn, div_equal, mod_equal;
+ rtx div_equal, mod_equal;
+ rtx_insn *insn;
div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
(ashift:TI
(zero_extend:TI
(mod:DI (match_operand:DI 1 "register_operand" "0,0")
- (match_operand:DI 2 "general_operand" "d,RT")))
+ (match_operand:DI 2 "general_operand" "d,T")))
(const_int 64))
(zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
"TARGET_ZARCH"
(zero_extend:TI
(mod:DI (match_operand:DI 1 "register_operand" "0,0")
(sign_extend:DI
- (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))
+ (match_operand:SI 2 "nonimmediate_operand" "d,T"))))
(const_int 64))
(zero_extend:TI
(div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
(clobber (match_dup 4))]
"TARGET_ZARCH"
{
- rtx insn, div_equal, mod_equal, equal;
+ rtx div_equal, mod_equal, equal;
+ rtx_insn *insn;
div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
(truncate:DI
(umod:TI (match_operand:TI 1 "register_operand" "0,0")
(zero_extend:TI
- (match_operand:DI 2 "nonimmediate_operand" "d,RT")))))
+ (match_operand:DI 2 "nonimmediate_operand" "d,T")))))
(const_int 64))
(zero_extend:TI
(truncate:DI
(clobber (match_dup 4))]
"!TARGET_ZARCH"
{
- rtx insn, div_equal, mod_equal, equal;
+ rtx div_equal, mod_equal, equal;
+ rtx_insn *insn;
div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
(set (match_operand:SI 3 "general_operand" "")
(umod:SI (match_dup 1) (match_dup 2)))])
(clobber (match_dup 4))]
- "!TARGET_ZARCH && TARGET_CPU_ZARCH"
+ "!TARGET_ZARCH"
{
- rtx insn, div_equal, mod_equal, equal;
+ rtx div_equal, mod_equal, equal;
+ rtx_insn *insn;
div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
(truncate:SI
(umod:DI (match_operand:DI 1 "register_operand" "0,0")
(zero_extend:DI
- (match_operand:SI 2 "nonimmediate_operand" "d,RT")))))
+ (match_operand:SI 2 "nonimmediate_operand" "d,T")))))
(const_int 32))
(zero_extend:DI
(truncate:SI
(udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
- "!TARGET_ZARCH && TARGET_CPU_ZARCH"
+ "!TARGET_ZARCH"
"@
dlr\t%0,%2
dl\t%0,%2"
[(set_attr "op_type" "RRE,RXY")
(set_attr "type" "idiv")])
-(define_expand "udivsi3"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (udiv:SI (match_operand:SI 1 "general_operand" "")
- (match_operand:SI 2 "general_operand" "")))
- (clobber (match_dup 3))]
- "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
-{
- rtx insn, udiv_equal, umod_equal, equal;
-
- udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
- umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
- equal = gen_rtx_IOR (DImode,
- gen_rtx_ASHIFT (DImode,
- gen_rtx_ZERO_EXTEND (DImode, umod_equal),
- GEN_INT (32)),
- gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
-
- operands[3] = gen_reg_rtx (DImode);
-
- if (CONSTANT_P (operands[2]))
- {
- if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
- {
- rtx_code_label *label1 = gen_label_rtx ();
-
- operands[1] = make_safe_from (operands[1], operands[0]);
- emit_move_insn (operands[0], const0_rtx);
- emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX,
- SImode, 1, label1);
- emit_move_insn (operands[0], const1_rtx);
- emit_label (label1);
- }
- else
- {
- operands[2] = force_reg (SImode, operands[2]);
- operands[2] = make_safe_from (operands[2], operands[0]);
-
- emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
- insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
- operands[2]));
- set_unique_reg_note (insn, REG_EQUAL, equal);
-
- insn = emit_move_insn (operands[0],
- gen_lowpart (SImode, operands[3]));
- set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
- }
- }
- else
- {
- rtx_code_label *label1 = gen_label_rtx ();
- rtx_code_label *label2 = gen_label_rtx ();
- rtx_code_label *label3 = gen_label_rtx ();
-
- operands[1] = force_reg (SImode, operands[1]);
- operands[1] = make_safe_from (operands[1], operands[0]);
- operands[2] = force_reg (SImode, operands[2]);
- operands[2] = make_safe_from (operands[2], operands[0]);
-
- emit_move_insn (operands[0], const0_rtx);
- emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
- SImode, 1, label3);
- emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
- SImode, 0, label2);
- emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
- SImode, 0, label1);
- emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
- insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
- operands[2]));
- set_unique_reg_note (insn, REG_EQUAL, equal);
-
- insn = emit_move_insn (operands[0],
- gen_lowpart (SImode, operands[3]));
- set_unique_reg_note (insn, REG_EQUAL, udiv_equal);
-
- emit_jump (label3);
- emit_label (label1);
- emit_move_insn (operands[0], operands[1]);
- emit_jump (label3);
- emit_label (label2);
- emit_move_insn (operands[0], const1_rtx);
- emit_label (label3);
- }
- emit_move_insn (operands[0], operands[0]);
- DONE;
-})
-
-(define_expand "umodsi3"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "nonimmediate_operand" "")))
- (clobber (match_dup 3))]
- "!TARGET_ZARCH && !TARGET_CPU_ZARCH"
-{
- rtx insn, udiv_equal, umod_equal, equal;
-
- udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
- umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
- equal = gen_rtx_IOR (DImode,
- gen_rtx_ASHIFT (DImode,
- gen_rtx_ZERO_EXTEND (DImode, umod_equal),
- GEN_INT (32)),
- gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
-
- operands[3] = gen_reg_rtx (DImode);
-
- if (CONSTANT_P (operands[2]))
- {
- if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
- {
- rtx_code_label *label1 = gen_label_rtx ();
-
- operands[1] = make_safe_from (operands[1], operands[0]);
- emit_move_insn (operands[0], operands[1]);
- emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX,
- SImode, 1, label1);
- emit_insn (gen_abssi2 (operands[0], operands[2]));
- emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
- emit_label (label1);
- }
- else
- {
- operands[2] = force_reg (SImode, operands[2]);
- operands[2] = make_safe_from (operands[2], operands[0]);
-
- emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
- insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
- operands[2]));
- set_unique_reg_note (insn, REG_EQUAL, equal);
-
- insn = emit_move_insn (operands[0],
- gen_highpart (SImode, operands[3]));
- set_unique_reg_note (insn, REG_EQUAL, umod_equal);
- }
- }
- else
- {
- rtx_code_label *label1 = gen_label_rtx ();
- rtx_code_label *label2 = gen_label_rtx ();
- rtx_code_label *label3 = gen_label_rtx ();
-
- operands[1] = force_reg (SImode, operands[1]);
- operands[1] = make_safe_from (operands[1], operands[0]);
- operands[2] = force_reg (SImode, operands[2]);
- operands[2] = make_safe_from (operands[2], operands[0]);
-
- emit_move_insn(operands[0], operands[1]);
- emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX,
- SImode, 1, label3);
- emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX,
- SImode, 0, label2);
- emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX,
- SImode, 0, label1);
- emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
- insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
- operands[2]));
- set_unique_reg_note (insn, REG_EQUAL, equal);
-
- insn = emit_move_insn (operands[0],
- gen_highpart (SImode, operands[3]));
- set_unique_reg_note (insn, REG_EQUAL, umod_equal);
-
- emit_jump (label3);
- emit_label (label1);
- emit_move_insn (operands[0], const0_rtx);
- emit_jump (label3);
- emit_label (label2);
- emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
- emit_label (label3);
- }
- DONE;
-})
-
;
; div(df|sf)3 instruction pattern(s).
;
; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr
(define_insn "div<mode>3"
- [(set (match_operand:FP 0 "register_operand" "=f, f,<vf>")
- (div:FP (match_operand:FP 1 "register_operand" "<f0>, 0,<v0>")
- (match_operand:FP 2 "general_operand" "f,<Rf>,<vf>")))]
+ [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v")
+ (div:FP (match_operand:FP 1 "register_operand" "f,0,0,v,v")
+ (match_operand:FP 2 "general_operand" "f,f,R,v,v")))]
"TARGET_HARD_FLOAT"
"@
- d<xde><bt>r\t%0,<op1>%2
+ d<xde>tr\t%0,%1,%2
+ d<xde>br\t%0,%2
d<xde>b\t%0,%2
- wfddb\t%v0,%v1,%v2"
- [(set_attr "op_type" "<RRer>,RXE,VRR")
+ wfddb\t%v0,%v1,%v2
+ wfdsb\t%v0,%v1,%v2"
+ [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR")
(set_attr "type" "fdiv<mode>")
- (set_attr "cpu_facility" "*,*,vec")])
+ (set_attr "cpu_facility" "*,*,*,vx,vxe")
+ (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")])
;;
(define_insn "*anddi3_cc"
[(set (reg CC_REGNUM)
(compare
- (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
- (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d")
+ (match_operand:DI 2 "general_operand" " d,d,T,NxxDw"))
(const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=d,d, d, d")
+ (set (match_operand:DI 0 "register_operand" "=d,d,d, d")
(and:DI (match_dup 1) (match_dup 2)))]
"TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)"
"@
(define_insn "*anddi3_cconly"
[(set (reg CC_REGNUM)
(compare
- (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d")
- (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq"))
+ (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d")
+ (match_operand:DI 2 "general_operand" " d,d,T,NxxDw"))
(const_int 0)))
- (clobber (match_scratch:DI 0 "=d,d, d, d"))]
+ (clobber (match_scratch:DI 0 "=d,d,d, d"))]
"TARGET_ZARCH
&& s390_match_ccmode(insn, CCTmode)
/* Do not steal TM patterns. */
(define_insn "*anddi3"
[(set (match_operand:DI 0 "nonimmediate_operand"
- "=d,d, d, d, d, d, d, d,d,d, d, d, AQ,Q")
+ "=d,d, d, d, d, d, d, d,d,d,d, d, AQ,Q")
(and:DI
(match_operand:DI 1 "nonimmediate_operand"
- "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, d, 0,0")
+ "%d,o, 0, 0, 0, 0, 0, 0,0,d,0, d, 0,0")
(match_operand:DI 2 "general_operand"
- "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q")))
+ "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,T,NxxDw,NxQDF,Q")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
"s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
;; These two are what combine generates for (ashift (zero_extract)).
-(define_insn "*extzv_<mode>_srl"
+(define_insn "*extzv_<mode>_srl<clobbercc_or_nocc>"
[(set (match_operand:GPR 0 "register_operand" "=d")
(and:GPR (lshiftrt:GPR
(match_operand:GPR 1 "register_operand" "d")
(match_operand:GPR 2 "nonzero_shift_count_operand" ""))
- (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_Z10
+ (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))]
+ "<z10_or_zEC12_cond>
/* Note that even for the SImode pattern, the rotate is always DImode. */
&& s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]),
INTVAL (operands[3]))"
- "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2"
+ "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2"
[(set_attr "op_type" "RIE")
(set_attr "z10prop" "z10_super_E1")])
-(define_insn "*extzv_<mode>_sll"
+(define_insn "*extzv_<mode>_sll<clobbercc_or_nocc>"
[(set (match_operand:GPR 0 "register_operand" "=d")
(and:GPR (ashift:GPR
(match_operand:GPR 1 "register_operand" "d")
(match_operand:GPR 2 "nonzero_shift_count_operand" ""))
- (match_operand:GPR 3 "contiguous_bitmask_operand" "")))
- (clobber (reg:CC CC_REGNUM))]
- "TARGET_Z10
+ (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))]
+ "<z10_or_zEC12_cond>
&& s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]),
INTVAL (operands[3]))"
- "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,%2"
+ "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,%2"
[(set_attr "op_type" "RIE")
(set_attr "z10prop" "z10_super_E1")])
ny\t%0,%2
risbg\t%0,%1,%t2,128+%f2,0"
[(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
- (set_attr "cpu_facility" "*,*,z196,*,*,z10")
+ (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
z10_super_E1,z10_super_E1,z10_super_E1")])
ny\t%0,%2
risbg\t%0,%1,%t2,128+%f2,0"
[(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE")
- (set_attr "cpu_facility" "*,*,z196,*,*,z10")
+ (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
z10_super_E1,z10_super_E1,z10_super_E1")])
(and:SI (match_operand:SI 1 "nonimmediate_operand"
"%d,o, 0, 0, 0,0,d,0,0, d, 0,0")
(match_operand:SI 2 "general_operand"
- " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q")))
+ " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSw,NxQSF,Q")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
#
#"
[(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS")
- (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*")
+ (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,longdisp,z10,*,*")
(set_attr "z10prop" "*,
*,
z10_super_E1,
niy\t%S0,%b2
#"
[(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
- (set_attr "cpu_facility" "*,z196,*,*,*,*")
+ (set_attr "cpu_facility" "*,z196,*,*,longdisp,*")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")])
(define_insn "*andqi3_esa"
[(set_attr "op_type" "RR,SI,SS")
(set_attr "z10prop" "z10_super_E1,z10_super,*")])
+;
+; And with complement
+;
+; c = ~b & a = (b & a) ^ a
+
+(define_insn_and_split "*andc_split_<mode>"
+ [(set (match_operand:GPR 0 "nonimmediate_operand" "")
+ (and:GPR (not:GPR (match_operand:GPR 1 "nonimmediate_operand" ""))
+ (match_operand:GPR 2 "general_operand" "")))
+ (clobber (reg:CC CC_REGNUM))]
+ "!TARGET_ARCH13
+ && ! reload_completed
+ && (GET_CODE (operands[0]) != MEM
+ /* Ensure that s390_logical_operator_ok_p will succeed even
+ on the split xor if (b & a) is stored into a pseudo. */
+ || rtx_equal_p (operands[0], operands[2]))"
+ "#"
+ "&& 1"
+ [
+ (parallel
+ [(set (match_dup 3) (and:GPR (match_dup 1) (match_dup 2)))
+ (clobber (reg:CC CC_REGNUM))])
+ (parallel
+ [(set (match_dup 0) (xor:GPR (match_dup 3) (match_dup 2)))
+ (clobber (reg:CC CC_REGNUM))])]
+{
+ if (reg_overlap_mentioned_p (operands[0], operands[2]))
+ operands[3] = gen_reg_rtx (<MODE>mode);
+ else
+ operands[3] = operands[0];
+})
+
;
; Block and (NC) patterns.
;
(define_insn "*iordi3_cc"
[(set (reg CC_REGNUM)
- (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
- (match_operand:DI 2 "general_operand" " d,d,RT"))
+ (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
+ (match_operand:DI 2 "general_operand" " d,d,T"))
(const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=d,d, d")
+ (set (match_operand:DI 0 "register_operand" "=d,d,d")
(ior:DI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@
(define_insn "*iordi3_cconly"
[(set (reg CC_REGNUM)
(compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
- (match_operand:DI 2 "general_operand" " d,d,RT"))
+ (match_operand:DI 2 "general_operand" " d,d,T"))
(const_int 0)))
(clobber (match_scratch:DI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
(define_insn "*iordi3"
[(set (match_operand:DI 0 "nonimmediate_operand"
- "=d, d, d, d, d, d,d,d, d, AQ,Q")
+ "=d, d, d, d, d, d,d,d,d, AQ,Q")
(ior:DI (match_operand:DI 1 "nonimmediate_operand"
- " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0")
+ " %0, 0, 0, 0, 0, 0,0,d,0, 0,0")
(match_operand:DI 2 "general_operand"
- "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
+ "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,T,NxQD0,Q")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
o\t%0,%2
oy\t%0,%2"
[(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
- (set_attr "cpu_facility" "*,*,z196,*,*")
+ (set_attr "cpu_facility" "*,*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
(define_insn "*iorsi3_cconly"
o\t%0,%2
oy\t%0,%2"
[(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
- (set_attr "cpu_facility" "*,*,z196,*,*")
+ (set_attr "cpu_facility" "*,*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")])
(define_insn "*iorsi3_zarch"
#
#"
[(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS")
- (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*")
+ (set_attr "cpu_facility" "*,*,*,*,z196,*,longdisp,*,*")
(set_attr "z10prop" "z10_super_E1,
z10_super_E1,
z10_super_E1,
oiy\t%S0,%b2
#"
[(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS")
- (set_attr "cpu_facility" "*,z196,*,*,*,*")
+ (set_attr "cpu_facility" "*,z196,*,*,longdisp,*")
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1,
z10_super,z10_super,*")])
[(set_attr "op_type" "RR,SI,SS")
(set_attr "z10prop" "z10_super_E1,z10_super,*")])
+;
+; And/Or with complement
+;
+
+; ncrk, ncgrk, ocrk, ocgrk
+(define_insn "*<ANDOR:bitops_name>c<GPR:mode>_cc"
+ [(set (reg CC_REGNUM)
+ (compare
+ (ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
+ (match_operand:GPR 2 "register_operand" "d"))
+ (const_int 0)))
+ (set (match_operand:GPR 0 "register_operand" "=d")
+ (ANDOR:GPR (not:GPR (match_dup 1))
+ (match_dup 2)))]
+ "TARGET_ARCH13 && s390_match_ccmode(insn, CCTmode)"
+ "<ANDOR:noxa>c<GPR:g>rk\t%0,%2,%1"
+ [(set_attr "op_type" "RRF")])
+
+; ncrk, ncgrk, ocrk, ocgrk
+(define_insn "*<ANDOR:bitops_name>c<GPR:mode>_cconly"
+ [(set (reg CC_REGNUM)
+ (compare
+ (ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
+ (match_operand:GPR 2 "register_operand" "d"))
+ (const_int 0)))
+ (clobber (match_scratch:GPR 0 "=d"))]
+ "TARGET_ARCH13 && s390_match_ccmode(insn, CCTmode)"
+ "<ANDOR:noxa>c<GPR:g>rk\t%0,%2,%1"
+ [(set_attr "op_type" "RRF")])
+
+; ncrk, ncgrk, ocrk, ocgrk
+(define_insn "*<ANDOR:bitops_name>c<GPR:mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
+ (match_operand:GPR 2 "register_operand" "d")))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_ARCH13"
+ "<ANDOR:noxa>c<GPR:g>rk\t%0,%2,%1"
+ [(set_attr "op_type" "RRF")])
+
+;
+;- Nand/Nor instructions.
+;
+
+; nnrk, nngrk, nork, nogrk
+(define_insn "*n<ANDOR:inv_bitops_name><GPR:mode>_cc"
+ [(set (reg CC_REGNUM)
+ (compare
+ (ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
+ (not:GPR (match_operand:GPR 2 "register_operand" "d")))
+ (const_int 0)))
+ (set (match_operand:GPR 0 "register_operand" "=d")
+ (ANDOR:GPR (not:GPR (match_dup 1))
+ (not:GPR (match_dup 2))))]
+ "TARGET_ARCH13 && s390_match_ccmode(insn, CCTmode)"
+ "n<ANDOR:inv_no><GPR:g>rk\t%0,%1,%2"
+ [(set_attr "op_type" "RRF")])
+
+; nnrk, nngrk, nork, nogrk
+(define_insn "*n<ANDOR:inv_bitops_name><mode>_cconly"
+ [(set (reg CC_REGNUM)
+ (compare
+ (ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
+ (not:GPR (match_operand:GPR 2 "register_operand" "d")))
+ (const_int 0)))
+ (clobber (match_scratch:GPR 0 "=d"))]
+ "TARGET_ARCH13 && s390_match_ccmode(insn, CCTmode)"
+ "n<ANDOR:inv_no><GPR:g>rk\t%0,%1,%2"
+ [(set_attr "op_type" "RRF")])
+
+; nnrk, nngrk, nork, nogrk
+(define_insn "*n<ANDOR:inv_bitops_name><mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
+ (not:GPR (match_operand:GPR 2 "register_operand" "d"))))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_ARCH13"
+ "n<ANDOR:inv_no><GPR:g>rk\t%0,%1,%2"
+ [(set_attr "op_type" "RRF")])
+
+
;
; Block inclusive or (OC) patterns.
;
(define_insn "*xordi3_cc"
[(set (reg CC_REGNUM)
- (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
- (match_operand:DI 2 "general_operand" " d,d,RT"))
+ (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
+ (match_operand:DI 2 "general_operand" " d,d,T"))
(const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=d,d, d")
+ (set (match_operand:DI 0 "register_operand" "=d,d,d")
(xor:DI (match_dup 1) (match_dup 2)))]
"s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@
(define_insn "*xordi3_cconly"
[(set (reg CC_REGNUM)
- (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0")
- (match_operand:DI 2 "general_operand" " d,d,RT"))
+ (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0")
+ (match_operand:DI 2 "general_operand" " d,d,T"))
(const_int 0)))
- (clobber (match_scratch:DI 0 "=d,d, d"))]
+ (clobber (match_scratch:DI 0 "=d,d,d"))]
"s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH"
"@
xgr\t%0,%2
(set_attr "z10prop" "z10_super_E1,*,z10_super_E1")])
(define_insn "*xordi3"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q")
- (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0")
- (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q")))
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d,d, AQ,Q")
+ (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d,0, 0,0")
+ (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,T,NxQD0,Q")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
"@
x\t%0,%2
xy\t%0,%2"
[(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
- (set_attr "cpu_facility" "*,*,z196,*,*")
+ (set_attr "cpu_facility" "*,*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
z10_super_E1,z10_super_E1")])
x\t%0,%2
xy\t%0,%2"
[(set_attr "op_type" "RIL,RR,RRF,RX,RXY")
- (set_attr "cpu_facility" "*,*,z196,*,*")
+ (set_attr "cpu_facility" "*,*,z196,*,longdisp")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
z10_super_E1,z10_super_E1")])
#
#"
[(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS")
- (set_attr "cpu_facility" "*,*,z196,*,*,*,*")
+ (set_attr "cpu_facility" "*,*,z196,*,longdisp,*,*")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,
z10_super_E1,z10_super_E1,*,*")])
xiy\t%S0,%b2
#"
[(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS")
- (set_attr "cpu_facility" "*,*,z196,*,*,*")
+ (set_attr "cpu_facility" "*,*,z196,*,longdisp,*")
(set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")])
"operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
+;
+;- Nxor instructions.
+;
-;;
+; nxrk, nxgrk
+(define_insn "*nxor<GPR:mode>_cc"
+ [(set (reg CC_REGNUM)
+ (compare
+ (not:GPR (xor:GPR (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:GPR 2 "register_operand" "d")))
+ (const_int 0)))
+ (set (match_operand:GPR 0 "register_operand" "=d")
+ (xor:GPR (not:GPR (match_dup 1))
+ (match_dup 2)))]
+ "TARGET_ARCH13 && s390_match_ccmode(insn, CCTmode)"
+ "nx<GPR:g>rk\t%0,%1,%2"
+ [(set_attr "op_type" "RRF")])
+
+; nxrk, nxgrk
+(define_insn "*nxor<mode>_cconly"
+ [(set (reg CC_REGNUM)
+ (compare
+ (not:GPR (xor:GPR (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:GPR 2 "register_operand" "d")))
+ (const_int 0)))
+ (clobber (match_scratch:GPR 0 "=d"))]
+ "TARGET_ARCH13 && s390_match_ccmode(insn, CCTmode)"
+ "nx<GPR:g>rk\t%0,%1,%2"
+ [(set_attr "op_type" "RRF")])
+
+; nxrk, nxgrk
+(define_insn "*nxor<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (not:GPR (xor:GPR (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:GPR 2 "register_operand" "d"))))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_ARCH13"
+ "nx<GPR:g>rk\t%0,%1,%2"
+ [(set_attr "op_type" "RRF")])
+
+;;
;;- Negate instructions.
;;
(define_expand "neg<mode>2"
[(parallel
- [(set (match_operand:BFP 0 "register_operand" "=f")
- (neg:BFP (match_operand:BFP 1 "register_operand" "f")))
+ [(set (match_operand:BFP 0 "register_operand")
+ (neg:BFP (match_operand:BFP 1 "register_operand")))
(clobber (reg:CC CC_REGNUM))])]
- "TARGET_HARD_FLOAT"
- "")
+ "TARGET_HARD_FLOAT")
; lcxbr, lcdbr, lcebr
(define_insn "*neg<mode>2_cc"
; lcxbr, lcdbr, lcebr
; FIXME: wflcdb does not clobber cc
+; FIXME: Does wflcdb ever match here?
(define_insn "*neg<mode>2"
- [(set (match_operand:BFP 0 "register_operand" "=f,<vf>")
- (neg:BFP (match_operand:BFP 1 "register_operand" "f,<vf>")))
+ [(set (match_operand:BFP 0 "register_operand" "=f,v,v")
+ (neg:BFP (match_operand:BFP 1 "register_operand" "f,v,v")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT"
"@
lc<xde>br\t%0,%1
- wflcdb\t%0,%1"
- [(set_attr "op_type" "RRE,VRR")
- (set_attr "cpu_facility" "*,vec")
- (set_attr "type" "fsimp<mode>,*")])
+ wflcdb\t%0,%1
+ wflcsb\t%0,%1"
+ [(set_attr "op_type" "RRE,VRR,VRR")
+ (set_attr "cpu_facility" "*,vx,vxe")
+ (set_attr "type" "fsimp<mode>,*,*")
+ (set_attr "enabled" "*,<DF>,<SF>")])
;;
; lpxbr, lpdbr, lpebr
; FIXME: wflpdb does not clobber cc
(define_insn "*abs<mode>2"
- [(set (match_operand:BFP 0 "register_operand" "=f,<vf>")
- (abs:BFP (match_operand:BFP 1 "register_operand" "f,<vf>")))
+ [(set (match_operand:BFP 0 "register_operand" "=f,v")
+ (abs:BFP (match_operand:BFP 1 "register_operand" "f,v")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT"
"@
lp<xde>br\t%0,%1
wflpdb\t%0,%1"
[(set_attr "op_type" "RRE,VRR")
- (set_attr "cpu_facility" "*,vec")
- (set_attr "type" "fsimp<mode>,*")])
+ (set_attr "cpu_facility" "*,vx")
+ (set_attr "type" "fsimp<mode>,*")
+ (set_attr "enabled" "*,<DFDI>")])
;;
; lnxbr, lndbr, lnebr
; FIXME: wflndb does not clobber cc
(define_insn "*negabs<mode>2"
- [(set (match_operand:BFP 0 "register_operand" "=f,<vf>")
- (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f,<vf>"))))
+ [(set (match_operand:BFP 0 "register_operand" "=f,v")
+ (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f,v"))))
(clobber (reg:CC CC_REGNUM))]
"TARGET_HARD_FLOAT"
"@
ln<xde>br\t%0,%1
wflndb\t%0,%1"
[(set_attr "op_type" "RRE,VRR")
- (set_attr "cpu_facility" "*,vec")
- (set_attr "type" "fsimp<mode>,*")])
+ (set_attr "cpu_facility" "*,vx")
+ (set_attr "type" "fsimp<mode>,*")
+ (set_attr "enabled" "*,<DFDI>")])
;;
;;- Square root instructions.
; sqxbr, sqdbr, sqebr, sqdb, sqeb
(define_insn "sqrt<mode>2"
- [(set (match_operand:BFP 0 "register_operand" "=f, f,<vf>")
- (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>,<vf>")))]
+ [(set (match_operand:BFP 0 "register_operand" "=f,f,v")
+ (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,R,v")))]
"TARGET_HARD_FLOAT"
"@
sq<xde>br\t%0,%1
wfsqdb\t%v0,%v1"
[(set_attr "op_type" "RRE,RXE,VRR")
(set_attr "type" "fsqrt<mode>")
- (set_attr "cpu_facility" "*,*,vec")])
+ (set_attr "cpu_facility" "*,*,vx")
+ (set_attr "enabled" "*,<DSF>,<DFDI>")])
;;
(clz:DI (match_operand:DI 1 "register_operand" "d")))]
"TARGET_EXTIMM && TARGET_ZARCH"
{
- rtx insn, clz_equal;
+ rtx_insn *insn;
+ rtx clz_equal;
rtx wide_reg = gen_reg_rtx (TImode);
- rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63);
+ rtx msb = gen_rtx_CONST_INT (DImode, HOST_WIDE_INT_1U << 63);
clz_equal = gen_rtx_CLZ (DImode, operands[1]);
DONE;
})
+; CLZ result is in hard reg op0 - this is the high part of the target operand
+; The source with the left-most one bit cleared is in hard reg op0 + 1 - the low part
(define_insn "clztidi2"
[(set (match_operand:TI 0 "register_operand" "=d")
(ior:TI
- (ashift:TI
- (zero_extend:TI
- (xor:DI (match_operand:DI 1 "register_operand" "d")
- (lshiftrt (match_operand:DI 2 "const_int_operand" "")
- (subreg:SI (clz:DI (match_dup 1)) 4))))
-
- (const_int 64))
- (zero_extend:TI (clz:DI (match_dup 1)))))
- (clobber (reg:CC CC_REGNUM))]
- "(unsigned HOST_WIDE_INT) INTVAL (operands[2])
- == (unsigned HOST_WIDE_INT) 1 << 63
+ (ashift:TI (zero_extend:TI (clz:DI (match_operand:DI 1 "register_operand" "d")))
+ (const_int 64))
+ (zero_extend:TI
+ (xor:DI (match_dup 1)
+ (lshiftrt (match_operand:DI 2 "const_int_operand" "")
+ (subreg:SI (clz:DI (match_dup 1)) 4))))))
+ (clobber (reg:CC CC_REGNUM))]
+ "UINTVAL (operands[2]) == HOST_WIDE_INT_1U << 63
&& TARGET_EXTIMM && TARGET_ZARCH"
"flogr\t%0,%1"
[(set_attr "op_type" "RRE")])
; rotl(di|si)3 instruction pattern(s).
;
-; rll, rllg
-(define_insn "rotl<mode>3"
- [(set (match_operand:GPR 0 "register_operand" "=d")
- (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
- (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
- "TARGET_CPU_ZARCH"
- "rll<g>\t%0,%1,%Y2"
- [(set_attr "op_type" "RSE")
- (set_attr "atype" "reg")
- (set_attr "z10prop" "z10_super_E1")])
+(define_expand "rotl<mode>3"
+ [(set (match_operand:GPR 0 "register_operand" "")
+ (rotate:GPR (match_operand:GPR 1 "register_operand" "")
+ (match_operand:SI 2 "nonmemory_operand" "")))]
+ ""
+ "")
; rll, rllg
-(define_insn "*rotl<mode>3_and"
- [(set (match_operand:GPR 0 "register_operand" "=d")
- (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
- (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
- (match_operand:SI 3 "const_int_operand" "n"))))]
- "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63"
- "rll<g>\t%0,%1,%Y2"
+(define_insn "*rotl<mode>3<addr_style_op><masked_op>"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (rotate:GPR (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:SI 2 "nonmemory_operand" "an")))]
+ ""
+ "rll<g>\t%0,%1,<addr_style_op_ops>"
[(set_attr "op_type" "RSE")
(set_attr "atype" "reg")
- (set_attr "z10prop" "z10_super_E1")])
+ (set_attr "z10prop" "z10_super_E1")])
;;
(define_expand "<shift><mode>3"
[(set (match_operand:DSI 0 "register_operand" "")
(SHIFT:DSI (match_operand:DSI 1 "register_operand" "")
- (match_operand:SI 2 "shift_count_or_setmem_operand" "")))]
+ (match_operand:SI 2 "nonmemory_operand" "")))]
""
"")
+; ESA 64 bit register pair shift with reg or imm shift count
; sldl, srdl
-(define_insn "*<shift>di3_31"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))]
+(define_insn "*<shift>di3_31<addr_style_op><masked_op>"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
+ (match_operand:SI 2 "nonmemory_operand" "an")))]
"!TARGET_ZARCH"
- "s<lr>dl\t%0,%Y2"
+ "s<lr>dl\t%0,<addr_style_op_ops>"
[(set_attr "op_type" "RS")
(set_attr "atype" "reg")
(set_attr "z196prop" "z196_cracked")])
+
+; 64 bit register shift with reg or imm shift count
; sll, srl, sllg, srlg, sllk, srlk
-(define_insn "*<shift><mode>3"
- [(set (match_operand:GPR 0 "register_operand" "=d,d")
- (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
- (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))]
+(define_insn "*<shift><mode>3<addr_style_op><masked_op>"
+ [(set (match_operand:GPR 0 "register_operand" "=d, d")
+ (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>, d")
+ (match_operand:SI 2 "nonmemory_operand" "an,an")))]
""
"@
- s<lr>l<g>\t%0,<1>%Y2
- s<lr>l<gk>\t%0,%1,%Y2"
- [(set_attr "op_type" "RS<E>,RSY")
- (set_attr "atype" "reg,reg")
- (set_attr "cpu_facility" "*,z196")
- (set_attr "z10prop" "z10_super_E1,*")])
-
-; sldl, srdl
-(define_insn "*<shift>di3_31_and"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (SHIFT:DI (match_operand:DI 1 "register_operand" "0")
- (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
- (match_operand:SI 3 "const_int_operand" "n"))))]
- "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
- "s<lr>dl\t%0,%Y2"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "reg")])
-
-; sll, srl, sllg, srlg, sllk, srlk
-(define_insn "*<shift><mode>3_and"
- [(set (match_operand:GPR 0 "register_operand" "=d,d")
- (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
- (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
- (match_operand:SI 3 "const_int_operand" "n,n"))))]
- "(INTVAL (operands[3]) & 63) == 63"
- "@
- s<lr>l<g>\t%0,<1>%Y2
- s<lr>l<gk>\t%0,%1,%Y2"
+ s<lr>l<g>\t%0,<1><addr_style_op_ops>
+ s<lr>l<gk>\t%0,%1,<addr_style_op_ops>"
[(set_attr "op_type" "RS<E>,RSY")
(set_attr "atype" "reg,reg")
(set_attr "cpu_facility" "*,z196")
- (set_attr "z10prop" "z10_super_E1,*")])
+ (set_attr "z10prop" "z10_super_E1,*")])
;
; ashr(di|si)3 instruction pattern(s).
[(parallel
[(set (match_operand:DSI 0 "register_operand" "")
(ashiftrt:DSI (match_operand:DSI 1 "register_operand" "")
- (match_operand:SI 2 "shift_count_or_setmem_operand" "")))
+ (match_operand:SI 2 "nonmemory_operand" "")))
(clobber (reg:CC CC_REGNUM))])]
""
"")
-(define_insn "*ashrdi3_cc_31"
- [(set (reg CC_REGNUM)
- (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
- (const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=d")
- (ashiftrt:DI (match_dup 1) (match_dup 2)))]
- "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
- "srda\t%0,%Y2"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "reg")])
-
-(define_insn "*ashrdi3_cconly_31"
- [(set (reg CC_REGNUM)
- (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))
- (const_int 0)))
- (clobber (match_scratch:DI 0 "=d"))]
- "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)"
- "srda\t%0,%Y2"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "reg")])
-
-(define_insn "*ashrdi3_31"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
- (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))
+; FIXME: The number of alternatives is doubled here to match the fix
+; number of 2 in the subst pattern for the (clobber (match_scratch...
+; The right fix should be to support match_scratch in the output
+; pattern of a define_subst.
+(define_insn "*ashrdi3_31<addr_style_op_cc><masked_op_cc><setcc><cconly>"
+ [(set (match_operand:DI 0 "register_operand" "=d, d")
+ (ashiftrt:DI (match_operand:DI 1 "register_operand" "0, 0")
+ (match_operand:SI 2 "nonmemory_operand" "an,an")))
(clobber (reg:CC CC_REGNUM))]
"!TARGET_ZARCH"
- "srda\t%0,%Y2"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "reg")])
-
-; sra, srag, srak
-(define_insn "*ashr<mode>3_cc"
- [(set (reg CC_REGNUM)
- (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
- (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
- (const_int 0)))
- (set (match_operand:GPR 0 "register_operand" "=d,d")
- (ashiftrt:GPR (match_dup 1) (match_dup 2)))]
- "s390_match_ccmode(insn, CCSmode)"
"@
- sra<g>\t%0,<1>%Y2
- sra<gk>\t%0,%1,%Y2"
- [(set_attr "op_type" "RS<E>,RSY")
- (set_attr "atype" "reg,reg")
- (set_attr "cpu_facility" "*,z196")
- (set_attr "z10prop" "z10_super_E1,*")])
+ srda\t%0,<addr_style_op_cc_ops>
+ srda\t%0,<addr_style_op_cc_ops>"
+ [(set_attr "op_type" "RS")
+ (set_attr "atype" "reg")])
-; sra, srag, srak
-(define_insn "*ashr<mode>3_cconly"
- [(set (reg CC_REGNUM)
- (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
- (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))
- (const_int 0)))
- (clobber (match_scratch:GPR 0 "=d,d"))]
- "s390_match_ccmode(insn, CCSmode)"
- "@
- sra<g>\t%0,<1>%Y2
- sra<gk>\t%0,%1,%Y2"
- [(set_attr "op_type" "RS<E>,RSY")
- (set_attr "atype" "reg,reg")
- (set_attr "cpu_facility" "*,z196")
- (set_attr "z10prop" "z10_super_E1,*")])
; sra, srag
-(define_insn "*ashr<mode>3"
- [(set (match_operand:GPR 0 "register_operand" "=d,d")
- (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
- (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))
+(define_insn "*ashr<mode>3<addr_style_op_cc><masked_op_cc><setcc><cconly>"
+ [(set (match_operand:GPR 0 "register_operand" "=d, d")
+ (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>, d")
+ (match_operand:SI 2 "nonmemory_operand" "an,an")))
(clobber (reg:CC CC_REGNUM))]
""
"@
- sra<g>\t%0,<1>%Y2
- sra<gk>\t%0,%1,%Y2"
+ sra<g>\t%0,<1><addr_style_op_cc_ops>
+ sra<gk>\t%0,%1,<addr_style_op_cc_ops>"
[(set_attr "op_type" "RS<E>,RSY")
- (set_attr "atype" "reg,reg")
- (set_attr "cpu_facility" "*,z196")
- (set_attr "z10prop" "z10_super_E1,*")])
-
-
-; shift pattern with implicit ANDs
-
-(define_insn "*ashrdi3_cc_31_and"
- [(set (reg CC_REGNUM)
- (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
- (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
- (match_operand:SI 3 "const_int_operand" "n")))
- (const_int 0)))
- (set (match_operand:DI 0 "register_operand" "=d")
- (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
- "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
- && (INTVAL (operands[3]) & 63) == 63"
- "srda\t%0,%Y2"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "reg")])
-
-(define_insn "*ashrdi3_cconly_31_and"
- [(set (reg CC_REGNUM)
- (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
- (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
- (match_operand:SI 3 "const_int_operand" "n")))
- (const_int 0)))
- (clobber (match_scratch:DI 0 "=d"))]
- "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)
- && (INTVAL (operands[3]) & 63) == 63"
- "srda\t%0,%Y2"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "reg")])
-
-(define_insn "*ashrdi3_31_and"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
- (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")
- (match_operand:SI 3 "const_int_operand" "n"))))
- (clobber (reg:CC CC_REGNUM))]
- "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63"
- "srda\t%0,%Y2"
- [(set_attr "op_type" "RS")
- (set_attr "atype" "reg")])
-
-; sra, srag, srak
-(define_insn "*ashr<mode>3_cc_and"
- [(set (reg CC_REGNUM)
- (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
- (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
- (match_operand:SI 3 "const_int_operand" "n,n")))
- (const_int 0)))
- (set (match_operand:GPR 0 "register_operand" "=d,d")
- (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))]
- "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
- "@
- sra<g>\t%0,<1>%Y2
- sra<gk>\t%0,%1,%Y2"
- [(set_attr "op_type" "RS<E>,RSY")
- (set_attr "atype" "reg,reg")
- (set_attr "cpu_facility" "*,z196")
- (set_attr "z10prop" "z10_super_E1,*")])
-
-; sra, srag, srak
-(define_insn "*ashr<mode>3_cconly_and"
- [(set (reg CC_REGNUM)
- (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
- (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
- (match_operand:SI 3 "const_int_operand" "n,n")))
- (const_int 0)))
- (clobber (match_scratch:GPR 0 "=d,d"))]
- "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63"
- "@
- sra<g>\t%0,<1>%Y2
- sra<gk>\t%0,%1,%Y2"
- [(set_attr "op_type" "RS<E>,RSY")
- (set_attr "atype" "reg,reg")
- (set_attr "cpu_facility" "*,z196")
- (set_attr "z10prop" "z10_super_E1,*")])
-
-; sra, srag, srak
-(define_insn "*ashr<mode>3_and"
- [(set (match_operand:GPR 0 "register_operand" "=d,d")
- (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d")
- (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")
- (match_operand:SI 3 "const_int_operand" "n,n"))))
- (clobber (reg:CC CC_REGNUM))]
- "(INTVAL (operands[3]) & 63) == 63"
- "@
- sra<g>\t%0,<1>%Y2
- sra<gk>\t%0,%1,%Y2"
- [(set_attr "op_type" "RS<E>,RSY")
- (set_attr "atype" "reg,reg")
+ (set_attr "atype" "reg")
(set_attr "cpu_facility" "*,z196")
(set_attr "z10prop" "z10_super_E1,*")])
(match_operand 2 "const_int_operand" "")])
(label_ref (match_operand 0 "" ""))
(pc)))]
- "TARGET_CPU_ZARCH"
+ ""
{
if (get_attr_length (insn) == 4)
return "j%C1\t%l0";
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
(const_int 4) (const_int 6)))])
-(define_insn "*cjump_31"
- [(set (pc)
- (if_then_else
- (match_operator 1 "s390_comparison" [(reg CC_REGNUM)
- (match_operand 2 "const_int_operand" "")])
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- "!TARGET_CPU_ZARCH"
-{
- gcc_assert (get_attr_length (insn) == 4);
- return "j%C1\t%l0";
-}
- [(set_attr "op_type" "RI")
- (set_attr "type" "branch")
- (set (attr "length")
- (if_then_else (not (match_test "flag_pic"))
- (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
- (const_int 4) (const_int 6))
- (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
- (const_int 4) (const_int 8))))])
-
(define_insn "*cjump_long"
[(set (pc)
(if_then_else
(match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
(match_operand 0 "address_operand" "ZQZR")
(pc)))]
- ""
+ "!TARGET_INDIRECT_BRANCH_NOBP_JUMP"
{
if (get_attr_op_type (insn) == OP_TYPE_RR)
return "b%C1r\t%0";
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
+ (set (attr "mnemonic")
+ (if_then_else (match_operand 0 "register_operand" "")
+ (const_string "bcr") (const_string "bc")))
(set_attr "type" "branch")
(set_attr "atype" "agen")])
(ANY_RETURN)
(pc)))]
"s390_can_use_<code>_insn ()"
- "b%C0r\t%%r14"
- [(set_attr "op_type" "RR")
+{
+ if (TARGET_INDIRECT_BRANCH_NOBP_RET)
+ {
+ s390_indirect_branch_via_thunk (RETURN_REGNUM,
+ INVALID_REGNUM,
+ operands[0],
+ s390_indirect_branch_type_return);
+ return "";
+ }
+ else
+ return "b%C0r\t%%r14";
+}
+ [(set (attr "op_type")
+ (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET")
+ (const_string "RIL")
+ (const_string "RR")))
+ (set (attr "mnemonic")
+ (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET")
+ (const_string "brcl")
+ (const_string "bcr")))
(set_attr "type" "jsr")
(set_attr "atype" "agen")])
(match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
(pc)
(label_ref (match_operand 0 "" ""))))]
- "TARGET_CPU_ZARCH"
+ ""
{
if (get_attr_length (insn) == 4)
return "j%D1\t%l0";
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
(const_int 4) (const_int 6)))])
-(define_insn "*icjump_31"
- [(set (pc)
- (if_then_else
- (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
- (pc)
- (label_ref (match_operand 0 "" ""))))]
- "!TARGET_CPU_ZARCH"
-{
- gcc_assert (get_attr_length (insn) == 4);
- return "j%D1\t%l0";
-}
- [(set_attr "op_type" "RI")
- (set_attr "type" "branch")
- (set (attr "length")
- (if_then_else (not (match_test "flag_pic"))
- (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
- (const_int 4) (const_int 6))
- (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
- (const_int 4) (const_int 8))))])
-
(define_insn "*icjump_long"
[(set (pc)
(if_then_else
(match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)])
(pc)
(match_operand 0 "address_operand" "ZQZR")))]
- ""
+ "!TARGET_INDIRECT_BRANCH_NOBP_JUMP"
{
if (get_attr_op_type (insn) == OP_TYPE_RR)
return "b%D1r\t%0";
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
+ (set (attr "mnemonic")
+ (if_then_else (match_operand 0 "register_operand" "")
+ (const_string "bcr") (const_string "bc")))
(set_attr "type" "branch")
(set_attr "atype" "agen")])
; clrt, clgrt, clfit, clgit, clt, clgt
(define_insn "*cmp_and_trap_unsigned_int<mode>"
[(trap_if (match_operator 0 "s390_unsigned_integer_comparison"
- [(match_operand:GPR 1 "register_operand" "d,d, d")
- (match_operand:GPR 2 "general_operand" "d,D,RT")])
+ [(match_operand:GPR 1 "register_operand" "d,d,d")
+ (match_operand:GPR 2 "general_operand" "d,D,T")])
(const_int 0))]
"TARGET_Z10"
"@
; lat, lgat
(define_insn "*load_and_trap<mode>"
- [(trap_if (eq (match_operand:GPR 0 "memory_operand" "RT")
+ [(trap_if (eq (match_operand:GPR 0 "memory_operand" "T")
(const_int 0))
(const_int 0))
(set (match_operand:GPR 1 "register_operand" "=d")
(set (match_operand:GPR 4 "nonimmediate_operand" "")
(plus:GPR (match_dup 1) (match_dup 2)))
(clobber (match_scratch:GPR 5 ""))]
- "TARGET_CPU_ZARCH"
+ ""
"#"
"!reload_completed && !reload_in_progress"
[(set (match_dup 7) (match_dup 2)) ; the increment
(subreg:SI (match_dup 2) 0)))
(clobber (match_scratch:SI 4 "=X,&1,&?d"))
(clobber (reg:CC CC_REGNUM))]
- "!TARGET_ZARCH && TARGET_CPU_ZARCH"
+ "!TARGET_ZARCH"
{
if (which_alternative != 0)
return "#";
(use (match_operand 1 "" ""))] ; label
""
{
- if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
- emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0]));
- else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
+ if (GET_MODE (operands[0]) == SImode)
emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0]));
else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH)
emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0]));
(plus:SI (match_dup 1) (const_int -1)))
(clobber (match_scratch:SI 3 "=X,&1,&?d"))
(clobber (reg:CC CC_REGNUM))]
- "TARGET_CPU_ZARCH"
+ ""
{
if (which_alternative != 0)
return "#";
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
(const_int 4) (const_int 10)))])
-(define_insn_and_split "doloop_si31"
- [(set (pc)
- (if_then_else
- (ne (match_operand:SI 1 "register_operand" "d,d,d")
- (const_int 1))
- (label_ref (match_operand 0 "" ""))
- (pc)))
- (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X")
- (plus:SI (match_dup 1) (const_int -1)))
- (clobber (match_scratch:SI 3 "=X,&1,&?d"))
- (clobber (reg:CC CC_REGNUM))]
- "!TARGET_CPU_ZARCH"
-{
- if (which_alternative != 0)
- return "#";
- else if (get_attr_length (insn) == 4)
- return "brct\t%1,%l0";
- else
- gcc_unreachable ();
-}
- "&& reload_completed
- && (! REG_P (operands[2])
- || ! rtx_equal_p (operands[1], operands[2]))"
- [(set (match_dup 3) (match_dup 1))
- (parallel [(set (reg:CCAN CC_REGNUM)
- (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
- (const_int 0)))
- (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
- (set (match_dup 2) (match_dup 3))
- (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0))
- (label_ref (match_dup 0))
- (pc)))]
- ""
- [(set_attr "op_type" "RI")
- ; Strictly speaking, the z10 properties are valid for brct only, however, it does not
- ; hurt us in the (rare) case of ahi.
- (set_attr "z10prop" "z10_super_E1")
- (set_attr "type" "branch")
- (set (attr "length")
- (if_then_else (not (match_test "flag_pic"))
- (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
- (const_int 4) (const_int 6))
- (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
- (const_int 4) (const_int 8))))])
-
-(define_insn "*doloop_si_long"
- [(set (pc)
- (if_then_else
- (ne (match_operand:SI 1 "register_operand" "d")
- (const_int 1))
- (match_operand 0 "address_operand" "ZQZR")
- (pc)))
- (set (match_operand:SI 2 "register_operand" "=1")
- (plus:SI (match_dup 1) (const_int -1)))
- (clobber (match_scratch:SI 3 "=X"))
- (clobber (reg:CC CC_REGNUM))]
- "!TARGET_CPU_ZARCH"
-{
- if (get_attr_op_type (insn) == OP_TYPE_RR)
- return "bctr\t%1,%0";
- else
- return "bct\t%1,%a0";
-}
- [(set (attr "op_type")
- (if_then_else (match_operand 0 "register_operand" "")
- (const_string "RR") (const_string "RX")))
- (set_attr "type" "branch")
- (set_attr "atype" "agen")
- (set_attr "z10prop" "z10_c")
- (set_attr "z196prop" "z196_cracked")])
-
(define_insn_and_split "doloop_di"
[(set (pc)
(if_then_else
(define_insn "*jump64"
[(set (pc) (label_ref (match_operand 0 "" "")))]
- "TARGET_CPU_ZARCH"
+ ""
{
if (get_attr_length (insn) == 4)
return "j\t%l0";
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
(const_int 4) (const_int 6)))])
-(define_insn "*jump31"
- [(set (pc) (label_ref (match_operand 0 "" "")))]
- "!TARGET_CPU_ZARCH"
-{
- gcc_assert (get_attr_length (insn) == 4);
- return "j\t%l0";
-}
- [(set_attr "op_type" "RI")
- (set_attr "type" "branch")
- (set (attr "length")
- (if_then_else (not (match_test "flag_pic"))
- (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
- (const_int 4) (const_int 6))
- (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
- (const_int 4) (const_int 8))))])
-
;
; indirect-jump instruction pattern(s).
;
-(define_insn "indirect_jump"
- [(set (pc) (match_operand 0 "address_operand" "ZQZR"))]
+(define_expand "indirect_jump"
+ [(set (pc) (match_operand 0 "nonimmediate_operand" ""))]
""
+{
+ if (address_operand (operands[0], GET_MODE (operands[0])))
+ ;
+ else if (TARGET_Z14
+ && GET_MODE (operands[0]) == Pmode
+ && memory_operand (operands[0], Pmode))
+ ;
+ else
+ operands[0] = force_reg (Pmode, operands[0]);
+
+ if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK)
+ {
+ operands[0] = force_reg (Pmode, operands[0]);
+ if (TARGET_CPU_Z10)
+ {
+ if (TARGET_64BIT)
+ emit_jump_insn (gen_indirect_jump_via_thunkdi_z10 (operands[0]));
+ else
+ emit_jump_insn (gen_indirect_jump_via_thunksi_z10 (operands[0]));
+ }
+ else
+ {
+ if (TARGET_64BIT)
+ emit_jump_insn (gen_indirect_jump_via_thunkdi (operands[0]));
+ else
+ emit_jump_insn (gen_indirect_jump_via_thunksi (operands[0]));
+ }
+ DONE;
+ }
+
+ if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK)
+ {
+ operands[0] = force_reg (Pmode, operands[0]);
+ rtx label_ref = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
+ if (TARGET_CPU_Z10)
+ {
+ if (TARGET_64BIT)
+ emit_jump_insn (gen_indirect_jump_via_inlinethunkdi_z10 (operands[0],
+ label_ref));
+ else
+ emit_jump_insn (gen_indirect_jump_via_inlinethunksi_z10 (operands[0],
+ label_ref));
+ }
+ else
+ {
+ if (TARGET_64BIT)
+ emit_jump_insn (gen_indirect_jump_via_inlinethunkdi (operands[0],
+ label_ref,
+ force_reg (Pmode, label_ref)));
+ else
+ emit_jump_insn (gen_indirect_jump_via_inlinethunksi (operands[0],
+ label_ref,
+ force_reg (Pmode, label_ref)));
+ }
+ DONE;
+ }
+})
+
+(define_insn "*indirect_jump"
+ [(set (pc)
+ (match_operand 0 "address_operand" "ZR"))]
+ "!TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK"
{
if (get_attr_op_type (insn) == OP_TYPE_RR)
return "br\t%0";
else
return "b\t%a0";
}
- [(set (attr "op_type")
- (if_then_else (match_operand 0 "register_operand" "")
- (const_string "RR") (const_string "RX")))
- (set_attr "type" "branch")
- (set_attr "atype" "agen")])
+ [(set (attr "op_type")
+ (if_then_else (match_operand 0 "register_operand" "")
+ (const_string "RR") (const_string "RX")))
+ (set (attr "mnemonic")
+ (if_then_else (match_operand 0 "register_operand" "")
+ (const_string "br") (const_string "b")))
+ (set_attr "type" "branch")
+ (set_attr "atype" "agen")])
+
+(define_insn "indirect_jump_via_thunk<mode>_z10"
+ [(set (pc)
+ (match_operand:P 0 "register_operand" "a"))]
+ "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK
+ && TARGET_CPU_Z10"
+{
+ s390_indirect_branch_via_thunk (REGNO (operands[0]),
+ INVALID_REGNUM,
+ NULL_RTX,
+ s390_indirect_branch_type_jump);
+ return "";
+}
+ [(set_attr "op_type" "RIL")
+ (set_attr "mnemonic" "jg")
+ (set_attr "type" "branch")
+ (set_attr "atype" "agen")])
+
+(define_insn "indirect_jump_via_thunk<mode>"
+ [(set (pc)
+ (match_operand:P 0 "register_operand" " a"))
+ (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))]
+ "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK
+ && !TARGET_CPU_Z10"
+{
+ s390_indirect_branch_via_thunk (REGNO (operands[0]),
+ INVALID_REGNUM,
+ NULL_RTX,
+ s390_indirect_branch_type_jump);
+ return "";
+}
+ [(set_attr "op_type" "RIL")
+ (set_attr "mnemonic" "jg")
+ (set_attr "type" "branch")
+ (set_attr "atype" "agen")])
+
+
+; The label_ref is wrapped into an if_then_else in order to hide it
+; from mark_jump_label. Without this the label_ref would become the
+; ONLY jump target of that jump breaking the control flow graph.
+(define_insn "indirect_jump_via_inlinethunk<mode>_z10"
+ [(unspec [(if_then_else (match_operand:P 1 "larl_operand" "X")
+ (const_int 0)
+ (const_int 0))
+ (const_int 0)] UNSPEC_EXECUTE_JUMP)
+ (set (pc) (match_operand:P 0 "register_operand" "a"))]
+ "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK
+ && TARGET_CPU_Z10"
+{
+ s390_indirect_branch_via_inline_thunk (operands[1]);
+ return "";
+}
+ [(set_attr "op_type" "RIL")
+ (set_attr "type" "branch")
+ (set_attr "length" "10")])
+
+(define_insn "indirect_jump_via_inlinethunk<mode>"
+ [(unspec [(if_then_else (match_operand:P 1 "larl_operand" "X")
+ (const_int 0)
+ (const_int 0))
+ (match_operand:P 2 "register_operand" "a")] UNSPEC_EXECUTE_JUMP)
+ (set (pc) (match_operand:P 0 "register_operand" "a"))]
+ "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK
+ && !TARGET_CPU_Z10"
+{
+ s390_indirect_branch_via_inline_thunk (operands[2]);
+ return "";
+}
+ [(set_attr "op_type" "RX")
+ (set_attr "type" "branch")
+ (set_attr "length" "8")])
+
+; FIXME: LRA does not appear to be able to deal with MEMs being
+; checked against address constraints like ZR above. So make this a
+; separate pattern for now.
+(define_insn "*indirect2_jump"
+ [(set (pc)
+ (match_operand 0 "nonimmediate_operand" "a,T"))]
+ "!TARGET_INDIRECT_BRANCH_NOBP_JUMP"
+ "@
+ br\t%0
+ bi\t%0"
+ [(set_attr "op_type" "RR,RXY")
+ (set_attr "type" "branch")
+ (set_attr "atype" "agen")
+ (set_attr "cpu_facility" "*,z14")])
;
; casesi instruction pattern(s).
;
-(define_insn "casesi_jump"
- [(set (pc) (match_operand 0 "address_operand" "ZQZR"))
- (use (label_ref (match_operand 1 "" "")))]
+(define_expand "casesi_jump"
+ [(parallel
+ [(set (pc) (match_operand 0 "address_operand"))
+ (use (label_ref (match_operand 1 "")))])]
""
+{
+ if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK)
+ {
+ operands[0] = force_reg (GET_MODE (operands[0]), operands[0]);
+
+ if (TARGET_CPU_Z10)
+ {
+ if (TARGET_64BIT)
+ emit_jump_insn (gen_casesi_jump_via_thunkdi_z10 (operands[0],
+ operands[1]));
+ else
+ emit_jump_insn (gen_casesi_jump_via_thunksi_z10 (operands[0],
+ operands[1]));
+ }
+ else
+ {
+ if (TARGET_64BIT)
+ emit_jump_insn (gen_casesi_jump_via_thunkdi (operands[0],
+ operands[1]));
+ else
+ emit_jump_insn (gen_casesi_jump_via_thunksi (operands[0],
+ operands[1]));
+ }
+ DONE;
+ }
+
+ if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK)
+ {
+ operands[0] = force_reg (Pmode, operands[0]);
+ rtx label_ref = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
+ if (TARGET_CPU_Z10)
+ {
+ if (TARGET_64BIT)
+ emit_jump_insn (gen_casesi_jump_via_inlinethunkdi_z10 (operands[0],
+ operands[1],
+ label_ref));
+ else
+ emit_jump_insn (gen_casesi_jump_via_inlinethunksi_z10 (operands[0],
+ operands[1],
+ label_ref));
+ }
+ else
+ {
+ if (TARGET_64BIT)
+ emit_jump_insn (gen_casesi_jump_via_inlinethunkdi (operands[0],
+ operands[1],
+ label_ref,
+ force_reg (Pmode, label_ref)));
+ else
+ emit_jump_insn (gen_casesi_jump_via_inlinethunksi (operands[0],
+ operands[1],
+ label_ref,
+ force_reg (Pmode, label_ref)));
+ }
+ DONE;
+ }
+})
+
+(define_insn "*casesi_jump"
+ [(set (pc) (match_operand 0 "address_operand" "ZR"))
+ (use (label_ref (match_operand 1 "" "")))]
+ "!TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK"
{
if (get_attr_op_type (insn) == OP_TYPE_RR)
return "br\t%0";
else
return "b\t%a0";
}
- [(set (attr "op_type")
- (if_then_else (match_operand 0 "register_operand" "")
- (const_string "RR") (const_string "RX")))
- (set_attr "type" "branch")
- (set_attr "atype" "agen")])
+ [(set (attr "op_type")
+ (if_then_else (match_operand 0 "register_operand" "")
+ (const_string "RR") (const_string "RX")))
+ (set (attr "mnemonic")
+ (if_then_else (match_operand 0 "register_operand" "")
+ (const_string "br") (const_string "b")))
+ (set_attr "type" "branch")
+ (set_attr "atype" "agen")])
+
+(define_insn "casesi_jump_via_thunk<mode>_z10"
+ [(set (pc) (match_operand:P 0 "register_operand" "a"))
+ (use (label_ref (match_operand 1 "" "")))]
+ "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK
+ && TARGET_CPU_Z10"
+{
+ s390_indirect_branch_via_thunk (REGNO (operands[0]),
+ INVALID_REGNUM,
+ NULL_RTX,
+ s390_indirect_branch_type_jump);
+ return "";
+}
+ [(set_attr "op_type" "RIL")
+ (set_attr "mnemonic" "jg")
+ (set_attr "type" "branch")
+ (set_attr "atype" "agen")])
+
+(define_insn "casesi_jump_via_thunk<mode>"
+ [(set (pc) (match_operand:P 0 "register_operand" "a"))
+ (use (label_ref (match_operand 1 "" "")))
+ (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))]
+ "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK
+ && !TARGET_CPU_Z10"
+{
+ s390_indirect_branch_via_thunk (REGNO (operands[0]),
+ INVALID_REGNUM,
+ NULL_RTX,
+ s390_indirect_branch_type_jump);
+ return "";
+}
+ [(set_attr "op_type" "RIL")
+ (set_attr "mnemonic" "jg")
+ (set_attr "type" "branch")
+ (set_attr "atype" "agen")])
+
+
+; The label_ref is wrapped into an if_then_else in order to hide it
+; from mark_jump_label. Without this the label_ref would become the
+; ONLY jump target of that jump breaking the control flow graph.
+(define_insn "casesi_jump_via_inlinethunk<mode>_z10"
+ [(unspec [(if_then_else (match_operand:P 2 "larl_operand" "X")
+ (const_int 0)
+ (const_int 0))
+ (const_int 0)] UNSPEC_EXECUTE_JUMP)
+ (set (pc) (match_operand:P 0 "register_operand" "a"))
+ (use (label_ref (match_operand 1 "" "")))]
+ "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK
+ && TARGET_CPU_Z10"
+{
+ s390_indirect_branch_via_inline_thunk (operands[2]);
+ return "";
+}
+ [(set_attr "op_type" "RIL")
+ (set_attr "type" "cs")
+ (set_attr "length" "10")])
+
+(define_insn "casesi_jump_via_inlinethunk<mode>"
+ [(unspec [(if_then_else (match_operand:P 2 "larl_operand" "X")
+ (const_int 0)
+ (const_int 0))
+ (match_operand:P 3 "register_operand" "a")] UNSPEC_EXECUTE_JUMP)
+ (set (pc) (match_operand:P 0 "register_operand" "a"))
+ (use (label_ref (match_operand 1 "" "")))]
+ "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK
+ && !TARGET_CPU_Z10"
+{
+ s390_indirect_branch_via_inline_thunk (operands[3]);
+ return "";
+}
+ [(set_attr "op_type" "RX")
+ (set_attr "type" "cs")
+ (set_attr "length" "8")])
(define_expand "casesi"
[(match_operand:SI 0 "general_operand" "")
(match_operand 0 "const_int_operand" "n"))]
"SIBLING_CALL_P (insn)
&& GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
- "br\t%%r1"
- [(set_attr "op_type" "RR")
+{
+ if (TARGET_INDIRECT_BRANCH_NOBP_CALL)
+ {
+ gcc_assert (TARGET_CPU_Z10);
+ s390_indirect_branch_via_thunk (SIBCALL_REGNUM,
+ INVALID_REGNUM,
+ NULL_RTX,
+ s390_indirect_branch_type_call);
+ return "";
+ }
+ else
+ return "br\t%%r1";
+}
+ [(set (attr "op_type")
+ (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL")
+ (const_string "RIL")
+ (const_string "RR")))
+ (set (attr "mnemonic")
+ (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL")
+ (const_string "jg")
+ (const_string "br")))
(set_attr "type" "branch")
(set_attr "atype" "agen")])
(define_insn "*sibcall_brcl"
[(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
(match_operand 1 "const_int_operand" "n"))]
- "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
+ "SIBLING_CALL_P (insn)"
"jg\t%0"
[(set_attr "op_type" "RIL")
(set_attr "type" "branch")])
(match_operand 1 "const_int_operand" "n")))]
"SIBLING_CALL_P (insn)
&& GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
- "br\t%%r1"
- [(set_attr "op_type" "RR")
+{
+ if (TARGET_INDIRECT_BRANCH_NOBP_CALL)
+ {
+ gcc_assert (TARGET_CPU_Z10);
+ s390_indirect_branch_via_thunk (SIBCALL_REGNUM,
+ INVALID_REGNUM,
+ NULL_RTX,
+ s390_indirect_branch_type_call);
+ return "";
+ }
+ else
+ return "br\t%%r1";
+}
+ [(set (attr "op_type")
+ (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL")
+ (const_string "RIL")
+ (const_string "RR")))
+ (set (attr "mnemonic")
+ (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL")
+ (const_string "jg")
+ (const_string "br")))
(set_attr "type" "branch")
(set_attr "atype" "agen")])
[(set (match_operand 0 "" "")
(call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
(match_operand 2 "const_int_operand" "n")))]
- "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
+ "SIBLING_CALL_P (insn)"
"jg\t%1"
[(set_attr "op_type" "RIL")
(set_attr "type" "branch")])
(match_operand 1 "const_int_operand" "n"))
(clobber (match_operand 2 "register_operand" "=r"))]
"!SIBLING_CALL_P (insn)
- && TARGET_CPU_ZARCH
+
&& GET_MODE (operands[2]) == Pmode"
"brasl\t%2,%0"
[(set_attr "op_type" "RIL")
(set_attr "type" "jsr")
- (set_attr "z196prop" "z196_cracked")])
+ (set_attr "z196prop" "z196_cracked")
+ (set_attr "relative_long" "yes")])
(define_insn "*basr"
- [(call (mem:QI (match_operand 0 "address_operand" "ZQZR"))
+ [(call (mem:QI (match_operand 0 "address_operand" "ZR"))
(match_operand 1 "const_int_operand" "n"))
(clobber (match_operand 2 "register_operand" "=r"))]
- "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
+ "!TARGET_INDIRECT_BRANCH_NOBP_CALL
+ && !SIBLING_CALL_P (insn)
+ && GET_MODE (operands[2]) == Pmode"
{
if (get_attr_op_type (insn) == OP_TYPE_RR)
return "basr\t%2,%0";
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
+ (set (attr "mnemonic")
+ (if_then_else (match_operand 0 "register_operand" "")
+ (const_string "basr") (const_string "bas")))
+ (set_attr "type" "jsr")
+ (set_attr "atype" "agen")
+ (set_attr "z196prop" "z196_cracked")])
+
+(define_insn "*basr_via_thunk<mode>_z10"
+ [(call (mem:QI (match_operand:P 0 "register_operand" "a"))
+ (match_operand 1 "const_int_operand" "n"))
+ (clobber (match_operand:P 2 "register_operand" "=&r"))]
+ "TARGET_INDIRECT_BRANCH_NOBP_CALL
+ && TARGET_CPU_Z10
+ && !SIBLING_CALL_P (insn)"
+{
+ s390_indirect_branch_via_thunk (REGNO (operands[0]),
+ REGNO (operands[2]),
+ NULL_RTX,
+ s390_indirect_branch_type_call);
+ return "";
+}
+ [(set_attr "op_type" "RIL")
+ (set_attr "mnemonic" "brasl")
+ (set_attr "type" "jsr")
+ (set_attr "atype" "agen")
+ (set_attr "z196prop" "z196_cracked")])
+
+(define_insn "*basr_via_thunk<mode>"
+ [(call (mem:QI (match_operand:P 0 "register_operand" "a"))
+ (match_operand 1 "const_int_operand" "n"))
+ (clobber (match_operand:P 2 "register_operand" "=&r"))
+ (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))]
+ "TARGET_INDIRECT_BRANCH_NOBP_CALL
+ && !TARGET_CPU_Z10
+ && !SIBLING_CALL_P (insn)"
+{
+ s390_indirect_branch_via_thunk (REGNO (operands[0]),
+ REGNO (operands[2]),
+ NULL_RTX,
+ s390_indirect_branch_type_call);
+ return "";
+}
+ [(set_attr "op_type" "RIL")
+ (set_attr "mnemonic" "brasl")
(set_attr "type" "jsr")
(set_attr "atype" "agen")
(set_attr "z196prop" "z196_cracked")])
(match_operand 2 "const_int_operand" "n")))
(clobber (match_operand 3 "register_operand" "=r"))]
"!SIBLING_CALL_P (insn)
- && TARGET_CPU_ZARCH
+
&& GET_MODE (operands[3]) == Pmode"
"brasl\t%3,%1"
[(set_attr "op_type" "RIL")
(set_attr "type" "jsr")
- (set_attr "z196prop" "z196_cracked")])
+ (set_attr "z196prop" "z196_cracked")
+ (set_attr "relative_long" "yes")])
(define_insn "*basr_r"
[(set (match_operand 0 "" "")
- (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
+ (call (mem:QI (match_operand 1 "address_operand" "ZR"))
(match_operand 2 "const_int_operand" "n")))
(clobber (match_operand 3 "register_operand" "=r"))]
- "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
+ "!TARGET_INDIRECT_BRANCH_NOBP_CALL
+ && !SIBLING_CALL_P (insn)
+ && GET_MODE (operands[3]) == Pmode"
{
if (get_attr_op_type (insn) == OP_TYPE_RR)
return "basr\t%3,%1";
[(set (attr "op_type")
(if_then_else (match_operand 1 "register_operand" "")
(const_string "RR") (const_string "RX")))
+ (set (attr "mnemonic")
+ (if_then_else (match_operand 1 "register_operand" "")
+ (const_string "basr") (const_string "bas")))
+ (set_attr "type" "jsr")
+ (set_attr "atype" "agen")
+ (set_attr "z196prop" "z196_cracked")])
+
+(define_insn "*basr_r_via_thunk_z10"
+ [(set (match_operand 0 "" "")
+ (call (mem:QI (match_operand 1 "register_operand" "a"))
+ (match_operand 2 "const_int_operand" "n")))
+ (clobber (match_operand 3 "register_operand" "=&r"))]
+ "TARGET_INDIRECT_BRANCH_NOBP_CALL
+ && TARGET_CPU_Z10
+ && !SIBLING_CALL_P (insn)
+ && GET_MODE (operands[3]) == Pmode"
+{
+ s390_indirect_branch_via_thunk (REGNO (operands[1]),
+ REGNO (operands[3]),
+ NULL_RTX,
+ s390_indirect_branch_type_call);
+ return "";
+}
+ [(set_attr "op_type" "RIL")
+ (set_attr "mnemonic" "brasl")
+ (set_attr "type" "jsr")
+ (set_attr "atype" "agen")
+ (set_attr "z196prop" "z196_cracked")])
+
+(define_insn "*basr_r_via_thunk"
+ [(set (match_operand 0 "" "")
+ (call (mem:QI (match_operand 1 "register_operand" "a"))
+ (match_operand 2 "const_int_operand" "n")))
+ (clobber (match_operand 3 "register_operand" "=&r"))
+ (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))]
+ "TARGET_INDIRECT_BRANCH_NOBP_CALL
+ && !TARGET_CPU_Z10
+ && !SIBLING_CALL_P (insn)
+ && GET_MODE (operands[3]) == Pmode"
+{
+ s390_indirect_branch_via_thunk (REGNO (operands[1]),
+ REGNO (operands[3]),
+ NULL_RTX,
+ s390_indirect_branch_type_call);
+ return "";
+}
+ [(set_attr "op_type" "RIL")
+ (set_attr "mnemonic" "brasl")
(set_attr "type" "jsr")
(set_attr "atype" "agen")
(set_attr "z196prop" "z196_cracked")])
(define_insn "*tls_load_64"
[(set (match_operand:DI 0 "register_operand" "=d")
- (unspec:DI [(match_operand:DI 1 "memory_operand" "RT")
+ (unspec:DI [(match_operand:DI 1 "memory_operand" "T")
(match_operand:DI 2 "" "")]
UNSPEC_TLS_LOAD))]
"TARGET_64BIT"
ly\t%0,%1%J2"
[(set_attr "op_type" "RX,RXY")
(set_attr "type" "load")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")])
(define_insn "*bras_tls"
(clobber (match_operand 3 "register_operand" "=r"))
(use (match_operand 4 "" ""))]
"!SIBLING_CALL_P (insn)
- && TARGET_CPU_ZARCH
+
&& GET_MODE (operands[3]) == Pmode"
"brasl\t%3,%1%J4"
[(set_attr "op_type" "RIL")
(set_attr "type" "jsr")
- (set_attr "z196prop" "z196_cracked")])
+ (set_attr "z196prop" "z196_cracked")
+ (set_attr "relative_long" "yes")])
(define_insn "*basr_tls"
[(set (match_operand 0 "" "")
- (call (mem:QI (match_operand 1 "address_operand" "ZQZR"))
+ (call (mem:QI (match_operand 1 "address_operand" "ZR"))
(match_operand 2 "const_int_operand" "n")))
(clobber (match_operand 3 "register_operand" "=r"))
(use (match_operand 4 "" ""))]
; memory barrier patterns.
;
-(define_expand "mem_signal_fence"
- [(match_operand:SI 0 "const_int_operand")] ;; model
- ""
-{
- /* The s390 memory model is strong enough not to require any
- barrier in order to synchronize a thread with itself. */
- DONE;
-})
-
(define_expand "mem_thread_fence"
[(match_operand:SI 0 "const_int_operand")] ;; model
""
ld\t%0,%1
ldy\t%0,%1"
[(set_attr "op_type" "RS,RSY,RS,RSY")
+ (set_attr "cpu_facility" "*,longdisp,*,longdisp")
(set_attr "type" "lm,lm,floaddf,floaddf")])
(define_insn "atomic_loadti_1"
[(set (match_operand:TI 0 "register_operand" "=r")
- (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")]
+ (unspec:TI [(match_operand:TI 1 "memory_operand" "T")]
UNSPEC_MOVA))]
"TARGET_ZARCH"
"lpq\t%0,%1"
std %1,%0
stdy %1,%0"
[(set_attr "op_type" "RS,RSY,RS,RSY")
+ (set_attr "cpu_facility" "*,longdisp,*,longdisp")
(set_attr "type" "stm,stm,fstoredf,fstoredf")])
(define_insn "atomic_storeti_1"
- [(set (match_operand:TI 0 "memory_operand" "=RT")
+ [(set (match_operand:TI 0 "memory_operand" "=T")
(unspec:TI [(match_operand:TI 1 "register_operand" "r")]
UNSPEC_MOVA))]
"TARGET_ZARCH"
(define_expand "atomic_compare_and_swap<mode>"
[(match_operand:SI 0 "register_operand") ;; bool success output
- (match_operand:DGPR 1 "nonimmediate_operand");; oldval output
- (match_operand:DGPR 2 "memory_operand") ;; memory
- (match_operand:DGPR 3 "register_operand") ;; expected intput
- (match_operand:DGPR 4 "register_operand") ;; newval intput
+ (match_operand:DINT 1 "nonimmediate_operand");; oldval output
+ (match_operand:DINT 2 "s_operand") ;; memory
+ (match_operand:DINT 3 "general_operand") ;; expected intput
+ (match_operand:DINT 4 "general_operand") ;; newval intput
(match_operand:SI 5 "const_int_operand") ;; is_weak
(match_operand:SI 6 "const_int_operand") ;; success model
(match_operand:SI 7 "const_int_operand")] ;; failure model
""
{
- rtx cc, cmp, output = operands[1];
-
- if (!register_operand (output, <MODE>mode))
- output = gen_reg_rtx (<MODE>mode);
-
- if (MEM_ALIGN (operands[2]) < GET_MODE_BITSIZE (GET_MODE (operands[2])))
+ if (GET_MODE_BITSIZE (<MODE>mode) >= 16
+ && GET_MODE_BITSIZE (<MODE>mode) > MEM_ALIGN (operands[2]))
FAIL;
- emit_insn (gen_atomic_compare_and_swap<mode>_internal
- (output, operands[2], operands[3], operands[4]));
-
- /* We deliberately accept non-register operands in the predicate
- to ensure the write back to the output operand happens *before*
- the store-flags code below. This makes it easier for combine
- to merge the store-flags code with a potential test-and-branch
- pattern following (immediately!) afterwards. */
- if (output != operands[1])
- emit_move_insn (operands[1], output);
-
- cc = gen_rtx_REG (CCZ1mode, CC_REGNUM);
- cmp = gen_rtx_EQ (SImode, cc, const0_rtx);
- emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx));
- DONE;
-})
-
-(define_expand "atomic_compare_and_swap<mode>"
- [(match_operand:SI 0 "register_operand") ;; bool success output
- (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output
- (match_operand:HQI 2 "memory_operand") ;; memory
- (match_operand:HQI 3 "general_operand") ;; expected intput
- (match_operand:HQI 4 "general_operand") ;; newval intput
- (match_operand:SI 5 "const_int_operand") ;; is_weak
- (match_operand:SI 6 "const_int_operand") ;; success model
- (match_operand:SI 7 "const_int_operand")] ;; failure model
- ""
-{
- s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2],
- operands[3], operands[4], INTVAL (operands[5]));
- DONE;
-})
+ s390_expand_cs (<MODE>mode, operands[0], operands[1], operands[2],
+ operands[3], operands[4], INTVAL (operands[5]));
+ DONE;})
(define_expand "atomic_compare_and_swap<mode>_internal"
[(parallel
[(set (match_operand:DGPR 0 "register_operand")
- (match_operand:DGPR 1 "memory_operand"))
+ (match_operand:DGPR 1 "s_operand"))
(set (match_dup 1)
(unspec_volatile:DGPR
[(match_dup 1)
(match_operand:DGPR 2 "register_operand")
(match_operand:DGPR 3 "register_operand")]
UNSPECV_CAS))
- (set (reg:CCZ1 CC_REGNUM)
- (compare:CCZ1 (match_dup 1) (match_dup 2)))])]
- "")
+ (set (match_operand 4 "cc_reg_operand")
+ (match_dup 5))])]
+ "GET_MODE (operands[4]) == CCZmode
+ || GET_MODE (operands[4]) == CCZ1mode"
+{
+ operands[5]
+ = gen_rtx_COMPARE (GET_MODE (operands[4]), operands[1], operands[2]);
+})
; cdsg, csg
(define_insn "*atomic_compare_and_swap<mode>_1"
[(set (match_operand:TDI 0 "register_operand" "=r")
- (match_operand:TDI 1 "memory_operand" "+QS"))
+ (match_operand:TDI 1 "nonsym_memory_operand" "+S"))
(set (match_dup 1)
(unspec_volatile:TDI
[(match_dup 1)
(match_operand:TDI 2 "register_operand" "0")
(match_operand:TDI 3 "register_operand" "r")]
UNSPECV_CAS))
- (set (reg:CCZ1 CC_REGNUM)
- (compare:CCZ1 (match_dup 1) (match_dup 2)))]
- "TARGET_ZARCH"
+ (set (reg CC_REGNUM)
+ (compare (match_dup 1) (match_dup 2)))]
+ "TARGET_ZARCH
+ && s390_match_ccmode (insn, CCZ1mode)"
"c<td>sg\t%0,%3,%S1"
[(set_attr "op_type" "RSY")
(set_attr "type" "sem")])
; cds, cdsy
(define_insn "*atomic_compare_and_swapdi_2"
[(set (match_operand:DI 0 "register_operand" "=r,r")
- (match_operand:DI 1 "memory_operand" "+Q,S"))
+ (match_operand:DI 1 "nonsym_memory_operand" "+Q,S"))
(set (match_dup 1)
(unspec_volatile:DI
[(match_dup 1)
(match_operand:DI 2 "register_operand" "0,0")
(match_operand:DI 3 "register_operand" "r,r")]
UNSPECV_CAS))
- (set (reg:CCZ1 CC_REGNUM)
- (compare:CCZ1 (match_dup 1) (match_dup 2)))]
- "!TARGET_ZARCH"
+ (set (reg CC_REGNUM)
+ (compare (match_dup 1) (match_dup 2)))]
+ "!TARGET_ZARCH
+ && s390_match_ccmode (insn, CCZ1mode)"
"@
cds\t%0,%3,%S1
cdsy\t%0,%3,%S1"
[(set_attr "op_type" "RS,RSY")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "type" "sem")])
; cs, csy
(define_insn "*atomic_compare_and_swapsi_3"
[(set (match_operand:SI 0 "register_operand" "=r,r")
- (match_operand:SI 1 "memory_operand" "+Q,S"))
+ (match_operand:SI 1 "nonsym_memory_operand" "+Q,S"))
(set (match_dup 1)
(unspec_volatile:SI
[(match_dup 1)
(match_operand:SI 2 "register_operand" "0,0")
(match_operand:SI 3 "register_operand" "r,r")]
UNSPECV_CAS))
- (set (reg:CCZ1 CC_REGNUM)
- (compare:CCZ1 (match_dup 1) (match_dup 2)))]
- ""
+ (set (reg CC_REGNUM)
+ (compare (match_dup 1) (match_dup 2)))]
+ "s390_match_ccmode (insn, CCZ1mode)"
"@
cs\t%0,%3,%S1
csy\t%0,%3,%S1"
[(set_attr "op_type" "RS,RSY")
+ (set_attr "cpu_facility" "*,longdisp")
(set_attr "type" "sem")])
;
; lan, lang, lao, laog, lax, laxg, laa, laag
(define_insn "atomic_fetch_<atomic><mode>_iaf"
[(set (match_operand:GPR 0 "register_operand" "=d")
- (match_operand:GPR 1 "memory_operand" "+QS"))
+ (match_operand:GPR 1 "memory_operand" "+S"))
(set (match_dup 1)
(unspec_volatile:GPR
[(ATOMIC_Z196:GPR (match_dup 1)
DONE;
})
+;; Pattern to implement atomic_exchange with a compare-and-swap loop. The code
+;; generated by the middleend is not good.
(define_expand "atomic_exchange<mode>"
- [(match_operand:HQI 0 "register_operand") ;; val out
- (match_operand:HQI 1 "memory_operand") ;; memory
- (match_operand:HQI 2 "general_operand") ;; val in
+ [(match_operand:DINT 0 "register_operand") ;; val out
+ (match_operand:DINT 1 "s_operand") ;; memory
+ (match_operand:DINT 2 "general_operand") ;; val in
(match_operand:SI 3 "const_int_operand")] ;; model
""
{
- s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1],
- operands[2], false);
+ if (<MODE>mode != QImode
+ && MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (<MODE>mode))
+ FAIL;
+ if (<MODE>mode == HImode || <MODE>mode == QImode)
+ s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], operands[2],
+ false);
+ else if (<MODE>mode == SImode || TARGET_ZARCH)
+ s390_expand_atomic_exchange_tdsi (operands[0], operands[1], operands[2]);
+ else
+ FAIL;
DONE;
})
(define_insn "nop"
[(const_int 0)]
""
+ "nopr\t%%r0"
+ [(set_attr "op_type" "RR")])
+
+; non-branch NOPs required for optimizing compare-and-branch patterns
+; on z10
+
+(define_insn "nop_lr0"
+ [(unspec_volatile [(const_int 0)] UNSPECV_NOP_LR_0)]
+ ""
"lr\t0,0"
[(set_attr "op_type" "RR")
(set_attr "z10prop" "z10_fr_E1")])
-(define_insn "nop1"
- [(const_int 1)]
+(define_insn "nop_lr1"
+ [(unspec_volatile [(const_int 0)] UNSPECV_NOP_LR_1)]
""
"lr\t1,1"
[(set_attr "op_type" "RR")])
(define_insn "nop_2_byte"
[(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)]
""
- "nopr\t%%r7"
+ "nopr\t%%r0"
[(set_attr "op_type" "RR")])
(define_insn "nop_4_byte"
(define_insn "nop_6_byte"
[(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)]
- "TARGET_CPU_ZARCH"
+ ""
"brcl\t0, 0"
- [(set_attr "op_type" "RIL")])
+ [(set_attr "op_type" "RIL")
+ (set_attr "relative_long" "yes")])
;
(define_insn "pool_section_start"
[(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
""
- ".section\t.rodata"
+{
+ switch_to_section (targetm.asm_out.function_rodata_section
+ (current_function_decl));
+ return "";
+}
[(set_attr "length" "0")])
(define_insn "pool_section_end"
[(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
""
- ".previous"
+{
+ switch_to_section (current_function_section ());
+ return "";
+}
[(set_attr "length" "0")])
-(define_insn "main_base_31_small"
- [(set (match_operand 0 "register_operand" "=a")
- (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
- "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
- "basr\t%0,0"
- [(set_attr "op_type" "RR")
- (set_attr "type" "la")
- (set_attr "z196prop" "z196_cracked")])
-
-(define_insn "main_base_31_large"
- [(set (match_operand 0 "register_operand" "=a")
- (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
- (set (pc) (label_ref (match_operand 2 "" "")))]
- "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
- "bras\t%0,%2"
- [(set_attr "op_type" "RI")
- (set_attr "z196prop" "z196_cracked")])
-
(define_insn "main_base_64"
[(set (match_operand 0 "register_operand" "=a")
(unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
- "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
+ "GET_MODE (operands[0]) == Pmode"
"larl\t%0,%1"
[(set_attr "op_type" "RIL")
(set_attr "type" "larl")
- (set_attr "z10prop" "z10_fwd_A1")])
+ (set_attr "z10prop" "z10_fwd_A1")
+ (set_attr "relative_long" "yes")])
(define_insn "main_pool"
[(set (match_operand 0 "register_operand" "=a")
gcc_unreachable ();
}
[(set (attr "type")
- (if_then_else (match_test "TARGET_CPU_ZARCH")
- (const_string "larl") (const_string "la")))])
-
-(define_insn "reload_base_31"
- [(set (match_operand 0 "register_operand" "=a")
- (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
- "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
- "basr\t%0,0\;la\t%0,%1-.(%0)"
- [(set_attr "length" "6")
- (set_attr "type" "la")
- (set_attr "z196prop" "z196_cracked")])
+ (const_string "larl"))])
(define_insn "reload_base_64"
[(set (match_operand 0 "register_operand" "=a")
(unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
- "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
+ "GET_MODE (operands[0]) == Pmode"
"larl\t%0,%1"
[(set_attr "op_type" "RIL")
(set_attr "type" "larl")
(define_insn "<code>"
[(ANY_RETURN)]
"s390_can_use_<code>_insn ()"
- "br\t%%r14"
- [(set_attr "op_type" "RR")
+{
+ if (TARGET_INDIRECT_BRANCH_NOBP_RET)
+ {
+ /* The target is always r14 so there is no clobber
+ of r1 needed for pre z10 targets. */
+ s390_indirect_branch_via_thunk (RETURN_REGNUM,
+ INVALID_REGNUM,
+ NULL_RTX,
+ s390_indirect_branch_type_return);
+ return "";
+ }
+ else
+ return "br\t%%r14";
+}
+ [(set (attr "op_type")
+ (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET")
+ (const_string "RIL")
+ (const_string "RR")))
+ (set (attr "mnemonic")
+ (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET")
+ (const_string "jg")
+ (const_string "br")))
(set_attr "type" "jsr")
(set_attr "atype" "agen")])
-(define_insn "*return"
+
+(define_expand "return_use"
+ [(parallel
+ [(return)
+ (use (match_operand 0 "register_operand" "a"))])]
+ ""
+{
+ if (!TARGET_CPU_Z10
+ && TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION)
+ {
+ if (TARGET_64BIT)
+ emit_jump_insn (gen_returndi_prez10 (operands[0]));
+ else
+ emit_jump_insn (gen_returnsi_prez10 (operands[0]));
+ DONE;
+ }
+})
+
+(define_insn "*return<mode>"
[(return)
- (use (match_operand 0 "register_operand" "a"))]
- "GET_MODE (operands[0]) == Pmode"
- "br\t%0"
- [(set_attr "op_type" "RR")
+ (use (match_operand:P 0 "register_operand" "a"))]
+ "TARGET_CPU_Z10 || !TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION"
+{
+ if (TARGET_INDIRECT_BRANCH_NOBP_RET)
+ {
+ s390_indirect_branch_via_thunk (REGNO (operands[0]),
+ INVALID_REGNUM,
+ NULL_RTX,
+ s390_indirect_branch_type_return);
+ return "";
+ }
+ else
+ return "br\t%0";
+}
+ [(set (attr "op_type")
+ (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET")
+ (const_string "RIL")
+ (const_string "RR")))
+ (set (attr "mnemonic")
+ (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET")
+ (const_string "jg")
+ (const_string "br")))
+ (set_attr "type" "jsr")
+ (set_attr "atype" "agen")])
+
+(define_insn "return<mode>_prez10"
+ [(return)
+ (use (match_operand:P 0 "register_operand" "a"))
+ (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))]
+ "!TARGET_CPU_Z10 && TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION"
+{
+ if (TARGET_INDIRECT_BRANCH_NOBP_RET)
+ {
+ s390_indirect_branch_via_thunk (REGNO (operands[0]),
+ INVALID_REGNUM,
+ NULL_RTX,
+ s390_indirect_branch_type_return);
+ return "";
+ }
+ else
+ return "br\t%0";
+}
+ [(set (attr "op_type")
+ (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET")
+ (const_string "RIL")
+ (const_string "RR")))
+ (set (attr "mnemonic")
+ (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET")
+ (const_string "jg")
+ (const_string "br")))
(set_attr "type" "jsr")
(set_attr "atype" "agen")])
[(set_attr "length" "0")])
+(define_insn "stack_restore_from_fpr"
+ [(set (reg:DI STACK_REGNUM)
+ (match_operand:DI 0 "register_operand" "f"))
+ (clobber (mem:BLK (scratch)))]
+ "TARGET_Z10"
+ "lgdr\t%%r15,%0"
+ [(set_attr "op_type" "RRE")])
+
;
; Data prefetch patterns
;
(define_insn "prefetch"
- [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X")
- (match_operand:SI 1 "const_int_operand" " n,n")
- (match_operand:SI 2 "const_int_operand" " n,n"))]
+ [(prefetch (match_operand 0 "address_operand" "ZT,X")
+ (match_operand:SI 1 "const_int_operand" " n,n")
+ (match_operand:SI 2 "const_int_operand" " n,n"))]
"TARGET_Z10"
{
switch (which_alternative)
case 1:
if (larl_operand (operands[0], Pmode))
return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0";
+ /* fallthrough */
default:
/* This might be reached for symbolic operands with an odd
[(set_attr "type" "load,larl")
(set_attr "op_type" "RXY,RIL")
(set_attr "z10prop" "z10_super")
- (set_attr "z196prop" "z196_alone")])
+ (set_attr "z196prop" "z196_alone")
+ (set_attr "relative_long" "yes")])
;
; Byte swap instructions
;
+; FIXME: There is also mvcin but we cannot use it since src and target
+; may overlap.
+; lrvr, lrv, strv, lrvgr, lrvg, strvg
(define_insn "bswap<mode>2"
- [(set (match_operand:GPR 0 "register_operand" "=d, d")
- (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))]
- "TARGET_CPU_ZARCH"
+ [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,T")
+ (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,T,d")))]
+ ""
"@
lrv<g>r\t%0,%1
- lrv<g>\t%0,%1"
- [(set_attr "type" "*,load")
- (set_attr "op_type" "RRE,RXY")
+ lrv<g>\t%0,%1
+ strv<g>\t%1,%0"
+ [(set_attr "type" "*,load,store")
+ (set_attr "op_type" "RRE,RXY,RXY")
+ (set_attr "z10prop" "z10_super")])
+
+(define_insn "bswaphi2"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,T")
+ (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,T,d")))]
+ ""
+ "@
+ #
+ lrvh\t%0,%1
+ strvh\t%1,%0"
+ [(set_attr "type" "*,load,store")
+ (set_attr "op_type" "RRE,RXY,RXY")
(set_attr "z10prop" "z10_super")])
+(define_split
+ [(set (match_operand:HI 0 "register_operand" "")
+ (bswap:HI (match_operand:HI 1 "register_operand" "")))]
+ ""
+ [(set (match_dup 2) (bswap:SI (match_dup 3)))
+ (set (match_dup 2) (lshiftrt:SI (match_dup 2) (const_int 16)))]
+{
+ operands[2] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
+ operands[3] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
+})
+
;
; Population count instruction
; Transaction abort
(define_expand "tabort"
- [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "")]
+ [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "")]
UNSPECV_TABORT)]
"TARGET_HTM && operands != NULL"
{
if (CONST_INT_P (operands[0])
&& INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255)
{
- error ("Invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC
- ". Values in range 0 through 255 are reserved.",
- INTVAL (operands[0]));
+ error ("invalid transaction abort code: %wd; values in range 0 "
+ "through 255 are reserved", INTVAL (operands[0]));
FAIL;
}
})
(define_insn "*tabort_1"
- [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "Y")]
+ [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "aJ")]
UNSPECV_TABORT)]
"TARGET_HTM && operands != NULL"
"tabort\t%Y0"
[(set_attr "op_type" "S")])
+(define_insn "*tabort_1_plus"
+ [(unspec_volatile [(plus:SI (match_operand:SI 0 "register_operand" "a")
+ (match_operand:SI 1 "const_int_operand" "J"))]
+ UNSPECV_TABORT)]
+ "TARGET_HTM && operands != NULL
+ && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'J', \"J\")"
+ "tabort\t%1(%0)"
+ [(set_attr "op_type" "S")])
+
; Transaction extract nesting depth
(define_insn "etnd"
; Non-transactional store
(define_insn "ntstg"
- [(set (match_operand:DI 0 "memory_operand" "=RT")
+ [(set (match_operand:DI 0 "memory_operand" "=T")
(unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")]
UNSPECV_NTSTG))]
"TARGET_HTM"
(define_expand "tx_assist"
[(unspec_volatile [(match_operand:SI 0 "register_operand" "")
(reg:SI GPR0_REGNUM)
- (const_int 1)]
+ (const_int PPA_TX_ABORT)]
UNSPECV_PPA)]
"TARGET_HTM"
"")
(match_operand:SI 1 "register_operand" "d")
(match_operand 2 "const_int_operand" "I")]
UNSPECV_PPA)]
- "TARGET_HTM && INTVAL (operands[2]) < 16"
+ "(TARGET_ZEC12 || TARGET_HTM) && INTVAL (operands[2]) < 16"
"ppa\t%0,%1,%2"
[(set_attr "op_type" "RRF")])
(define_insn "lcbb"
[(set (match_operand:SI 0 "register_operand" "=d")
- (unspec:SI [(match_operand:SI 1 "address_operand" "ZQZR")
+ (unspec:SI [(match_operand 1 "address_operand" "ZR")
(match_operand:SI 2 "immediate_operand" "C")] UNSPEC_LCBB))
(clobber (reg:CC CC_REGNUM))]
"TARGET_Z13"
- "lcbb\t%0,%1,%b2"
+ "lcbb\t%0,%a1,%b2"
[(set_attr "op_type" "VRX")])
+
+; Handle -fsplit-stack.
+
+(define_expand "split_stack_prologue"
+ [(const_int 0)]
+ ""
+{
+ s390_expand_split_stack_prologue ();
+ DONE;
+})
+
+;; If there are operand 0 bytes available on the stack, jump to
+;; operand 1.
+
+(define_expand "split_stack_space_check"
+ [(set (pc) (if_then_else
+ (ltu (minus (reg 15)
+ (match_operand 0 "register_operand"))
+ (unspec [(const_int 0)] UNSPEC_STACK_CHECK))
+ (label_ref (match_operand 1))
+ (pc)))]
+ ""
+{
+ /* Offset from thread pointer to __private_ss. */
+ int psso = TARGET_64BIT ? 0x38 : 0x20;
+ rtx tp = s390_get_thread_pointer ();
+ rtx guard = gen_rtx_MEM (Pmode, plus_constant (Pmode, tp, psso));
+ rtx reg = gen_reg_rtx (Pmode);
+ rtx cc;
+ if (TARGET_64BIT)
+ emit_insn (gen_subdi3 (reg, stack_pointer_rtx, operands[0]));
+ else
+ emit_insn (gen_subsi3 (reg, stack_pointer_rtx, operands[0]));
+ cc = s390_emit_compare (GT, reg, guard);
+ s390_emit_jump (operands[1], cc);
+
+ DONE;
+})
+
+;; __morestack parameter block for split stack prologue. Parameters are:
+;; parameter block label, label to be called by __morestack, frame size,
+;; stack parameter size.
+
+(define_insn "split_stack_data"
+ [(unspec_volatile [(match_operand 0 "" "X")
+ (match_operand 1 "" "X")
+ (match_operand 2 "const_int_operand" "X")
+ (match_operand 3 "const_int_operand" "X")]
+ UNSPECV_SPLIT_STACK_DATA)]
+ ""
+{
+ switch_to_section (targetm.asm_out.function_rodata_section
+ (current_function_decl));
+
+ if (TARGET_64BIT)
+ output_asm_insn (".align\t8", operands);
+ else
+ output_asm_insn (".align\t4", operands);
+ (*targetm.asm_out.internal_label) (asm_out_file, "L",
+ CODE_LABEL_NUMBER (operands[0]));
+ if (TARGET_64BIT)
+ {
+ output_asm_insn (".quad\t%2", operands);
+ output_asm_insn (".quad\t%3", operands);
+ output_asm_insn (".quad\t%1-%0", operands);
+ }
+ else
+ {
+ output_asm_insn (".long\t%2", operands);
+ output_asm_insn (".long\t%3", operands);
+ output_asm_insn (".long\t%1-%0", operands);
+ }
+
+ switch_to_section (current_function_section ());
+ return "";
+}
+ [(set_attr "length" "0")])
+
+
+;; A jg with minimal fuss for use in split stack prologue.
+
+(define_expand "split_stack_call"
+ [(match_operand 0 "bras_sym_operand" "X")
+ (match_operand 1 "" "")]
+ ""
+{
+ if (TARGET_64BIT)
+ emit_jump_insn (gen_split_stack_call_di (operands[0], operands[1]));
+ else
+ emit_jump_insn (gen_split_stack_call_si (operands[0], operands[1]));
+ DONE;
+})
+
+(define_insn "split_stack_call_<mode>"
+ [(set (pc) (label_ref (match_operand 1 "" "")))
+ (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X")
+ (reg:P 1)]
+ UNSPECV_SPLIT_STACK_CALL))]
+ ""
+ "jg\t%0"
+ [(set_attr "op_type" "RIL")
+ (set_attr "type" "branch")])
+
+;; Also a conditional one.
+
+(define_expand "split_stack_cond_call"
+ [(match_operand 0 "bras_sym_operand" "X")
+ (match_operand 1 "" "")
+ (match_operand 2 "" "")]
+ ""
+{
+ if (TARGET_64BIT)
+ emit_jump_insn (gen_split_stack_cond_call_di (operands[0], operands[1], operands[2]));
+ else
+ emit_jump_insn (gen_split_stack_cond_call_si (operands[0], operands[1], operands[2]));
+ DONE;
+})
+
+(define_insn "split_stack_cond_call_<mode>"
+ [(set (pc)
+ (if_then_else
+ (match_operand 1 "" "")
+ (label_ref (match_operand 2 "" ""))
+ (pc)))
+ (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X")
+ (reg:P 1)]
+ UNSPECV_SPLIT_STACK_CALL))]
+ ""
+ "jg%C1\t%0"
+ [(set_attr "op_type" "RIL")
+ (set_attr "type" "branch")])
+
+(define_insn "osc_break"
+ [(unspec_volatile [(const_int 0)] UNSPECV_OSC_BREAK)]
+ ""
+ "bcr\t7,%%r0"
+ [(set_attr "op_type" "RR")])
+
+(define_expand "speculation_barrier"
+ [(unspec_volatile [(reg:SI GPR0_REGNUM)
+ (reg:SI GPR0_REGNUM)
+ (const_int PPA_OOO_BARRIER)]
+ UNSPECV_PPA)]
+ "TARGET_ZEC12"
+ "")