/* ??? No longer true. */
extern int code_for_indirect_jump_scratch;
-/* Generate SDB debugging information. */
-
-#define SDB_DEBUGGING_INFO
-
-/* Output DBX (stabs) debugging information if doing -gstabs. */
-
-#include "dbxcoff.h"
-
-#define SDB_DELIM ";"
-
-#define CPP_SPEC " \
-%{m5-64media|m5-64media-nofpu|m5-32media|m5-32media-nofpu:-D__SHMEDIA__=1} \
-%{m5-compact|m5-compact-nofpu:-D__SHMEDIA__=0} \
-%{m5-64media|m5-64media-nofpu:-D__SH5__=64 -D__LONG_MAX__=9223372036854775807L} \
-%{m5-32media|m5-32media-nofpu|m5-compact|m5-compact-nofpu:-D__SH5__=32} \
-%{m5-64media-nofpu|m5-32media-nofpu|m5-compact-nofpu:-D__SH4_NOFPU__} \
-%{m1:-D__sh1__} \
-%{m2:-D__sh2__} \
-%{m3:-D__sh3__} \
-%{m3e:-D__SH3E__} \
-%{m4-single-only:-D__SH4_SINGLE_ONLY__} \
-%{m4-single:-D__SH4_SINGLE__} \
-%{m4-nofpu:-D__sh3__ -D__SH4_NOFPU__} \
-%{m4:-D__SH4__} \
-%{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(cpp_default_cpu_spec)}}}}} \
-%{mhitachi:-D__HITACHI__} \
-%(subtarget_cpp_spec) \
-%(subtarget_cpp_endian_spec) "
-
-#ifndef SUBTARGET_CPP_ENDIAN_SPEC
-#define SUBTARGET_CPP_ENDIAN_SPEC "%{ml:-D__LITTLE_ENDIAN__}"
-#endif
-
-#ifndef SUBTARGET_CPP_SPEC
-#define SUBTARGET_CPP_SPEC ""
-#endif
-
-#ifndef CPP_DEFAULT_CPU_SPEC
-#define CPP_DEFAULT_CPU_SPEC "-D__sh1__"
-#endif
-
-
-#define EXTRA_SPECS \
- { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
- { "subtarget_cpp_endian_spec", SUBTARGET_CPP_ENDIAN_SPEC }, \
- { "cpp_default_cpu_spec", CPP_DEFAULT_CPU_SPEC }, \
- { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC },
-
-#define CPP_PREDEFINES "-D__sh__ -Acpu=sh -Amachine=sh"
-
-#define ASM_SPEC "%(subtarget_asm_endian_spec) %{mrelax:-relax}"
-
-#ifndef SUBTARGET_ASM_ENDIAN_SPEC
-#define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little}"
-#endif
-
-#define LINK_SPEC "%{ml:-m shl} %{mrelax:-relax}"
+#define TARGET_CPU_CPP_BUILTINS() \
+do { \
+ builtin_define ("__sh__"); \
+ builtin_assert ("cpu=sh"); \
+ builtin_assert ("machine=sh"); \
+ switch ((int) sh_cpu) \
+ { \
+ case PROCESSOR_SH1: \
+ builtin_define ("__sh1__"); \
+ break; \
+ case PROCESSOR_SH2: \
+ builtin_define ("__sh2__"); \
+ break; \
+ case PROCESSOR_SH3: \
+ builtin_define ("__sh3__"); \
+ builtin_define ("__SH3__"); \
+ if (TARGET_HARD_SH4) \
+ builtin_define ("__SH4_NOFPU__"); \
+ break; \
+ case PROCESSOR_SH3E: \
+ builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
+ break; \
+ case PROCESSOR_SH4: \
+ builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
+ break; \
+ case PROCESSOR_SH5: \
+ { \
+ builtin_define_with_value ("__SH5__", \
+ TARGET_SHMEDIA64 ? "64" : "32", 0); \
+ builtin_define_with_value ("__SHMEDIA__", \
+ TARGET_SHMEDIA ? "1" : "0", 0); \
+ if (! TARGET_FPU_DOUBLE) \
+ builtin_define ("__SH4_NOFPU__"); \
+ } \
+ } \
+ if (TARGET_HITACHI) \
+ builtin_define ("__HITACHI__"); \
+ builtin_define (TARGET_LITTLE_ENDIAN \
+ ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
+ if (flag_pic) \
+ { \
+ builtin_define ("__pic__"); \
+ builtin_define ("__PIC__"); \
+ } \
+ TARGET_OBJFMT_CPP_BUILTINS (); \
+} while (0)
/* We can not debug without a frame pointer. */
/* #define CAN_DEBUG_WITHOUT_FP */
/* Nonzero if we should prefer @GOT calls when generating PIC. */
#define TARGET_PREFERGOT (target_flags & PREFERGOT_BIT)
+#define SELECT_SH1 (SH1_BIT)
+#define SELECT_SH2 (SH2_BIT | SELECT_SH1)
+#define SELECT_SH3 (SH3_BIT | SELECT_SH2)
+#define SELECT_SH3E (SH3E_BIT | FPU_SINGLE_BIT | SELECT_SH3)
+#define SELECT_SH4_NOFPU (HARD_SH4_BIT | SELECT_SH3)
+#define SELECT_SH4_SINGLE_ONLY (HARD_SH4_BIT | SELECT_SH3E)
+#define SELECT_SH4 (SH4_BIT|SH3E_BIT|HARD_SH4_BIT | SELECT_SH3)
+#define SELECT_SH4_SINGLE (FPU_SINGLE_BIT | SELECT_SH4)
+#define SELECT_SH5_64 (SH5_BIT | SH4_BIT)
+#define SELECT_SH5_64_NOFPU (SH5_BIT)
+#define SELECT_SH5_32 (SH5_BIT | SH4_BIT | SH3E_BIT)
+#define SELECT_SH5_32_NOFPU (SH5_BIT | SH3E_BIT)
+#define SELECT_SH5_COMPACT (SH5_BIT | SH4_BIT | SELECT_SH3E)
+#define SELECT_SH5_COMPACT_NOFPU (SH5_BIT | SELECT_SH3)
+
/* Reset all target-selection flags. */
#define TARGET_NONE -(SH1_BIT | SH2_BIT | SH3_BIT | SH3E_BIT | SH4_BIT \
| HARD_SH4_BIT | FPU_SINGLE_BIT | SH5_BIT)
#define TARGET_SWITCHES \
{ {"1", TARGET_NONE, "" }, \
- {"1", SH1_BIT, "" }, \
+ {"1", SELECT_SH1, "" }, \
{"2", TARGET_NONE, "" }, \
- {"2", SH2_BIT|SH1_BIT, "" }, \
+ {"2", SELECT_SH2, "" }, \
{"3", TARGET_NONE, "" }, \
- {"3", SH3_BIT|SH2_BIT|SH1_BIT, "" }, \
+ {"3", SELECT_SH3, "" }, \
{"3e", TARGET_NONE, "" }, \
- {"3e", SH3E_BIT|SH3_BIT|SH2_BIT|SH1_BIT|FPU_SINGLE_BIT, "" }, \
+ {"3e", SELECT_SH3E, "" }, \
{"4-single-only", TARGET_NONE, "" }, \
- {"4-single-only", SH3E_BIT|SH3_BIT|SH2_BIT|SH1_BIT|HARD_SH4_BIT|FPU_SINGLE_BIT, "" }, \
+ {"4-single-only", SELECT_SH4_SINGLE_ONLY, "" }, \
{"4-single", TARGET_NONE, "" }, \
- {"4-single", SH4_BIT|SH3E_BIT|SH3_BIT|SH2_BIT|SH1_BIT|HARD_SH4_BIT|FPU_SINGLE_BIT, "" },\
+ {"4-single", SELECT_SH4_SINGLE, "" },\
{"4-nofpu", TARGET_NONE, "" }, \
- {"4-nofpu", SH3_BIT|SH2_BIT|SH1_BIT|HARD_SH4_BIT, "" },\
+ {"4-nofpu", SELECT_SH4_NOFPU, "" },\
{"4", TARGET_NONE, "" }, \
- {"4", SH4_BIT|SH3E_BIT|SH3_BIT|SH2_BIT|SH1_BIT|HARD_SH4_BIT, "" }, \
+ {"4", SELECT_SH4, "" }, \
{"5-64media", TARGET_NONE, "" }, \
- {"5-64media", SH5_BIT|SH4_BIT, "Generate 64-bit SHmedia code" }, \
+ {"5-64media", SELECT_SH5_64, "Generate 64-bit SHmedia code" }, \
{"5-64media-nofpu", TARGET_NONE, "" }, \
- {"5-64media-nofpu", SH5_BIT, "Generate 64-bit FPU-less SHmedia code" }, \
+ {"5-64media-nofpu", SELECT_SH5_64_NOFPU, "Generate 64-bit FPU-less SHmedia code" }, \
{"5-32media", TARGET_NONE, "" }, \
- {"5-32media", SH5_BIT|SH4_BIT|SH3E_BIT, "Generate 32-bit SHmedia code" }, \
+ {"5-32media", SELECT_SH5_32, "Generate 32-bit SHmedia code" }, \
{"5-32media-nofpu", TARGET_NONE, "" }, \
- {"5-32media-nofpu", SH5_BIT|SH3E_BIT, "Generate 32-bit FPU-less SHmedia code" }, \
+ {"5-32media-nofpu", SELECT_SH5_32_NOFPU, "Generate 32-bit FPU-less SHmedia code" }, \
{"5-compact", TARGET_NONE, "" }, \
- {"5-compact", SH5_BIT|SH4_BIT|SH3E_BIT|SH3_BIT|SH2_BIT|SH1_BIT|FPU_SINGLE_BIT, "Generate SHcompact code" }, \
+ {"5-compact", SELECT_SH5_COMPACT, "Generate SHcompact code" }, \
{"5-compact-nofpu", TARGET_NONE, "" }, \
- {"5-compact-nofpu", SH5_BIT|SH3_BIT|SH2_BIT|SH1_BIT, "Generate FPU-less SHcompact code" }, \
+ {"5-compact-nofpu", SELECT_SH5_COMPACT_NOFPU, "Generate FPU-less SHcompact code" }, \
{"b", -LITTLE_ENDIAN_BIT, "" }, \
{"bigtable", BIGTABLE_BIT, "" }, \
{"dalign", DALIGN_BIT, "" }, \
/* This are meant to be redefined in the host dependent files */
#define SUBTARGET_SWITCHES
-#define TARGET_DEFAULT (SH1_BIT)
+/* This defaults us to big-endian. */
+#ifndef TARGET_ENDIAN_DEFAULT
+#define TARGET_ENDIAN_DEFAULT 0
+#endif
+
+#ifndef TARGET_CPU_DEFAULT
+#define TARGET_CPU_DEFAULT SELECT_SH1
+#endif
+
+#define TARGET_DEFAULT (TARGET_CPU_DEFAULT|TARGET_ENDIAN_DEFAULT)
+
+#define CPP_SPEC " %(subtarget_cpp_spec) "
+
+#ifndef SUBTARGET_CPP_SPEC
+#define SUBTARGET_CPP_SPEC ""
+#endif
+
+#ifndef SUBTARGET_EXTRA_SPECS
+#define SUBTARGET_EXTRA_SPECS
+#endif
+
+#define EXTRA_SPECS \
+ { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
+ { "link_emul_prefix", LINK_EMUL_PREFIX }, \
+ { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
+ { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
+ { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
+ { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
+ SUBTARGET_EXTRA_SPECS
+
+#define ASM_SPEC "%(subtarget_asm_endian_spec) %{mrelax:-relax}"
+
+#ifndef SUBTARGET_ASM_ENDIAN_SPEC
+#if TARGET_ENDIAN_DEFAULT == LITTLE_ENDIAN_BIT
+#define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
+#else
+#define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
+#endif
+#endif
+
+#define LINK_EMUL_PREFIX "sh%{ml:l}"
+
+#if TARGET_CPU_DEFAULT & SH5_BIT
+#if TARGET_CPU_DEFAULT & SH3E_BIT
+#define LINK_DEFAULT_CPU_EMUL "32"
+#else
+#define LINK_DEFAULT_CPU_EMUL "64"
+#endif /* SH3E_BIT */
+#else
+#define LINK_DEFAULT_CPU_EMUL ""
+#endif /* SH5_BIT */
+
+#define SUBTARGET_LINK_EMUL_SUFFIX ""
+#define SUBTARGET_LINK_SPEC ""
+
+/* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
+ so that we can undo the damage without code replication. */
+#define LINK_SPEC SH_LINK_SPEC
+
+#define SH_LINK_SPEC "\
+-m %(link_emul_prefix)\
+%{m5-compact*|m5-32media*:32}\
+%{m5-64media*:64}\
+%{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
+%(subtarget_link_emul_suffix) \
+%{mrelax:-relax} %(subtarget_link_spec)"
#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
do { \
&& (ALIGN) < FASTEST_ALIGNMENT) \
? FASTEST_ALIGNMENT : (ALIGN))
-#ifndef MAX_OFILE_ALIGNMENT
-#define MAX_OFILE_ALIGNMENT 128
-#endif
-
/* Make arrays of chars word-aligned for the same reasons. */
#define DATA_ALIGNMENT(TYPE, ALIGN) \
(TREE_CODE (TYPE) == ARRAY_TYPE \
/* Value is 1 if MODE is a supported vector mode. */
#define VECTOR_MODE_SUPPORTED_P(MODE) \
- (TARGET_FPU_ANY \
- && ((MODE) == V2SFmode || (MODE) == V4SFmode || (MODE) == V16SFmode))
+ ((TARGET_FPU_ANY \
+ && ((MODE) == V2SFmode || (MODE) == V4SFmode || (MODE) == V16SFmode)) \
+ || (TARGET_SHMEDIA \
+ && ((MODE) == V8QImode || (MODE) == V2HImode || (MODE) == V4HImode \
+ || (MODE) == V2SImode)))
/* Value is 1 if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
&& (GET_MODE_SIZE (MODE2) <= 4)) \
: ((MODE1) != SFmode && (MODE2) != SFmode))))
+/* A C expression that is nonzero if hard register NEW_REG can be
+ considered for use as a rename register for OLD_REG register */
+
+#define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
+ sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
+
/* Specify the registers used for certain standard purposes.
The values of these macros are register numbers. */
(CUM).arg_count[(int) SH_ARG_INT] += numregs; \
if (TARGET_SHCOMPACT \
&& SHCOMPACT_FORCE_ON_STACK (MODE_, TYPE_)) \
- (CUM).call_cookie \
- |= CALL_COOKIE_INT_REG (((CUM).arg_count[(int) SH_ARG_INT] \
- - numregs), 1); \
+ { \
+ (CUM).call_cookie \
+ |= CALL_COOKIE_INT_REG (((CUM).arg_count[(int) SH_ARG_INT] \
+ - numregs), 1); \
+ /* N.B. We want this also for outgoing. */\
+ (CUM).stack_regs += numregs; \
+ } \
else if ((CUM).byref) \
{ \
if (! (CUM).outgoing) \
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
((! TARGET_SH5 \
&& PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
- && ((NAMED) \
- || (! TARGET_HITACHI && (TARGET_SH3E || ! current_function_varargs)))) \
+ && ((NAMED) || !TARGET_HITACHI)) \
? gen_rtx_REG ((MODE), \
((BASE_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))) \
^ ((MODE) == SFmode && TARGET_SH4 \
later. Fortunately, we already have two flags that are part of struct
function that tell if a function uses varargs or stdarg. */
#define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) do \
- if (! current_function_varargs && ! current_function_stdarg) \
+ if (! current_function_stdarg) \
abort (); \
while (0)
(VALIST) = sh_build_va_list ()
/* Implement `va_start' for varargs and stdarg. */
-#define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
- sh_va_start (stdarg, valist, nextarg)
+#define EXPAND_BUILTIN_VA_START(valist, nextarg) \
+ sh_va_start (valist, nextarg)
/* Implement `va_arg'. */
#define EXPAND_BUILTIN_VA_ARG(valist, type) \
(((COUNT) == 0) \
? get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG) \
: (rtx) 0)
+
+/* A C expression whose value is RTL representing the location of the
+ incoming return address at the beginning of any function, before the
+ prologue. This RTL is either a REG, indicating that the return
+ value is saved in REG, or a MEM representing a location in
+ the stack. */
+#define INCOMING_RETURN_ADDR_RTX \
+ gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
\f
/* Generate necessary RTL for __builtin_saveregs(). */
#define EXPAND_BUILTIN_SAVEREGS() sh_builtin_saveregs ()
#define EXTRA_CONSTRAINT_T(OP) \
(NON_PIC_REFERENCE_P (OP))
+/* A zero in any shape or form. */
+#define EXTRA_CONSTRAINT_U(OP) \
+ ((OP) == const0_rtx \
+ || (GET_CODE (OP) == SUBREG && VECTOR_MODE_SUPPORTED_P(GET_MODE (OP)) \
+ && SUBREG_REG (OP) == const0_rtx && SUBREG_BYTE (OP) == 0) \
+ || GET_CODE (OP) == CONST_VECTOR && zero_vec_operand ((OP), VOIDmode))
+
+/* Any vector constant we can handle. */
+#define EXTRA_CONSTRAINT_W(OP) \
+ (GET_CODE (OP) == CONST_VECTOR \
+ && (sh_rep_vec ((OP), VOIDmode) \
+ || (HOST_BITS_PER_WIDE_INT >= 64 \
+ ? sh_const_vec ((OP), VOIDmode) \
+ : sh_1el_vec ((OP), VOIDmode))))
+
#define EXTRA_CONSTRAINT(OP, C) \
((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
: (C) == 'S' ? EXTRA_CONSTRAINT_S (OP) \
: (C) == 'T' ? EXTRA_CONSTRAINT_T (OP) \
+ : (C) == 'U' ? EXTRA_CONSTRAINT_U (OP) \
+ : (C) == 'W' ? EXTRA_CONSTRAINT_W (OP) \
: 0)
\f
/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
case CONST_INT: \
if (TARGET_SHMEDIA) \
{ \
+ if (INTVAL (RTX) == 0) \
+ return 0; \
+ if ((OUTER_CODE) == AND && and_operand ((RTX), DImode)) \
+ return 0; \
+ if (((OUTER_CODE) == IOR || (OUTER_CODE) == XOR \
+ || (OUTER_CODE) == PLUS) \
+ && CONST_OK_FOR_P (INTVAL (RTX))) \
+ return 0; \
if (CONST_OK_FOR_J (INTVAL (RTX))) \
- return COSTS_N_INSNS (1); \
+ return COSTS_N_INSNS ((OUTER_CODE) != SET); \
else if (CONST_OK_FOR_J (INTVAL (RTX) >> 16)) \
return COSTS_N_INSNS (2); \
else if (CONST_OK_FOR_J ((INTVAL (RTX) >> 16) >> 16)) \
nor can we indirect via the constant pool. */
#define LEGITIMATE_PIC_OPERAND_P(X) \
(! nonpic_symbol_mentioned_p (X) \
- && (! CONSTANT_POOL_ADDRESS_P (X) \
+ && (GET_CODE (X) != SYMBOL_REF \
+ || ! CONSTANT_POOL_ADDRESS_P (X) \
|| ! nonpic_symbol_mentioned_p (get_pool_constant (X))))
#define SYMBOLIC_CONST_P(X) \
#define ASM_FILE_START(STREAM) \
output_file_start (STREAM)
-#define ASM_FILE_END(STREAM)
-
#define ASM_APP_ON ""
#define ASM_APP_OFF ""
#define FILE_ASM_OP "\t.file\n"
-#define IDENT_ASM_OP "\t.ident\t"
#define SET_ASM_OP "\t.set\t"
/* How to change between sections. */
which could be text or it could be a user defined section. */
#define JUMP_TABLES_IN_TEXT_SECTION 1
-/* Switch into a generic section. */
-#define TARGET_ASM_NAMED_SECTION sh_asm_named_section
-
#undef DO_GLOBAL_CTORS_BODY
#define DO_GLOBAL_CTORS_BODY \
{ \
if ((LOG) != 0) \
fprintf ((FILE), "\t.align %d\n", (LOG))
-/* Output a function label definition. */
-#define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
- ASM_OUTPUT_LABEL((STREAM), (NAME))
-
/* Output a globalising directive for a label. */
#define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
(fprintf ((STREAM), "\t.global\t"), \
assemble_name ((STREAM), (NAME)), \
fputc ('\n', (STREAM)))
-/* The prefix to add to user-visible assembler symbols. */
-
-#define USER_LABEL_PREFIX "_"
-
-/* The prefix to add to an internally generated label. */
-
-#define LOCAL_LABEL_PREFIX ""
-
-/* Make an internal label into a string. */
-#define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
- sprintf ((STRING), "*%s%s%ld", LOCAL_LABEL_PREFIX, (PREFIX), (long)(NUM))
-
-/* Output an internal label definition. */
-#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
- asm_fprintf ((FILE), "%L%s%d:\n", (PREFIX), (NUM))
-
/* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
/* Construct a private name. */
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
if (TARGET_BIGTABLE) \
- asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
+ asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
else \
- asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE)); \
+ asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
-/* Output various types of constants. */
-
-/* Loop alignment is now done in machine_dependent_reorg, so that
- branch shortening can know about it. */
-
-/* This is how to output an assembler line
- that says to advance the location counter by SIZE bytes. */
-
-#define ASM_OUTPUT_SKIP(FILE,SIZE) \
- fprintf ((FILE), "\t.space %d\n", (SIZE))
-
-/* This says how to output an assembler line
- to define a global common symbol. */
-
-#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
-( fputs ("\t.comm ", (FILE)), \
- assemble_name ((FILE), (NAME)), \
- fprintf ((FILE), ",%d\n", (SIZE)))
-
-/* This says how to output an assembler line
- to define a local common symbol. */
-
-#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
-( fputs ("\t.lcomm ", (FILE)), \
- assemble_name ((FILE), (NAME)), \
- fprintf ((FILE), ",%d\n", (SIZE)))
\f
/* A C statement to be executed just prior to the output of
assembler code for INSN, to modify the extracted operands so
#define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
- || (CHAR) == '$')
+ || (CHAR) == '$'|| (CHAR) == '\'')
/* Recognize machine-specific patterns that may appear within
constants. Used for PIC-specific UNSPECs. */
extern struct rtx_def *sp_switch;
extern int rtx_equal_function_value_matters;
-extern struct rtx_def *fpscr_rtx;
\f
/* Instructions with unfilled delay slots take up an
\f
/* Define the codes that are matched by predicates in sh.c. */
#define PREDICATE_CODES \
+ {"and_operand", {SUBREG, REG, CONST_INT}}, \
{"arith_operand", {SUBREG, REG, CONST_INT}}, \
+ {"arith_reg_dest", {SUBREG, REG}}, \
{"arith_reg_operand", {SUBREG, REG}}, \
- {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
+ {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_VECTOR}}, \
{"binary_float_operator", {PLUS, MULT}}, \
{"commutative_float_operator", {PLUS, MULT}}, \
+ {"equality_comparison_operator", {EQ,NE}}, \
+ {"extend_reg_operand", {SUBREG, REG, TRUNCATE}}, \
+ {"extend_reg_or_0_operand", {SUBREG, REG, TRUNCATE, CONST_INT}}, \
{"fp_arith_reg_operand", {SUBREG, REG}}, \
{"fpscr_operand", {REG}}, \
{"fpul_operand", {REG}}, \
+ {"general_extend_operand", {SUBREG, REG, MEM, TRUNCATE}}, \
{"general_movsrc_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
{"general_movdst_operand", {SUBREG, REG, MEM}}, \
+ {"greater_comparison_operator", {GT,GE,GTU,GEU}}, \
+ {"inqhi_operand", {TRUNCATE}}, \
+ {"less_comparison_operator", {LT,LE,LTU,LEU}}, \
{"logical_operand", {SUBREG, REG, CONST_INT}}, \
+ {"mextr_bit_offset", {CONST_INT}}, \
{"noncommutative_float_operator", {MINUS, DIV}}, \
{"shmedia_6bit_operand", {SUBREG, REG, CONST_INT}}, \
{"target_reg_operand", {SUBREG, REG}}, \
- {"target_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF}}, \
+ {"target_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, CONST, UNSPEC}},\
{"register_operand", {SUBREG, REG}}, \
- {"symbol_ref_operand", {SYMBOL_REF}},
+ {"sh_const_vec", {CONST_VECTOR}}, \
+ {"sh_1el_vec", {CONST_VECTOR, PARALLEL}}, \
+ {"sh_rep_vec", {CONST_VECTOR, PARALLEL}}, \
+ {"symbol_ref_operand", {SYMBOL_REF}}, \
+ {"zero_vec_operand", {CONST_VECTOR}},
/* Define this macro if it is advisable to hold scalars in registers
in a wider mode than that declared by the program. In such cases,
#define OPTIMIZE_MODE_SWITCHING(ENTITY) TARGET_SH4
#define NORMAL_MODE(ENTITY) \
- (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
+ (sh_cfun_interrupt_handler_p () ? FP_MODE_NONE \
+ : TARGET_FPU_SINGLE ? FP_MODE_SINGLE \
+ : FP_MODE_DOUBLE)
#define EPILOGUE_USES(REGNO) ((TARGET_SH3E || TARGET_SH4) \
&& (REGNO) == FPSCR_REG)
#define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
sh_can_redirect_branch ((INSN), (SEQ))
+#define DWARF_FRAME_RETURN_COLUMN (TARGET_SH5 ? PR_MEDIA_REG : PR_REG)
+
#if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
/* SH constant pool breaks the devices in crtstuff.c to control section
in where code resides. We have to write it as asm code. */
projects / gcc.git / blobdiff