-@c Copyright (C) 2002-2016 Free Software Foundation, Inc.
+@c Copyright (C) 2002-2018 Free Software Foundation, Inc.
@c This is part of the GCC manual.
@c For copying conditions, see the file gcc.texi.
@table @file
@item boehm-gc
-The Boehm conservative garbage collector, used as part of the Java
-runtime library.
+The Boehm conservative garbage collector, optionally used as part of
+the ObjC runtime library when configured with @option{--enable-objc-gc}.
@item config
Autoconf macros and Makefile fragments used throughout the tree.
The Decimal Float support library.
@item libffi
-The @code{libffi} library, used as part of the Java runtime library.
+The @code{libffi} library, used as part of the Go runtime library.
@item libgcc
The GCC runtime library.
@item libitm
The runtime support library for transactional memory.
-@item libjava
-The Java runtime library.
-
@item libobjc
The Objective-C and Objective-C++ runtime library.
Scripts used by the @code{gccadmin} account on @code{gcc.gnu.org}.
@item zlib
-The @code{zlib} compression library, used by the Java front end, as
-part of the Java runtime library, and for compressing and uncompressing
-GCC's intermediate language in LTO object files.
+The @code{zlib} compression library, used for compressing and
+uncompressing GCC's intermediate language in LTO object files.
@end table
The build system in the top level directory, including how recursion
If defined, this variable lists (space-separated) language front ends
other than C that this front end requires to be enabled (with the
names given being their @code{language} settings). For example, the
-Java front end depends on the C++ front end, so sets
-@samp{lang_requires=c++}.
+Obj-C++ front end depends on the C++ and ObjC front ends, so sets
+@samp{lang_requires="objc c++"}.
@item subdir_requires
If defined, this variable lists (space-separated) front end directories
other than C that this front end requires to be present. For example,
chapter of this manual.
@end itemize
+The @file{@var{machine}.h} header is included very early in GCC's
+standard sequence of header files, while @file{@var{machine}-protos.h}
+is included late in the sequence. Thus @file{@var{machine}-protos.h}
+can include declarations referencing types that are not defined when
+@file{@var{machine}.h} is included, specifically including those from
+@file{rtl.h} and @file{tree.h}. Since both RTL and tree types may not
+be available in every context where @file{@var{machine}-protos.h} is
+included, in this file you should guard declarations using these types
+inside appropriate @code{#ifdef RTX_CODE} or @code{#ifdef TREE_CODE}
+conditional code segments.
+
+If the backend uses shared data structures that require @code{GTY} markers
+for garbage collection (@pxref{Type Information}), you must declare those
+in @file{@var{machine}.h} rather than @file{@var{machine}-protos.h}.
+Any definitions required for building libgcc must also go in
+@file{@var{machine}.h}.
+
+GCC uses the macro @code{IN_TARGET_CODE} to distinguish between
+machine-specific @file{.c} and @file{.cc} files and
+machine-independent @file{.c} and @file{.cc} files. Machine-specific
+files should use the directive:
+
+@example
+#define IN_TARGET_CODE 1
+@end example
+
+before including @code{config.h}.
+
If the back end is added to the official GCC source repository, the
following are also necessary:
* Test Directives:: Directives used within DejaGnu tests.
* Ada Tests:: The Ada language testsuites.
* C Tests:: The C language testsuites.
-* libgcj Tests:: The Java library testsuites.
* LTO Testing:: Support for testing link-time optimizations.
* gcov Testing:: Support for testing gcov.
* profopt Testing:: Support for testing profile-directed optimizations.
* compat Testing:: Support for testing binary compatibility.
* Torture Tests:: Support for torture testing using multiple options.
+* GIMPLE Tests:: Support for testing GIMPLE passes.
+* RTL Tests:: Support for testing RTL passes.
@end menu
@node Test Idioms
to indicate that the message is a known problem for a particular set of
targets.
+@item @{ dg-line @var{linenumvar} @}
+This DejaGnu directive sets the variable @var{linenumvar} to the line number of
+the source line. The variable @var{linenumvar} can then be used in subsequent
+@code{dg-error}, @code{dg-warning}, @code{dg-message} and @code{dg-bogus}
+directives. For example:
+
+@smallexample
+int a; /* @{ dg-line first_def_a @} */
+float a; /* @{ dg-error "conflicting types of" @} */
+/* @{ dg-message "previous declaration of" "" @{ target *-*-* @} first_def_a @} */
+@end smallexample
+
@item @{ dg-excess-errors @var{comment} [@{ target/xfail @var{selector} @}] @}
This DejaGnu directive indicates that the test is expected to fail due
to compiler messages that are not handled by @samp{dg-error},
@item 4byte_wchar_t
Target has @code{wchar_t} that is at least 4 bytes.
+
+@item float@var{n}
+Target has the @code{_Float@var{n}} type.
+
+@item float@var{n}x
+Target has the @code{_Float@var{n}x} type.
+
+@item float@var{n}_runtime
+Target has the @code{_Float@var{n}} type, including runtime support
+for any options added with @code{dg-add-options}.
+
+@item float@var{n}x_runtime
+Target has the @code{_Float@var{n}x} type, including runtime support
+for any options added with @code{dg-add-options}.
+
+@item floatn_nx_runtime
+Target has runtime support for any options added with
+@code{dg-add-options} for any @code{_Float@var{n}} or
+@code{_Float@var{n}x} type.
@end table
@subsubsection Fortran-specific attributes
@item fortran_integer_16
Target supports Fortran @code{integer} that is 16 bytes or longer.
+@item fortran_real_10
+Target supports Fortran @code{real} that is 10 bytes or longer.
+
+@item fortran_real_16
+Target supports Fortran @code{real} that is 16 bytes or longer.
+
@item fortran_large_int
Target supports Fortran @code{integer} kinds larger than @code{integer(8)}.
@subsubsection Vector-specific attributes
@table @code
+@item vect_align_stack_vars
+The target's ABI allows stack variables to be aligned to the preferred
+vector alignment.
+
@item vect_condition
Target supports vector conditional operations.
@item vect_double
Target supports hardware vectors of @code{double}.
+@item vect_element_align_preferred
+The target's preferred vector alignment is the same as the element
+alignment.
+
@item vect_float
-Target supports hardware vectors of @code{float}.
+Target supports hardware vectors of @code{float} when
+@option{-funsafe-math-optimizations} is in effect.
+
+@item vect_float_strict
+Target supports hardware vectors of @code{float} when
+@option{-funsafe-math-optimizations} is not in effect.
+This implies @code{vect_float}.
@item vect_int
Target supports hardware vectors of @code{int}.
@item vect_long_long
Target supports hardware vectors of @code{long long}.
+@item vect_fully_masked
+Target supports fully-masked (also known as fully-predicated) loops,
+so that vector loops can handle partial as well as full vectors.
+
+@item vect_masked_store
+Target supports vector masked stores.
+
+@item vect_scatter_store
+Target supports vector scatter stores.
+
@item vect_aligned_arrays
Target aligns arrays to vector alignment boundary.
@item vect_no_align
Target does not support a vector alignment mechanism.
+@item vect_peeling_profitable
+Target might require to peel loops for alignment purposes.
+
@item vect_no_int_min_max
Target does not support a vector min and max instruction on @code{int}.
@item vect_int_mult
Target supports @code{vector int} multiplication.
+@item vect_long_mult
+Target supports 64 bit @code{vector long} multiplication.
+
@item vect_extract_even_odd
Target supports vector even/odd element extraction.
@item vect_perm
Target supports vector permutation.
+@item vect_perm_byte
+Target supports permutation of vectors with 8-bit elements.
+
+@item vect_perm_short
+Target supports permutation of vectors with 16-bit elements.
+
+@item vect_perm3_byte
+Target supports permutation of vectors with 8-bit elements, and for the
+default vector length it is possible to permute:
+@example
+@{ a0, a1, a2, b0, b1, b2, @dots{} @}
+@end example
+to:
+@example
+@{ a0, a0, a0, b0, b0, b0, @dots{} @}
+@{ a1, a1, a1, b1, b1, b1, @dots{} @}
+@{ a2, a2, a2, b2, b2, b2, @dots{} @}
+@end example
+using only two-vector permutes, regardless of how long the sequence is.
+
+@item vect_perm3_int
+Like @code{vect_perm3_byte}, but for 32-bit elements.
+
+@item vect_perm3_short
+Like @code{vect_perm3_byte}, but for 16-bit elements.
+
@item vect_shift
Target supports a hardware vector shift operation.
+@item vect_unaligned_possible
+Target prefers vectors to have an alignment greater than element
+alignment, but also allows unaligned vector accesses in some
+circumstances.
+
+@item vect_variable_length
+Target has variable-length vectors.
+
@item vect_widen_sum_hi_to_si
Target supports a vector widening summation of @code{short} operands
into @code{int} results, or can promote (unpack) from @code{short}
@item vect_floatuint_cvt
Target supports conversion from @code{float} to @code{unsigned int}.
+@item vect_intdouble_cvt
+Target supports conversion from @code{signed int} to @code{double}.
+
+@item vect_doubleint_cvt
+Target supports conversion from @code{double} to @code{signed int}.
+
@item vect_max_reduc
Target supports max reduction for vectors.
+
+@item vect_sizes_16B_8B
+Target supports 16- and 8-bytes vectors.
+
+@item vect_sizes_32B_16B
+Target supports 32- and 16-bytes vectors.
+
+@item vect_logical_reduc
+Target supports AND, IOR and XOR reduction on vectors.
+
+@item vect_fold_extract_last
+Target supports the @code{fold_extract_last} optab.
@end table
@subsubsection Thread Local Storage attributes
variant of the ABI for the ARM Architecture (as selected with
@code{-mfloat-abi=hard}).
+@item arm_softfloat
+ARM target uses the soft-float ABI with no floating-point instructions
+used whatsoever (as selected with @code{-mfloat-abi=soft}).
+
@item arm_hard_vfp_ok
ARM target supports @code{-mfpu=vfp -mfloat-abi=hard}.
Some multilibs may be incompatible with these options.
ARM Target supports @code{-mfpu=neon -mfloat-abi=softfp} or compatible
options. Some multilibs may be incompatible with these options.
+@item arm_neon_ok_no_float_abi
+@anchor{arm_neon_ok_no_float_abi}
+ARM Target supports NEON with @code{-mfpu=neon}, but without any
+-mfloat-abi= option. Some multilibs may be incompatible with this
+option.
+
@item arm_neonv2_ok
@anchor{arm_neonv2_ok}
ARM Target supports @code{-mfpu=neon-vfpv4 -mfloat-abi=softfp} or compatible
Test system supports executing Neon half-precision float instructions.
(Implies previous.)
+@item arm_fp16_alternative_ok
+ARM target supports the ARM FP16 alternative format. Some multilibs
+may be incompatible with the options needed.
+
+@item arm_fp16_none_ok
+ARM target supports specifying none as the ARM FP16 format.
+
@item arm_thumb1_ok
ARM target generates Thumb-1 code for @code{-mthumb}.
Some multilibs may be incompatible with these options.
@item arm_v8_1a_neon_ok
-ARM target supports options to generate ARMv8.1 Adv.SIMD instructions.
+@anchor{arm_v8_1a_neon_ok}
+ARM target supports options to generate ARMv8.1-A Adv.SIMD instructions.
Some multilibs may be incompatible with these options.
@item arm_v8_1a_neon_hw
-ARM target supports executing ARMv8.1 Adv.SIMD instructions. Some
+ARM target supports executing ARMv8.1-A Adv.SIMD instructions. Some
multilibs may be incompatible with the options needed. Implies
arm_v8_1a_neon_ok.
@item arm_acq_rel
ARM target supports acquire-release instructions.
+@item arm_v8_2a_fp16_scalar_ok
+@anchor{arm_v8_2a_fp16_scalar_ok}
+ARM target supports options to generate instructions for ARMv8.2-A and
+scalar instructions from the FP16 extension. Some multilibs may be
+incompatible with these options.
+
+@item arm_v8_2a_fp16_scalar_hw
+ARM target supports executing instructions for ARMv8.2-A and scalar
+instructions from the FP16 extension. Some multilibs may be
+incompatible with these options. Implies arm_v8_2a_fp16_neon_ok.
+
+@item arm_v8_2a_fp16_neon_ok
+@anchor{arm_v8_2a_fp16_neon_ok}
+ARM target supports options to generate instructions from ARMv8.2-A with
+the FP16 extension. Some multilibs may be incompatible with these
+options. Implies arm_v8_2a_fp16_scalar_ok.
+
+@item arm_v8_2a_fp16_neon_hw
+ARM target supports executing instructions from ARMv8.2-A with the FP16
+extension. Some multilibs may be incompatible with these options.
+Implies arm_v8_2a_fp16_neon_ok and arm_v8_2a_fp16_scalar_hw.
+
+@item arm_v8_2a_dotprod_neon_ok
+@anchor{arm_v8_2a_dotprod_neon_ok}
+ARM target supports options to generate instructions from ARMv8.2-A with
+the Dot Product extension. Some multilibs may be incompatible with these
+options.
+
+@item arm_v8_2a_dotprod_neon_hw
+ARM target supports executing instructions from ARMv8.2-A with the Dot
+Product extension. Some multilibs may be incompatible with these options.
+Implies arm_v8_2a_dotprod_neon_ok.
+
+@item arm_fp16fml_neon_ok
+@anchor{arm_fp16fml_neon_ok}
+ARM target supports extensions to generate the @code{VFMAL} and @code{VFMLS}
+half-precision floating-point instructions available from ARMv8.2-A and
+onwards. Some multilibs may be incompatible with these options.
+
@item arm_prefer_ldrd_strd
ARM target prefers @code{LDRD} and @code{STRD} instructions over
@code{LDM} and @code{STM} instructions.
ARM target generates Thumb-1 code for @code{-mthumb} with
@code{CBZ} and @code{CBNZ} instructions available.
+@item arm_divmod_simode
+ARM target for which divmod transform is disabled, if it supports hardware
+div instruction.
+
+@item arm_cmse_ok
+ARM target supports ARMv8-M Security Extensions, enabled by the @code{-mcmse}
+option.
+
+@item arm_coproc1_ok
+@anchor{arm_coproc1_ok}
+ARM target supports the following coprocessor instructions: @code{CDP},
+@code{LDC}, @code{STC}, @code{MCR} and @code{MRC}.
+
+@item arm_coproc2_ok
+@anchor{arm_coproc2_ok}
+ARM target supports all the coprocessor instructions also listed as supported
+in @ref{arm_coproc1_ok} in addition to the following: @code{CDP2}, @code{LDC2},
+@code{LDC2l}, @code{STC2}, @code{STC2l}, @code{MCR2} and @code{MRC2}.
+
+@item arm_coproc3_ok
+@anchor{arm_coproc3_ok}
+ARM target supports all the coprocessor instructions also listed as supported
+in @ref{arm_coproc2_ok} in addition the following: @code{MCRR} and @code{MRRC}.
+
+@item arm_coproc4_ok
+ARM target supports all the coprocessor instructions also listed as supported
+in @ref{arm_coproc3_ok} in addition the following: @code{MCRR2} and @code{MRRC2}.
@end table
@subsubsection AArch64-specific attributes
@item powerpc_p8vector_ok
PowerPC target supports @code{-mpower8-vector}
+@item powerpc_popcntb_ok
+PowerPC target supports the @code{popcntb} instruction, indicating
+that this target supports @code{-mcpu=power5}.
+
@item powerpc_ppu_ok
PowerPC target supports @code{-mcpu=cell}.
@subsubsection Other hardware attributes
+@c Please keep this table sorted alphabetically.
@table @code
+@item autoincdec
+Target supports autoincrement/decrement addressing.
+
@item avx
Target supports compiling @code{avx} instructions.
@item avx_runtime
Target supports the execution of @code{avx} instructions.
+@item avx2
+Target supports compiling @code{avx2} instructions.
+
+@item avx2_runtime
+Target supports the execution of @code{avx2} instructions.
+
+@item avx512f
+Target supports compiling @code{avx512f} instructions.
+
+@item avx512f_runtime
+Target supports the execution of @code{avx512f} instructions.
+
@item cell_hw
Test system can execute AltiVec and Cell PPU instructions.
@item coldfire_fpu
Target uses a ColdFire FPU.
+@item divmod
+Target supporting hardware divmod insn or divmod libcall.
+
+@item divmod_simode
+Target supporting hardware divmod insn or divmod libcall for SImode.
+
@item hard_float
Target supports FPU instructions.
@item non_strict_align
Target does not require strict alignment.
+@item pie_copyreloc
+The x86-64 target linker supports PIE with copy reloc.
+
+@item rdrand
+Target supports x86 @code{rdrand} instruction.
+
@item sqrt_insn
Target has a square root instruction that the compiler can generate.
@item vect_cmdline_needed
Target requires a command line argument to enable a SIMD instruction set.
-@item pie_copyreloc
-The x86-64 target linker supports PIE with copy reloc.
+@item xorsign
+Target supports the xorsign optab expansion.
+
@end table
@subsubsection Environment attributes
Effectively, it is a target which supports no extra headers or libraries
other than what is considered essential.
+@item gettimeofday
+Target supports @code{gettimeofday}.
+
@item init_priority
Target supports constructors with initialization priority arguments.
Test system runs executables on a simulator (i.e. slowly) rather than
hardware (i.e. fast).
+@item signal
+Target has @code{signal.h}.
+
@item stabs
Target supports the stabs debugging format.
@item automatic_stack_alignment
Target supports automatic stack alignment.
-@item cilkplus_runtime
-Target supports the Cilk Plus runtime library.
+@item branch_cost
+Target supports @option{-branch-cost=N}.
@item cxa_atexit
Target uses @code{__cxa_atexit}.
@item pie
Target supports @option{-pie}, @option{-fpie} and @option{-fPIE}.
+@item rdynamic
+Target supports @option{-rdynamic}.
+
@item section_anchors
Target supports section anchors.
@item short_enums
Target defaults to short enums.
+@item stack_size
+@anchor{stack_size_et}
+Target has limited stack size. The stack size limit can be obtained using the
+STACK_SIZE macro defined by @ref{stack_size_ao,,@code{dg-add-options} feature
+@code{stack_size}}.
+
@item static
Target supports @option{-static}.
arm vfp3 floating point support; see
the @ref{arm_vfp3_ok,,arm_vfp3_ok effective target keyword}.
+@item arm_v8_1a_neon
+Add options for ARMv8.1-A with Adv.SIMD support, if this is supported
+by the target; see the @ref{arm_v8_1a_neon_ok,,arm_v8_1a_neon_ok}
+effective target keyword.
+
+@item arm_v8_2a_fp16_scalar
+Add options for ARMv8.2-A with scalar FP16 support, if this is
+supported by the target; see the
+@ref{arm_v8_2a_fp16_scalar_ok,,arm_v8_2a_fp16_scalar_ok} effective
+target keyword.
+
+@item arm_v8_2a_fp16_neon
+Add options for ARMv8.2-A with Adv.SIMD FP16 support, if this is
+supported by the target; see the
+@ref{arm_v8_2a_fp16_neon_ok,,arm_v8_2a_fp16_neon_ok} effective target
+keyword.
+
+@item arm_v8_2a_dotprod_neon
+Add options for ARMv8.2-A with Adv.SIMD Dot Product support, if this is
+supported by the target; see the
+@ref{arm_v8_2a_dotprod_neon_ok} effective target keyword.
+
+@item arm_fp16fml_neon
+Add options to enable generation of the @code{VFMAL} and @code{VFMSL}
+instructions, if this is supported by the target; see the
+@ref{arm_fp16fml_neon_ok} effective target keyword.
+
@item bind_pic_locally
Add the target-specific flags needed to enable functions to bind
locally when using pic/PIC passes in the testsuite.
@item c99_runtime
Add the target-specific flags needed to access the C99 runtime.
+@item float@var{n}
+Add the target-specific flags needed to use the @code{_Float@var{n}} type.
+
+@item float@var{n}x
+Add the target-specific flags needed to use the @code{_Float@var{n}x} type.
+
@item ieee
Add the target-specific flags needed to enable full IEEE
compliance mode.
@code{mips16} function attributes.
Only MIPS targets support this feature, and only then in certain modes.
+@item stack_size
+@anchor{stack_size_ao}
+Add the flags needed to define macro STACK_SIZE and set it to the stack size
+limit associated with the @ref{stack_size_et,,@code{stack_size} effective
+target}.
+
@item tls
Add the target-specific flags needed to use thread-local storage.
@end table
Skip the test if the target does not support profiling with option
@var{profopt}.
+@item dg-require-stack-check @var{check}
+Skip the test if the target does not support the @code{-fstack-check}
+option. If @var{check} is @code{""}, support for @code{-fstack-check}
+is checked, for @code{-fstack-check=("@var{check}")} otherwise.
+
+@item dg-require-stack-size @var{size}
+Skip the test if the target does not support a stack size of @var{size}.
+
@item dg-require-visibility @var{vis}
Skip the test if the target does not support the @code{visibility} attribute.
If @var{vis} is @code{""}, support for @code{visibility("hidden")} is
@subsubsection Scan optimization dump files
-These commands are available for @var{kind} of @code{tree}, @code{rtl},
-and @code{ipa}.
+These commands are available for @var{kind} of @code{tree}, @code{ltrans-tree},
+@code{rtl}, @code{ipa}, and @code{wpa-ipa}.
@table @code
@item scan-@var{kind}-dump @var{regex} @var{suffix} [@{ target/xfail @var{selector} @}]
a chapter of the Ada Reference Manual. So for example, @file{c9} corresponds
to chapter 9, which deals with tasking features of the language.
-There is also an extra chapter called @file{gcc} containing a template for
-creating new executable tests, although this is deprecated in favor of
-the @file{gnat.dg} testsuite.
-
The tests are run using two @command{sh} scripts: @file{run_acats} and
@file{run_all.sh}. To run the tests using a simulator or a cross
target, see the small
While special options can be set, and tests disabled on specific
platforms, by the use of @file{.x} files, mostly these test cases
should not contain platform dependencies. FIXME: discuss how defines
-such as @code{NO_LABEL_VALUES} and @code{STACK_SIZE} are used.
+such as @code{STACK_SIZE} are used.
@item gcc.c-torture/execute
This testsuite contains test cases that should compile, link and run;
otherwise the same comments as for @file{gcc.c-torture/compile} apply.
FIXME: merge in @file{testsuite/README.gcc} and discuss the format of
test cases and magic comments more.
-@node libgcj Tests
-@section The Java library testsuites.
-
-Runtime tests are executed via @samp{make check} in the
-@file{@var{target}/libjava/testsuite} directory in the build
-tree. Additional runtime tests can be checked into this testsuite.
-
-Regression testing of the core packages in libgcj is also covered by the
-Mauve testsuite. The @uref{http://sourceware.org/mauve/,,Mauve Project}
-develops tests for the Java Class Libraries. These tests are run as part
-of libgcj testing by placing the Mauve tree within the libjava testsuite
-sources at @file{libjava/testsuite/libjava.mauve/mauve}, or by specifying
-the location of that tree when invoking @samp{make}, as in
-@samp{make MAUVEDIR=~/mauve check}.
-
-To detect regressions, a mechanism in @file{mauve.exp} compares the
-failures for a test run against the list of expected failures in
-@file{libjava/testsuite/libjava.mauve/xfails} from the source hierarchy.
-Update this file when adding new failing tests to Mauve, or when fixing
-bugs in libgcj that had caused Mauve test failures.
-
-We encourage developers to contribute test cases to Mauve.
-
@node LTO Testing
@section Support for testing link-time optimizations
@{ -O2 -ftree-loop-linear @} \
@{ -O2 -fpeel-loops @} ]
@end smallexample
+
+@node GIMPLE Tests
+@section Support for testing GIMPLE passes
+
+As of gcc 7, C functions can be tagged with @code{__GIMPLE} to indicate
+that the function body will be GIMPLE, rather than C. The compiler requires
+the option @option{-fgimple} to enable this functionality. For example:
+
+@smallexample
+/* @{ dg-do compile @} */
+/* @{ dg-options "-O -fgimple" @} */
+
+void __GIMPLE (startwith ("dse2")) foo ()
+@{
+ int a;
+
+bb_2:
+ if (a > 4)
+ goto bb_3;
+ else
+ goto bb_4;
+
+bb_3:
+ a_2 = 10;
+ goto bb_5;
+
+bb_4:
+ a_3 = 20;
+
+bb_5:
+ a_1 = __PHI (bb_3: a_2, bb_4: a_3);
+ a_4 = a_1 + 4;
+
+ return;
+@}
+@end smallexample
+
+The @code{startwith} argument indicates at which pass to begin.
+
+Use the dump modifier @code{-gimple} (e.g. @option{-fdump-tree-all-gimple})
+to make tree dumps more closely follow the format accepted by the GIMPLE
+parser.
+
+Example DejaGnu tests of GIMPLE can be seen in the source tree at
+@file{gcc/testsuite/gcc.dg/gimplefe-*.c}.
+
+The @code{__GIMPLE} parser is integrated with the C tokenizer and
+preprocessor, so it should be possible to use macros to build out
+test coverage.
+
+@node RTL Tests
+@section Support for testing RTL passes
+
+As of gcc 7, C functions can be tagged with @code{__RTL} to indicate that the
+function body will be RTL, rather than C. For example:
+
+@smallexample
+double __RTL (startwith ("ira")) test (struct foo *f, const struct bar *b)
+@{
+ (function "test"
+ [...snip; various directives go in here...]
+ ) ;; function "test"
+@}
+@end smallexample
+
+The @code{startwith} argument indicates at which pass to begin.
+
+The parser expects the RTL body to be in the format emitted by this
+dumping function:
+
+@smallexample
+DEBUG_FUNCTION void
+print_rtx_function (FILE *outfile, function *fn, bool compact);
+@end smallexample
+
+when "compact" is true. So you can capture RTL in the correct format
+from the debugger using:
+
+@smallexample
+(gdb) print_rtx_function (stderr, cfun, true);
+@end smallexample
+
+and copy and paste the output into the body of the C function.
+
+Example DejaGnu tests of RTL can be seen in the source tree under
+@file{gcc/testsuite/gcc.dg/rtl}.
+
+The @code{__RTL} parser is not integrated with the C tokenizer or
+preprocessor, and works simply by reading the relevant lines within
+the braces. In particular, the RTL body must be on separate lines from
+the enclosing braces, and the preprocessor is not usable within it.
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