/* Integrated Register Allocator (IRA) intercommunication header file.
- Copyright (C) 2006-2013 Free Software Foundation, Inc.
+ Copyright (C) 2006-2015 Free Software Foundation, Inc.
Contributed by Vladimir Makarov <vmakarov@redhat.com>.
This file is part of GCC.
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
+#ifndef GCC_IRA_INT_H
+#define GCC_IRA_INT_H
+
#include "cfgloop.h"
#include "ira.h"
#include "alloc-pool.h"
profile driven feedback is available and the function is never
executed, frequency is always equivalent. Otherwise rescale the
edge frequency. */
-#define REG_FREQ_FROM_EDGE_FREQ(freq) \
- (optimize_size || (flag_branch_probabilities && !ENTRY_BLOCK_PTR->count) \
- ? REG_FREQ_MAX : (freq * REG_FREQ_MAX / BB_FREQ_MAX) \
+#define REG_FREQ_FROM_EDGE_FREQ(freq) \
+ (optimize_function_for_size_p (cfun) \
+ ? REG_FREQ_MAX : (freq * REG_FREQ_MAX / BB_FREQ_MAX) \
? (freq * REG_FREQ_MAX / BB_FREQ_MAX) : 1)
/* A modified value of flag `-fira-verbose' used internally. */
/* Mode of the allocno which is the mode of the corresponding
pseudo-register. */
ENUM_BITFIELD (machine_mode) mode : 8;
+ /* Widest mode of the allocno which in at least one case could be
+ for paradoxical subregs where wmode > mode. */
+ ENUM_BITFIELD (machine_mode) wmode : 8;
/* Register class which should be used for allocation for given
allocno. NO_REGS means that we should use memory. */
ENUM_BITFIELD (reg_class) aclass : 16;
number (0, ...) - 2. Value -1 is used for allocnos spilled by the
reload (at this point pseudo-register has only one allocno) which
did not get stack slot yet. */
- short int hard_regno;
+ signed int hard_regno : 16;
/* Allocnos with the same regno are linked by the following member.
Allocnos corresponding to inner loops are first in the list (it
corresponds to depth-first traverse of the loops). */
/* The number of calls across which it is live, but which should not
affect register preferences. */
int cheap_calls_crossed_num;
+ /* Registers clobbered by intersected calls. */
+ HARD_REG_SET crossed_calls_clobbered_regs;
/* Array of usage costs (accumulated and the one updated during
coloring) for each hard register of the allocno class. The
member value can be NULL if all costs are the same and equal to
#define ALLOCNO_CALL_FREQ(A) ((A)->call_freq)
#define ALLOCNO_CALLS_CROSSED_NUM(A) ((A)->calls_crossed_num)
#define ALLOCNO_CHEAP_CALLS_CROSSED_NUM(A) ((A)->cheap_calls_crossed_num)
+#define ALLOCNO_CROSSED_CALLS_CLOBBERED_REGS(A) \
+ ((A)->crossed_calls_clobbered_regs)
#define ALLOCNO_MEM_OPTIMIZED_DEST(A) ((A)->mem_optimized_dest)
#define ALLOCNO_MEM_OPTIMIZED_DEST_P(A) ((A)->mem_optimized_dest_p)
#define ALLOCNO_SOMEWHERE_RENAMED_P(A) ((A)->somewhere_renamed_p)
#define ALLOCNO_BAD_SPILL_P(A) ((A)->bad_spill_p)
#define ALLOCNO_ASSIGNED_P(A) ((A)->assigned_p)
#define ALLOCNO_MODE(A) ((A)->mode)
+#define ALLOCNO_WMODE(A) ((A)->wmode)
#define ALLOCNO_PREFS(A) ((A)->allocno_prefs)
#define ALLOCNO_COPIES(A) ((A)->allocno_copies)
#define ALLOCNO_HARD_REG_COSTS(A) ((A)->hard_reg_costs)
/* The size of the previous array. */
extern int ira_objects_num;
-/* The following structure represents a hard register prefererence of
+/* The following structure represents a hard register preference of
allocno. The preference represent move insns or potential move
insns usually because of two operand insn constraints. One move
operand is a hard register. */
int freq;
/* Given allocno. */
ira_allocno_t allocno;
- /* All prefernces with the same allocno are linked by the following
+ /* All preferences with the same allocno are linked by the following
member. */
ira_pref_t next_pref;
};
for the copy created to remove register shuffle is NULL. In last
case the copy frequency is smaller than the corresponding insn
execution frequency. */
- rtx insn;
+ rtx_insn *insn;
/* All copies with the same allocno as FIRST are linked by the two
following members. */
ira_copy_t prev_first_allocno_copy, next_first_allocno_copy;
allocnos assigned to hard-registers, cost of the allocnos assigned
to memory, cost of loads, stores and register move insns generated
for pseudo-register live range splitting (see ira-emit.c). */
-extern int ira_overall_cost;
-extern int ira_reg_cost, ira_mem_cost;
-extern int ira_load_cost, ira_store_cost, ira_shuffle_cost;
+extern int64_t ira_overall_cost;
+extern int64_t ira_reg_cost, ira_mem_cost;
+extern int64_t ira_load_cost, ira_store_cost, ira_shuffle_cost;
extern int ira_move_loops_num, ira_additional_jumps_num;
\f
#endif
/* The iterator for min/max sets. */
-typedef struct {
+struct minmax_set_iterator {
/* Array containing the bit vector. */
IRA_INT_TYPE *vec;
/* The word of the bit vector currently visited. */
unsigned IRA_INT_TYPE word;
-} minmax_set_iterator;
+};
/* Initialize the iterator I for bit vector VEC containing minimal and
maximal values MIN and MAX. */
minmax_set_iter_next (&(ITER)))
\f
struct target_ira_int {
+ ~target_ira_int ();
+
+ void free_ira_costs ();
+ void free_register_move_costs ();
+
/* Initialized once. It is a maximal possible size of the allocated
struct costs. */
int x_max_struct_costs_size;
unavailable for the allocation. */
short x_ira_class_hard_reg_index[N_REG_CLASSES][FIRST_PSEUDO_REGISTER];
- /* Array whose values are hard regset of hard registers available for
- the allocation of given register class whose HARD_REGNO_MODE_OK
- values for given mode are zero. */
- HARD_REG_SET x_ira_prohibited_class_mode_regs[N_REG_CLASSES][NUM_MACHINE_MODES];
-
/* Index [CL][M] contains R if R appears somewhere in a register of the form:
(reg:M R'), R' not in x_ira_prohibited_class_mode_regs[CL][M]
(this_target_ira_int->x_ira_non_ordered_class_hard_regs)
#define ira_class_hard_reg_index \
(this_target_ira_int->x_ira_class_hard_reg_index)
-#define ira_prohibited_class_mode_regs \
- (this_target_ira_int->x_ira_prohibited_class_mode_regs)
#define ira_useful_class_mode_regs \
(this_target_ira_int->x_ira_useful_class_mode_regs)
#define ira_important_classes_num \
extern void ira_print_disposition (FILE *);
extern void ira_debug_disposition (void);
extern void ira_debug_allocno_classes (void);
-extern void ira_init_register_move_cost (enum machine_mode);
-extern void ira_setup_alts (rtx insn, HARD_REG_SET &alts);
+extern void ira_init_register_move_cost (machine_mode);
+extern void ira_setup_alts (rtx_insn *insn, HARD_REG_SET &alts);
extern int ira_get_dup_out_num (int op_num, HARD_REG_SET &alts);
/* ira-build.c */
extern void ira_remove_pref (ira_pref_t);
extern void ira_remove_allocno_prefs (ira_allocno_t);
extern ira_copy_t ira_create_copy (ira_allocno_t, ira_allocno_t,
- int, bool, rtx, ira_loop_tree_node_t);
+ int, bool, rtx_insn *,
+ ira_loop_tree_node_t);
extern ira_copy_t ira_add_allocno_copy (ira_allocno_t, ira_allocno_t, int,
- bool, rtx, ira_loop_tree_node_t);
+ bool, rtx_insn *,
+ ira_loop_tree_node_t);
extern int *ira_allocate_cost_vector (reg_class_t);
extern void ira_free_cost_vector (int *, reg_class_t);
/* ira-costs.c */
extern void ira_init_costs_once (void);
extern void ira_init_costs (void);
-extern void ira_finish_costs_once (void);
extern void ira_costs (void);
extern void ira_tune_allocno_costs (void);
/* Initialize register costs for MODE if necessary. */
static inline void
-ira_init_register_move_cost_if_necessary (enum machine_mode mode)
+ira_init_register_move_cost_if_necessary (machine_mode mode)
{
if (ira_register_move_cost[mode] == NULL)
ira_init_register_move_cost (mode);
\f
/* The iterator for all allocnos. */
-typedef struct {
+struct ira_allocno_iterator {
/* The number of the current element in IRA_ALLOCNOS. */
int n;
-} ira_allocno_iterator;
+};
/* Initialize the iterator I. */
static inline void
ira_allocno_iter_cond (&(ITER), &(A));)
\f
/* The iterator for all objects. */
-typedef struct {
+struct ira_object_iterator {
/* The number of the current element in ira_object_id_map. */
int n;
-} ira_object_iterator;
+};
/* Initialize the iterator I. */
static inline void
ira_object_iter_cond (&(ITER), &(OBJ));)
\f
/* The iterator for objects associated with an allocno. */
-typedef struct {
+struct ira_allocno_object_iterator {
/* The number of the element the allocno's object array. */
int n;
-} ira_allocno_object_iterator;
+};
/* Initialize the iterator I. */
static inline void
\f
/* The iterator for prefs. */
-typedef struct {
+struct ira_pref_iterator {
/* The number of the current element in IRA_PREFS. */
int n;
-} ira_pref_iterator;
+};
/* Initialize the iterator I. */
static inline void
\f
/* The iterator for copies. */
-typedef struct {
+struct ira_copy_iterator {
/* The number of the current element in IRA_COPIES. */
int n;
-} ira_copy_iterator;
+};
/* Initialize the iterator I. */
static inline void
ira_copy_iter_cond (&(ITER), &(C));)
\f
/* The iterator for object conflicts. */
-typedef struct {
+struct ira_object_conflict_iterator {
/* TRUE if the conflicts are represented by vector of allocnos. */
bool conflict_vec_p;
/* The word of bit vector currently visited. It is defined only if
OBJECT_CONFLICT_VEC_P is FALSE. */
unsigned IRA_INT_TYPE word;
-} ira_object_conflict_iterator;
+};
/* Initialize the iterator I with ALLOCNO conflicts. */
static inline void
starting with HARD_REGNO and containing value of MODE are in set
HARD_REGSET. */
static inline bool
-ira_hard_reg_set_intersection_p (int hard_regno, enum machine_mode mode,
+ira_hard_reg_set_intersection_p (int hard_regno, machine_mode mode,
HARD_REG_SET hard_regset)
{
int i;
HARD_REGNO and containing value of MODE are fully in set
HARD_REGSET. */
static inline bool
-ira_hard_reg_in_set_p (int hard_regno, enum machine_mode mode,
+ira_hard_reg_in_set_p (int hard_regno, machine_mode mode,
HARD_REG_SET hard_regset)
{
int i;
extern rtx ira_create_new_reg (rtx);
extern int first_moveable_pseudo, last_moveable_pseudo;
+
+#endif /* GCC_IRA_INT_H */
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