is properly defined. */
#include "insn-config.h"
#include "rtl.h"
-#include "hash-set.h"
-#include "machmode.h"
-#include "vec.h"
-#include "double-int.h"
-#include "input.h"
#include "alias.h"
#include "symtab.h"
-#include "wide-int.h"
-#include "inchash.h"
#include "tree.h"
#include "tree-hasher.h"
#include "stor-layout.h"
#include "hard-reg-set.h"
#include "function.h"
#include "except.h"
-#include "hashtab.h"
-#include "statistics.h"
-#include "real.h"
-#include "fixed-value.h"
#include "expmed.h"
#include "dojump.h"
#include "explow.h"
#include "libfuncs.h"
#include "recog.h"
#include "reload.h"
-#include "ggc.h"
#include "predict.h"
#include "dominance.h"
#include "cfg.h"
}
-#if HAVE_conditional_move
/* Try implementing expand_doubleword_shift using conditional moves.
The shift is by < BITS_PER_WORD if (CMP_CODE CMP1 CMP2) is true,
otherwise it is by >= BITS_PER_WORD. SUBWORD_OP1 and SUPERWORD_OP1
return true;
}
-#endif
/* Expand a doubleword shift (ashl, ashr or lshr) using word-mode shifts.
OUTOF_INPUT and INTO_INPUT are the two word-sized halves of the first
unsignedp, methods, shift_mask);
}
-#if HAVE_conditional_move
/* Try using conditional moves to generate straight-line code. */
- {
- rtx_insn *start = get_last_insn ();
- if (expand_doubleword_shift_condmove (op1_mode, binoptab,
- cmp_code, cmp1, cmp2,
- outof_input, into_input,
- op1, superword_op1,
- outof_target, into_target,
- unsignedp, methods, shift_mask))
- return true;
- delete_insns_since (start);
- }
-#endif
+ if (HAVE_conditional_move)
+ {
+ rtx_insn *start = get_last_insn ();
+ if (expand_doubleword_shift_condmove (op1_mode, binoptab,
+ cmp_code, cmp1, cmp2,
+ outof_input, into_input,
+ op1, superword_op1,
+ outof_target, into_target,
+ unsignedp, methods, shift_mask))
+ return true;
+ delete_insns_since (start);
+ }
/* As a last resort, use branches to select the correct alternative. */
rtx_code_label *subword_label = gen_label_rtx ();
if (optab_handler (mov_optab, mode) != CODE_FOR_nothing
|| ! rtx_equal_p (target, xtarget))
{
- rtx temp = emit_move_insn (target, xtarget);
+ rtx_insn *temp = emit_move_insn (target, xtarget);
set_dst_reg_note (temp, REG_EQUAL,
gen_rtx_fmt_ee (optab_to_code (binoptab),
if (code_to_optab (swapped)
&& (libfunc = optab_libfunc (code_to_optab (swapped), mode)))
{
- rtx tmp;
- tmp = x; x = y; y = tmp;
+ std::swap (x, y);
comparison = swapped;
break;
}
#endif
}
\f
-#if HAVE_conditional_move
/* Emit a conditional move instruction if the machine supports one for that
condition and machine mode.
return 0;
}
-#endif /* HAVE_conditional_move */
-
/* Emit a conditional addition instruction if the machine supports one for that
condition and machine mode.
/* Generate and return an insn body to add Y to X. */
-rtx
+rtx_insn *
gen_add2_insn (rtx x, rtx y)
{
enum insn_code icode = optab_handler (add_optab, GET_MODE (x));
/* Generate and return an insn body to add r1 and c,
storing the result in r0. */
-rtx
+rtx_insn *
gen_add3_insn (rtx r0, rtx r1, rtx c)
{
enum insn_code icode = optab_handler (add_optab, GET_MODE (r0));
|| !insn_operand_matches (icode, 0, r0)
|| !insn_operand_matches (icode, 1, r1)
|| !insn_operand_matches (icode, 2, c))
- return NULL_RTX;
+ return NULL;
return GEN_FCN (icode) (r0, r1, c);
}
/* Generate and return an insn body to add Y to X. */
-rtx
+rtx_insn *
gen_addptr3_insn (rtx x, rtx y, rtx z)
{
enum insn_code icode = optab_handler (addptr3_optab, GET_MODE (x));
/* Generate and return an insn body to subtract Y from X. */
-rtx
+rtx_insn *
gen_sub2_insn (rtx x, rtx y)
{
enum insn_code icode = optab_handler (sub_optab, GET_MODE (x));
/* Generate and return an insn body to subtract r1 and c,
storing the result in r0. */
-rtx
+rtx_insn *
gen_sub3_insn (rtx r0, rtx r1, rtx c)
{
enum insn_code icode = optab_handler (sub_optab, GET_MODE (r0));
|| !insn_operand_matches (icode, 0, r0)
|| !insn_operand_matches (icode, 1, r1)
|| !insn_operand_matches (icode, 2, c))
- return NULL_RTX;
+ return NULL;
return GEN_FCN (icode) (r0, r1, c);
}
/* Generate the body of an insn to extend Y (with mode MFROM)
into X (with mode MTO). Do zero-extension if UNSIGNEDP is nonzero. */
-rtx
+rtx_insn *
gen_extend_insn (rtx x, rtx y, machine_mode mto,
machine_mode mfrom, int unsignedp)
{
/* Hashtable callbacks for libfunc_decls. */
-struct libfunc_decl_hasher : ggc_hasher<tree>
+struct libfunc_decl_hasher : ggc_ptr_hash<tree_node>
{
static hashval_t
hash (tree entry)
/* Generate insns to trap with code TCODE if OP1 and OP2 satisfy condition
CODE. Return 0 on failure. */
-rtx
+rtx_insn *
gen_cond_trap (enum rtx_code code, rtx op1, rtx op2, rtx tcode)
{
machine_mode mode = GET_MODE (op1);
enum insn_code icode;
- rtx insn;
+ rtx_insn *insn;
rtx trap_rtx;
if (mode == VOIDmode)
prepare_cmp_insn (op1, op2, code, NULL_RTX, false, OPTAB_DIRECT,
&trap_rtx, &mode);
if (!trap_rtx)
- insn = NULL_RTX;
+ insn = NULL;
else
insn = GEN_FCN (icode) (trap_rtx, XEXP (trap_rtx, 0), XEXP (trap_rtx, 1),
tcode);
tab1 = uns_p ? vec_widen_umult_lo_optab : vec_widen_smult_lo_optab;
tab2 = uns_p ? vec_widen_umult_hi_optab : vec_widen_smult_hi_optab;
if (BYTES_BIG_ENDIAN)
- {
- optab t = tab1;
- tab1 = tab2;
- tab2 = t;
- }
+ std::swap (tab1, tab2);
break;
default:
gcc_unreachable ();
/* This routine will either emit the mem_thread_fence pattern or issue a
sync_synchronize to generate a fence for memory model MEMMODEL. */
-#ifndef HAVE_mem_thread_fence
-# define HAVE_mem_thread_fence 0
-# define gen_mem_thread_fence(x) (gcc_unreachable (), NULL_RTX)
-#endif
-#ifndef HAVE_memory_barrier
-# define HAVE_memory_barrier 0
-# define gen_memory_barrier() (gcc_unreachable (), NULL_RTX)
-#endif
-
void
expand_mem_thread_fence (enum memmodel model)
{
/* This routine will either emit the mem_signal_fence pattern or issue a
sync_synchronize to generate a fence for memory model MEMMODEL. */
-#ifndef HAVE_mem_signal_fence
-# define HAVE_mem_signal_fence 0
-# define gen_mem_signal_fence(x) (gcc_unreachable (), NULL_RTX)
-#endif
-
void
expand_mem_signal_fence (enum memmodel model)
{
maybe_expand_insn (enum insn_code icode, unsigned int nops,
struct expand_operand *ops)
{
- rtx pat = maybe_gen_insn (icode, nops, ops);
+ rtx_insn *pat = maybe_gen_insn (icode, nops, ops);
if (pat)
{
emit_insn (pat);
maybe_expand_jump_insn (enum insn_code icode, unsigned int nops,
struct expand_operand *ops)
{
- rtx pat = maybe_gen_insn (icode, nops, ops);
+ rtx_insn *pat = maybe_gen_insn (icode, nops, ops);
if (pat)
{
emit_jump_insn (pat);
projects / gcc.git / blobdiff