/* Create but don't emit one rtl instruction to perform certain operations.
Modes must match; operands must meet the operation's predicates.
Likewise for subtraction and for just copying. */
-extern rtx gen_add2_insn (rtx, rtx);
-extern rtx gen_add3_insn (rtx, rtx, rtx);
+extern rtx_insn *gen_add2_insn (rtx, rtx);
+extern rtx_insn *gen_add3_insn (rtx, rtx, rtx);
extern int have_add2_insn (rtx, rtx);
-extern rtx gen_addptr3_insn (rtx, rtx, rtx);
+extern rtx_insn *gen_addptr3_insn (rtx, rtx, rtx);
extern int have_addptr3_insn (rtx, rtx, rtx);
-extern rtx gen_sub2_insn (rtx, rtx);
-extern rtx gen_sub3_insn (rtx, rtx, rtx);
+extern rtx_insn *gen_sub2_insn (rtx, rtx);
+extern rtx_insn *gen_sub3_insn (rtx, rtx, rtx);
extern int have_sub2_insn (rtx, rtx);
/* Return the INSN_CODE to use for an extend operation. */
/* Generate the body of an insn to extend Y (with mode MFROM)
into X (with mode MTO). Do zero-extension if UNSIGNEDP is nonzero. */
-extern rtx gen_extend_insn (rtx, rtx, machine_mode,
- machine_mode, int);
+extern rtx_insn *gen_extend_insn (rtx, rtx, machine_mode, machine_mode, int);
/* Return the insn_code for a FLOAT_EXPR. */
enum insn_code can_float_p (machine_mode, machine_mode, int);
extern void init_sync_libfuncs (int max);
/* Generate a conditional trap instruction. */
-extern rtx gen_cond_trap (enum rtx_code, rtx, rtx, rtx);
+extern rtx_insn *gen_cond_trap (enum rtx_code, rtx, rtx, rtx);
/* Return true if target supports vector operations for VEC_PERM_EXPR. */
extern bool can_vec_perm_p (machine_mode, bool, const unsigned char *);