/* Definitions for code generation pass of GNU compiler.
- Copyright (C) 2001-2014 Free Software Foundation, Inc.
+ Copyright (C) 2001-2015 Free Software Foundation, Inc.
This file is part of GCC.
enum optab_methods methods);
extern bool force_expand_binop (machine_mode, optab, rtx, rtx, rtx, int,
enum optab_methods);
-/* Generate code for VEC_RSHIFT_EXPR. */
-extern rtx expand_vec_shift_expr (struct separate_ops *, rtx);
/* Generate code for a simple binary or unary operation. "Simple" in
this case means "can be unambiguously described by a (mode, code)
#error "insn-config.h must be included before optabs.h"
#endif
-#ifdef HAVE_conditional_move
/* Emit a conditional move operation. */
rtx emit_conditional_move (rtx, enum rtx_code, rtx, rtx, machine_mode,
rtx, rtx, machine_mode, int);
/* Return nonzero if the conditional move is supported. */
int can_conditionally_move_p (machine_mode mode);
-#endif
rtx emit_conditional_add (rtx, enum rtx_code, rtx, rtx, machine_mode,
rtx, rtx, machine_mode, int);
/* Create but don't emit one rtl instruction to perform certain operations.
Modes must match; operands must meet the operation's predicates.
Likewise for subtraction and for just copying. */
-extern rtx gen_add2_insn (rtx, rtx);
-extern rtx gen_add3_insn (rtx, rtx, rtx);
+extern rtx_insn *gen_add2_insn (rtx, rtx);
+extern rtx_insn *gen_add3_insn (rtx, rtx, rtx);
extern int have_add2_insn (rtx, rtx);
-extern rtx gen_addptr3_insn (rtx, rtx, rtx);
+extern rtx_insn *gen_addptr3_insn (rtx, rtx, rtx);
extern int have_addptr3_insn (rtx, rtx, rtx);
-extern rtx gen_sub2_insn (rtx, rtx);
-extern rtx gen_sub3_insn (rtx, rtx, rtx);
+extern rtx_insn *gen_sub2_insn (rtx, rtx);
+extern rtx_insn *gen_sub3_insn (rtx, rtx, rtx);
extern int have_sub2_insn (rtx, rtx);
/* Return the INSN_CODE to use for an extend operation. */
/* Generate the body of an insn to extend Y (with mode MFROM)
into X (with mode MTO). Do zero-extension if UNSIGNEDP is nonzero. */
-extern rtx gen_extend_insn (rtx, rtx, machine_mode,
- machine_mode, int);
+extern rtx_insn *gen_extend_insn (rtx, rtx, machine_mode, machine_mode, int);
/* Return the insn_code for a FLOAT_EXPR. */
enum insn_code can_float_p (machine_mode, machine_mode, int);
extern void init_sync_libfuncs (int max);
/* Generate a conditional trap instruction. */
-extern rtx gen_cond_trap (enum rtx_code, rtx, rtx, rtx);
+extern rtx_insn *gen_cond_trap (enum rtx_code, rtx, rtx, rtx);
/* Return true if target supports vector operations for VEC_PERM_EXPR. */
extern bool can_vec_perm_p (machine_mode, bool, const unsigned char *);
extern bool maybe_legitimize_operands (enum insn_code icode,
unsigned int opno, unsigned int nops,
struct expand_operand *ops);
-extern rtx maybe_gen_insn (enum insn_code icode, unsigned int nops,
- struct expand_operand *ops);
+extern rtx_insn *maybe_gen_insn (enum insn_code icode, unsigned int nops,
+ struct expand_operand *ops);
extern bool maybe_expand_insn (enum insn_code icode, unsigned int nops,
struct expand_operand *ops);
extern bool maybe_expand_jump_insn (enum insn_code icode, unsigned int nops,
extern bool lshift_cheap_p (bool);
+extern enum rtx_code get_rtx_code (enum tree_code tcode, bool unsignedp);
+
#endif /* GCC_OPTABS_H */