/* This file contains the definitions and documentation for the
Register Transfer Expressions (rtx's) that make up the
Register Transfer Language (rtl) used in the Back End of the GNU compiler.
- Copyright (C) 1987, 88, 92, 94, 95, 97, 98, 1999, 2000
- Free Software Foundation, Inc.
+ Copyright (C) 1987-2015 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
-Software Foundation; either version 2, or (at your option) any later
+Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
for more details.
You should have received a copy of the GNU General Public License
-along with GCC; see the file COPYING. If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA. */
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
/* Expression definitions and descriptions for all targets are in this file.
These names are stored in rtx_name[].
By convention these are the internal (field 1) names in lower_case.
- 3. The print format, and type of each rtx->fld[] (field) in this rtx.
+ 3. The print format, and type of each rtx->u.fld[] (field) in this rtx.
These formats are stored in rtx_format[].
The meaning of the formats is documented in front of this array in rtl.c
-
+
4. The class of the rtx. These are stored in rtx_class and are accessed
via the GET_RTX_CLASS macro. They are defined as follows:
- "o" an rtx code that can be used to represent an object (e.g, REG, MEM)
- "<" an rtx code for a comparison (e.g, EQ, NE, LT)
- "1" an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
- "c" an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
- "3" an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
- "2" an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
- "b" an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
- "i" an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
- "m" an rtx code for something that matches in insns (e.g, MATCH_DUP)
- "g" an rtx code for grouping insns together (e.g, GROUP_PARALLEL)
- "a" an rtx code for autoincrement addressing modes (e.g. POST_DEC)
- "x" everything else
-
- */
+ RTX_CONST_OBJ
+ an rtx code that can be used to represent a constant object
+ (e.g, CONST_INT)
+ RTX_OBJ
+ an rtx code that can be used to represent an object (e.g, REG, MEM)
+ RTX_COMPARE
+ an rtx code for a comparison (e.g, LT, GT)
+ RTX_COMM_COMPARE
+ an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED)
+ RTX_UNARY
+ an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
+ RTX_COMM_ARITH
+ an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
+ RTX_TERNARY
+ an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
+ RTX_BIN_ARITH
+ an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
+ RTX_BITFIELD_OPS
+ an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
+ RTX_INSN
+ an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN) or
+ data that will be output as assembly pseudo-ops (DEBUG_INSN)
+ RTX_MATCH
+ an rtx code for something that matches in insns (e.g, MATCH_DUP)
+ RTX_AUTOINC
+ an rtx code for autoincrement addressing modes (e.g. POST_DEC)
+ RTX_EXTRA
+ everything else
+
+ All of the expressions that appear only in machine descriptions,
+ not in RTL used by the compiler itself, are at the end of the file. */
+
+/* Unknown, or no such operation; the enumeration constant should have
+ value zero. */
+DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA)
+
+/* Used in the cselib routines to describe a value. Objects of this
+ kind are only allocated in cselib.c, in an alloc pool instead of in
+ GC memory. The only operand of a VALUE is a cselib_val.
+ var-tracking requires this to have a distinct integral value from
+ DECL codes in trees. */
+DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ)
+
+/* The RTL generated for a DEBUG_EXPR_DECL. It links back to the
+ DEBUG_EXPR_DECL in the first operand. */
+DEF_RTL_EXPR(DEBUG_EXPR, "debug_expr", "0", RTX_OBJ)
/* ---------------------------------------------------------------------
- Expressions (and "meta" expressions) used for structuring the
- rtl representation of a program.
+ Expressions used in constructing lists.
--------------------------------------------------------------------- */
-/* an expression code name unknown to the reader */
-DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", 'x')
+/* A linked list of expressions. */
+DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA)
-/* (NIL) is used by rtl reader and printer to represent a null pointer. */
+/* A linked list of instructions.
+ The insns are represented in print by their uids. */
+DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA)
-DEF_RTL_EXPR(NIL, "nil", "*", 'x')
+/* A linked list of integers. */
+DEF_RTL_EXPR(INT_LIST, "int_list", "ie", RTX_EXTRA)
+/* SEQUENCE is used in late passes of the compiler to group insns for
+ one reason or another.
-/* include a file */
+ For example, after delay slot filling, branch instructions with filled
+ delay slots are represented as a SEQUENCE of length 1 + n_delay_slots,
+ with the branch instruction in XEXPVEC(seq, 0, 0) and the instructions
+ occupying the delay slots in the remaining XEXPVEC slots.
-DEF_RTL_EXPR(INCLUDE, "include", "s", 'x')
+ Another place where a SEQUENCE may appear, is in REG_FRAME_RELATED_EXPR
+ notes, to express complex operations that are not obvious from the insn
+ to which the REG_FRAME_RELATED_EXPR note is attached. In this usage of
+ SEQUENCE, the sequence vector slots do not hold real instructions but
+ only pseudo-instructions that can be translated to DWARF CFA expressions.
-/* ---------------------------------------------------------------------
- Expressions used in constructing lists.
- --------------------------------------------------------------------- */
+ Some back ends also use SEQUENCE to group insns in bundles.
-/* a linked list of expressions */
-DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", 'x')
+ Much of the compiler infrastructure is not prepared to handle SEQUENCE
+ objects. Only passes after pass_free_cfg are expected to handle them. */
+DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA)
-/* a linked list of instructions.
- The insns are represented in print by their uids. */
-DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", 'x')
+/* Represents a non-global base address. This is only used in alias.c. */
+DEF_RTL_EXPR(ADDRESS, "address", "i", RTX_EXTRA)
/* ----------------------------------------------------------------------
- Expression types for machine descriptions.
- These do not appear in actual rtl code in the compiler.
- ---------------------------------------------------------------------- */
-
-/* Appears only in machine descriptions.
- Means use the function named by the second arg (the string)
- as a predicate; if matched, store the structure that was matched
- in the operand table at index specified by the first arg (the integer).
- If the second arg is the null string, the structure is just stored.
+ Expression types used for things in the instruction chain.
- A third string argument indicates to the register allocator restrictions
- on where the operand can be allocated.
+ All formats must start with "iuu" to handle the chain.
+ Each insn expression holds an rtl instruction and its semantics
+ during back-end processing.
+ See macros's in "rtl.h" for the meaning of each rtx->u.fld[].
- If the target needs no restriction on any instruction this field should
- be the null string.
+ ---------------------------------------------------------------------- */
- The string is prepended by:
- '=' to indicate the operand is only written to.
- '+' to indicate the operand is both read and written to.
+/* An annotation for variable assignment tracking. */
+DEF_RTL_EXPR(DEBUG_INSN, "debug_insn", "uuBeiie", RTX_INSN)
- Each character in the string represents an allocable class for an operand.
- 'g' indicates the operand can be any valid class.
- 'i' indicates the operand can be immediate (in the instruction) data.
- 'r' indicates the operand can be in a register.
- 'm' indicates the operand can be in memory.
- 'o' a subset of the 'm' class. Those memory addressing modes that
- can be offset at compile time (have a constant added to them).
+/* An instruction that cannot jump. */
+DEF_RTL_EXPR(INSN, "insn", "uuBeiie", RTX_INSN)
- Other characters indicate target dependent operand classes and
- are described in each target's machine description.
+/* An instruction that can possibly jump.
+ Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
+DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "uuBeiie0", RTX_INSN)
- For instructions with more than one operand, sets of classes can be
- separated by a comma to indicate the appropriate multi-operand constraints.
- There must be a 1 to 1 correspondence between these sets of classes in
- all operands for an instruction.
- */
-DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", 'm')
+/* An instruction that can possibly call a subroutine
+ but which will not change which instruction comes next
+ in the current function.
+ Field ( rtx->u.fld[8] ) is CALL_INSN_FUNCTION_USAGE.
+ All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
+DEF_RTL_EXPR(CALL_INSN, "call_insn", "uuBeiiee", RTX_INSN)
-/* Appears only in machine descriptions.
- Means match a SCRATCH or a register. When used to generate rtl, a
- SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
- the desired mode and the first argument is the operand number.
- The second argument is the constraint. */
-DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", 'm')
+/* Placeholder for tablejump JUMP_INSNs. The pattern of this kind
+ of rtx is always either an ADDR_VEC or an ADDR_DIFF_VEC. These
+ placeholders do not appear as real instructions inside a basic
+ block, but are considered active_insn_p instructions for historical
+ reasons, when jump table data was represented with JUMP_INSNs. */
+DEF_RTL_EXPR(JUMP_TABLE_DATA, "jump_table_data", "uuBe0000", RTX_INSN)
-/* Appears only in machine descriptions.
- Means match only something equal to what is stored in the operand table
- at the index specified by the argument. */
-DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", 'm')
+/* A marker that indicates that control will not flow through. */
+DEF_RTL_EXPR(BARRIER, "barrier", "uu00000", RTX_EXTRA)
-/* Appears only in machine descriptions.
- Means apply a predicate, AND match recursively the operands of the rtx.
- Operand 0 is the operand-number, as in match_operand.
- Operand 1 is a predicate to apply (as a string, a function name).
- Operand 2 is a vector of expressions, each of which must match
- one subexpression of the rtx this construct is matching. */
-DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", 'm')
+/* Holds a label that is followed by instructions.
+ Operand:
+ 3: is used in jump.c for the use-count of the label.
+ 4: is used in the sh backend.
+ 5: is a number that is unique in the entire compilation.
+ 6: is the user-given name of the label, if any. */
+DEF_RTL_EXPR(CODE_LABEL, "code_label", "uuB00is", RTX_EXTRA)
-/* Appears only in machine descriptions.
- Means to match a PARALLEL of arbitrary length. The predicate is applied
- to the PARALLEL and the initial expressions in the PARALLEL are matched.
- Operand 0 is the operand-number, as in match_operand.
- Operand 1 is a predicate to apply to the PARALLEL.
- Operand 2 is a vector of expressions, each of which must match the
- corresponding element in the PARALLEL. */
-DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", 'm')
+/* Say where in the code a source line starts, for symbol table's sake.
+ Operand:
+ 3: note-specific data
+ 4: enum insn_note
+ 5: unique number if insn_note == note_insn_deleted_label. */
+DEF_RTL_EXPR(NOTE, "note", "uuB0ni", RTX_EXTRA)
-/* Appears only in machine descriptions.
- Means match only something equal to what is stored in the operand table
- at the index specified by the argument. For MATCH_OPERATOR. */
-DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", 'm')
+/* ----------------------------------------------------------------------
+ Top level constituents of INSN, JUMP_INSN and CALL_INSN.
+ ---------------------------------------------------------------------- */
-/* Appears only in machine descriptions.
- Means match only something equal to what is stored in the operand table
- at the index specified by the argument. For MATCH_PARALLEL. */
-DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", 'm')
+/* Conditionally execute code.
+ Operand 0 is the condition that if true, the code is executed.
+ Operand 1 is the code to be executed (typically a SET).
-/* Appears only in machine descriptions.
- Operand 0 is the operand number, as in match_operand.
- Operand 1 is the predicate to apply to the insn. */
-DEF_RTL_EXPR(MATCH_INSN, "match_insn", "is", 'm')
+ Semantics are that there are no side effects if the condition
+ is false. This pattern is created automatically by the if_convert
+ pass run after reload or by target-specific splitters. */
+DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA)
-/* Appears only in machine descriptions.
- Defines the pattern for one kind of instruction.
- Operand:
- 0: names this instruction.
- If the name is the null string, the instruction is in the
- machine description just to be recognized, and will never be emitted by
- the tree to rtl expander.
- 1: is the pattern.
- 2: is a string which is a C expression
- giving an additional condition for recognizing this pattern.
- A null string means no extra condition.
- 3: is the action to execute if this pattern is matched.
- If this assembler code template starts with a * then it is a fragment of
- C code to run to decide on a template to use. Otherwise, it is the
- template to use.
- 4: optionally, a vector of attributes for this insn.
- */
-DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", 'x')
+/* Several operations to be done in parallel (perhaps under COND_EXEC). */
+DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA)
-/* Definition of a peephole optimization.
- 1st operand: vector of insn patterns to match
- 2nd operand: C expression that must be true
- 3rd operand: template or C code to produce assembler output.
- 4: optionally, a vector of attributes for this insn.
- */
-DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", 'x')
+/* A string that is passed through to the assembler as input.
+ One can obviously pass comments through by using the
+ assembler comment syntax.
+ These occur in an insn all by themselves as the PATTERN.
+ They also appear inside an ASM_OPERANDS
+ as a convenient way to hold a string. */
+DEF_RTL_EXPR(ASM_INPUT, "asm_input", "si", RTX_EXTRA)
-/* Definition of a split operation.
- 1st operand: insn pattern to match
- 2nd operand: C expression that must be true
- 3rd operand: vector of insn patterns to place into a SEQUENCE
- 4th operand: optionally, some C code to execute before generating the
- insns. This might, for example, create some RTX's and store them in
- elements of `recog_data.operand' for use by the vector of
- insn-patterns.
- (`operands' is an alias here for `recog_data.operand'). */
-DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", 'x')
+/* An assembler instruction with operands.
+ 1st operand is the instruction template.
+ 2nd operand is the constraint for the output.
+ 3rd operand is the number of the output this expression refers to.
+ When an insn stores more than one value, a separate ASM_OPERANDS
+ is made for each output; this integer distinguishes them.
+ 4th is a vector of values of input operands.
+ 5th is a vector of modes and constraints for the input operands.
+ Each element is an ASM_INPUT containing a constraint string
+ and whose mode indicates the mode of the input operand.
+ 6th is a vector of labels that may be branched to by the asm.
+ 7th is the source line number. */
+DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEEi", RTX_EXTRA)
-/* Definition of an insn and associated split.
- This is the concatenation, with a few modifications, of a define_insn
- and a define_split which share the same pattern.
- Operand:
- 0: names this instruction.
- If the name is the null string, the instruction is in the
- machine description just to be recognized, and will never be emitted by
- the tree to rtl expander.
- 1: is the pattern.
- 2: is a string which is a C expression
- giving an additional condition for recognizing this pattern.
- A null string means no extra condition.
- 3: is the action to execute if this pattern is matched.
- If this assembler code template starts with a * then it is a fragment of
- C code to run to decide on a template to use. Otherwise, it is the
- template to use.
- 4: C expression that must be true for split. This may start with "&&"
- in which case the split condition is the logical and of the insn
- condition and what follows the "&&" of this operand.
- 5: vector of insn patterns to place into a SEQUENCE
- 6: optionally, some C code to execute before generating the
- insns. This might, for example, create some RTX's and store them in
- elements of `recog_data.operand' for use by the vector of
- insn-patterns.
- (`operands' is an alias here for `recog_data.operand').
- 7: optionally, a vector of attributes for this insn. */
-DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", 'x')
+/* A machine-specific operation.
+ 1st operand is a vector of operands being used by the operation so that
+ any needed reloads can be done.
+ 2nd operand is a unique value saying which of a number of machine-specific
+ operations is to be performed.
+ (Note that the vector must be the first operand because of the way that
+ genrecog.c record positions within an insn.)
-/* Definition of an RTL peephole operation.
- Follows the same arguments as define_split. */
-DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", 'x')
+ UNSPEC can occur all by itself in a PATTERN, as a component of a PARALLEL,
+ or inside an expression.
+ UNSPEC by itself or as a component of a PARALLEL
+ is currently considered not deletable.
-/* Definition of a combiner pattern.
- Operands not defined yet. */
-DEF_RTL_EXPR(DEFINE_COMBINE, "define_combine", "Ess", 'x')
+ FIXME: Replace all uses of UNSPEC that appears by itself or as a component
+ of a PARALLEL with USE.
+ */
+DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA)
-/* Define how to generate multiple insns for a standard insn name.
- 1st operand: the insn name.
- 2nd operand: vector of insn-patterns.
- Use match_operand to substitute an element of `recog_data.operand'.
- 3rd operand: C expression that must be true for this to be available.
- This may not test any operands.
- 4th operand: Extra C code to execute before generating the insns.
- This might, for example, create some RTX's and store them in
- elements of `recog_data.operand' for use by the vector of
- insn-patterns.
- (`operands' is an alias here for `recog_data.operand'). */
-DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", 'x')
-
-/* Define a requirement for delay slots.
- 1st operand: Condition involving insn attributes that, if true,
- indicates that the insn requires the number of delay slots
- shown.
- 2nd operand: Vector whose length is the three times the number of delay
- slots required.
- Each entry gives three conditions, each involving attributes.
- The first must be true for an insn to occupy that delay slot
- location. The second is true for all insns that can be
- annulled if the branch is true and the third is true for all
- insns that can be annulled if the branch is false.
+/* Similar, but a volatile operation and one which may trap. */
+DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA)
- Multiple DEFINE_DELAYs may be present. They indicate differing
- requirements for delay slots. */
-DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", 'x')
-
-/* Define a set of insns that requires a function unit. This means that
- these insns produce their result after a delay and that there may be
- restrictions on the number of insns of this type that can be scheduled
- simultaneously.
-
- More than one DEFINE_FUNCTION_UNIT can be specified for a function unit.
- Each gives a set of operations and associated delays. The first three
- operands must be the same for each operation for the same function unit.
-
- All delays are specified in cycles.
-
- 1st operand: Name of function unit (mostly for documentation)
- 2nd operand: Number of identical function units in CPU
- 3rd operand: Total number of simultaneous insns that can execute on this
- function unit; 0 if unlimited.
- 4th operand: Condition involving insn attribute, that, if true, specifies
- those insns that this expression applies to.
- 5th operand: Constant delay after which insn result will be
- available.
- 6th operand: Delay until next insn can be scheduled on the function unit
- executing this operation. The meaning depends on whether or
- not the next operand is supplied.
- 7th operand: If this operand is not specified, the 6th operand gives the
- number of cycles after the instruction matching the 4th
- operand begins using the function unit until a subsequent
- insn can begin. A value of zero should be used for a
- unit with no issue constraints. If only one operation can
- be executed a time and the unit is busy for the entire time,
- the 3rd operand should be specified as 1, the 6th operand
- should be specified as 0, and the 7th operand should not
- be specified.
-
- If this operand is specified, it is a list of attribute
- expressions. If an insn for which any of these expressions
- is true is currently executing on the function unit, the
- issue delay will be given by the 6th operand. Otherwise,
- the insn can be immediately scheduled (subject to the limit
- on the number of simultaneous operations executing on the
- unit.) */
-DEF_RTL_EXPR(DEFINE_FUNCTION_UNIT, "define_function_unit", "siieiiV", 'x')
+/* ----------------------------------------------------------------------
+ Table jump addresses.
+ ---------------------------------------------------------------------- */
-/* Define attribute computation for `asm' instructions. */
-DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", 'x' )
+/* Vector of addresses, stored as full words.
+ Each element is a LABEL_REF to a CODE_LABEL whose address we want. */
+DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA)
-/* Definition of a conditional execution meta operation. Automatically
- generates new instances of DEFINE_INSN, selected by having attribute
- "predicable" true. The new pattern will contain a COND_EXEC and the
- predicate at top-level.
+/* Vector of address differences X0 - BASE, X1 - BASE, ...
+ First operand is BASE; the vector contains the X's.
+ The machine mode of this rtx says how much space to leave
+ for each difference and is adjusted by branch shortening if
+ CASE_VECTOR_SHORTEN_MODE is defined.
+ The third and fourth operands store the target labels with the
+ minimum and maximum addresses respectively.
+ The fifth operand stores flags for use by branch shortening.
+ Set at the start of shorten_branches:
+ min_align: the minimum alignment for any of the target labels.
+ base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
+ min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
+ max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
+ min_after_base: true iff minimum address target label is after BASE.
+ max_after_base: true iff maximum address target label is after BASE.
+ Set by the actual branch shortening process:
+ offset_unsigned: true iff offsets have to be treated as unsigned.
+ scale: scaling that is necessary to make offsets fit into the mode.
- Operand:
- 0: The predicate pattern. The top-level form should match a
- relational operator. Operands should have only one alternative.
- 1: A C expression giving an additional condition for recognizing
- the generated pattern.
- 2: A template or C code to produce assembler output. */
-DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", 'x')
+ The third, fourth and fifth operands are only valid when
+ CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
+ compilation. */
+DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA)
-/* SEQUENCE appears in the result of a `gen_...' function
- for a DEFINE_EXPAND that wants to make several insns.
- Its elements are the bodies of the insns that should be made.
- `emit_insn' takes the SEQUENCE apart and makes separate insns. */
-DEF_RTL_EXPR(SEQUENCE, "sequence", "E", 'x')
+/* Memory prefetch, with attributes supported on some targets.
+ Operand 1 is the address of the memory to fetch.
+ Operand 2 is 1 for a write access, 0 otherwise.
+ Operand 3 is the level of temporal locality; 0 means there is no
+ temporal locality and 1, 2, and 3 are for increasing levels of temporal
+ locality.
-/* Refers to the address of its argument. This is only used in alias.c. */
-DEF_RTL_EXPR(ADDRESS, "address", "e", 'm')
+ The attributes specified by operands 2 and 3 are ignored for targets
+ whose prefetch instructions do not support them. */
+DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA)
/* ----------------------------------------------------------------------
- Constructions for CPU pipeline description described by NDFAs.
- These do not appear in actual rtl code in the compiler.
+ At the top level of an instruction (perhaps under PARALLEL).
---------------------------------------------------------------------- */
-/* (define_cpu_unit string [string]) describes cpu functional
- units (separated by comma).
+/* Assignment.
+ Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
+ Operand 2 is the value stored there.
+ ALL assignment must use SET.
+ Instructions that do multiple assignments must use multiple SET,
+ under PARALLEL. */
+DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA)
- 1st operand: Names of cpu functional units.
- 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
+/* Indicate something is used in a way that we don't want to explain.
+ For example, subroutine calls will use the register
+ in which the static chain is passed.
- All define_reservations, define_cpu_units, and
- define_query_cpu_units should have unique names which may not be
- "nothing". */
-DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", 'x')
+ USE can not appear as an operand of other rtx except for PARALLEL.
+ USE is not deletable, as it indicates that the operand
+ is used in some unknown way. */
+DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA)
-/* (define_query_cpu_unit string [string]) describes cpu functional
- units analogously to define_cpu_unit. The reservation of such
- units can be queried for automaton state. */
-DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", 'x')
+/* Indicate something is clobbered in a way that we don't want to explain.
+ For example, subroutine calls will clobber some physical registers
+ (the ones that are by convention not saved).
-/* (exclusion_set string string) means that each CPU functional unit
- in the first string can not be reserved simultaneously with any
- unit whose name is in the second string and vise versa. CPU units
- in the string are separated by commas. For example, it is useful
- for description CPU with fully pipelined floating point functional
- unit which can execute simultaneously only single floating point
- insns or only double floating point insns. All CPU functional
- units in a set should belong to the same automaton. */
-DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", 'x')
+ CLOBBER can not appear as an operand of other rtx except for PARALLEL.
+ CLOBBER of a hard register appearing by itself (not within PARALLEL)
+ is considered undeletable before reload. */
+DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA)
-/* (presence_set string string) means that each CPU functional unit in
- the first string can not be reserved unless at least one of pattern
- of units whose names are in the second string is reserved. This is
- an asymmetric relation. CPU units or unit patterns in the strings
- are separated by commas. Pattern is one unit name or unit names
- separated by white-spaces.
-
- For example, it is useful for description that slot1 is reserved
- after slot0 reservation for a VLIW processor. We could describe it
- by the following construction
+/* Call a subroutine.
+ Operand 1 is the address to call.
+ Operand 2 is the number of arguments. */
- (presence_set "slot1" "slot0")
+DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA)
- Or slot1 is reserved only after slot0 and unit b0 reservation. In
- this case we could write
-
- (presence_set "slot1" "slot0 b0")
+/* Return from a subroutine. */
- All CPU functional units in a set should belong to the same
- automaton. */
-DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", 'x')
+DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA)
-/* (final_presence_set string string) is analogous to `presence_set'.
- The difference between them is when checking is done. When an
- instruction is issued in given automaton state reflecting all
- current and planned unit reservations, the automaton state is
- changed. The first state is a source state, the second one is a
- result state. Checking for `presence_set' is done on the source
- state reservation, checking for `final_presence_set' is done on the
- result reservation. This construction is useful to describe a
- reservation which is actually two subsequent reservations. For
- example, if we use
+/* Like RETURN, but truly represents only a function return, while
+ RETURN may represent an insn that also performs other functions
+ of the function epilogue. Like RETURN, this may also occur in
+ conditional jumps. */
+DEF_RTL_EXPR(SIMPLE_RETURN, "simple_return", "", RTX_EXTRA)
- (presence_set "slot1" "slot0")
+/* Special for EH return from subroutine. */
- the following insn will be never issued (because slot1 requires
- slot0 which is absent in the source state).
+DEF_RTL_EXPR(EH_RETURN, "eh_return", "", RTX_EXTRA)
- (define_reservation "insn_and_nop" "slot0 + slot1")
+/* Conditional trap.
+ Operand 1 is the condition.
+ Operand 2 is the trap code.
+ For an unconditional trap, make the condition (const_int 1). */
+DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA)
- but it can be issued if we use analogous `final_presence_set'. */
-DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", 'x')
+/* ----------------------------------------------------------------------
+ Primitive values for use in expressions.
+ ---------------------------------------------------------------------- */
-/* (absence_set string string) means that each CPU functional unit in
- the first string can be reserved only if each pattern of units
- whose names are in the second string is not reserved. This is an
- asymmetric relation (actually exclusion set is analogous to this
- one but it is symmetric). CPU units or unit patterns in the string
- are separated by commas. Pattern is one unit name or unit names
- separated by white-spaces.
+/* numeric integer constant */
+DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ)
- For example, it is useful for description that slot0 can not be
- reserved after slot1 or slot2 reservation for a VLIW processor. We
- could describe it by the following construction
+/* numeric integer constant */
+DEF_RTL_EXPR(CONST_WIDE_INT, "const_wide_int", "", RTX_CONST_OBJ)
- (absence_set "slot2" "slot0, slot1")
+/* fixed-point constant */
+DEF_RTL_EXPR(CONST_FIXED, "const_fixed", "www", RTX_CONST_OBJ)
- Or slot2 can not be reserved if slot0 and unit b0 are reserved or
- slot1 and unit b1 are reserved . In this case we could write
+/* numeric floating point or integer constant. If the mode is
+ VOIDmode it is an int otherwise it has a floating point mode and a
+ floating point value. Operands hold the value. They are all 'w'
+ and there may be from 2 to 6; see real.h. */
+DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ)
- (absence_set "slot2" "slot0 b0, slot1 b1")
+/* Describes a vector constant. */
+DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_CONST_OBJ)
- All CPU functional units in a set should to belong the same
- automaton. */
-DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", 'x')
+/* String constant. Used for attributes in machine descriptions and
+ for special cases in DWARF2 debug output. NOT used for source-
+ language string constants. */
+DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ)
-/* (final_absence_set string string) is analogous to `absence_set' but
- checking is done on the result (state) reservation. See comments
- for `final_presence_set'. */
-DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", 'x')
+/* This is used to encapsulate an expression whose value is constant
+ (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
+ recognized as a constant operand rather than by arithmetic instructions. */
-/* (define_bypass number out_insn_names in_insn_names) names bypass
- with given latency (the first number) from insns given by the first
- string (see define_insn_reservation) into insns given by the second
- string. Insn names in the strings are separated by commas. The
- third operand is optional name of function which is additional
- guard for the bypass. The function will get the two insns as
- parameters. If the function returns zero the bypass will be
- ignored for this case. Additional guard is necessary to recognize
- complicated bypasses, e.g. when consumer is load address. */
-DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", 'x')
+DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ)
-/* (define_automaton string) describes names of automata generated and
- used for pipeline hazards recognition. The names are separated by
- comma. Actually it is possibly to generate the single automaton
- but unfortunately it can be very large. If we use more one
- automata, the summary size of the automata usually is less than the
- single one. The automaton name is used in define_cpu_unit and
- define_query_cpu_unit. All automata should have unique names. */
-DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", 'x')
+/* program counter. Ordinary jumps are represented
+ by a SET whose first operand is (PC). */
+DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ)
-/* (automata_option string) describes option for generation of
- automata. Currently there are the following options:
+/* A register. The "operand" is the register number, accessed with
+ the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
+ than a hardware register is being referred to. The second operand
+ points to a reg_attrs structure.
+ This rtx needs to have as many (or more) fields as a MEM, since we
+ can change REG rtx's into MEMs during reload. */
+DEF_RTL_EXPR(REG, "reg", "r", RTX_OBJ)
- o "no-minimization" which makes no minimization of automata. This
- is only worth to do when we are debugging the description and
- need to look more accurately at reservations of states.
+/* A scratch register. This represents a register used only within a
+ single insn. It will be replaced by a REG during register allocation
+ or reload unless the constraint indicates that the register won't be
+ needed, in which case it can remain a SCRATCH. */
+DEF_RTL_EXPR(SCRATCH, "scratch", "", RTX_OBJ)
- o "time" which means printing additional time statistics about
- generation of automata.
-
- o "v" which means generation of file describing the result
- automata. The file has suffix `.dfa' and can be used for the
- description verification and debugging.
+/* A reference to a part of another value. The first operand is the
+ complete value and the second is the byte offset of the selected part. */
+DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA)
- o "w" which means generation of warning instead of error for
- non-critical errors.
+/* This one-argument rtx is used for move instructions
+ that are guaranteed to alter only the low part of a destination.
+ Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
+ has an unspecified effect on the high part of REG,
+ but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
+ is guaranteed to alter only the bits of REG that are in HImode.
- o "ndfa" which makes nondeterministic finite state automata. */
-DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", 'x')
+ The actual instruction used is probably the same in both cases,
+ but the register constraints may be tighter when STRICT_LOW_PART
+ is in use. */
-/* (define_reservation string string) names reservation (the first
- string) of cpu functional units (the 2nd string). Sometimes unit
- reservations for different insns contain common parts. In such
- case, you can describe common part and use its name (the 1st
- parameter) in regular expression in define_insn_reservation. All
- define_reservations, define_cpu_units, and define_query_cpu_units
- should have unique names which may not be "nothing". */
-DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", 'x')
+DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA)
-/* (define_insn_reservation name default_latency condition regexpr)
- describes reservation of cpu functional units (the 3nd operand) for
- instruction which is selected by the condition (the 2nd parameter).
- The first parameter is used for output of debugging information.
- The reservations are described by a regular expression according
- the following syntax:
+/* (CONCAT a b) represents the virtual concatenation of a and b
+ to make a value that has as many bits as a and b put together.
+ This is used for complex values. Normally it appears only
+ in DECL_RTLs and during RTL generation, but not in the insn chain. */
+DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ)
- regexp = regexp "," oneof
- | oneof
+/* (CONCATN [a1 a2 ... an]) represents the virtual concatenation of
+ all An to make a value. This is an extension of CONCAT to larger
+ number of components. Like CONCAT, it should not appear in the
+ insn chain. Every element of the CONCATN is the same size. */
+DEF_RTL_EXPR(CONCATN, "concatn", "E", RTX_OBJ)
- oneof = oneof "|" allof
- | allof
+/* A memory location; operand is the address. The second operand is the
+ alias set to which this MEM belongs. We use `0' instead of `w' for this
+ field so that the field need not be specified in machine descriptions. */
+DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ)
- allof = allof "+" repeat
- | repeat
-
- repeat = element "*" number
- | element
+/* Reference to an assembler label in the code for this function.
+ The operand is a CODE_LABEL found in the insn chain. */
+DEF_RTL_EXPR(LABEL_REF, "label_ref", "u", RTX_CONST_OBJ)
- element = cpu_function_unit_name
- | reservation_name
- | result_name
- | "nothing"
- | "(" regexp ")"
+/* Reference to a named label:
+ Operand 0: label name
+ Operand 1: tree from which this symbol is derived, or null.
+ This is either a DECL node, or some kind of constant. */
+DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s0", RTX_CONST_OBJ)
- 1. "," is used for describing start of the next cycle in
- reservation.
+/* The condition code register is represented, in our imagination,
+ as a register holding a value that can be compared to zero.
+ In fact, the machine has already compared them and recorded the
+ results; but instructions that look at the condition code
+ pretend to be looking at the entire value and comparing it. */
+DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ)
- 2. "|" is used for describing the reservation described by the
- first regular expression *or* the reservation described by the
- second regular expression *or* etc.
+/* ----------------------------------------------------------------------
+ Expressions for operators in an rtl pattern
+ ---------------------------------------------------------------------- */
- 3. "+" is used for describing the reservation described by the
- first regular expression *and* the reservation described by the
- second regular expression *and* etc.
+/* if_then_else. This is used in representing ordinary
+ conditional jump instructions.
+ Operand:
+ 0: condition
+ 1: then expr
+ 2: else expr */
+DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY)
- 4. "*" is used for convenience and simply means sequence in
- which the regular expression are repeated NUMBER times with
- cycle advancing (see ",").
+/* Comparison, produces a condition code result. */
+DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH)
- 5. cpu functional unit name which means its reservation.
+/* plus */
+DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH)
- 6. reservation name -- see define_reservation.
+/* Operand 0 minus operand 1. */
+DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH)
- 7. string "nothing" means no units reservation. */
+/* Minus operand 0. */
+DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY)
-DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", 'x')
+DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH)
-/* ----------------------------------------------------------------------
- Expressions used for insn attributes. These also do not appear in
- actual rtl code in the compiler.
- ---------------------------------------------------------------------- */
+/* Multiplication with signed saturation */
+DEF_RTL_EXPR(SS_MULT, "ss_mult", "ee", RTX_COMM_ARITH)
+/* Multiplication with unsigned saturation */
+DEF_RTL_EXPR(US_MULT, "us_mult", "ee", RTX_COMM_ARITH)
-/* Definition of an insn attribute.
- 1st operand: name of the attribute
- 2nd operand: comma-separated list of possible attribute values
- 3rd operand: expression for the default value of the attribute. */
-DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", 'x')
+/* Operand 0 divided by operand 1. */
+DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH)
+/* Division with signed saturation */
+DEF_RTL_EXPR(SS_DIV, "ss_div", "ee", RTX_BIN_ARITH)
+/* Division with unsigned saturation */
+DEF_RTL_EXPR(US_DIV, "us_div", "ee", RTX_BIN_ARITH)
-/* Marker for the name of an attribute. */
-DEF_RTL_EXPR(ATTR, "attr", "s", 'x')
+/* Remainder of operand 0 divided by operand 1. */
+DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH)
-/* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
- in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
- pattern.
+/* Unsigned divide and remainder. */
+DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH)
+DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH)
- (set_attr "name" "value") is equivalent to
- (set (attr "name") (const_string "value")) */
-DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", 'x')
+/* Bitwise operations. */
+DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH)
+DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH)
+DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH)
+DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY)
-/* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
- specify that attribute values are to be assigned according to the
- alternative matched.
+/* Operand:
+ 0: value to be shifted.
+ 1: number of bits. */
+DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */
+DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */
+DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */
+DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */
+DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */
- The following three expressions are equivalent:
+/* Minimum and maximum values of two operands. We need both signed and
+ unsigned forms. (We cannot use MIN for SMIN because it conflicts
+ with a macro of the same name.) The signed variants should be used
+ with floating point. Further, if both operands are zeros, or if either
+ operand is NaN, then it is unspecified which of the two operands is
+ returned as the result. */
- (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
- (eq_attrq "alternative" "2") (const_string "a2")]
- (const_string "a3")))
- (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
- (const_string "a3")])
- (set_attr "att" "a1,a2,a3")
- */
-DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", 'x')
+DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH)
+DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH)
+DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH)
+DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH)
-/* A conditional expression true if the value of the specified attribute of
- the current insn equals the specified value. The first operand is the
- attribute name and the second is the comparison value. */
-DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", 'x')
+/* These unary operations are used to represent incrementation
+ and decrementation as they occur in memory addresses.
+ The amount of increment or decrement are not represented
+ because they can be understood from the machine-mode of the
+ containing MEM. These operations exist in only two cases:
+ 1. pushes onto the stack.
+ 2. created automatically by the auto-inc-dec pass. */
+DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC)
+DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC)
+DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC)
+DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC)
-/* A conditional expression which is true if the specified flag is
- true for the insn being scheduled in reorg.
+/* These binary operations are used to represent generic address
+ side-effects in memory addresses, except for simple incrementation
+ or decrementation which use the above operations. They are
+ created automatically by the life_analysis pass in flow.c.
+ The first operand is a REG which is used as the address.
+ The second operand is an expression that is assigned to the
+ register, either before (PRE_MODIFY) or after (POST_MODIFY)
+ evaluating the address.
+ Currently, the compiler can only handle second operands of the
+ form (plus (reg) (reg)) and (plus (reg) (const_int)), where
+ the first operand of the PLUS has to be the same register as
+ the first operand of the *_MODIFY. */
+DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC)
+DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC)
- genattr.c defines the following flags which can be tested by
- (attr_flag "foo") expressions in eligible_for_delay.
+/* Comparison operations. The ordered comparisons exist in two
+ flavors, signed and unsigned. */
+DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE)
+DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE)
+DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE)
+DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE)
+DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE)
+DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE)
+DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE)
+DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE)
+DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE)
+DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE)
- forward, backward, very_likely, likely, very_unlikely, and unlikely. */
+/* Additional floating point unordered comparison flavors. */
+DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE)
+DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE)
-DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", 'x')
+/* These are equivalent to unordered or ... */
+DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE)
+DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE)
+DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE)
+DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE)
+DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE)
-/* ----------------------------------------------------------------------
- Expression types used for things in the instruction chain.
+/* This is an ordered NE, ie !UNEQ, ie false for NaN. */
+DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE)
- All formats must start with "iuu" to handle the chain.
- Each insn expression holds an rtl instruction and its semantics
- during back-end processing.
- See macros's in "rtl.h" for the meaning of each rtx->fld[].
+/* Represents the result of sign-extending the sole operand.
+ The machine modes of the operand and of the SIGN_EXTEND expression
+ determine how much sign-extension is going on. */
+DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY)
- ---------------------------------------------------------------------- */
+/* Similar for zero-extension (such as unsigned short to int). */
+DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY)
-/* An instruction that cannot jump. */
-DEF_RTL_EXPR(INSN, "insn", "iuuBieiee", 'i')
+/* Similar but here the operand has a wider mode. */
+DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY)
-/* An instruction that can possibly jump.
- Fields ( rtx->fld[] ) have exact same meaning as INSN's. */
-DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBieiee0", 'i')
+/* Similar for extending floating-point values (such as SFmode to DFmode). */
+DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY)
+DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY)
-/* An instruction that can possibly call a subroutine
- but which will not change which instruction comes next
- in the current function.
- Field ( rtx->fld[9] ) is CALL_INSN_FUNCTION_USAGE.
- All other fields ( rtx->fld[] ) have exact same meaning as INSN's. */
-DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBieieee", 'i')
+/* Conversion of fixed point operand to floating point value. */
+DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY)
-/* A marker that indicates that control will not flow through. */
-DEF_RTL_EXPR(BARRIER, "barrier", "iuu000000", 'x')
+/* With fixed-point machine mode:
+ Conversion of floating point operand to fixed point value.
+ Value is defined only when the operand's value is an integer.
+ With floating-point machine mode (and operand with same mode):
+ Operand is rounded toward zero to produce an integer value
+ represented in floating point. */
+DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY)
-/* Holds a label that is followed by instructions.
- Operand:
- 5: is used in jump.c for the use-count of the label.
- 6: is used in flow.c to point to the chain of label_ref's to this label.
- 7: is a number that is unique in the entire compilation.
- 8: is the user-given name of the label, if any. */
-DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", 'x')
+/* Conversion of unsigned fixed point operand to floating point value. */
+DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY)
-/* Say where in the code a source line starts, for symbol table's sake.
- Operand:
- 5: filename, if line number > 0, note-specific data otherwise.
- 6: line number if > 0, enum note_insn otherwise.
- 7: unique number if line number == note_insn_deleted_label.
- 8-9: padding so that notes and insns are the same size, and thus
- allocated from the same page ordering. */
-DEF_RTL_EXPR(NOTE, "note", "iuuB0ni00", 'x')
+/* With fixed-point machine mode:
+ Conversion of floating point operand to *unsigned* fixed point value.
+ Value is defined only when the operand's value is an integer. */
+DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY)
+
+/* Conversions involving fractional fixed-point types without saturation,
+ including:
+ fractional to fractional (of different precision),
+ signed integer to fractional,
+ fractional to signed integer,
+ floating point to fractional,
+ fractional to floating point.
+ NOTE: fractional can be either signed or unsigned for conversions. */
+DEF_RTL_EXPR(FRACT_CONVERT, "fract_convert", "e", RTX_UNARY)
+
+/* Conversions involving fractional fixed-point types and unsigned integer
+ without saturation, including:
+ unsigned integer to fractional,
+ fractional to unsigned integer.
+ NOTE: fractional can be either signed or unsigned for conversions. */
+DEF_RTL_EXPR(UNSIGNED_FRACT_CONVERT, "unsigned_fract_convert", "e", RTX_UNARY)
+
+/* Conversions involving fractional fixed-point types with saturation,
+ including:
+ fractional to fractional (of different precision),
+ signed integer to fractional,
+ floating point to fractional.
+ NOTE: fractional can be either signed or unsigned for conversions. */
+DEF_RTL_EXPR(SAT_FRACT, "sat_fract", "e", RTX_UNARY)
+
+/* Conversions involving fractional fixed-point types and unsigned integer
+ with saturation, including:
+ unsigned integer to fractional.
+ NOTE: fractional can be either signed or unsigned for conversions. */
+DEF_RTL_EXPR(UNSIGNED_SAT_FRACT, "unsigned_sat_fract", "e", RTX_UNARY)
-/* ----------------------------------------------------------------------
- Top level constituents of INSN, JUMP_INSN and CALL_INSN.
- ---------------------------------------------------------------------- */
-
-/* Conditionally execute code.
- Operand 0 is the condition that if true, the code is executed.
- Operand 1 is the code to be executed (typically a SET).
+/* Absolute value */
+DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY)
- Semantics are that there are no side effects if the condition
- is false. This pattern is created automatically by the if_convert
- pass run after reload or by target-specific splitters. */
-DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", 'x')
+/* Square root */
+DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY)
-/* Several operations to be done in parallel (perhaps under COND_EXEC). */
-DEF_RTL_EXPR(PARALLEL, "parallel", "E", 'x')
+/* Swap bytes. */
+DEF_RTL_EXPR(BSWAP, "bswap", "e", RTX_UNARY)
-/* A string that is passed through to the assembler as input.
- One can obviously pass comments through by using the
- assembler comment syntax.
- These occur in an insn all by themselves as the PATTERN.
- They also appear inside an ASM_OPERANDS
- as a convenient way to hold a string. */
-DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", 'x')
+/* Find first bit that is set.
+ Value is 1 + number of trailing zeros in the arg.,
+ or 0 if arg is 0. */
+DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY)
-/* An assembler instruction with operands.
- 1st operand is the instruction template.
- 2nd operand is the constraint for the output.
- 3rd operand is the number of the output this expression refers to.
- When an insn stores more than one value, a separate ASM_OPERANDS
- is made for each output; this integer distinguishes them.
- 4th is a vector of values of input operands.
- 5th is a vector of modes and constraints for the input operands.
- Each element is an ASM_INPUT containing a constraint string
- and whose mode indicates the mode of the input operand.
- 6th is the name of the containing source file.
- 7th is the source line number. */
-DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", 'x')
+/* Count number of leading redundant sign bits (number of leading
+ sign bits minus one). */
+DEF_RTL_EXPR(CLRSB, "clrsb", "e", RTX_UNARY)
-/* A machine-specific operation.
- 1st operand is a vector of operands being used by the operation so that
- any needed reloads can be done.
- 2nd operand is a unique value saying which of a number of machine-specific
- operations is to be performed.
- (Note that the vector must be the first operand because of the way that
- genrecog.c record positions within an insn.)
- This can occur all by itself in a PATTERN, as a component of a PARALLEL,
- or inside an expression. */
-DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", 'x')
+/* Count leading zeros. */
+DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY)
-/* Similar, but a volatile operation and one which may trap. */
-DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", 'x')
+/* Count trailing zeros. */
+DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY)
-/* Vector of addresses, stored as full words. */
-/* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */
-DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", 'x')
+/* Population count (number of 1 bits). */
+DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY)
-/* Vector of address differences X0 - BASE, X1 - BASE, ...
- First operand is BASE; the vector contains the X's.
- The machine mode of this rtx says how much space to leave
- for each difference and is adjusted by branch shortening if
- CASE_VECTOR_SHORTEN_MODE is defined.
- The third and fourth operands store the target labels with the
- minimum and maximum addresses respectively.
- The fifth operand stores flags for use by branch shortening.
- Set at the start of shorten_branches:
- min_align: the minimum alignment for any of the target labels.
- base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
- min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
- max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
- min_after_base: true iff minimum address target label is after BASE.
- max_after_base: true iff maximum address target label is after BASE.
- Set by the actual branch shortening process:
- offset_unsigned: true iff offsets have to be treated as unsigned.
- scale: scaling that is necessary to make offsets fit into the mode.
+/* Population parity (number of 1 bits modulo 2). */
+DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY)
- The third, fourth and fifth operands are only valid when
- CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
- compilations. */
-
-DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", 'x')
+/* Reference to a signed bit-field of specified size and position.
+ Operand 0 is the memory unit (usually SImode or QImode) which
+ contains the field's first bit. Operand 1 is the width, in bits.
+ Operand 2 is the number of bits in the memory unit before the
+ first bit of this field.
+ If BITS_BIG_ENDIAN is defined, the first bit is the msb and
+ operand 2 counts from the msb of the memory unit.
+ Otherwise, the first bit is the lsb and operand 2 counts from
+ the lsb of the memory unit.
+ This kind of expression can not appear as an lvalue in RTL. */
+DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS)
-/* Memory prefetch, with attributes supported on some targets.
- Operand 1 is the address of the memory to fetch.
- Operand 2 is 1 for a write access, 0 otherwise.
- Operand 3 is the level of temporal locality; 0 means there is no
- temporal locality and 1, 2, and 3 are for increasing levels of temporal
- locality.
+/* Similar for unsigned bit-field.
+ But note! This kind of expression _can_ appear as an lvalue. */
+DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS)
- The attributes specified by operands 2 and 3 are ignored for targets
- whose prefetch instructions do not support them. */
-DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", 'x')
+/* For RISC machines. These save memory when splitting insns. */
-/* ----------------------------------------------------------------------
- At the top level of an instruction (perhaps under PARALLEL).
- ---------------------------------------------------------------------- */
+/* HIGH are the high-order bits of a constant expression. */
+DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ)
-/* Assignment.
- Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
- Operand 2 is the value stored there.
- ALL assignment must use SET.
- Instructions that do multiple assignments must use multiple SET,
- under PARALLEL. */
-DEF_RTL_EXPR(SET, "set", "ee", 'x')
+/* LO_SUM is the sum of a register and the low-order bits
+ of a constant expression. */
+DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ)
-/* Indicate something is used in a way that we don't want to explain.
- For example, subroutine calls will use the register
- in which the static chain is passed. */
-DEF_RTL_EXPR(USE, "use", "e", 'x')
+/* Describes a merge operation between two vector values.
+ Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
+ that specifies where the parts of the result are taken from. Set bits
+ indicate operand 0, clear bits indicate operand 1. The parts are defined
+ by the mode of the vectors. */
+DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY)
-/* Indicate something is clobbered in a way that we don't want to explain.
- For example, subroutine calls will clobber some physical registers
- (the ones that are by convention not saved). */
-DEF_RTL_EXPR(CLOBBER, "clobber", "e", 'x')
+/* Describes an operation that selects parts of a vector.
+ Operands 0 is the source vector, operand 1 is a PARALLEL that contains
+ a CONST_INT for each of the subparts of the result vector, giving the
+ number of the source subpart that should be stored into it. */
+DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH)
-/* Call a subroutine.
- Operand 1 is the address to call.
- Operand 2 is the number of arguments. */
+/* Describes a vector concat operation. Operands 0 and 1 are the source
+ vectors, the result is a vector that is as long as operands 0 and 1
+ combined and is the concatenation of the two source vectors. */
+DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH)
-DEF_RTL_EXPR(CALL, "call", "ee", 'x')
+/* Describes an operation that converts a small vector into a larger one by
+ duplicating the input values. The output vector mode must have the same
+ submodes as the input vector mode, and the number of output parts must be
+ an integer multiple of the number of input parts. */
+DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY)
-/* Return from a subroutine. */
+/* Addition with signed saturation */
+DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH)
-DEF_RTL_EXPR(RETURN, "return", "", 'x')
+/* Addition with unsigned saturation */
+DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH)
-/* Conditional trap.
- Operand 1 is the condition.
- Operand 2 is the trap code.
- For an unconditional trap, make the condition (const_int 1). */
-DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", 'x')
+/* Operand 0 minus operand 1, with signed saturation. */
+DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH)
-/* Placeholder for _Unwind_Resume before we know if a function call
- or a branch is needed. Operand 1 is the exception region from
- which control is flowing. */
-DEF_RTL_EXPR(RESX, "resx", "i", 'x')
+/* Negation with signed saturation. */
+DEF_RTL_EXPR(SS_NEG, "ss_neg", "e", RTX_UNARY)
+/* Negation with unsigned saturation. */
+DEF_RTL_EXPR(US_NEG, "us_neg", "e", RTX_UNARY)
-/* ----------------------------------------------------------------------
- Primitive values for use in expressions.
- ---------------------------------------------------------------------- */
+/* Absolute value with signed saturation. */
+DEF_RTL_EXPR(SS_ABS, "ss_abs", "e", RTX_UNARY)
-/* numeric integer constant */
-DEF_RTL_EXPR(CONST_INT, "const_int", "w", 'o')
+/* Shift left with signed saturation. */
+DEF_RTL_EXPR(SS_ASHIFT, "ss_ashift", "ee", RTX_BIN_ARITH)
-/* numeric floating point constant.
- Operands hold the value. They are all 'w' and there may be from 2 to 6;
- see real.h. */
-DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, 'o')
+/* Shift left with unsigned saturation. */
+DEF_RTL_EXPR(US_ASHIFT, "us_ashift", "ee", RTX_BIN_ARITH)
-/* Describes a vector constant. */
-DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", 'x')
+/* Operand 0 minus operand 1, with unsigned saturation. */
+DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH)
-/* String constant. Used only for attributes right now. */
-DEF_RTL_EXPR(CONST_STRING, "const_string", "s", 'o')
+/* Signed saturating truncate. */
+DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY)
-/* This is used to encapsulate an expression whose value is constant
- (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
- recognized as a constant operand rather than by arithmetic instructions. */
+/* Unsigned saturating truncate. */
+DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY)
-DEF_RTL_EXPR(CONST, "const", "e", 'o')
+/* Floating point multiply/add combined instruction. */
+DEF_RTL_EXPR(FMA, "fma", "eee", RTX_TERNARY)
-/* program counter. Ordinary jumps are represented
- by a SET whose first operand is (PC). */
-DEF_RTL_EXPR(PC, "pc", "", 'o')
+/* Information about the variable and its location. */
+DEF_RTL_EXPR(VAR_LOCATION, "var_location", "te", RTX_EXTRA)
-/* Used in the cselib routines to describe a value. */
-DEF_RTL_EXPR(VALUE, "value", "0", 'o')
+/* Used in VAR_LOCATION for a pointer to a decl that is no longer
+ addressable. */
+DEF_RTL_EXPR(DEBUG_IMPLICIT_PTR, "debug_implicit_ptr", "t", RTX_OBJ)
-/* A register. The "operand" is the register number, accessed with
- the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
- than a hardware register is being referred to. The second operand
- holds the original register number - this will be different for a
- pseudo register that got turned into a hard register.
- This rtx needs to have as many (or more) fields as a MEM, since we
- can change REG rtx's into MEMs during reload. */
-DEF_RTL_EXPR(REG, "reg", "i00", 'o')
+/* Represents value that argument had on function entry. The
+ single argument is the DECL_INCOMING_RTL of the corresponding
+ parameter. */
+DEF_RTL_EXPR(ENTRY_VALUE, "entry_value", "0", RTX_OBJ)
-/* A scratch register. This represents a register used only within a
- single insn. It will be turned into a REG during register allocation
- or reload unless the constraint indicates that the register won't be
- needed, in which case it can remain a SCRATCH. This code is
- marked as having one operand so it can be turned into a REG. */
-DEF_RTL_EXPR(SCRATCH, "scratch", "0", 'o')
+/* Used in VAR_LOCATION for a reference to a parameter that has
+ been optimized away completely. */
+DEF_RTL_EXPR(DEBUG_PARAMETER_REF, "debug_parameter_ref", "t", RTX_OBJ)
-/* One word of a multi-word value.
- The first operand is the complete value; the second says which word.
- The WORDS_BIG_ENDIAN flag controls whether word number 0
- (as numbered in a SUBREG) is the most or least significant word.
+/* All expressions from this point forward appear only in machine
+ descriptions. */
+#ifdef GENERATOR_FILE
- This is also used to refer to a value in a different machine mode.
- For example, it can be used to refer to a SImode value as if it were
- Qimode, or vice versa. Then the word number is always 0. */
-DEF_RTL_EXPR(SUBREG, "subreg", "ei", 'x')
+/* Pattern-matching operators: */
-/* This one-argument rtx is used for move instructions
- that are guaranteed to alter only the low part of a destination.
- Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
- has an unspecified effect on the high part of REG,
- but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
- is guaranteed to alter only the bits of REG that are in HImode.
+/* Use the function named by the second arg (the string)
+ as a predicate; if matched, store the structure that was matched
+ in the operand table at index specified by the first arg (the integer).
+ If the second arg is the null string, the structure is just stored.
- The actual instruction used is probably the same in both cases,
- but the register constraints may be tighter when STRICT_LOW_PART
- is in use. */
+ A third string argument indicates to the register allocator restrictions
+ on where the operand can be allocated.
-DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", 'x')
+ If the target needs no restriction on any instruction this field should
+ be the null string.
-/* (CONCAT a b) represents the virtual concatenation of a and b
- to make a value that has as many bits as a and b put together.
- This is used for complex values. Normally it appears only
- in DECL_RTLs and during RTL generation, but not in the insn chain. */
-DEF_RTL_EXPR(CONCAT, "concat", "ee", 'o')
+ The string is prepended by:
+ '=' to indicate the operand is only written to.
+ '+' to indicate the operand is both read and written to.
-/* A memory location; operand is the address. The second operand is the
- alias set to which this MEM belongs. We use `0' instead of `w' for this
- field so that the field need not be specified in machine descriptions. */
-DEF_RTL_EXPR(MEM, "mem", "e0", 'o')
+ Each character in the string represents an allocable class for an operand.
+ 'g' indicates the operand can be any valid class.
+ 'i' indicates the operand can be immediate (in the instruction) data.
+ 'r' indicates the operand can be in a register.
+ 'm' indicates the operand can be in memory.
+ 'o' a subset of the 'm' class. Those memory addressing modes that
+ can be offset at compile time (have a constant added to them).
-/* Reference to an assembler label in the code for this function.
- The operand is a CODE_LABEL found in the insn chain.
- The unprinted fields 1 and 2 are used in flow.c for the
- LABEL_NEXTREF and CONTAINING_INSN. */
-DEF_RTL_EXPR(LABEL_REF, "label_ref", "u00", 'o')
+ Other characters indicate target dependent operand classes and
+ are described in each target's machine description.
-/* Reference to a named label:
- Operand 0: label name
- Operand 1: flags (see SYMBOL_FLAG_* in rtl.h)
- Operand 2: tree from which this symbol is derived, or null.
- This is either a DECL node, or some kind of constant. */
-DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", 'o')
+ For instructions with more than one operand, sets of classes can be
+ separated by a comma to indicate the appropriate multi-operand constraints.
+ There must be a 1 to 1 correspondence between these sets of classes in
+ all operands for an instruction.
+ */
+DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH)
-/* The condition code register is represented, in our imagination,
- as a register holding a value that can be compared to zero.
- In fact, the machine has already compared them and recorded the
- results; but instructions that look at the condition code
- pretend to be looking at the entire value and comparing it. */
-DEF_RTL_EXPR(CC0, "cc0", "", 'o')
-
-/* Reference to the address of a register. Removed by purge_addressof after
- CSE has elided as many as possible.
- 1st operand: the register we may need the address of.
- 2nd operand: the original pseudo regno we were generated for.
- 3rd operand: the decl for the object in the register, for
- put_reg_in_stack. */
-
-DEF_RTL_EXPR(ADDRESSOF, "addressof", "eit", 'o')
-
-/* =====================================================================
- A QUEUED expression really points to a member of the queue of instructions
- to be output later for postincrement/postdecrement.
- QUEUED expressions never become part of instructions.
- When a QUEUED expression would be put into an instruction,
- instead either the incremented variable or a copy of its previous
- value is used.
-
- Operands are:
- 0. the variable to be incremented (a REG rtx).
- 1. the incrementing instruction, or 0 if it hasn't been output yet.
- 2. A REG rtx for a copy of the old value of the variable, or 0 if none yet.
- 3. the body to use for the incrementing instruction
- 4. the next QUEUED expression in the queue.
- ====================================================================== */
-
-DEF_RTL_EXPR(QUEUED, "queued", "eeeee", 'x')
+/* Match a SCRATCH or a register. When used to generate rtl, a
+ SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
+ the desired mode and the first argument is the operand number.
+ The second argument is the constraint. */
+DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH)
+
+/* Apply a predicate, AND match recursively the operands of the rtx.
+ Operand 0 is the operand-number, as in match_operand.
+ Operand 1 is a predicate to apply (as a string, a function name).
+ Operand 2 is a vector of expressions, each of which must match
+ one subexpression of the rtx this construct is matching. */
+DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH)
+
+/* Match a PARALLEL of arbitrary length. The predicate is applied
+ to the PARALLEL and the initial expressions in the PARALLEL are matched.
+ Operand 0 is the operand-number, as in match_operand.
+ Operand 1 is a predicate to apply to the PARALLEL.
+ Operand 2 is a vector of expressions, each of which must match the
+ corresponding element in the PARALLEL. */
+DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH)
+
+/* Match only something equal to what is stored in the operand table
+ at the index specified by the argument. Use with MATCH_OPERAND. */
+DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH)
+
+/* Match only something equal to what is stored in the operand table
+ at the index specified by the argument. Use with MATCH_OPERATOR. */
+DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH)
+
+/* Match only something equal to what is stored in the operand table
+ at the index specified by the argument. Use with MATCH_PARALLEL. */
+DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH)
+
+/* Appears only in define_predicate/define_special_predicate
+ expressions. Evaluates true only if the operand has an RTX code
+ from the set given by the argument (a comma-separated list). If the
+ second argument is present and nonempty, it is a sequence of digits
+ and/or letters which indicates the subexpression to test, using the
+ same syntax as genextract/genrecog's location strings: 0-9 for
+ XEXP (op, n), a-z for XVECEXP (op, 0, n); each character applies to
+ the result of the one before it. */
+DEF_RTL_EXPR(MATCH_CODE, "match_code", "ss", RTX_MATCH)
+
+/* Used to inject a C conditional expression into an .md file. It can
+ appear in a predicate definition or an attribute expression. */
+DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH)
+
+/* Insn (and related) definitions. */
+
+/* Definition of the pattern for one kind of instruction.
+ Operand:
+ 0: names this instruction.
+ If the name is the null string, the instruction is in the
+ machine description just to be recognized, and will never be emitted by
+ the tree to rtl expander.
+ 1: is the pattern.
+ 2: is a string which is a C expression
+ giving an additional condition for recognizing this pattern.
+ A null string means no extra condition.
+ 3: is the action to execute if this pattern is matched.
+ If this assembler code template starts with a * then it is a fragment of
+ C code to run to decide on a template to use. Otherwise, it is the
+ template to use.
+ 4: optionally, a vector of attributes for this insn.
+ */
+DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA)
+
+/* Definition of a peephole optimization.
+ 1st operand: vector of insn patterns to match
+ 2nd operand: C expression that must be true
+ 3rd operand: template or C code to produce assembler output.
+ 4: optionally, a vector of attributes for this insn.
+
+ This form is deprecated; use define_peephole2 instead. */
+DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA)
+
+/* Definition of a split operation.
+ 1st operand: insn pattern to match
+ 2nd operand: C expression that must be true
+ 3rd operand: vector of insn patterns to place into a SEQUENCE
+ 4th operand: optionally, some C code to execute before generating the
+ insns. This might, for example, create some RTX's and store them in
+ elements of `recog_data.operand' for use by the vector of
+ insn-patterns.
+ (`operands' is an alias here for `recog_data.operand'). */
+DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA)
+
+/* Definition of an insn and associated split.
+ This is the concatenation, with a few modifications, of a define_insn
+ and a define_split which share the same pattern.
+ Operand:
+ 0: names this instruction.
+ If the name is the null string, the instruction is in the
+ machine description just to be recognized, and will never be emitted by
+ the tree to rtl expander.
+ 1: is the pattern.
+ 2: is a string which is a C expression
+ giving an additional condition for recognizing this pattern.
+ A null string means no extra condition.
+ 3: is the action to execute if this pattern is matched.
+ If this assembler code template starts with a * then it is a fragment of
+ C code to run to decide on a template to use. Otherwise, it is the
+ template to use.
+ 4: C expression that must be true for split. This may start with "&&"
+ in which case the split condition is the logical and of the insn
+ condition and what follows the "&&" of this operand.
+ 5: vector of insn patterns to place into a SEQUENCE
+ 6: optionally, some C code to execute before generating the
+ insns. This might, for example, create some RTX's and store them in
+ elements of `recog_data.operand' for use by the vector of
+ insn-patterns.
+ (`operands' is an alias here for `recog_data.operand').
+ 7: optionally, a vector of attributes for this insn. */
+DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA)
+
+/* Definition of an RTL peephole operation.
+ Follows the same arguments as define_split. */
+DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA)
+
+/* Define how to generate multiple insns for a standard insn name.
+ 1st operand: the insn name.
+ 2nd operand: vector of insn-patterns.
+ Use match_operand to substitute an element of `recog_data.operand'.
+ 3rd operand: C expression that must be true for this to be available.
+ This may not test any operands.
+ 4th operand: Extra C code to execute before generating the insns.
+ This might, for example, create some RTX's and store them in
+ elements of `recog_data.operand' for use by the vector of
+ insn-patterns.
+ (`operands' is an alias here for `recog_data.operand').
+ 5th: optionally, a vector of attributes for this expand. */
+DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEssV", RTX_EXTRA)
+
+/* Define a requirement for delay slots.
+ 1st operand: Condition involving insn attributes that, if true,
+ indicates that the insn requires the number of delay slots
+ shown.
+ 2nd operand: Vector whose length is the three times the number of delay
+ slots required.
+ Each entry gives three conditions, each involving attributes.
+ The first must be true for an insn to occupy that delay slot
+ location. The second is true for all insns that can be
+ annulled if the branch is true and the third is true for all
+ insns that can be annulled if the branch is false.
+
+ Multiple DEFINE_DELAYs may be present. They indicate differing
+ requirements for delay slots. */
+DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA)
+
+/* Define attribute computation for `asm' instructions. */
+DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA)
+
+/* Definition of a conditional execution meta operation. Automatically
+ generates new instances of DEFINE_INSN, selected by having attribute
+ "predicable" true. The new pattern will contain a COND_EXEC and the
+ predicate at top-level.
+
+ Operand:
+ 0: The predicate pattern. The top-level form should match a
+ relational operator. Operands should have only one alternative.
+ 1: A C expression giving an additional condition for recognizing
+ the generated pattern.
+ 2: A template or C code to produce assembler output.
+ 3: A vector of attributes to append to the resulting cond_exec insn. */
+DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "EssV", RTX_EXTRA)
+
+/* Definition of an operand predicate. The difference between
+ DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will
+ not warn about a match_operand with no mode if it has a predicate
+ defined with DEFINE_SPECIAL_PREDICATE.
+
+ Operand:
+ 0: The name of the predicate.
+ 1: A boolean expression which computes whether or not the predicate
+ matches. This expression can use IOR, AND, NOT, MATCH_OPERAND,
+ MATCH_CODE, and MATCH_TEST. It must be specific enough that genrecog
+ can calculate the set of RTX codes that can possibly match.
+ 2: A C function body which must return true for the predicate to match.
+ Optional. Use this when the test is too complicated to fit into a
+ match_test expression. */
+DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA)
+DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA)
+
+/* Definition of a register operand constraint. This simply maps the
+ constraint string to a register class.
+
+ Operand:
+ 0: The name of the constraint (often, but not always, a single letter).
+ 1: A C expression which evaluates to the appropriate register class for
+ this constraint. If this is not just a constant, it should look only
+ at -m switches and the like.
+ 2: A docstring for this constraint, in Texinfo syntax; not currently
+ used, in future will be incorporated into the manual's list of
+ machine-specific operand constraints. */
+DEF_RTL_EXPR(DEFINE_REGISTER_CONSTRAINT, "define_register_constraint", "sss", RTX_EXTRA)
+
+/* Definition of a non-register operand constraint. These look at the
+ operand and decide whether it fits the constraint.
+
+ DEFINE_CONSTRAINT gets no special treatment if it fails to match.
+ It is appropriate for constant-only constraints, and most others.
+
+ DEFINE_MEMORY_CONSTRAINT tells reload that this constraint can be made
+ to match, if it doesn't already, by converting the operand to the form
+ (mem (reg X)) where X is a base register. It is suitable for constraints
+ that describe a subset of all memory references.
+
+ DEFINE_ADDRESS_CONSTRAINT tells reload that this constraint can be made
+ to match, if it doesn't already, by converting the operand to the form
+ (reg X) where X is a base register. It is suitable for constraints that
+ describe a subset of all address references.
+
+ When in doubt, use plain DEFINE_CONSTRAINT.
+
+ Operand:
+ 0: The name of the constraint (often, but not always, a single letter).
+ 1: A docstring for this constraint, in Texinfo syntax; not currently
+ used, in future will be incorporated into the manual's list of
+ machine-specific operand constraints.
+ 2: A boolean expression which computes whether or not the constraint
+ matches. It should follow the same rules as a define_predicate
+ expression, including the bit about specifying the set of RTX codes
+ that could possibly match. MATCH_TEST subexpressions may make use of
+ these variables:
+ `op' - the RTL object defining the operand.
+ `mode' - the mode of `op'.
+ `ival' - INTVAL(op), if op is a CONST_INT.
+ `hval' - CONST_DOUBLE_HIGH(op), if op is an integer CONST_DOUBLE.
+ `lval' - CONST_DOUBLE_LOW(op), if op is an integer CONST_DOUBLE.
+ `rval' - CONST_DOUBLE_REAL_VALUE(op), if op is a floating-point
+ CONST_DOUBLE.
+ Do not use ival/hval/lval/rval if op is not the appropriate kind of
+ RTL object. */
+DEF_RTL_EXPR(DEFINE_CONSTRAINT, "define_constraint", "sse", RTX_EXTRA)
+DEF_RTL_EXPR(DEFINE_MEMORY_CONSTRAINT, "define_memory_constraint", "sse", RTX_EXTRA)
+DEF_RTL_EXPR(DEFINE_ADDRESS_CONSTRAINT, "define_address_constraint", "sse", RTX_EXTRA)
+
+
+/* Constructions for CPU pipeline description described by NDFAs. */
+
+/* (define_cpu_unit string [string]) describes cpu functional
+ units (separated by comma).
+
+ 1st operand: Names of cpu functional units.
+ 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
+
+ All define_reservations, define_cpu_units, and
+ define_query_cpu_units should have unique names which may not be
+ "nothing". */
+DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA)
+
+/* (define_query_cpu_unit string [string]) describes cpu functional
+ units analogously to define_cpu_unit. The reservation of such
+ units can be queried for automaton state. */
+DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA)
+
+/* (exclusion_set string string) means that each CPU functional unit
+ in the first string can not be reserved simultaneously with any
+ unit whose name is in the second string and vise versa. CPU units
+ in the string are separated by commas. For example, it is useful
+ for description CPU with fully pipelined floating point functional
+ unit which can execute simultaneously only single floating point
+ insns or only double floating point insns. All CPU functional
+ units in a set should belong to the same automaton. */
+DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA)
+
+/* (presence_set string string) means that each CPU functional unit in
+ the first string can not be reserved unless at least one of pattern
+ of units whose names are in the second string is reserved. This is
+ an asymmetric relation. CPU units or unit patterns in the strings
+ are separated by commas. Pattern is one unit name or unit names
+ separated by white-spaces.
-/* ----------------------------------------------------------------------
- Expressions for operators in an rtl pattern
- ---------------------------------------------------------------------- */
+ For example, it is useful for description that slot1 is reserved
+ after slot0 reservation for a VLIW processor. We could describe it
+ by the following construction
-/* if_then_else. This is used in representing ordinary
- conditional jump instructions.
- Operand:
- 0: condition
- 1: then expr
- 2: else expr */
-DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", '3')
+ (presence_set "slot1" "slot0")
-/* General conditional. The first operand is a vector composed of pairs of
- expressions. The first element of each pair is evaluated, in turn.
- The value of the conditional is the second expression of the first pair
- whose first expression evaluates nonzero. If none of the expressions is
- true, the second operand will be used as the value of the conditional.
+ Or slot1 is reserved only after slot0 and unit b0 reservation. In
+ this case we could write
- This should be replaced with use of IF_THEN_ELSE. */
-DEF_RTL_EXPR(COND, "cond", "Ee", 'x')
+ (presence_set "slot1" "slot0 b0")
-/* Comparison, produces a condition code result. */
-DEF_RTL_EXPR(COMPARE, "compare", "ee", '2')
+ All CPU functional units in a set should belong to the same
+ automaton. */
+DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA)
-/* plus */
-DEF_RTL_EXPR(PLUS, "plus", "ee", 'c')
+/* (final_presence_set string string) is analogous to `presence_set'.
+ The difference between them is when checking is done. When an
+ instruction is issued in given automaton state reflecting all
+ current and planned unit reservations, the automaton state is
+ changed. The first state is a source state, the second one is a
+ result state. Checking for `presence_set' is done on the source
+ state reservation, checking for `final_presence_set' is done on the
+ result reservation. This construction is useful to describe a
+ reservation which is actually two subsequent reservations. For
+ example, if we use
-/* Operand 0 minus operand 1. */
-DEF_RTL_EXPR(MINUS, "minus", "ee", '2')
+ (presence_set "slot1" "slot0")
-/* Minus operand 0. */
-DEF_RTL_EXPR(NEG, "neg", "e", '1')
+ the following insn will be never issued (because slot1 requires
+ slot0 which is absent in the source state).
-DEF_RTL_EXPR(MULT, "mult", "ee", 'c')
+ (define_reservation "insn_and_nop" "slot0 + slot1")
-/* Operand 0 divided by operand 1. */
-DEF_RTL_EXPR(DIV, "div", "ee", '2')
-/* Remainder of operand 0 divided by operand 1. */
-DEF_RTL_EXPR(MOD, "mod", "ee", '2')
+ but it can be issued if we use analogous `final_presence_set'. */
+DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA)
-/* Unsigned divide and remainder. */
-DEF_RTL_EXPR(UDIV, "udiv", "ee", '2')
-DEF_RTL_EXPR(UMOD, "umod", "ee", '2')
+/* (absence_set string string) means that each CPU functional unit in
+ the first string can be reserved only if each pattern of units
+ whose names are in the second string is not reserved. This is an
+ asymmetric relation (actually exclusion set is analogous to this
+ one but it is symmetric). CPU units or unit patterns in the string
+ are separated by commas. Pattern is one unit name or unit names
+ separated by white-spaces.
-/* Bitwise operations. */
-DEF_RTL_EXPR(AND, "and", "ee", 'c')
+ For example, it is useful for description that slot0 can not be
+ reserved after slot1 or slot2 reservation for a VLIW processor. We
+ could describe it by the following construction
-DEF_RTL_EXPR(IOR, "ior", "ee", 'c')
+ (absence_set "slot2" "slot0, slot1")
-DEF_RTL_EXPR(XOR, "xor", "ee", 'c')
+ Or slot2 can not be reserved if slot0 and unit b0 are reserved or
+ slot1 and unit b1 are reserved . In this case we could write
-DEF_RTL_EXPR(NOT, "not", "e", '1')
+ (absence_set "slot2" "slot0 b0, slot1 b1")
-/* Operand:
- 0: value to be shifted.
- 1: number of bits. */
-DEF_RTL_EXPR(ASHIFT, "ashift", "ee", '2') /* shift left */
-DEF_RTL_EXPR(ROTATE, "rotate", "ee", '2') /* rotate left */
-DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", '2') /* arithmetic shift right */
-DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", '2') /* logical shift right */
-DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", '2') /* rotate right */
+ All CPU functional units in a set should to belong the same
+ automaton. */
+DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA)
-/* Minimum and maximum values of two operands. We need both signed and
- unsigned forms. (We cannot use MIN for SMIN because it conflicts
- with a macro of the same name.) */
+/* (final_absence_set string string) is analogous to `absence_set' but
+ checking is done on the result (state) reservation. See comments
+ for `final_presence_set'. */
+DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA)
-DEF_RTL_EXPR(SMIN, "smin", "ee", 'c')
-DEF_RTL_EXPR(SMAX, "smax", "ee", 'c')
-DEF_RTL_EXPR(UMIN, "umin", "ee", 'c')
-DEF_RTL_EXPR(UMAX, "umax", "ee", 'c')
+/* (define_bypass number out_insn_names in_insn_names) names bypass
+ with given latency (the first number) from insns given by the first
+ string (see define_insn_reservation) into insns given by the second
+ string. Insn names in the strings are separated by commas. The
+ third operand is optional name of function which is additional
+ guard for the bypass. The function will get the two insns as
+ parameters. If the function returns zero the bypass will be
+ ignored for this case. Additional guard is necessary to recognize
+ complicated bypasses, e.g. when consumer is load address. If there
+ are more one bypass with the same output and input insns, the
+ chosen bypass is the first bypass with a guard in description whose
+ guard function returns nonzero. If there is no such bypass, then
+ bypass without the guard function is chosen. */
+DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA)
-/* These unary operations are used to represent incrementation
- and decrementation as they occur in memory addresses.
- The amount of increment or decrement are not represented
- because they can be understood from the machine-mode of the
- containing MEM. These operations exist in only two cases:
- 1. pushes onto the stack.
- 2. created automatically by the life_analysis pass in flow.c. */
-DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", 'a')
-DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", 'a')
-DEF_RTL_EXPR(POST_DEC, "post_dec", "e", 'a')
-DEF_RTL_EXPR(POST_INC, "post_inc", "e", 'a')
+/* (define_automaton string) describes names of automata generated and
+ used for pipeline hazards recognition. The names are separated by
+ comma. Actually it is possibly to generate the single automaton
+ but unfortunately it can be very large. If we use more one
+ automata, the summary size of the automata usually is less than the
+ single one. The automaton name is used in define_cpu_unit and
+ define_query_cpu_unit. All automata should have unique names. */
+DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA)
-/* These binary operations are used to represent generic address
- side-effects in memory addresses, except for simple incrementation
- or decrementation which use the above operations. They are
- created automatically by the life_analysis pass in flow.c.
- The first operand is a REG which is used as the address.
- The second operand is an expression that is assigned to the
- register, either before (PRE_MODIFY) or after (POST_MODIFY)
- evaluating the address.
- Currently, the compiler can only handle second operands of the
- form (plus (reg) (reg)) and (plus (reg) (const_int)), where
- the first operand of the PLUS has to be the same register as
- the first operand of the *_MODIFY. */
-DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", 'a')
-DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", 'a')
+/* (automata_option string) describes option for generation of
+ automata. Currently there are the following options:
-/* Comparison operations. The ordered comparisons exist in two
- flavors, signed and unsigned. */
-DEF_RTL_EXPR(NE, "ne", "ee", '<')
-DEF_RTL_EXPR(EQ, "eq", "ee", '<')
-DEF_RTL_EXPR(GE, "ge", "ee", '<')
-DEF_RTL_EXPR(GT, "gt", "ee", '<')
-DEF_RTL_EXPR(LE, "le", "ee", '<')
-DEF_RTL_EXPR(LT, "lt", "ee", '<')
-DEF_RTL_EXPR(GEU, "geu", "ee", '<')
-DEF_RTL_EXPR(GTU, "gtu", "ee", '<')
-DEF_RTL_EXPR(LEU, "leu", "ee", '<')
-DEF_RTL_EXPR(LTU, "ltu", "ee", '<')
+ o "no-minimization" which makes no minimization of automata. This
+ is only worth to do when we are debugging the description and
+ need to look more accurately at reservations of states.
-/* Additional floating point unordered comparison flavors. */
-DEF_RTL_EXPR(UNORDERED, "unordered", "ee", '<')
-DEF_RTL_EXPR(ORDERED, "ordered", "ee", '<')
+ o "time" which means printing additional time statistics about
+ generation of automata.
-/* These are equivalent to unordered or ... */
-DEF_RTL_EXPR(UNEQ, "uneq", "ee", '<')
-DEF_RTL_EXPR(UNGE, "unge", "ee", '<')
-DEF_RTL_EXPR(UNGT, "ungt", "ee", '<')
-DEF_RTL_EXPR(UNLE, "unle", "ee", '<')
-DEF_RTL_EXPR(UNLT, "unlt", "ee", '<')
+ o "v" which means generation of file describing the result
+ automata. The file has suffix `.dfa' and can be used for the
+ description verification and debugging.
-/* This is an ordered NE, ie !UNEQ, ie false for NaN. */
-DEF_RTL_EXPR(LTGT, "ltgt", "ee", '<')
+ o "w" which means generation of warning instead of error for
+ non-critical errors.
-/* Represents the result of sign-extending the sole operand.
- The machine modes of the operand and of the SIGN_EXTEND expression
- determine how much sign-extension is going on. */
-DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", '1')
+ o "ndfa" which makes nondeterministic finite state automata.
-/* Similar for zero-extension (such as unsigned short to int). */
-DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", '1')
+ o "progress" which means output of a progress bar showing how many
+ states were generated so far for automaton being processed. */
+DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA)
-/* Similar but here the operand has a wider mode. */
-DEF_RTL_EXPR(TRUNCATE, "truncate", "e", '1')
+/* (define_reservation string string) names reservation (the first
+ string) of cpu functional units (the 2nd string). Sometimes unit
+ reservations for different insns contain common parts. In such
+ case, you can describe common part and use its name (the 1st
+ parameter) in regular expression in define_insn_reservation. All
+ define_reservations, define_cpu_units, and define_query_cpu_units
+ should have unique names which may not be "nothing". */
+DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA)
-/* Similar for extending floating-point values (such as SFmode to DFmode). */
-DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", '1')
-DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", '1')
+/* (define_insn_reservation name default_latency condition regexpr)
+ describes reservation of cpu functional units (the 3nd operand) for
+ instruction which is selected by the condition (the 2nd parameter).
+ The first parameter is used for output of debugging information.
+ The reservations are described by a regular expression according
+ the following syntax:
-/* Conversion of fixed point operand to floating point value. */
-DEF_RTL_EXPR(FLOAT, "float", "e", '1')
+ regexp = regexp "," oneof
+ | oneof
-/* With fixed-point machine mode:
- Conversion of floating point operand to fixed point value.
- Value is defined only when the operand's value is an integer.
- With floating-point machine mode (and operand with same mode):
- Operand is rounded toward zero to produce an integer value
- represented in floating point. */
-DEF_RTL_EXPR(FIX, "fix", "e", '1')
+ oneof = oneof "|" allof
+ | allof
-/* Conversion of unsigned fixed point operand to floating point value. */
-DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", '1')
+ allof = allof "+" repeat
+ | repeat
-/* With fixed-point machine mode:
- Conversion of floating point operand to *unsigned* fixed point value.
- Value is defined only when the operand's value is an integer. */
-DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", '1')
+ repeat = element "*" number
+ | element
-/* Absolute value */
-DEF_RTL_EXPR(ABS, "abs", "e", '1')
+ element = cpu_function_unit_name
+ | reservation_name
+ | result_name
+ | "nothing"
+ | "(" regexp ")"
-/* Square root */
-DEF_RTL_EXPR(SQRT, "sqrt", "e", '1')
+ 1. "," is used for describing start of the next cycle in
+ reservation.
-/* Find first bit that is set.
- Value is 1 + number of trailing zeros in the arg.,
- or 0 if arg is 0. */
-DEF_RTL_EXPR(FFS, "ffs", "e", '1')
+ 2. "|" is used for describing the reservation described by the
+ first regular expression *or* the reservation described by the
+ second regular expression *or* etc.
-/* Count leading zeros. */
-DEF_RTL_EXPR(CLZ, "clz", "e", '1')
+ 3. "+" is used for describing the reservation described by the
+ first regular expression *and* the reservation described by the
+ second regular expression *and* etc.
-/* Count trailing zeros. */
-DEF_RTL_EXPR(CTZ, "ctz", "e", '1')
+ 4. "*" is used for convenience and simply means sequence in
+ which the regular expression are repeated NUMBER times with
+ cycle advancing (see ",").
-/* Population count (number of 1 bits). */
-DEF_RTL_EXPR(POPCOUNT, "popcount", "e", '1')
+ 5. cpu functional unit name which means its reservation.
-/* Population parity (number of 1 bits modulo 2). */
-DEF_RTL_EXPR(PARITY, "parity", "e", '1')
+ 6. reservation name -- see define_reservation.
-/* Reference to a signed bit-field of specified size and position.
- Operand 0 is the memory unit (usually SImode or QImode) which
- contains the field's first bit. Operand 1 is the width, in bits.
- Operand 2 is the number of bits in the memory unit before the
- first bit of this field.
- If BITS_BIG_ENDIAN is defined, the first bit is the msb and
- operand 2 counts from the msb of the memory unit.
- Otherwise, the first bit is the lsb and operand 2 counts from
- the lsb of the memory unit. */
-DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", 'b')
+ 7. string "nothing" means no units reservation. */
-/* Similar for unsigned bit-field. */
-DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", 'b')
+DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA)
-/* For RISC machines. These save memory when splitting insns. */
+/* Expressions used for insn attributes. */
-/* HIGH are the high-order bits of a constant expression. */
-DEF_RTL_EXPR(HIGH, "high", "e", 'o')
+/* Definition of an insn attribute.
+ 1st operand: name of the attribute
+ 2nd operand: comma-separated list of possible attribute values
+ 3rd operand: expression for the default value of the attribute. */
+DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA)
-/* LO_SUM is the sum of a register and the low-order bits
- of a constant expression. */
-DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", 'o')
-
-/* Header for range information. Operand 0 is the NOTE_INSN_RANGE_BEG insn.
- Operand 1 is the NOTE_INSN_RANGE_END insn. Operand 2 is a vector of all of
- the registers that can be substituted within this range. Operand 3 is the
- number of calls in the range. Operand 4 is the number of insns in the
- range. Operand 5 is the unique range number for this range. Operand 6 is
- the basic block # of the start of the live range. Operand 7 is the basic
- block # of the end of the live range. Operand 8 is the loop depth. Operand
- 9 is a bitmap of the registers live at the start of the range. Operand 10
- is a bitmap of the registers live at the end of the range. Operand 11 is
- marker number for the start of the range. Operand 12 is the marker number
- for the end of the range. */
-DEF_RTL_EXPR(RANGE_INFO, "range_info", "uuEiiiiiibbii", 'x')
-
-/* Registers that can be substituted within the range. Operand 0 is the
- original pseudo register number. Operand 1 will be filled in with the
- pseudo register the value is copied for the duration of the range. Operand
- 2 is the number of references within the range to the register. Operand 3
- is the number of sets or clobbers of the register in the range. Operand 4
- is the number of deaths the register has. Operand 5 is the copy flags that
- give the status of whether a copy is needed from the original register to
- the new register at the beginning of the range, or whether a copy from the
- new register back to the original at the end of the range. Operand 6 is the
- live length. Operand 7 is the number of calls that this register is live
- across. Operand 8 is the symbol node of the variable if the register is a
- user variable. Operand 9 is the block node that the variable is declared
- in if the register is a user variable. */
-DEF_RTL_EXPR(RANGE_REG, "range_reg", "iiiiiiiitt", 'x')
-
-/* Information about a local variable's ranges. Operand 0 is an EXPR_LIST of
- the different ranges a variable is in where it is copied to a different
- pseudo register. Operand 1 is the block that the variable is declared in.
- Operand 2 is the number of distinct ranges. */
-DEF_RTL_EXPR(RANGE_VAR, "range_var", "eti", 'x')
-
-/* Information about the registers that are live at the current point. Operand
- 0 is the live bitmap. Operand 1 is the original block number. */
-DEF_RTL_EXPR(RANGE_LIVE, "range_live", "bi", 'x')
-
-/* A unary `__builtin_constant_p' expression. These are only emitted
- during RTL generation, and then only if optimize > 0. They are
- eliminated by the first CSE pass. */
-DEF_RTL_EXPR(CONSTANT_P_RTX, "constant_p_rtx", "e", 'x')
-
-/* A placeholder for a CALL_INSN which may be turned into a normal call,
- a sibling (tail) call or tail recursion.
-
- Immediately after RTL generation, this placeholder will be replaced
- by the insns to perform the call, sibcall or tail recursion.
-
- This RTX has 4 operands. The first three are lists of instructions to
- perform the call as a normal call, sibling call and tail recursion
- respectively. The latter two lists may be NULL, the first may never
- be NULL.
-
- The last operand is the tail recursion CODE_LABEL, which may be NULL if no
- potential tail recursive calls were found.
-
- The tail recursion label is needed so that we can clear LABEL_PRESERVE_P
- after we select a call method.
-
- This method of tail-call elimination is intended to be replaced by
- tree-based optimizations once front-end conversions are complete. */
-DEF_RTL_EXPR(CALL_PLACEHOLDER, "call_placeholder", "uuuu", 'x')
+/* Definition of an insn attribute that uses an existing enumerated type.
+ 1st operand: name of the attribute
+ 2nd operand: the name of the enumerated type
+ 3rd operand: expression for the default value of the attribute. */
+DEF_RTL_EXPR(DEFINE_ENUM_ATTR, "define_enum_attr", "sse", RTX_EXTRA)
-/* Describes a merge operation between two vector values.
- Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
- that specifies where the parts of the result are taken from. Set bits
- indicate operand 0, clear bits indicate operand 1. The parts are defined
- by the mode of the vectors. */
-DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", '3')
+/* Marker for the name of an attribute. */
+DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA)
-/* Describes an operation that selects parts of a vector.
- Operands 0 is the source vector, operand 1 is a PARALLEL that contains
- a CONST_INT for each of the subparts of the result vector, giving the
- number of the source subpart that should be stored into it. */
-DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", '2')
+/* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
+ in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
+ pattern.
-/* Describes a vector concat operation. Operands 0 and 1 are the source
- vectors, the result is a vector that is as long as operands 0 and 1
- combined and is the concatenation of the two source vectors. */
-DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", '2')
+ (set_attr "name" "value") is equivalent to
+ (set (attr "name") (const_string "value")) */
+DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA)
-/* Describes an operation that converts a small vector into a larger one by
- duplicating the input values. The output vector mode must have the same
- submodes as the input vector mode, and the number of output parts must be
- an integer multiple of the number of input parts. */
-DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", '1')
-
-/* Addition with signed saturation */
-DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", 'c')
+/* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
+ specify that attribute values are to be assigned according to the
+ alternative matched.
-/* Addition with unsigned saturation */
-DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", 'c')
+ The following three expressions are equivalent:
-/* Operand 0 minus operand 1, with signed saturation. */
-DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", '2')
+ (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
+ (eq_attrq "alternative" "2") (const_string "a2")]
+ (const_string "a3")))
+ (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
+ (const_string "a3")])
+ (set_attr "att" "a1,a2,a3")
+ */
+DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA)
-/* Operand 0 minus operand 1, with unsigned saturation. */
-DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", '2')
+/* A conditional expression true if the value of the specified attribute of
+ the current insn equals the specified value. The first operand is the
+ attribute name and the second is the comparison value. */
+DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA)
-/* Signed saturating truncate. */
-DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", '1')
+/* A special case of the above representing a set of alternatives. The first
+ operand is bitmap of the set, the second one is the default value. */
+DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA)
-/* Unsigned saturating truncate. */
-DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", '1')
+/* A conditional expression which is true if the specified flag is
+ true for the insn being scheduled in reorg.
-/* The SSA phi operator.
+ genattr.c defines the following flags which can be tested by
+ (attr_flag "foo") expressions in eligible_for_delay: forward, backward. */
+
+DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA)
- The argument is a vector of 2N rtxes. Element 2N+1 is a CONST_INT
- containing the block number of the predecessor through which control
- has passed when the register at element 2N is used.
+/* General conditional. The first operand is a vector composed of pairs of
+ expressions. The first element of each pair is evaluated, in turn.
+ The value of the conditional is the second expression of the first pair
+ whose first expression evaluates nonzero. If none of the expressions is
+ true, the second operand will be used as the value of the conditional. */
+DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA)
- Note that PHI may only appear at the beginning of a basic block.
+/* Definition of a pattern substitution meta operation on a DEFINE_EXPAND
+ or a DEFINE_INSN. Automatically generates new instances of DEFINE_INSNs
+ that match the substitution pattern.
- ??? There may be multiple PHI insns, but they are all evaluated
- in parallel. This probably ought to be changed to use a real
- PARALLEL, as that would be less confusing and more in the spirit
- of canonical RTL. It is, however, easier to manipulate this way. */
-DEF_RTL_EXPR(PHI, "phi", "E", 'x')
+ Operand:
+ 0: The name of the substitition template.
+ 1: Input template to match to see if a substitution is applicable.
+ 2: A C expression giving an additional condition for the generated
+ new define_expand or define_insn.
+ 3: Output tempalate to generate via substitution.
+
+ Within a DEFINE_SUBST template, the meaning of some RTL expressions is
+ different from their usual interpretation: a MATCH_OPERAND matches any
+ expression tree with matching machine mode or with VOIDmode. Likewise,
+ MATCH_OP_DUP and MATCH_DUP match more liberally in a DEFINE_SUBST than
+ in other RTL expressions. MATCH_OPERATOR matches all common operators
+ but also UNSPEC, UNSPEC_VOLATILE, and MATCH_OPERATORS from the input
+ DEFINE_EXPAND or DEFINE_INSN. */
+DEF_RTL_EXPR(DEFINE_SUBST, "define_subst", "sEsE", RTX_EXTRA)
+
+/* Substitution attribute to apply a DEFINE_SUBST to a pattern.
+ Operand:
+ 0: The name of the subst-attribute.
+ 1: The name of the DEFINE_SUBST to be applied for this attribute.
+ 2: String to substitute for the subst-attribute name in the pattern
+ name, for the case that the DEFINE_SUBST is not applied (i.e. the
+ unmodified version of the pattern).
+ 3: String to substitute for the subst-attribute name in the pattern
+ name, for the case that the DEFINE_SUBST is applied to the patten.
+
+ The use of DEFINE_SUBST and DEFINE_SUBST_ATTR is explained in the
+ GCC internals manual, under "RTL Templates Transformations". */
+DEF_RTL_EXPR(DEFINE_SUBST_ATTR, "define_subst_attr", "ssss", RTX_EXTRA)
+
+#endif /* GENERATOR_FILE */
/*
Local variables: