re PR debug/66691 (ICE on valid code at -O3 with -g enabled in simplify_subreg, at...

[gcc.git] / gcc / sched-rgn.c

diff --git a/gcc/sched-rgn.c b/gcc/sched-rgn.c
index 2a1c18c1eded32a0a80acc9a60d288991e742865..ccdde706ea7866434c35d36deb0f4915e358d28f 100644 (file)
--- a/gcc/sched-rgn.c
+++ b/gcc/sched-rgn.c
@@ -1,5 +1,5 @@
 /* Instruction scheduling pass.
-   Copyright (C) 1992-2014 Free Software Foundation, Inc.
+   Copyright (C) 1992-2015 Free Software Foundation, Inc.
    Contributed by Michael Tiemann (tiemann@cygnus.com) Enhanced by,
    and currently maintained by, Jim Wilson (wilson@cygnus.com)
 
@@ -52,11 +52,6 @@ along with GCC; see the file COPYING3.  If not see
 #include "tm_p.h"
 #include "hard-reg-set.h"
 #include "regs.h"
-#include "hashtab.h"
-#include "hash-set.h"
-#include "vec.h"
-#include "machmode.h"
-#include "input.h"
 #include "function.h"
 #include "profile.h"
 #include "flags.h"
@@ -75,6 +70,7 @@ along with GCC; see the file COPYING3.  If not see
 #include "target.h"
 #include "tree-pass.h"
 #include "dbgcnt.h"
+#include "emit-rtl.h"
 
 #ifdef INSN_SCHEDULING
 
@@ -240,10 +236,10 @@ static edgeset *ancestor_edges;
 static int check_live_1 (int, rtx);
 static void update_live_1 (int, rtx);
 static int is_pfree (rtx, int, int);
-static int find_conditional_protection (rtx, int);
+static int find_conditional_protection (rtx_insn *, int);
 static int is_conditionally_protected (rtx, int, int);
 static int is_prisky (rtx, int, int);
-static int is_exception_free (rtx, int, int);
+static int is_exception_free (rtx_insn *, int, int);
 
 static bool sets_likely_spilled (rtx);
 static void sets_likely_spilled_1 (rtx, const_rtx, void *);
@@ -1720,7 +1716,7 @@ check_live_1 (int src, rtx x)
       if (regno < FIRST_PSEUDO_REGISTER)
        {
          /* Check for hard registers.  */
-         int j = hard_regno_nregs[regno][GET_MODE (reg)];
+         int j = REG_NREGS (reg);
          while (--j >= 0)
            {
              for (i = 0; i < candidate_table[src].split_bbs.nr_members; i++)
@@ -1801,12 +1797,7 @@ update_live_1 (int src, rtx x)
       for (i = 0; i < candidate_table[src].update_bbs.nr_members; i++)
        {
          basic_block b = candidate_table[src].update_bbs.first_member[i];
-
-         if (HARD_REGISTER_NUM_P (regno))
-           bitmap_set_range (df_get_live_in (b), regno,
-                             hard_regno_nregs[regno][GET_MODE (reg)]);
-         else
-           bitmap_set_bit (df_get_live_in (b), regno);
+         bitmap_set_range (df_get_live_in (b), regno, REG_NREGS (reg));
        }
     }
 }
@@ -1841,7 +1832,7 @@ check_live (rtx_insn *insn, int src)
    block src to trg.  */
 
 static void
-update_live (rtx insn, int src)
+update_live (rtx_insn *insn, int src)
 {
   /* Find the registers set by instruction.  */
   if (GET_CODE (PATTERN (insn)) == SET
@@ -1882,7 +1873,7 @@ set_spec_fed (rtx load_insn)
 branch depending on insn, that guards the speculative load.  */
 
 static int
-find_conditional_protection (rtx insn, int load_insn_bb)
+find_conditional_protection (rtx_insn *insn, int load_insn_bb)
 {
   sd_iterator_def sd_it;
   dep_t dep;
@@ -2042,7 +2033,7 @@ is_prisky (rtx load_insn, int bb_src, int bb_trg)
    and 0 otherwise.  */
 
 static int
-is_exception_free (rtx insn, int bb_src, int bb_trg)
+is_exception_free (rtx_insn *insn, int bb_src, int bb_trg)
 {
   int insn_class = haifa_classify_insn (insn);
 
@@ -2487,9 +2478,7 @@ add_branch_dependences (rtx_insn *head, rtx_insn *tail)
             && (GET_CODE (PATTERN (insn)) == USE
                 || GET_CODE (PATTERN (insn)) == CLOBBER
                 || can_throw_internal (insn)
-#ifdef HAVE_cc0
-                || sets_cc0_p (PATTERN (insn))
-#endif
+                || (HAVE_cc0 && sets_cc0_p (PATTERN (insn)))
                 || (!reload_completed
                     && sets_likely_spilled (PATTERN (insn)))))
         || NOTE_P (insn)