/* Target hook definitions.
- Copyright (C) 2001-2014 Free Software Foundation, Inc.
+ Copyright (C) 2001-2015 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
DEFHOOK_UNDOC
(print_operand_address,
"",
- void, (FILE *file, rtx addr),
+ void, (FILE *file, machine_mode mode, rtx addr),
default_print_operand_address)
/* Determine whether CODE is a valid punctuation character for the
DEFHOOK
(macro_fusion_pair_p,
- "This hook is used to check whether two insns could be macro fused for\n\
-target microarchitecture. If this hook returns true for the given insn pair\n\
-(@var{condgen} and @var{condjmp}), scheduler will put them into a sched\n\
-group, and they will not be scheduled apart.",
- bool, (rtx_insn *condgen, rtx_insn *condjmp), NULL)
+ "This hook is used to check whether two insns should be macro fused for\n\
+a target microarchitecture. If this hook returns true for the given insn pair\n\
+(@var{prev} and @var{curr}), the scheduler will put them into a sched\n\
+group, and they will not be scheduled apart. The two insns will be either\n\
+two SET insns or a compare and a conditional jump and this hook should\n\
+validate any dependencies needed to fuse the two insns together.",
+ bool, (rtx_insn *prev, rtx_insn *curr), NULL)
/* The following member value is a pointer to a function called
after evaluation forward dependencies of insns in chain given
\n\
Given below example:\n\
\n\
+@smallexample\n\
ldr r10, [r1, 4]\n\
add r4, r4, r10\n\
ldr r15, [r2, 8]\n\
add r4, r4, r11\n\
ldr r16, [r2, 12]\n\
sub r5, r5, r16\n\
+@end smallexample\n\
\n\
On targets like ARM/AArch64, the two pairs of consecutive loads should be\n\
merged. Since peephole2 pass can't help in this case unless consecutive\n\
this scheduling fusion pass works. This hook calculates priority for each\n\
instruction based on its fustion type, like:\n\
\n\
- ldr r10, [r1, 4] ; fusion_pri=99, pri=96 \n\
- add r4, r4, r10 ; fusion_pri=100, pri=100 \n\
- ldr r15, [r2, 8] ; fusion_pri=98, pri=92 \n\
- sub r5, r5, r15 ; fusion_pri=100, pri=100 \n\
- ldr r11, [r1, 0] ; fusion_pri=99, pri=100 \n\
- add r4, r4, r11 ; fusion_pri=100, pri=100 \n\
- ldr r16, [r2, 12] ; fusion_pri=98, pri=88 \n\
- sub r5, r5, r16 ; fusion_pri=100, pri=100 \n\
+@smallexample\n\
+ ldr r10, [r1, 4] ; fusion_pri=99, pri=96\n\
+ add r4, r4, r10 ; fusion_pri=100, pri=100\n\
+ ldr r15, [r2, 8] ; fusion_pri=98, pri=92\n\
+ sub r5, r5, r15 ; fusion_pri=100, pri=100\n\
+ ldr r11, [r1, 0] ; fusion_pri=99, pri=100\n\
+ add r4, r4, r11 ; fusion_pri=100, pri=100\n\
+ ldr r16, [r2, 12] ; fusion_pri=98, pri=88\n\
+ sub r5, r5, r16 ; fusion_pri=100, pri=100\n\
+@end smallexample\n\
\n\
Scheduling fusion pass then sorts all ready to issue instructions according\n\
to the priorities. As a result, instructions of same fusion type will be\n\
pushed together in instruction flow, like:\n\
\n\
+@smallexample\n\
ldr r11, [r1, 0]\n\
ldr r10, [r1, 4]\n\
ldr r15, [r2, 8]\n\
sub r5, r5, r15\n\
add r4, r4, r11\n\
sub r5, r5, r16\n\
+@end smallexample\n\
\n\
Now peephole2 pass can simply merge the two pairs of loads.\n\
\n\
HOOK_VECTOR_END (simd_clone)
+/* Functions relating to openacc. */
+#undef HOOK_PREFIX
+#define HOOK_PREFIX "TARGET_GOACC_"
+HOOK_VECTOR (TARGET_GOACC, goacc)
+
+DEFHOOK
+(validate_dims,
+"This hook should check the launch dimensions provided for an OpenACC\n\
+compute region, or routine. Defaulted values are represented as -1\n\
+and non-constant values as 0. The @var{fn_level} is negative for the\n\
+function corresponding to the compute region. For a routine is is the\n\
+outermost level at which partitioned execution may be spawned. It\n\
+should fill in anything that needs to default to non-unity and verify\n\
+non-defaults. Diagnostics should be issued as appropriate. Return\n\
+true, if changes have been made. You must override this hook to\n\
+provide dimensions larger than 1.",
+bool, (tree decl, int *dims, int fn_level),
+default_goacc_validate_dims)
+
+DEFHOOK
+(dim_limit,
+"This hook should return the maximum size of a particular dimension,\n\
+or zero if unbounded.",
+int, (int axis),
+default_goacc_dim_limit)
+
+DEFHOOK
+(fork_join,
+"This hook can be used to convert IFN_GOACC_FORK and IFN_GOACC_JOIN\n\
+function calls to target-specific gimple, or indicate whether they\n\
+should be retained. It is executed during the oacc_device_lower pass.\n\
+It should return true, if the call should be retained. It should\n\
+return false, if it is to be deleted (either because target-specific\n\
+gimple has been inserted before it, or there is no need for it).\n\
+The default hook returns false, if there are no RTL expanders for them.",
+bool, (gcall *call, const int *dims, bool is_fork),
+default_goacc_fork_join)
+
+DEFHOOK
+(reduction,
+"This hook is used by the oacc_transform pass to expand calls to the\n\
+@var{GOACC_REDUCTION} internal function, into a sequence of gimple\n\
+instructions. @var{call} is gimple statement containing the call to\n\
+the function. This hook removes statement @var{call} after the\n\
+expanded sequence has been inserted. This hook is also responsible\n\
+for allocating any storage for reductions when necessary.",
+void, (gcall *call),
+default_goacc_reduction)
+
+HOOK_VECTOR_END (goacc)
+
/* Functions relating to vectorization. */
#undef HOOK_PREFIX
#define HOOK_PREFIX "TARGET_VECTORIZE_"
log2(@var{VS}) @minus{} 1 bits of @var{addr} will be considered.",
tree, (void), NULL)
-/* Returns a code for builtin that realizes vectorized version of
- function, or NULL_TREE if not available. */
+/* Returns a built-in function that realizes the vectorized version of
+ a target-independent function, or NULL_TREE if not available. */
DEFHOOK
(builtin_vectorized_function,
"This hook should return the decl of a function that implements the\n\
-vectorized variant of the builtin function with builtin function code\n\
+vectorized variant of the function with the @code{combined_fn} code\n\
@var{code} or @code{NULL_TREE} if such a function is not available.\n\
-The value of @var{fndecl} is the builtin function declaration. The\n\
+The return type of the vectorized function shall be of vector type\n\
+@var{vec_type_out} and the argument types should be @var{vec_type_in}.",
+ tree, (unsigned code, tree vec_type_out, tree vec_type_in),
+ default_builtin_vectorized_function)
+
+/* Returns a built-in function that realizes the vectorized version of
+ a target-specific function, or NULL_TREE if not available. */
+DEFHOOK
+(builtin_md_vectorized_function,
+ "This hook should return the decl of a function that implements the\n\
+vectorized variant of target built-in function @code{fndecl}. The\n\
return type of the vectorized function shall be of vector type\n\
@var{vec_type_out} and the argument types should be @var{vec_type_in}.",
tree, (tree fndecl, tree vec_type_out, tree vec_type_in),
- default_builtin_vectorized_function)
+ default_builtin_md_vectorized_function)
/* Returns a function declaration for a builtin that realizes the
vector conversion, or NULL_TREE if not available. */
(void),
default_autovectorize_vector_sizes)
+/* Function to get a target mode for a vector mask. */
+DEFHOOK
+(get_mask_mode,
+ "This hook returns mode to be used for a mask to be used for a vector\n\
+of specified @var{length} with @var{nunits} elements. By default an integer\n\
+vector mode of a proper size is returned.",
+ machine_mode,
+ (unsigned nunits, unsigned length),
+ default_get_mask_mode)
+
/* Target builtin that implements vector gather operation. */
DEFHOOK
(builtin_gather,
(const_tree mem_vectype, const_tree index_type, int scale),
NULL)
+/* Target builtin that implements vector scatter operation. */
+DEFHOOK
+(builtin_scatter,
+"Target builtin that implements vector scatter operation. @var{vectype}\n\
+is the vector type of the store and @var{index_type} is scalar type of\n\
+the index, scaled by @var{scale}.\n\
+The default is @code{NULL_TREE} which means to not vectorize scatter\n\
+stores.",
+ tree,
+ (const_tree vectype, const_tree index_type, int scale),
+ NULL)
+
/* Target function to initialize the cost model for a loop or block. */
DEFHOOK
(init_cost,
void, (tree),
hook_void_tree)
+DEFHOOKPOD
+(absolute_biggest_alignment,
+ "If defined, this target hook specifies the absolute biggest alignment\n\
+that a type or variable can have on this machine, otherwise,\n\
+@code{BIGGEST_ALIGNMENT} is used.",
+ HOST_WIDE_INT, BIGGEST_ALIGNMENT)
+
/* Allow target specific overriding of option settings after options have
been changed by an attribute or pragma or when it is reset at the
end of the code affected by an attribute or pragma. */
DEFHOOKPOD
(attribute_table,
"If defined, this target hook points to an array of @samp{struct\n\
-attribute_spec} (defined in @file{tree.h}) specifying the machine\n\
+attribute_spec} (defined in @file{tree-core.h}) specifying the machine\n\
specific attributes for this target and some of the restrictions on the\n\
entities to which these attributes are applied and the arguments they\n\
take.",
tree, (void *decl), NULL)
/* Returns a code for a target-specific builtin that implements
- reciprocal of the function, or NULL_TREE if not available. */
+ reciprocal of a target-specific function, or NULL_TREE if not available. */
DEFHOOK
(builtin_reciprocal,
- "This hook should return the DECL of a function that implements reciprocal of\n\
-the builtin function with builtin function code @var{fn}, or\n\
-@code{NULL_TREE} if such a function is not available. @var{md_fn} is true\n\
-when @var{fn} is a code of a machine-dependent builtin function. When\n\
-@var{sqrt} is true, additional optimizations that apply only to the reciprocal\n\
-of a square root function are performed, and only reciprocals of @code{sqrt}\n\
-function are valid.",
- tree, (unsigned fn, bool md_fn, bool sqrt),
+ "This hook should return the DECL of a function that implements the\n\
+reciprocal of the machine-specific builtin function @var{fndecl}, or\n\
+@code{NULL_TREE} if such a function is not available.",
+ tree, (tree fndecl),
default_builtin_reciprocal)
/* For a vendor-specific TYPE, return a pointer to a statically-allocated
DEFHOOK
(gen_ccmp_first,
- "This function emits a comparison insn for the first of a sequence of\n\
- conditional comparisions. It returns a comparison expression appropriate\n\
- for passing to @code{gen_ccmp_next} or @code{cbranch_optab}. @var{code} is\n\
+ "This function prepares to emit a comparison insn for the first compare in a\n\
+ sequence of conditional comparisions. It returns a appropriate @code{CC}\n\
+ for passing to @code{gen_ccmp_next} or @code{cbranch_optab}. The insns to\n\
+ prepare the compare are saved in @var{prep_seq} and the compare insns are\n\
+ saved in @var{gen_seq}. They will be emitted when all the compares in the\n\
+ the conditional comparision are generated without error. @var{code} is\n\
the @code{rtx_code} of the compare for @var{op0} and @var{op1}.",
- rtx, (int code, rtx op0, rtx op1),
+ rtx, (rtx *prep_seq, rtx *gen_seq, int code, tree op0, tree op1),
NULL)
DEFHOOK
(gen_ccmp_next,
- "This function emits a conditional comparison within a sequence of\n\
- conditional comparisons. The @var{prev} expression is the result of a\n\
- prior call to @code{gen_ccmp_first} or @code{gen_ccmp_next}. It may return\n\
- @code{NULL} if the combination of @var{prev} and this comparison is\n\
+ "This function prepare to emit a conditional comparison within a sequence of\n\
+ conditional comparisons. It returns a appropriate @code{CC} for passing to\n\
+ @code{gen_ccmp_next} or @code{cbranch_optab}. The insns to prepare the\n\
+ compare are saved in @var{prep_seq} and the compare insns are saved in\n\
+ @var{gen_seq}. They will be emitted when all the compares in the conditional\n\
+ comparision are generated without error. The @var{prev} expression is the\n\
+ result of a prior call to @code{gen_ccmp_first} or @code{gen_ccmp_next}. It\n\
+ may return @code{NULL} if the combination of @var{prev} and this comparison is\n\
not supported, otherwise the result must be appropriate for passing to\n\
@code{gen_ccmp_next} or @code{cbranch_optab}. @var{code} is the\n\
@code{rtx_code} of the compare for @var{op0} and @var{op1}. @var{bit_code}\n\
is @code{AND} or @code{IOR}, which is the op on the two compares.",
- rtx, (rtx prev, int cmp_code, rtx op0, rtx op1, int bit_code),
+ rtx, (rtx *prep_seq, rtx *gen_seq, rtx prev, int cmp_code, tree op0, tree op1, int bit_code),
NULL)
/* Return a new value for loop unroll size. */
(pointer_mode,
"Define this to return the machine mode to use for pointers to\n\
@var{address_space} if the target supports named address spaces.\n\
-The default version of this hook returns @code{ptr_mode} for the\n\
-generic address space only.",
+The default version of this hook returns @code{ptr_mode}.",
machine_mode, (addr_space_t address_space),
default_addr_space_pointer_mode)
(address_mode,
"Define this to return the machine mode to use for addresses in\n\
@var{address_space} if the target supports named address spaces.\n\
-The default version of this hook returns @code{Pmode} for the\n\
-generic address space only.",
+The default version of this hook returns @code{Pmode}.",
machine_mode, (addr_space_t address_space),
default_addr_space_address_mode)
bool, (addr_space_t subset, addr_space_t superset),
default_addr_space_subset_p)
+/* True if 0 is a valid address in the address space, or false if
+ 0 is a NULL in the address space. */
+DEFHOOK
+(zero_address_valid,
+ "Define this to modify the default handling of address 0 for the\n\
+address space. Return true if 0 should be considered a valid address.",
+ bool, (addr_space_t as),
+ default_addr_space_zero_address_valid)
+
/* Function to convert an rtl expression from one address space to another. */
DEFHOOK
(convert,
rtx, (rtx op, tree from_type, tree to_type),
default_addr_space_convert)
+/* Function to encode an address space into dwarf. */
+DEFHOOK
+(debug,
+ "Define this to define how the address space is encoded in dwarf.\n\
+The result is the value to be used with @code{DW_AT_address_class}.",
+ int, (addr_space_t as),
+ default_addr_space_debug)
+
HOOK_VECTOR_END (addr_space)
#undef HOOK_PREFIX
enum by_pieces_operation op, bool speed_p),
default_use_by_pieces_infrastructure_p)
+DEFHOOK
+(optab_supported_p,
+ "Return true if the optimizers should use optab @var{op} with\n\
+modes @var{mode1} and @var{mode2} for optimization type @var{opt_type}.\n\
+The optab is known to have an associated @file{.md} instruction\n\
+whose C condition is true. @var{mode2} is only meaningful for conversion\n\
+optabs; for direct optabs it is a copy of @var{mode1}.\n\
+\n\
+For example, when called with @var{op} equal to @code{rint_optab} and\n\
+@var{mode1} equal to @code{DFmode}, the hook should say whether the\n\
+optimizers should use optab @code{rintdf2}.\n\
+\n\
+The default hook returns true for all inputs.",
+ bool, (int op, machine_mode mode1, machine_mode mode2,
+ optimization_type opt_type),
+ default_optab_supported_p)
+
/* True for MODE if the target expects that registers in this mode will
be allocated to registers in a small register class. The compiler is
allowed to use registers explicitly used in the rtl as spill registers
/* Compute a (partial) cost for rtx X. Return true if the complete
cost has been computed, and false if subexpressions should be
scanned. In either case, *TOTAL contains the cost result. */
-/* Note that CODE and OUTER_CODE ought to be RTX_CODE, but that's
+/* Note that OUTER_CODE ought to be RTX_CODE, but that's
not necessarily defined at this point. */
DEFHOOK
(rtx_costs,
either (a) @samp{XEXP (@var{y}, @var{opno}) == @var{x}} or\n\
(b) @samp{XVEC (@var{y}, @var{opno})} contains @var{x}.\n\
\n\
-@var{code} is @var{x}'s expression code---redundant, since it can be\n\
-obtained with @code{GET_CODE (@var{x})}.\n\
+@var{mode} is @var{x}'s machine mode, or for cases like @code{const_int} that\n\
+do not have a mode, the mode in which @var{x} is used.\n\
\n\
In implementing this hook, you can use the construct\n\
@code{COSTS_N_INSNS (@var{n})} to specify a cost equal to @var{n} fast\n\
\n\
The hook returns true when all subexpressions of @var{x} have been\n\
processed, and false when @code{rtx_cost} should recurse.",
- bool, (rtx x, int code, int outer_code, int opno, int *total, bool speed),
- hook_bool_rtx_int_int_int_intp_bool_false)
+ bool, (rtx x, machine_mode mode, int outer_code, int opno, int *total, bool speed),
+ hook_bool_rtx_mode_int_int_intp_bool_false)
/* Compute the cost of X, used as an address. Never called with
invalid addresses. */
int, (rtx address, machine_mode mode, addr_space_t as, bool speed),
default_address_cost)
+/* Permit speculative instructions in delay slots during delayed-branch
+ scheduling. */
+DEFHOOK
+(no_speculation_in_delay_slots_p,
+ "This predicate controls the use of the eager delay slot filler to disallow\n\
+speculatively executed instructions being placed in delay slots. Targets\n\
+such as certain MIPS architectures possess both branches with and without\n\
+delay slots. As the eager delay slot filler can decrease performance,\n\
+disabling it is beneficial when ordinary branches are available. Use of\n\
+delay slot branches filled using the basic filler is often still desirable\n\
+as the delay slot can hide a pipeline bubble.", bool, (void),
+ hook_bool_void_false)
+
/* Return where to allocate pseudo for a given hard register initial value. */
DEFHOOK
(allocate_initial_value,
rtx, (void),
default_builtin_setjmp_frame_value)
-/* This target hook should add STRING_CST trees for any hard regs
- the port wishes to automatically clobber for an asm. */
-DEFHOOK
-(md_asm_clobbers,
- "This target hook should add to @var{clobbers} @code{STRING_CST} trees for\n\
-any hard regs the port wishes to automatically clobber for an asm.\n\
-It should return the result of the last @code{tree_cons} used to add a\n\
-clobber. The @var{outputs}, @var{inputs} and @var{clobber} lists are the\n\
-corresponding parameters to the asm and may be inspected to avoid\n\
-clobbering a register that is an input or output of the asm. You can use\n\
-@code{tree_overlaps_hard_reg_set}, declared in @file{tree.h}, to test\n\
-for overlap with regards to asm-declared registers.",
- tree, (tree outputs, tree inputs, tree clobbers),
- hook_tree_tree_tree_tree_3rd_identity)
+/* This target hook should manipulate the outputs, inputs, constraints,
+ and clobbers the port wishes for pre-processing the asm. */
+DEFHOOK
+(md_asm_adjust,
+ "This target hook may add @dfn{clobbers} to @var{clobbers} and\n\
+@var{clobbered_regs} for any hard regs the port wishes to automatically\n\
+clobber for an asm. The @var{outputs} and @var{inputs} may be inspected\n\
+to avoid clobbering a register that is already used by the asm.\n\
+\n\
+It may modify the @var{outputs}, @var{inputs}, and @var{constraints}\n\
+as necessary for other pre-processing. In this case the return value is\n\
+a sequence of insns to emit after the asm.",
+ rtx_insn *,
+ (vec<rtx>& outputs, vec<rtx>& inputs, vec<const char *>& constraints,
+ vec<rtx>& clobbers, HARD_REG_SET& clobbered_regs),
+ NULL)
/* This target hook allows the backend to specify a calling convention
in the debug information. This function actually returns an
"Perform architecture specific checking of statements gimplified\
from @code{VA_ARG_EXPR}. @var{stmt} is the statement. Returns true if\
the statement doesn't need to be checked for @code{va_list} references.",
- bool, (struct stdarg_info *ai, const_gimple stmt), NULL)
+ bool, (struct stdarg_info *ai, const gimple *stmt), NULL)
/* This target hook allows the operating system to override the DECL
that represents the external variable that contains the stack
tree, (tree type, tree expr),
hook_tree_tree_tree_null)
+/* Change pseudo allocno class calculated by IRA. */
+DEFHOOK
+(ira_change_pseudo_allocno_class,
+ "A target hook which can change allocno class for given pseudo from\n\
+ allocno class calculated by IRA.\n\
+ \n\
+ The default version of this target hook always returns given class.",
+ reg_class_t, (int, reg_class_t),
+ default_ira_change_pseudo_allocno_class)
+
/* Return true if we use LRA instead of reload. */
DEFHOOK
(lra_p,
reg_class_t, (reg_class_t rclass),
default_preferred_rename_class)
+/* This target hook allows the backend to avoid unsafe substitution
+ during register allocation. */
+DEFHOOK
+(cannot_substitute_mem_equiv_p,
+ "A target hook which returns @code{true} if @var{subst} can't\n\
+substitute safely pseudos with equivalent memory values during\n\
+register allocation.\n\
+The default version of this target hook returns @code{false}.\n\
+On most machines, this default should be used. For generally\n\
+machines with non orthogonal register usage for addressing, such\n\
+as SH, this hook can be used to avoid excessive spilling.",
+ bool, (rtx subst),
+ hook_bool_rtx_false)
+
+/* This target hook allows the backend to legitimize base plus
+ displacement addressing. */
+DEFHOOK
+(legitimize_address_displacement,
+ "A target hook which returns @code{true} if *@var{disp} is\n\
+legitimezed to valid address displacement with subtracting *@var{offset}\n\
+at memory mode @var{mode}.\n\
+The default version of this target hook returns @code{false}.\n\
+This hook will benefit machines with limited base plus displacement\n\
+addressing.",
+ bool, (rtx *disp, rtx *offset, machine_mode mode),
+ default_legitimize_address_displacement)
+
/* This target hook allows the backend to perform additional
processing while initializing for variable expansion. */
DEFHOOK
function-specific options to the @code{struct gcc_options} structure.",
void, (struct gcc_options *opts, struct cl_target_option *ptr), NULL)
+/* Function to update target-specific option information after being
+ streamed in. */
+DEFHOOK
+(post_stream_in,
+ "This hook is called to update target-specific information in the\n\
+@code{struct cl_target_option} structure after it is streamed in from\n\
+LTO bytecode.",
+ void, (struct cl_target_option *ptr), NULL)
+
/* Function to print any extra target state from the target options
structure. */
DEFHOOK
bool, (tree caller, tree callee),
default_target_can_inline_p)
+DEFHOOK
+(relayout_function,
+"This target hook fixes function @var{fndecl} after attributes are processed. Default does nothing. On ARM, the default function's alignment is updated with the attribute target.",
+ void, (tree fndecl),
+ hook_void_tree)
+
HOOK_VECTOR_END (target_option)
/* For targets that need to mark extra registers as live on entry to
modifiable by the callee. The affected registers may be mentioned explicitly\n\
in the call pattern, or included as clobbers in CALL_INSN_FUNCTION_USAGE.\n\
The default version of this hook is set to false. The purpose of this hook\n\
-is to enable the fuse-caller-save optimization.",
+is to enable the fipa-ra optimization.",
bool,
false)
this to be done. The default is false.",
bool, false)
-/* True if the target is allowed to reorder memory accesses unless
- synchronization is explicitly requested. */
-DEFHOOKPOD
-(relaxed_ordering,
- "If set to @code{true}, means that the target's memory model does not\n\
-guarantee that loads which do not depend on one another will access\n\
-main memory in the order of the instruction stream; if ordering is\n\
-important, an explicit memory barrier must be used. This is true of\n\
-many recent processors which implement a policy of ``relaxed,''\n\
-``weak,'' or ``release'' memory consistency, such as Alpha, PowerPC,\n\
-and ia64. The default is @code{false}.",
- bool, false)
-
/* Returns true if we should generate exception tables for use with the
ARM EABI. The effects the encoding of function exception specifications. */
DEFHOOKPOD
HOOK_VECTOR_END (mode_switching)
+#undef HOOK_PREFIX
+#define HOOK_PREFIX "TARGET_"
+
+#define DEF_TARGET_INSN(NAME, PROTO) \
+ DEFHOOK_UNDOC (have_##NAME, "", bool, (void), false)
+#include "target-insns.def"
+#undef DEF_TARGET_INSN
+
+#define DEF_TARGET_INSN(NAME, PROTO) \
+ DEFHOOK_UNDOC (gen_##NAME, "", rtx_insn *, PROTO, NULL)
+#include "target-insns.def"
+#undef DEF_TARGET_INSN
+
+#define DEF_TARGET_INSN(NAME, PROTO) \
+ DEFHOOKPOD (code_for_##NAME, "*", enum insn_code, CODE_FOR_nothing)
+#include "target-insns.def"
+#undef DEF_TARGET_INSN
+
/* Close the 'struct gcc_target' definition. */
HOOK_VECTOR_END (C90_EMPTY_HACK)
projects / gcc.git / blobdiff