* config/arm/arm-cores.def (cortex-m1, cortex-m0)

[gcc.git] / gcc / testsuite / gcc.dg / tree-ssa / ssa-dom-thread-4.c

diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-4.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-4.c
index 1396831ac1593bfdd1c4aa17321520eb2e077c13..1cf3f0bf5714d523f7fc40ded1d289f7ca8463ba 100644 (file)
--- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-4.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-4.c
@@ -59,7 +59,9 @@ bitmap_ior_and_compl (bitmap dst, const_bitmap a, const_bitmap b,
    code we missed the edge when the first conditional is false
    (b_elt is zero, which means the second conditional is always
    zero.  */
-/* { dg-final { scan-tree-dump-times "Threaded" 3 "dom1" { target { ! mips*-*-* } } } } */
+/* ARM Cortex-M0 defined LOGICAL_OP_NON_SHORT_CIRCUIT to false,
+   so skip below test.  */
+/* { dg-final { scan-tree-dump-times "Threaded" 3 "dom1" { target { ! { mips*-*-* || { arm_cortex_m && arm_thumb1 } } } } } } */
 /* MIPS defines LOGICAL_OP_NON_SHORT_CIRCUIT to 0, so we split var1 || var2
    into two conditions, rather than use (var1 != 0) | (var2 != 0).  */
 /* { dg-final { scan-tree-dump-times "Threaded" 4 "dom1" { target mips*-*-* } } } */