gdb: include gdbsupport/buildargv.h in ser-mingw.c

[binutils-gdb.git] / gdb / aarch64-tdep.c

diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index 392110afd2b0a23c2c3ae8394cd8959591b62589..63d626f90ace55f80c5d3e3d557993d905a90da1 100644 (file)
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -1,6 +1,6 @@
 /* Common target dependent code for GDB on AArch64 systems.
 
-   Copyright (C) 2009-2021 Free Software Foundation, Inc.
+   Copyright (C) 2009-2022 Free Software Foundation, Inc.
    Contributed by ARM Ltd.
 
    This file is part of GDB.
@@ -516,6 +516,9 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
              /* Return addresses are not mangled.  */
              ra_state_val = 0;
            }
+         else if (IS_BTI (insn))
+           /* We don't need to do anything special for a BTI instruction.  */
+           continue;
          else
            {
              aarch64_debug_printf ("prologue analysis gave up addr=%s"
@@ -870,6 +873,39 @@ aarch64_analyze_prologue_test (void)
          SELF_CHECK (cache.saved_regs[regnum].is_value ());
        }
     }
+
+  /* Test a prologue with a BTI instruction.  */
+    {
+      static const uint32_t insns[] = {
+       0xd503245f, /* bti */
+       0xa9bd7bfd, /* stp      x29, x30, [sp, #-48]! */
+       0x910003fd, /* mov      x29, sp */
+       0xf801c3f3, /* str      x19, [sp, #28] */
+       0xb9401fa0, /* ldr      x19, [x29, #28] */
+      };
+      instruction_reader_test reader (insns);
+
+      trad_frame_reset_saved_regs (gdbarch, cache.saved_regs);
+      CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache,
+                                               reader);
+
+      SELF_CHECK (end == 4 * 4);
+      SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM);
+      SELF_CHECK (cache.framesize == 48);
+
+      for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
+       {
+         if (i == 19)
+           SELF_CHECK (cache.saved_regs[i].addr () == -20);
+         else if (i == AARCH64_FP_REGNUM)
+           SELF_CHECK (cache.saved_regs[i].addr () == -48);
+         else if (i == AARCH64_LR_REGNUM)
+           SELF_CHECK (cache.saved_regs[i].addr () == -40);
+         else
+           SELF_CHECK (cache.saved_regs[i].is_realreg ()
+                       && cache.saved_regs[i].realreg () == i);
+       }
+    }
 }
 } // namespace selftests
 #endif /* GDB_SELF_TEST */
@@ -1881,7 +1917,7 @@ aarch64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
        case TYPE_CODE_CHAR:
        case TYPE_CODE_RANGE:
        case TYPE_CODE_ENUM:
-         if (len < 4)
+         if (len < 4 && !is_fixed_point_type (arg_type))
            {
              /* Promote to 32 bit integer.  */
              if (arg_type->is_unsigned ())
@@ -3616,8 +3652,8 @@ aarch64_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
   if (tdep == NULL)
     return;
 
-  fprintf_unfiltered (file, _("aarch64_dump_tdep: Lowest pc = 0x%s"),
-                     paddress (gdbarch, tdep->lowest_pc));
+  fprintf_filtered (file, _("aarch64_dump_tdep: Lowest pc = 0x%s"),
+                   paddress (gdbarch, tdep->lowest_pc));
 }
 
 #if GDB_SELF_TEST
@@ -4621,10 +4657,11 @@ aarch64_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
   ret = aarch64_record_decode_insn_handler (&aarch64_record);
   if (ret == AARCH64_RECORD_UNSUPPORTED)
     {
-      printf_unfiltered (_("Process record does not support instruction "
-                          "0x%0x at address %s.\n"),
-                        aarch64_record.aarch64_insn,
-                        paddress (gdbarch, insn_addr));
+      fprintf_unfiltered (gdb_stderr,
+                         _("Process record does not support instruction "
+                           "0x%0x at address %s.\n"),
+                         aarch64_record.aarch64_insn,
+                         paddress (gdbarch, insn_addr));
       ret = -1;
     }