/* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
- Copyright (C) 1988-2017 Free Software Foundation, Inc.
+ Copyright (C) 1988-2022 Free Software Foundation, Inc.
Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
#include "infcall.h"
#include "remote.h"
#include "target-descriptions.h"
-#include "dwarf2-frame.h"
+#include "dwarf2/frame.h"
#include "user-regs.h"
#include "valprint.h"
#include "ax.h"
+#include "target-float.h"
#include <algorithm>
-static const struct objfile_data *mips_pdr_data;
-
static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum);
static int mips32_instruction_has_delay_slot (struct gdbarch *gdbarch,
CORE_ADDR addr, int mustbe32);
static void mips_print_float_info (struct gdbarch *, struct ui_file *,
- struct frame_info *, const char *);
+ frame_info_ptr, const char *);
/* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
/* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
struct target_desc *mips_tdesc_gp32;
struct target_desc *mips_tdesc_gp64;
+/* The current set of options to be passed to the disassembler. */
+static char *mips_disassembler_options;
+
+/* Implicit disassembler options for individual ABIs. These tell
+ libopcodes to use general-purpose register names corresponding
+ to the ABI we have selected, perhaps via a `set mips abi ...'
+ override, rather than ones inferred from the ABI set in the ELF
+ headers of the binary file selected for debugging. */
+static const char mips_disassembler_options_o32[] = "gpr-names=32";
+static const char mips_disassembler_options_n32[] = "gpr-names=n32";
+static const char mips_disassembler_options_n64[] = "gpr-names=64";
+
const struct mips_regnum *
mips_regnum (struct gdbarch *gdbarch)
{
- return gdbarch_tdep (gdbarch)->regnum;
+ mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch);
+ return tdep->regnum;
}
static int
&& rawnum < mips_regnum (gdbarch)->fp0 + 32);
}
-#define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
- == MIPS_ABI_EABI32 \
- || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
+static bool
+mips_eabi (gdbarch *arch)
+{
+ mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (arch);
+ return (tdep->mips_abi == MIPS_ABI_EABI32 \
+ || tdep->mips_abi == MIPS_ABI_EABI64);
+}
-#define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
- (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
+static int
+mips_last_fp_arg_regnum (gdbarch *arch)
+{
+ mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (arch);
+ return tdep->mips_last_fp_arg_regnum;
+}
-#define MIPS_LAST_ARG_REGNUM(gdbarch) \
- (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
+static int
+mips_last_arg_regnum (gdbarch *arch)
+{
+ mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (arch);
+ return tdep->mips_last_arg_regnum;
+}
-#define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
+static enum mips_fpu_type
+mips_get_fpu_type (gdbarch *arch)
+{
+ mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (arch);
+ return tdep->mips_fpu_type;
+}
/* Return the MIPS ABI associated with GDBARCH. */
enum mips_abi
mips_abi (struct gdbarch *gdbarch)
{
- return gdbarch_tdep (gdbarch)->mips_abi;
+ mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch);
+ return tdep->mips_abi;
}
int
mips_isa_regsize (struct gdbarch *gdbarch)
{
- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch);
/* If we know how big the registers are, use that size. */
if (tdep->register_size_valid_p)
case MIPS_ABI_UNKNOWN:
case MIPS_ABI_LAST:
default:
- internal_error (__FILE__, __LINE__, _("bad switch"));
+ internal_error (_("bad switch"));
}
}
static int
is_mips16_isa (struct gdbarch *gdbarch)
{
- return gdbarch_tdep (gdbarch)->mips_isa == ISA_MIPS16;
+ mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch);
+ return tdep->mips_isa == ISA_MIPS16;
}
/* Return one iff compressed code is the microMIPS instruction set. */
static int
is_micromips_isa (struct gdbarch *gdbarch)
{
- return gdbarch_tdep (gdbarch)->mips_isa == ISA_MICROMIPS;
+ mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch);
+ return tdep->mips_isa == ISA_MICROMIPS;
}
/* Return one iff ADDR denotes compressed code. */
if (ELF_ST_IS_MICROMIPS (st_other))
{
- MSYMBOL_TARGET_FLAG_MICROMIPS (msym) = 1;
- SET_MSYMBOL_VALUE_ADDRESS (msym, MSYMBOL_VALUE_RAW_ADDRESS (msym) | 1);
+ SET_MSYMBOL_TARGET_FLAG_MICROMIPS (msym);
+ msym->set_value_address (msym->value_raw_address () | 1);
}
else if (ELF_ST_IS_MIPS16 (st_other))
{
- MSYMBOL_TARGET_FLAG_MIPS16 (msym) = 1;
- SET_MSYMBOL_VALUE_ADDRESS (msym, MSYMBOL_VALUE_RAW_ADDRESS (msym) | 1);
+ SET_MSYMBOL_TARGET_FLAG_MIPS16 (msym);
+ msym->set_value_address (msym->value_raw_address () | 1);
}
}
msymbol_is_mips (struct minimal_symbol *msym)
{
return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym)
- | MSYMBOL_TARGET_FLAG_MICROMIPS (msym));
+ || MSYMBOL_TARGET_FLAG_MICROMIPS (msym));
}
/* Return one iff MSYM refers to MIPS16 code. */
static void
mips_make_symbol_special (struct symbol *sym, struct objfile *objfile)
{
- if (SYMBOL_CLASS (sym) == LOC_BLOCK)
+ if (sym->aclass () == LOC_BLOCK)
{
/* We are in symbol reading so it is OK to cast away constness. */
- struct block *block = (struct block *) SYMBOL_BLOCK_VALUE (sym);
+ struct block *block = (struct block *) sym->value_block ();
CORE_ADDR compact_block_start;
struct bound_minimal_symbol msym;
- compact_block_start = BLOCK_START (block) | 1;
+ compact_block_start = block->start () | 1;
msym = lookup_minimal_symbol_by_pc (compact_block_start);
if (msym.minsym && !msymbol_is_mips (msym.minsym))
{
- BLOCK_START (block) = compact_block_start;
+ block->set_start (compact_block_start);
}
}
}
reg_offset = 0;
break;
default:
- internal_error (__FILE__, __LINE__, _("bad switch"));
+ internal_error (_("bad switch"));
}
if (mips_debug)
- fprintf_unfiltered (gdb_stderr,
- "xfer $%d, reg offset %d, buf offset %d, length %d, ",
- reg_num, reg_offset, buf_offset, length);
+ gdb_printf (gdb_stderr,
+ "xfer $%d, reg offset %d, buf offset %d, length %d, ",
+ reg_num, reg_offset, buf_offset, length);
if (mips_debug && out != NULL)
{
int i;
- fprintf_unfiltered (gdb_stdlog, "out ");
+ gdb_printf (gdb_stdlog, "out ");
for (i = 0; i < length; i++)
- fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]);
+ gdb_printf (gdb_stdlog, "%02x", out[buf_offset + i]);
}
if (in != NULL)
- regcache_cooked_read_part (regcache, reg_num, reg_offset, length,
- in + buf_offset);
+ regcache->cooked_read_part (reg_num, reg_offset, length, in + buf_offset);
if (out != NULL)
- regcache_cooked_write_part (regcache, reg_num, reg_offset, length,
- out + buf_offset);
+ regcache->cooked_write_part (reg_num, reg_offset, length, out + buf_offset);
if (mips_debug && in != NULL)
{
int i;
- fprintf_unfiltered (gdb_stdlog, "in ");
+ gdb_printf (gdb_stdlog, "in ");
for (i = 0; i < length; i++)
- fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]);
+ gdb_printf (gdb_stdlog, "%02x", in[buf_offset + i]);
}
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog, "\n");
+ gdb_printf (gdb_stdlog, "\n");
}
/* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
physical 64-bit registers, but should treat them as 32-bit registers. */
static int
-mips2_fp_compat (struct frame_info *frame)
+mips2_fp_compat (frame_info_ptr frame)
{
struct gdbarch *gdbarch = get_frame_arch (frame);
/* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR);
-static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *);
-
/* The list of available "set mips " and "show mips " commands. */
static struct cmd_list_element *setmipscmdlist = NULL;
/* Generic MIPS. */
-static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
+static const char * const mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
"sr", "lo", "hi", "bad", "cause", "pc",
"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
/* Names of tx39 registers. */
-static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
+static const char * const mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
"sr", "lo", "hi", "bad", "cause", "pc",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
};
/* Names of registers with Linux kernels. */
-static const char *mips_linux_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
+static const char * const mips_linux_reg_names[NUM_MIPS_PROCESSOR_REGS] = {
"sr", "lo", "hi", "bad", "cause", "pc",
"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
static const char *
mips_register_name (struct gdbarch *gdbarch, int regno)
{
- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch);
/* GPR names for all ABIs other than n32/n64. */
static const char *mips_gpr_names[] = {
"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
return "";
}
else
- internal_error (__FILE__, __LINE__,
- _("mips_register_name: bad register number %d"), rawnum);
+ internal_error (_("mips_register_name: bad register number %d"), rawnum);
}
/* Return the groups that a MIPS register can be categorised into. */
static int
mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
- struct reggroup *reggroup)
+ const struct reggroup *reggroup)
{
int vector_p;
int float_p;
int pseudo = regnum / gdbarch_num_regs (gdbarch);
if (reggroup == all_reggroup)
return pseudo;
- vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
- float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
+ vector_p = register_type (gdbarch, regnum)->is_vector ();
+ float_p = register_type (gdbarch, regnum)->code () == TYPE_CODE_FLT;
/* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
(gdbarch), as not all architectures are multi-arch. */
raw_p = rawnum < gdbarch_num_regs (gdbarch);
- if (gdbarch_register_name (gdbarch, regnum) == NULL
- || gdbarch_register_name (gdbarch, regnum)[0] == '\0')
+ if (gdbarch_register_name (gdbarch, regnum)[0] == '\0')
return 0;
if (reggroup == float_reggroup)
return float_p && pseudo;
static int
mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
- struct reggroup *reggroup)
+ const struct reggroup *reggroup)
{
int rawnum = regnum % gdbarch_num_regs (gdbarch);
int pseudo = regnum / gdbarch_num_regs (gdbarch);
registers. Take care of alignment and size problems. */
static enum register_status
-mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
+mips_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache,
int cookednum, gdb_byte *buf)
{
int rawnum = cookednum % gdbarch_num_regs (gdbarch);
gdb_assert (cookednum >= gdbarch_num_regs (gdbarch)
&& cookednum < 2 * gdbarch_num_regs (gdbarch));
if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
- return regcache_raw_read (regcache, rawnum, buf);
+ return regcache->raw_read (rawnum, buf);
else if (register_size (gdbarch, rawnum) >
register_size (gdbarch, cookednum))
{
- if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
- return regcache_raw_read_part (regcache, rawnum, 0, 4, buf);
+ mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch);
+
+ if (tdep->mips64_transfers_32bit_regs_p)
+ return regcache->raw_read_part (rawnum, 0, 4, buf);
else
{
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
LONGEST regval;
enum register_status status;
- status = regcache_raw_read_signed (regcache, rawnum, ®val);
+ status = regcache->raw_read (rawnum, ®val);
if (status == REG_VALID)
store_signed_integer (buf, 4, byte_order, regval);
return status;
}
}
else
- internal_error (__FILE__, __LINE__, _("bad register size"));
+ internal_error (_("bad register size"));
}
static void
gdb_assert (cookednum >= gdbarch_num_regs (gdbarch)
&& cookednum < 2 * gdbarch_num_regs (gdbarch));
if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum))
- regcache_raw_write (regcache, rawnum, buf);
+ regcache->raw_write (rawnum, buf);
else if (register_size (gdbarch, rawnum) >
register_size (gdbarch, cookednum))
{
- if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
- regcache_raw_write_part (regcache, rawnum, 0, 4, buf);
+ mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch);
+
+ if (tdep->mips64_transfers_32bit_regs_p)
+ regcache->raw_write_part (rawnum, 0, 4, buf);
else
{
/* Sign extend the shortened version of the register prior
}
}
else
- internal_error (__FILE__, __LINE__, _("bad register size"));
+ internal_error (_("bad register size"));
}
static int
ax_reg (ax, rawnum);
if (register_size (gdbarch, rawnum) > register_size (gdbarch, reg))
- {
- if (!gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p
+ {
+ mips_gdbarch_tdep *tdep
+ = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch);
+
+ if (!tdep->mips64_transfers_32bit_regs_p
|| gdbarch_byte_order (gdbarch) != BFD_ENDIAN_BIG)
{
ax_const_l (ax, 32);
}
}
else
- internal_error (__FILE__, __LINE__, _("bad register size"));
+ internal_error (_("bad register size"));
return 0;
}
register N. NOTE: This defines the pseudo register type so need to
rebuild the architecture vector. */
-static int mips64_transfers_32bit_regs_p = 0;
+static bool mips64_transfers_32bit_regs_p = false;
static void
-set_mips64_transfers_32bit_regs (char *args, int from_tty,
+set_mips64_transfers_32bit_regs (const char *args, int from_tty,
struct cmd_list_element *c)
{
struct gdbarch_info info;
- gdbarch_info_init (&info);
/* FIXME: cagney/2003-11-15: Should be setting a field in "info"
instead of relying on globals. Doing that would let generic code
handle the search for this specific architecture. */
return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG
&& register_size (gdbarch, regnum) == 4
&& mips_float_register_p (gdbarch, regnum)
- && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8);
+ && type->code () == TYPE_CODE_FLT && type->length () == 8);
}
/* This predicate tests for the case of a value of less than 8
int num_regs = gdbarch_num_regs (gdbarch);
return (register_size (gdbarch, regnum) == 8
- && regnum % num_regs > 0 && regnum % num_regs < 32
- && TYPE_LENGTH (type) < 8);
+ && regnum % num_regs > 0 && regnum % num_regs < 32
+ && type->length () < 8);
}
static int
}
static int
-mips_register_to_value (struct frame_info *frame, int regnum,
+mips_register_to_value (frame_info_ptr frame, int regnum,
struct type *type, gdb_byte *to,
int *optimizedp, int *unavailablep)
{
get_frame_register (frame, regnum + 0, to + 4);
get_frame_register (frame, regnum + 1, to + 0);
- if (!get_frame_register_bytes (frame, regnum + 0, 0, 4, to + 4,
+ if (!get_frame_register_bytes (frame, regnum + 0, 0, {to + 4, 4},
optimizedp, unavailablep))
return 0;
- if (!get_frame_register_bytes (frame, regnum + 1, 0, 4, to + 0,
+ if (!get_frame_register_bytes (frame, regnum + 1, 0, {to + 0, 4},
optimizedp, unavailablep))
return 0;
*optimizedp = *unavailablep = 0;
}
else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type))
{
- int len = TYPE_LENGTH (type);
+ size_t len = type->length ();
CORE_ADDR offset;
offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 8 - len : 0;
- if (!get_frame_register_bytes (frame, regnum, offset, len, to,
+ if (!get_frame_register_bytes (frame, regnum, offset, {to, len},
optimizedp, unavailablep))
return 0;
}
else
{
- internal_error (__FILE__, __LINE__,
- _("mips_register_to_value: unrecognized case"));
+ internal_error (_("mips_register_to_value: unrecognized case"));
}
}
static void
-mips_value_to_register (struct frame_info *frame, int regnum,
+mips_value_to_register (frame_info_ptr frame, int regnum,
struct type *type, const gdb_byte *from)
{
struct gdbarch *gdbarch = get_frame_arch (frame);
else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type))
{
gdb_byte fill[8];
- int len = TYPE_LENGTH (type);
+ size_t len = type->length ();
/* Sign extend values, irrespective of type, that are stored to
- a 64-bit general purpose register. (32-bit unsigned values
+ a 64-bit general purpose register. (32-bit unsigned values
are stored as signed quantities within a 64-bit register.
When performing an operation, in compiled code, that combines
a 32-bit unsigned value with a signed 64-bit value, a type
store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1);
else
store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0);
- put_frame_register_bytes (frame, regnum, 0, 8 - len, fill);
- put_frame_register_bytes (frame, regnum, 8 - len, len, from);
+ put_frame_register_bytes (frame, regnum, 0, {fill, 8 - len});
+ put_frame_register_bytes (frame, regnum, 8 - len, {from, len});
}
else
{
store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1);
else
store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0);
- put_frame_register_bytes (frame, regnum, 0, len, from);
- put_frame_register_bytes (frame, regnum, len, 8 - len, fill);
+ put_frame_register_bytes (frame, regnum, 0, {from, len});
+ put_frame_register_bytes (frame, regnum, len, {fill, 8 - len});
}
}
else
{
- internal_error (__FILE__, __LINE__,
- _("mips_value_to_register: unrecognized case"));
+ internal_error (_("mips_value_to_register: unrecognized case"));
}
}
if (mips_float_register_p (gdbarch, regnum))
{
/* The floating-point registers raw, or cooked, always match
- mips_isa_regsize(), and also map 1:1, byte for byte. */
+ mips_isa_regsize(), and also map 1:1, byte for byte. */
if (mips_isa_regsize (gdbarch) == 4)
return builtin_type (gdbarch)->builtin_float;
else
else
{
int rawnum = regnum - gdbarch_num_regs (gdbarch);
+ mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch);
/* The cooked or ABI registers. These are sized according to
the ABI (with a few complications). */
/* The pseudo/cooked view of the embedded registers is always
32-bit. The raw view is handled below. */
return builtin_type (gdbarch)->builtin_int32;
- else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p)
+ else if (tdep->mips64_transfers_32bit_regs_p)
/* The target, while possibly using a 64-bit register buffer,
is only transfering 32-bits of each integer register.
Reflect this in the cooked/pseudo (ABI) register value. */
/* Absent registers are still absent. */
rawtype = gdbarch_register_type (gdbarch, rawnum);
- if (TYPE_LENGTH (rawtype) == 0)
+ if (rawtype->length () == 0)
return rawtype;
/* Present the floating point registers however the hardware did;
/* Use pointer types for registers if we can. For n32 we can not,
since we do not have a 64-bit pointer type. */
if (mips_abi_regsize (gdbarch)
- == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr))
+ == builtin_type (gdbarch)->builtin_data_ptr->length())
{
if (rawnum == MIPS_SP_REGNUM
|| rawnum == mips_regnum (gdbarch)->badvaddr)
return builtin_type (gdbarch)->builtin_func_ptr;
}
- if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8
+ if (mips_abi_regsize (gdbarch) == 4 && rawtype->length () == 8
&& ((rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_PS_REGNUM)
|| rawnum == mips_regnum (gdbarch)->lo
|| rawnum == mips_regnum (gdbarch)->hi
}
/* Should the upper word of 64-bit addresses be zeroed? */
-enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO;
+static enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO;
static int
-mips_mask_address_p (struct gdbarch_tdep *tdep)
+mips_mask_address_p (mips_gdbarch_tdep *tdep)
{
switch (mask_address_var)
{
case AUTO_BOOLEAN_AUTO:
return tdep->default_mask_address_p;
default:
- internal_error (__FILE__, __LINE__,
- _("mips_mask_address_p: bad switch"));
+ internal_error (_("mips_mask_address_p: bad switch"));
return -1;
}
}
show_mask_address (struct ui_file *file, int from_tty,
struct cmd_list_element *c, const char *value)
{
- struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ());
-
- deprecated_show_value_hack (file, from_tty, c, value);
- switch (mask_address_var)
+ const char *additional_text = "";
+ if (mask_address_var == AUTO_BOOLEAN_AUTO)
{
- case AUTO_BOOLEAN_TRUE:
- printf_filtered ("The 32 bit mips address mask is enabled\n");
- break;
- case AUTO_BOOLEAN_FALSE:
- printf_filtered ("The 32 bit mips address mask is disabled\n");
- break;
- case AUTO_BOOLEAN_AUTO:
- printf_filtered
- ("The 32 bit address mask is set automatically. Currently %s\n",
- mips_mask_address_p (tdep) ? "enabled" : "disabled");
- break;
- default:
- internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch"));
- break;
+ if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips)
+ additional_text = _(" (current architecture is not MIPS)");
+ else
+ {
+ mips_gdbarch_tdep *tdep
+ = gdbarch_tdep<mips_gdbarch_tdep> (target_gdbarch ());
+
+ if (mips_mask_address_p (tdep))
+ additional_text = _(" (currently \"on\")");
+ else
+ additional_text = _(" (currently \"off\")");
+ }
}
+
+ gdb_printf (file, _("Zeroing of upper 32 bits of 64-bit addresses is \"%s\"%s.\n"),
+ value, additional_text);
}
/* Tell if the program counter value in MEMADDR is in a standard ISA
all registers should be sign extended for simplicity? */
static CORE_ADDR
-mips_read_pc (struct regcache *regcache)
+mips_read_pc (readable_regcache *regcache)
{
- int regnum = gdbarch_pc_regnum (get_regcache_arch (regcache));
+ int regnum = gdbarch_pc_regnum (regcache->arch ());
LONGEST pc;
- regcache_cooked_read_signed (regcache, regnum, &pc);
+ regcache->cooked_read (regnum, &pc);
return pc;
}
static CORE_ADDR
-mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
+mips_unwind_pc (struct gdbarch *gdbarch, frame_info_ptr next_frame)
{
CORE_ADDR pc;
}
static CORE_ADDR
-mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
+mips_unwind_sp (struct gdbarch *gdbarch, frame_info_ptr next_frame)
{
return frame_unwind_register_signed
(next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM);
breakpoint. */
static struct frame_id
-mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
+mips_dummy_id (struct gdbarch *gdbarch, frame_info_ptr this_frame)
{
return frame_id_build
(get_frame_register_signed (this_frame,
void
mips_write_pc (struct regcache *regcache, CORE_ADDR pc)
{
- int regnum = gdbarch_pc_regnum (get_regcache_arch (regcache));
+ int regnum = gdbarch_pc_regnum (regcache->arch ());
regcache_cooked_write_unsigned (regcache, regnum, pc);
}
instlen = MIPS_INSN32_SIZE;
break;
default:
- internal_error (__FILE__, __LINE__, _("invalid ISA"));
+ internal_error (_("invalid ISA"));
break;
}
err = target_read_memory (addr, buf, instlen);
case ISA_MICROMIPS:
if ((micromips_op (insn) & 0x4) == 0x4
|| (micromips_op (insn) & 0x7) == 0x0)
- return 2 * MIPS_INSN16_SIZE;
+ return 2 * MIPS_INSN16_SIZE;
else
- return MIPS_INSN16_SIZE;
+ return MIPS_INSN16_SIZE;
case ISA_MIPS16:
if ((insn & 0xf800) == 0xf000)
return 2 * MIPS_INSN16_SIZE;
case ISA_MIPS:
return MIPS_INSN32_SIZE;
}
- internal_error (__FILE__, __LINE__, _("invalid ISA"));
+ internal_error (_("invalid ISA"));
}
static LONGEST
const struct bfd_arch_info *info = gdbarch_bfd_arch_info (gdbarch);
return (info->mach == bfd_mach_mips_octeon
- || info->mach == bfd_mach_mips_octeonp
- || info->mach == bfd_mach_mips_octeon2);
+ || info->mach == bfd_mach_mips_octeonp
+ || info->mach == bfd_mach_mips_octeon2);
}
/* Return true if the OP represents the Octeon's BBIT instruction. */
static CORE_ADDR
mips32_next_pc (struct regcache *regcache, CORE_ADDR pc)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
unsigned long inst;
int op;
inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL);
if (((regcache_raw_get_signed (regcache,
itype_rs (inst)) >> bit) & 1)
- == branch_if)
+ == branch_if)
pc += mips32_relative_offset (inst) + 4;
- else
+ else
pc += 8; /* After the delay slot. */
}
break;
case 12: /* SYSCALL */
{
- struct gdbarch_tdep *tdep;
+ mips_gdbarch_tdep *tdep
+ = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch);
- tdep = gdbarch_tdep (gdbarch);
if (tdep->syscall_next_pc != NULL)
pc = tdep->syscall_next_pc (get_current_frame ());
else
static CORE_ADDR
micromips_next_pc (struct regcache *regcache, CORE_ADDR pc)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
ULONGEST insn;
insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL);
switch (micromips_op (insn >> 16))
{
case 0x00: /* POOL32A: bits 000000 */
- if (b0s6_op (insn) == 0x3c
- /* POOL32Axf: bits 000000 ... 111100 */
- && (b6s10_ext (insn) & 0x2bf) == 0x3c)
- /* JALR, JALR.HB: 000000 000x111100 111100 */
- /* JALRS, JALRS.HB: 000000 010x111100 111100 */
- pc = regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16));
+ switch (b0s6_op (insn))
+ {
+ case 0x3c: /* POOL32Axf: bits 000000 ... 111100 */
+ switch (b6s10_ext (insn))
+ {
+ case 0x3c: /* JALR: 000000 0000111100 111100 */
+ case 0x7c: /* JALR.HB: 000000 0001111100 111100 */
+ case 0x13c: /* JALRS: 000000 0100111100 111100 */
+ case 0x17c: /* JALRS.HB: 000000 0101111100 111100 */
+ pc = regcache_raw_get_signed (regcache,
+ b0s5_reg (insn >> 16));
+ break;
+ case 0x22d: /* SYSCALL: 000000 1000101101 111100 */
+ {
+ mips_gdbarch_tdep *tdep
+ = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch);
+
+ if (tdep->syscall_next_pc != NULL)
+ pc = tdep->syscall_next_pc (get_current_frame ());
+ }
+ break;
+ }
+ break;
+ }
break;
case 0x10: /* POOL32I: bits 010000 */
if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16))
!= regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16)))
pc += micromips_relative_offset16 (insn);
- else
+ else
pc += micromips_pc_insn_size (gdbarch, pc);
break;
break;
}
default:
- internal_error (__FILE__, __LINE__, _("bad switch"));
+ internal_error (_("bad switch"));
}
upk->offset = offset;
upk->regx = regx;
extended_mips16_next_pc (regcache *regcache, CORE_ADDR pc,
unsigned int extension, unsigned int insn)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
int op = (insn >> 11);
switch (op)
{
}
case 30:
/* This is an instruction extension. Fetch the real instruction
- (which follows the extension) and decode things based on
- that. */
+ (which follows the extension) and decode things based on
+ that. */
{
pc += 2;
pc = extended_mips16_next_pc (regcache, pc, insn,
static CORE_ADDR
mips16_next_pc (struct regcache *regcache, CORE_ADDR pc)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
unsigned int insn = fetch_mips_16 (gdbarch, pc);
return extended_mips16_next_pc (regcache, pc, 0, insn);
}
static CORE_ADDR
mips_next_pc (struct regcache *regcache, CORE_ADDR pc)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
if (mips_pc_is_mips16 (gdbarch, pc))
return mips16_next_pc (regcache, pc);
struct mips_frame_cache
{
CORE_ADDR base;
- struct trad_frame_saved_reg *saved_regs;
+ trad_frame_saved_reg *saved_regs;
};
/* Set a register's saved stack address in temp_saved_regs. If an
int regnum, CORE_ADDR offset)
{
if (this_cache != NULL
- && this_cache->saved_regs[regnum].addr == -1)
+ && this_cache->saved_regs[regnum].is_realreg ()
+ && this_cache->saved_regs[regnum].realreg () == regnum)
{
- this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr
- = offset;
- this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr
- = offset;
+ this_cache->saved_regs[regnum + 0
+ * gdbarch_num_regs (gdbarch)].set_addr (offset);
+ this_cache->saved_regs[regnum + 1
+ * gdbarch_num_regs (gdbarch)].set_addr (offset);
}
}
static CORE_ADDR
mips16_scan_prologue (struct gdbarch *gdbarch,
CORE_ADDR start_pc, CORE_ADDR limit_pc,
- struct frame_info *this_frame,
- struct mips_frame_cache *this_cache)
+ frame_info_ptr this_frame,
+ struct mips_frame_cache *this_cache)
{
int prev_non_prologue_insn = 0;
int this_non_prologue_insn;
in_delay_slot = 0;
/* Save the previous instruction. If it's an EXTEND, we'll extract
- the immediate offset extension from it in mips16_get_imm. */
+ the immediate offset extension from it in mips16_get_imm. */
prev_inst = inst;
/* Fetch and decode the instruction. */
cur_pc, NULL);
/* Normally we ignore extend instructions. However, if it is
- not followed by a valid prologue instruction, then this
- instruction is not part of the prologue either. We must
- remember in this case to adjust the end_prologue_addr back
- over the extend. */
+ not followed by a valid prologue instruction, then this
+ instruction is not part of the prologue either. We must
+ remember in this case to adjust the end_prologue_addr back
+ over the extend. */
if ((inst & 0xf800) == 0xf000) /* extend */
- {
- extend_bytes = MIPS_INSN16_SIZE;
- continue;
- }
+ {
+ extend_bytes = MIPS_INSN16_SIZE;
+ continue;
+ }
prev_extend_bytes = extend_bytes;
extend_bytes = 0;
set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset);
}
else if ((inst & 0xf81f) == 0xe809
- && (inst & 0x700) != 0x700) /* entry */
+ && (inst & 0x700) != 0x700) /* entry */
entry_inst = inst; /* Save for later processing. */
else if ((inst & 0xff80) == 0x6480) /* save */
{
save_inst |= prev_inst << 16;
}
else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
- {
- /* This instruction is part of the prologue, but we don't
- need to do anything special to handle it. */
- }
+ {
+ /* This instruction is part of the prologue, but we don't
+ need to do anything special to handle it. */
+ }
else if (mips16_instruction_has_delay_slot (inst, 0))
/* JAL/JALR/JALX/JR */
{
}
}
else
- {
+ {
this_non_prologue_insn = 1;
- }
+ }
non_prologue_insns += this_non_prologue_insn;
/* A jump or branch, or enough non-prologue insns seen? If so,
- then we must have reached the end of the prologue by now. */
+ then we must have reached the end of the prologue by now. */
if (prev_delay_slot || non_prologue_insns > 1
|| mips16_instruction_is_compact_branch (inst))
break;
frame_offset += 32;
/* Now we can calculate what the SP must have been at the
- start of the function prologue. */
+ start of the function prologue. */
sp += frame_offset;
/* Check if a0-a3 were saved in the caller's argument save area. */
frame_offset += frame_size;
/* Now we can calculate what the SP must have been at the
- start of the function prologue. */
+ start of the function prologue. */
sp += frame_offset;
/* Check if A0-A3 were saved in the caller's argument save area. */
if (this_cache != NULL)
{
this_cache->base =
- (get_frame_register_signed (this_frame,
+ (get_frame_register_signed (this_frame,
gdbarch_num_regs (gdbarch) + frame_reg)
- + frame_offset - frame_adjust);
+ + frame_offset - frame_adjust);
/* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
- be able to get rid of the assignment below, evetually. But it's
- still needed for now. */
+ be able to get rid of the assignment below, evetually. But it's
+ still needed for now. */
this_cache->saved_regs[gdbarch_num_regs (gdbarch)
+ mips_regnum (gdbarch)->pc]
- = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM];
+ = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM];
}
/* Set end_prologue_addr to the address of the instruction immediately
mips_insn32 unwinder. */
static struct mips_frame_cache *
-mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache)
+mips_insn16_frame_cache (frame_info_ptr this_frame, void **this_cache)
{
struct gdbarch *gdbarch = get_frame_arch (this_frame);
struct mips_frame_cache *cache;
}
/* gdbarch_sp_regnum contains the value and not the address. */
- trad_frame_set_value (cache->saved_regs,
- gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM,
- cache->base);
+ cache->saved_regs[gdbarch_num_regs (gdbarch)
+ + MIPS_SP_REGNUM].set_value (cache->base);
return (struct mips_frame_cache *) (*this_cache);
}
static void
-mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache,
+mips_insn16_frame_this_id (frame_info_ptr this_frame, void **this_cache,
struct frame_id *this_id)
{
struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
}
static struct value *
-mips_insn16_frame_prev_register (struct frame_info *this_frame,
+mips_insn16_frame_prev_register (frame_info_ptr this_frame,
void **this_cache, int regnum)
{
struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
static int
mips_insn16_frame_sniffer (const struct frame_unwind *self,
- struct frame_info *this_frame, void **this_cache)
+ frame_info_ptr this_frame, void **this_cache)
{
struct gdbarch *gdbarch = get_frame_arch (this_frame);
CORE_ADDR pc = get_frame_pc (this_frame);
static const struct frame_unwind mips_insn16_frame_unwind =
{
+ "mips insn16 prologue",
NORMAL_FRAME,
default_frame_unwind_stop_reason,
mips_insn16_frame_this_id,
};
static CORE_ADDR
-mips_insn16_frame_base_address (struct frame_info *this_frame,
+mips_insn16_frame_base_address (frame_info_ptr this_frame,
void **this_cache)
{
struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame,
};
static const struct frame_base *
-mips_insn16_frame_base_sniffer (struct frame_info *this_frame)
+mips_insn16_frame_base_sniffer (frame_info_ptr this_frame)
{
struct gdbarch *gdbarch = get_frame_arch (this_frame);
CORE_ADDR pc = get_frame_pc (this_frame);
static CORE_ADDR
micromips_scan_prologue (struct gdbarch *gdbarch,
CORE_ADDR start_pc, CORE_ADDR limit_pc,
- struct frame_info *this_frame,
+ frame_info_ptr this_frame,
struct mips_frame_cache *this_cache)
{
CORE_ADDR end_prologue_addr;
default:
/* The instruction in the delay slot can be a part
- of the prologue, so move forward once more. */
+ of the prologue, so move forward once more. */
if (micromips_instruction_has_delay_slot (insn, 0))
in_delay_slot = 1;
else
default:
/* The instruction in the delay slot can be a part
- of the prologue, so move forward once more. */
+ of the prologue, so move forward once more. */
if (micromips_instruction_has_delay_slot (insn << 16, 0))
in_delay_slot = 1;
else
non_prologue_insns += this_non_prologue_insn;
/* A jump or branch, enough non-prologue insns seen or positive
- stack adjustment? If so, then we must have reached the end
- of the prologue by now. */
+ stack adjustment? If so, then we must have reached the end
+ of the prologue by now. */
if (prev_delay_slot || non_prologue_insns > 1 || sp_adj > 0
|| micromips_instruction_is_compact_branch (insn))
break;
mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
static struct mips_frame_cache *
-mips_micro_frame_cache (struct frame_info *this_frame, void **this_cache)
+mips_micro_frame_cache (frame_info_ptr this_frame, void **this_cache)
{
struct gdbarch *gdbarch = get_frame_arch (this_frame);
struct mips_frame_cache *cache;
}
/* gdbarch_sp_regnum contains the value and not the address. */
- trad_frame_set_value (cache->saved_regs,
- gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM,
- cache->base);
+ cache->saved_regs[gdbarch_num_regs (gdbarch)
+ + MIPS_SP_REGNUM].set_value (cache->base);
return (struct mips_frame_cache *) (*this_cache);
}
static void
-mips_micro_frame_this_id (struct frame_info *this_frame, void **this_cache,
+mips_micro_frame_this_id (frame_info_ptr this_frame, void **this_cache,
struct frame_id *this_id)
{
struct mips_frame_cache *info = mips_micro_frame_cache (this_frame,
}
static struct value *
-mips_micro_frame_prev_register (struct frame_info *this_frame,
+mips_micro_frame_prev_register (frame_info_ptr this_frame,
void **this_cache, int regnum)
{
struct mips_frame_cache *info = mips_micro_frame_cache (this_frame,
static int
mips_micro_frame_sniffer (const struct frame_unwind *self,
- struct frame_info *this_frame, void **this_cache)
+ frame_info_ptr this_frame, void **this_cache)
{
struct gdbarch *gdbarch = get_frame_arch (this_frame);
CORE_ADDR pc = get_frame_pc (this_frame);
static const struct frame_unwind mips_micro_frame_unwind =
{
+ "mips micro prologue",
NORMAL_FRAME,
default_frame_unwind_stop_reason,
mips_micro_frame_this_id,
};
static CORE_ADDR
-mips_micro_frame_base_address (struct frame_info *this_frame,
+mips_micro_frame_base_address (frame_info_ptr this_frame,
void **this_cache)
{
struct mips_frame_cache *info = mips_micro_frame_cache (this_frame,
};
static const struct frame_base *
-mips_micro_frame_base_sniffer (struct frame_info *this_frame)
+mips_micro_frame_base_sniffer (frame_info_ptr this_frame)
{
struct gdbarch *gdbarch = get_frame_arch (this_frame);
CORE_ADDR pc = get_frame_pc (this_frame);
const int num_regs = gdbarch_num_regs (gdbarch);
int i;
+ /* Reset the register values to their default state. Register i's value
+ is in register i. */
for (i = 0; i < num_regs; i++)
- {
- this_cache->saved_regs[i].addr = -1;
- }
+ this_cache->saved_regs[i].set_realreg (i);
}
}
static CORE_ADDR
mips32_scan_prologue (struct gdbarch *gdbarch,
CORE_ADDR start_pc, CORE_ADDR limit_pc,
- struct frame_info *this_frame,
- struct mips_frame_cache *this_cache)
+ frame_info_ptr this_frame,
+ struct mips_frame_cache *this_cache)
{
int prev_non_prologue_insn;
int this_non_prologue_insn;
|| high_word == 0x67bd) /* daddiu $sp,$sp,-i */
{
if (offset < 0) /* Negative stack adjustment? */
- frame_offset -= offset;
+ frame_offset -= offset;
else
/* Exit loop if a positive stack adjustment is found, which
usually means that the stack cleanup code in the function
epilogue is reached. */
break;
- seen_sp_adjust = 1;
+ seen_sp_adjust = 1;
}
else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
- && !regsize_is_64_bits)
+ && !regsize_is_64_bits)
{
set_reg_offset (gdbarch, this_cache, reg, sp + offset);
}
else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
- && regsize_is_64_bits)
+ && regsize_is_64_bits)
{
/* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
set_reg_offset (gdbarch, this_cache, reg, sp + offset);
alloca_adjust = (unsigned) (frame_addr - (sp + offset));
if (alloca_adjust > 0)
{
- /* FP > SP + frame_size. This may be because of
- an alloca or somethings similar. Fix sp to
- "pre-alloca" value, and try again. */
+ /* FP > SP + frame_size. This may be because of
+ an alloca or somethings similar. Fix sp to
+ "pre-alloca" value, and try again. */
sp += alloca_adjust;
- /* Need to reset the status of all registers. Otherwise,
- we will hit a guard that prevents the new address
- for each register to be recomputed during the second
- pass. */
- reset_saved_regs (gdbarch, this_cache);
+ /* Need to reset the status of all registers. Otherwise,
+ we will hit a guard that prevents the new address
+ for each register to be recomputed during the second
+ pass. */
+ reset_saved_regs (gdbarch, this_cache);
goto restart;
}
}
}
/* move $30,$sp. With different versions of gas this will be either
- `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
- Accept any one of these. */
+ `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
+ Accept any one of these. */
else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d)
{
/* New gcc frame, virtual frame pointer is at r30 + frame_size. */
alloca_adjust = (unsigned) (frame_addr - sp);
if (alloca_adjust > 0)
- {
- /* FP > SP + frame_size. This may be because of
- an alloca or somethings similar. Fix sp to
- "pre-alloca" value, and try again. */
- sp = frame_addr;
- /* Need to reset the status of all registers. Otherwise,
- we will hit a guard that prevents the new address
- for each register to be recomputed during the second
- pass. */
- reset_saved_regs (gdbarch, this_cache);
- goto restart;
- }
+ {
+ /* FP > SP + frame_size. This may be because of
+ an alloca or somethings similar. Fix sp to
+ "pre-alloca" value, and try again. */
+ sp = frame_addr;
+ /* Need to reset the status of all registers. Otherwise,
+ we will hit a guard that prevents the new address
+ for each register to be recomputed during the second
+ pass. */
+ reset_saved_regs (gdbarch, this_cache);
+ goto restart;
+ }
}
}
else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
- && !regsize_is_64_bits)
+ && !regsize_is_64_bits)
{
set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset);
}
else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
- || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
- || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
- || high_word == 0x3c1c /* lui $gp,n */
- || high_word == 0x279c /* addiu $gp,$gp,n */
- || inst == 0x0399e021 /* addu $gp,$gp,$t9 */
- || inst == 0x033ce021 /* addu $gp,$t9,$gp */
- )
+ || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
+ || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
+ || high_word == 0x3c1c /* lui $gp,n */
+ || high_word == 0x279c /* addiu $gp,$gp,n */
+ || high_word == 0x679c /* daddiu $gp,$gp,n */
+ || inst == 0x0399e021 /* addu $gp,$gp,$t9 */
+ || inst == 0x033ce021 /* addu $gp,$t9,$gp */
+ || inst == 0x0399e02d /* daddu $gp,$gp,$t9 */
+ || inst == 0x033ce02d /* daddu $gp,$t9,$gp */
+ )
{
/* These instructions are part of the prologue, but we don't
need to do anything special to handle them. */
}
/* The instructions below load $at or $t0 with an immediate
- value in preparation for a stack adjustment via
- subu $sp,$sp,[$at,$t0]. These instructions could also
- initialize a local variable, so we accept them only before
- a stack adjustment instruction was seen. */
+ value in preparation for a stack adjustment via
+ subu $sp,$sp,[$at,$t0]. These instructions could also
+ initialize a local variable, so we accept them only before
+ a stack adjustment instruction was seen. */
else if (!seen_sp_adjust
&& !prev_delay_slot
&& (high_word == 0x3c01 /* lui $at,n */
load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */
}
/* Check for branches and jumps. The instruction in the delay
- slot can be a part of the prologue, so move forward once more. */
+ slot can be a part of the prologue, so move forward once more. */
else if (mips32_instruction_has_delay_slot (gdbarch, inst))
{
in_delay_slot = 1;
}
/* This instruction is not an instruction typically found
- in a prologue, so we must have reached the end of the
- prologue. */
+ in a prologue, so we must have reached the end of the
+ prologue. */
else
{
this_non_prologue_insn = 1;
non_prologue_insns += this_non_prologue_insn;
/* A jump or branch, or enough non-prologue insns seen? If so,
- then we must have reached the end of the prologue by now. */
+ then we must have reached the end of the prologue by now. */
if (prev_delay_slot || non_prologue_insns > 1)
break;
if (this_cache != NULL)
{
this_cache->base =
- (get_frame_register_signed (this_frame,
+ (get_frame_register_signed (this_frame,
gdbarch_num_regs (gdbarch) + frame_reg)
- + frame_offset);
+ + frame_offset);
/* FIXME: brobecker/2004-09-15: We should be able to get rid of
- this assignment below, eventually. But it's still needed
- for now. */
+ this assignment below, eventually. But it's still needed
+ for now. */
this_cache->saved_regs[gdbarch_num_regs (gdbarch)
+ mips_regnum (gdbarch)->pc]
- = this_cache->saved_regs[gdbarch_num_regs (gdbarch)
+ = this_cache->saved_regs[gdbarch_num_regs (gdbarch)
+ MIPS_RA_REGNUM];
}
unwinder. Likewise microMIPS and the mips_micro unwinder. */
static struct mips_frame_cache *
-mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache)
+mips_insn32_frame_cache (frame_info_ptr this_frame, void **this_cache)
{
struct gdbarch *gdbarch = get_frame_arch (this_frame);
struct mips_frame_cache *cache;
}
/* gdbarch_sp_regnum contains the value and not the address. */
- trad_frame_set_value (cache->saved_regs,
- gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM,
- cache->base);
+ cache->saved_regs[gdbarch_num_regs (gdbarch)
+ + MIPS_SP_REGNUM].set_value (cache->base);
return (struct mips_frame_cache *) (*this_cache);
}
static void
-mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache,
+mips_insn32_frame_this_id (frame_info_ptr this_frame, void **this_cache,
struct frame_id *this_id)
{
struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
}
static struct value *
-mips_insn32_frame_prev_register (struct frame_info *this_frame,
+mips_insn32_frame_prev_register (frame_info_ptr this_frame,
void **this_cache, int regnum)
{
struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
static int
mips_insn32_frame_sniffer (const struct frame_unwind *self,
- struct frame_info *this_frame, void **this_cache)
+ frame_info_ptr this_frame, void **this_cache)
{
CORE_ADDR pc = get_frame_pc (this_frame);
if (mips_pc_is_mips (pc))
static const struct frame_unwind mips_insn32_frame_unwind =
{
+ "mips insn32 prologue",
NORMAL_FRAME,
default_frame_unwind_stop_reason,
mips_insn32_frame_this_id,
};
static CORE_ADDR
-mips_insn32_frame_base_address (struct frame_info *this_frame,
+mips_insn32_frame_base_address (frame_info_ptr this_frame,
void **this_cache)
{
struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame,
};
static const struct frame_base *
-mips_insn32_frame_base_sniffer (struct frame_info *this_frame)
+mips_insn32_frame_base_sniffer (frame_info_ptr this_frame)
{
CORE_ADDR pc = get_frame_pc (this_frame);
if (mips_pc_is_mips (pc))
}
static struct trad_frame_cache *
-mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache)
+mips_stub_frame_cache (frame_info_ptr this_frame, void **this_cache)
{
CORE_ADDR pc;
CORE_ADDR start_addr;
}
static void
-mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache,
+mips_stub_frame_this_id (frame_info_ptr this_frame, void **this_cache,
struct frame_id *this_id)
{
struct trad_frame_cache *this_trad_cache
}
static struct value *
-mips_stub_frame_prev_register (struct frame_info *this_frame,
+mips_stub_frame_prev_register (frame_info_ptr this_frame,
void **this_cache, int regnum)
{
struct trad_frame_cache *this_trad_cache
static int
mips_stub_frame_sniffer (const struct frame_unwind *self,
- struct frame_info *this_frame, void **this_cache)
+ frame_info_ptr this_frame, void **this_cache)
{
gdb_byte dummy[4];
- struct obj_section *s;
CORE_ADDR pc = get_frame_address_in_block (this_frame);
struct bound_minimal_symbol msym;
stub. The stub for foo is named ".pic.foo". */
msym = lookup_minimal_symbol_by_pc (pc);
if (msym.minsym != NULL
- && MSYMBOL_LINKAGE_NAME (msym.minsym) != NULL
- && startswith (MSYMBOL_LINKAGE_NAME (msym.minsym), ".pic."))
+ && msym.minsym->linkage_name () != NULL
+ && startswith (msym.minsym->linkage_name (), ".pic."))
return 1;
return 0;
static const struct frame_unwind mips_stub_frame_unwind =
{
+ "mips stub",
NORMAL_FRAME,
default_frame_unwind_stop_reason,
mips_stub_frame_this_id,
};
static CORE_ADDR
-mips_stub_frame_base_address (struct frame_info *this_frame,
+mips_stub_frame_base_address (frame_info_ptr this_frame,
void **this_cache)
{
struct trad_frame_cache *this_trad_cache
};
static const struct frame_base *
-mips_stub_frame_base_sniffer (struct frame_info *this_frame)
+mips_stub_frame_base_sniffer (frame_info_ptr this_frame)
{
if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL))
return &mips_stub_frame_base;
static CORE_ADDR
mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr)
{
- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch);
if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL))
/* This hack is a work-around for existing boards using PMON, the
static std::vector<CORE_ADDR>
mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
{
- CORE_ADDR breaks[2] = {-1, -1};
+ CORE_ADDR breaks[2] = {CORE_ADDR_MAX, CORE_ADDR_MAX};
CORE_ADDR loc = pc;
CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */
ULONGEST insn;
{
const int atomic_sequence_length = 16; /* Instruction sequence length. */
int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
- CORE_ADDR breaks[2] = {-1, -1};
+ CORE_ADDR breaks[2] = {CORE_ADDR_MAX, CORE_ADDR_MAX};
CORE_ADDR branch_bp = 0; /* Breakpoint at branch instruction's
destination. */
CORE_ADDR loc = pc;
loc += MIPS_INSN16_SIZE;
/* Assume that there is at most one conditional branch in the
- atomic sequence. If a branch is found, put a breakpoint in
- its destination address. */
+ atomic sequence. If a branch is found, put a breakpoint in
+ its destination address. */
switch (mips_insn_size (ISA_MICROMIPS, insn))
{
/* 32-bit instructions. */
case 0x11: /* POOL16C: bits 010001 */
if ((b5s5_op (insn) & 0x1c) != 0xc
/* JR16, JRC, JALR16, JALRS16: 010001 011xx */
- && b5s5_op (insn) != 0x18)
+ && b5s5_op (insn) != 0x18)
/* JRADDIUSP: bits 010001 11000 */
- break;
+ break;
return {}; /* Fall back to the standard single-step code. */
case 0x33: /* B16: bits 110011 */
std::vector<CORE_ADDR>
mips_software_single_step (struct regcache *regcache)
{
- struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch *gdbarch = regcache->arch ();
CORE_ADDR pc, next_pc;
pc = regcache_read_pc (regcache);
particular. This message needs to give people
in that situation enough information to
determine that it's no big deal. */
- printf_filtered ("\n\
+ gdb_printf ("\n\
GDB is unable to find the start of the function at %s\n\
and thus can't determine the size of that function's stack frame.\n\
This means that GDB may be unable to access that stack frame, or\n\
from %s for code which looks like the beginning of a\n\
function, you can increase the range of the search using the `set\n\
heuristic-fence-post' command.\n",
- paddress (gdbarch, pc), paddress (gdbarch, pc));
+ paddress (gdbarch, pc), paddress (gdbarch, pc));
blurb_printed = 1;
}
}
/* On MIPS16, any one of the following is likely to be the
start of a function:
- extend save
+ extend save
save
entry
addiu sp,-n
struct type *arg_type)
{
return ((typecode == TYPE_CODE_FLT
- || (MIPS_EABI (gdbarch)
+ || (mips_eabi (gdbarch)
&& (typecode == TYPE_CODE_STRUCT
|| typecode == TYPE_CODE_UNION)
- && TYPE_NFIELDS (arg_type) == 1
- && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0)))
+ && arg_type->num_fields () == 1
+ && check_typedef (arg_type->field (0).type ())->code ()
== TYPE_CODE_FLT))
- && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE);
+ && mips_get_fpu_type (gdbarch) != MIPS_FPU_NONE);
}
/* On o32, argument passing in GPRs depends on the alignment of the type being
static int
mips_type_needs_double_align (struct type *type)
{
- enum type_code typecode = TYPE_CODE (type);
+ enum type_code typecode = type->code ();
- if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8)
+ if (typecode == TYPE_CODE_FLT && type->length () == 8)
return 1;
else if (typecode == TYPE_CODE_STRUCT)
{
- if (TYPE_NFIELDS (type) < 1)
+ if (type->num_fields () < 1)
return 0;
- return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0));
+ return mips_type_needs_double_align (type->field (0).type ());
}
else if (typecode == TYPE_CODE_UNION)
{
int i, n;
- n = TYPE_NFIELDS (type);
+ n = type->num_fields ();
for (i = 0; i < n; i++)
- if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i)))
+ if (mips_type_needs_double_align (type->field (i).type ()))
return 1;
return 0;
}
mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
struct regcache *regcache, CORE_ADDR bp_addr,
int nargs, struct value **args, CORE_ADDR sp,
- int struct_return, CORE_ADDR struct_addr)
+ function_call_return_method return_method,
+ CORE_ADDR struct_addr)
{
int argreg;
int float_argreg;
int argnum;
- int len = 0;
+ int arg_space = 0;
int stack_offset = 0;
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
CORE_ADDR func_addr = find_function_addr (function, NULL);
than necessary for EABI, because the first few arguments are
passed in registers, but that's OK. */
for (argnum = 0; argnum < nargs; argnum++)
- len += align_up (TYPE_LENGTH (value_type (args[argnum])), abi_regsize);
- sp -= align_up (len, 16);
+ arg_space += align_up (value_type (args[argnum])->length (),
+ abi_regsize);
+ sp -= align_up (arg_space, 16);
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog,
- "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
- paddress (gdbarch, sp), (long) align_up (len, 16));
+ gdb_printf (gdb_stdlog,
+ "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
+ paddress (gdbarch, sp),
+ (long) align_up (arg_space, 16));
/* Initialize the integer and float register pointers. */
argreg = MIPS_A0_REGNUM;
float_argreg = mips_fpa0_regnum (gdbarch);
/* The struct_return pointer occupies the first parameter-passing reg. */
- if (struct_return)
+ if (return_method == return_method_struct)
{
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog,
- "mips_eabi_push_dummy_call: "
- "struct_return reg=%d %s\n",
- argreg, paddress (gdbarch, struct_addr));
+ gdb_printf (gdb_stdlog,
+ "mips_eabi_push_dummy_call: "
+ "struct_return reg=%d %s\n",
+ argreg, paddress (gdbarch, struct_addr));
regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
}
gdb_byte ref_valbuf[MAX_MIPS_ABI_REGSIZE];
struct value *arg = args[argnum];
struct type *arg_type = check_typedef (value_type (arg));
- int len = TYPE_LENGTH (arg_type);
- enum type_code typecode = TYPE_CODE (arg_type);
+ int len = arg_type->length ();
+ enum type_code typecode = arg_type->code ();
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog,
- "mips_eabi_push_dummy_call: %d len=%d type=%d",
- argnum + 1, len, (int) typecode);
+ gdb_printf (gdb_stdlog,
+ "mips_eabi_push_dummy_call: %d len=%d type=%d",
+ argnum + 1, len, (int) typecode);
/* The EABI passes structures that do not fit in a register by
- reference. */
+ reference. */
if (len > abi_regsize
&& (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION))
{
len = abi_regsize;
val = ref_valbuf;
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog, " push");
+ gdb_printf (gdb_stdlog, " push");
}
else
- val = value_contents (arg);
+ val = value_contents (arg).data ();
/* 32-bit ABIs always start floating point arguments in an
- even-numbered floating point register. Round the FP register
- up before the check to see if there are any FP registers
- left. Non MIPS_EABI targets also pass the FP in the integer
- registers so also round up normal registers. */
+ even-numbered floating point register. Round the FP register
+ up before the check to see if there are any FP registers
+ left. Non MIPS_EABI targets also pass the FP in the integer
+ registers so also round up normal registers. */
if (abi_regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type))
{
if ((float_argreg & 1))
}
/* Floating point arguments passed in registers have to be
- treated specially. On 32-bit architectures, doubles
- are passed in register pairs; the even register gets
- the low word, and the odd register gets the high word.
- On non-EABI processors, the first two floating point arguments are
- also copied to general registers, because MIPS16 functions
- don't use float registers for arguments. This duplication of
- arguments in general registers can't hurt non-MIPS16 functions
- because those registers are normally skipped. */
+ treated specially. On 32-bit architectures, doubles
+ are passed in register pairs; the even register gets
+ the low word, and the odd register gets the high word.
+ On non-EABI processors, the first two floating point arguments are
+ also copied to general registers, because MIPS16 functions
+ don't use float registers for arguments. This duplication of
+ arguments in general registers can't hurt non-MIPS16 functions
+ because those registers are normally skipped. */
/* MIPS_EABI squeezes a struct that contains a single floating
- point value into an FP register instead of pushing it onto the
- stack. */
+ point value into an FP register instead of pushing it onto the
+ stack. */
if (fp_register_arg_p (gdbarch, typecode, arg_type)
- && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch))
+ && float_argreg <= mips_last_fp_arg_regnum (gdbarch))
{
/* EABI32 will pass doubles in consecutive registers, even on
64-bit cores. At one time, we used to check the size of
regval = extract_signed_integer (val + low_offset,
4, byte_order);
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
- float_argreg, phex (regval, 4));
+ gdb_printf (gdb_stdlog, " - fpreg=%d val=%s",
+ float_argreg, phex (regval, 4));
regcache_cooked_write_signed (regcache, float_argreg++, regval);
/* Write the high word of the double to the odd register(s). */
regval = extract_signed_integer (val + 4 - low_offset,
4, byte_order);
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
- float_argreg, phex (regval, 4));
+ gdb_printf (gdb_stdlog, " - fpreg=%d val=%s",
+ float_argreg, phex (regval, 4));
regcache_cooked_write_signed (regcache, float_argreg++, regval);
}
else
{
/* This is a floating point value that fits entirely
- in a single register. */
+ in a single register. */
/* On 32 bit ABI's the float_argreg is further adjusted
- above to ensure that it is even register aligned. */
+ above to ensure that it is even register aligned. */
LONGEST regval = extract_signed_integer (val, len, byte_order);
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
- float_argreg, phex (regval, len));
+ gdb_printf (gdb_stdlog, " - fpreg=%d val=%s",
+ float_argreg, phex (regval, len));
regcache_cooked_write_signed (regcache, float_argreg++, regval);
}
}
int partial_len = (len < abi_regsize ? len : abi_regsize);
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
- partial_len);
+ gdb_printf (gdb_stdlog, " -- partial=%d",
+ partial_len);
/* Write this portion of the argument to the stack. */
- if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)
+ if (argreg > mips_last_arg_regnum (gdbarch)
|| odd_sized_struct
|| fp_register_arg_p (gdbarch, typecode, arg_type))
{
longword_offset = abi_regsize - len;
else if ((typecode == TYPE_CODE_STRUCT
|| typecode == TYPE_CODE_UNION)
- && TYPE_LENGTH (arg_type) < abi_regsize)
+ && arg_type->length () < abi_regsize)
longword_offset = abi_regsize - len;
}
if (mips_debug)
{
- fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
- paddress (gdbarch, stack_offset));
- fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
- paddress (gdbarch, longword_offset));
+ gdb_printf (gdb_stdlog, " - stack_offset=%s",
+ paddress (gdbarch, stack_offset));
+ gdb_printf (gdb_stdlog, " longword_offset=%s",
+ paddress (gdbarch, longword_offset));
}
addr = sp + stack_offset + longword_offset;
if (mips_debug)
{
int i;
- fprintf_unfiltered (gdb_stdlog, " @%s ",
- paddress (gdbarch, addr));
+ gdb_printf (gdb_stdlog, " @%s ",
+ paddress (gdbarch, addr));
for (i = 0; i < partial_len; i++)
{
- fprintf_unfiltered (gdb_stdlog, "%02x",
- val[i] & 0xff);
+ gdb_printf (gdb_stdlog, "%02x",
+ val[i] & 0xff);
}
}
write_memory (addr, val, partial_len);
}
/* Note!!! This is NOT an else clause. Odd sized
- structs may go thru BOTH paths. Floating point
- arguments will not. */
+ structs may go thru BOTH paths. Floating point
+ arguments will not. */
/* Write this portion of the argument to a general
- purpose register. */
- if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)
+ purpose register. */
+ if (argreg <= mips_last_arg_regnum (gdbarch)
&& !fp_register_arg_p (gdbarch, typecode, arg_type))
{
LONGEST regval =
extract_signed_integer (val, partial_len, byte_order);
if (mips_debug)
- fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
- argreg,
- phex (regval, abi_regsize));
+ gdb_printf (gdb_stdlog, " - reg=%d val=%s",
+ argreg,
+ phex (regval, abi_regsize));
regcache_cooked_write_signed (regcache, argreg, regval);
argreg++;
}
val += partial_len;
/* Compute the offset into the stack at which we will
- copy the next parameter.
+ copy the next parameter.
- In the new EABI (and the NABI32), the stack_offset
- only needs to be adjusted when it has been used. */
+ In the new EABI (and the NABI32), the stack_offset
+ only needs to be adjusted when it has been used. */
if (stack_used_p)
stack_offset += align_up (partial_len, abi_regsize);
}
}
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog, "\n");
+ gdb_printf (gdb_stdlog, "\n");
}
regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
struct type *type, struct regcache *regcache,
gdb_byte *readbuf, const gdb_byte *writebuf)
{
- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch);
int fp_return_type = 0;
int offset, regnum, xfer;
- if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch))
+ if (type->length () > 2 * mips_abi_regsize (gdbarch))
return RETURN_VALUE_STRUCT_CONVENTION;
/* Floating point type? */
if (tdep->mips_fpu_type != MIPS_FPU_NONE)
{
- if (TYPE_CODE (type) == TYPE_CODE_FLT)
+ if (type->code () == TYPE_CODE_FLT)
fp_return_type = 1;
/* Structs with a single field of float type
are returned in a floating point register. */
- if ((TYPE_CODE (type) == TYPE_CODE_STRUCT
- || TYPE_CODE (type) == TYPE_CODE_UNION)
- && TYPE_NFIELDS (type) == 1)
+ if ((type->code () == TYPE_CODE_STRUCT
+ || type->code () == TYPE_CODE_UNION)
+ && type->num_fields () == 1)
{
- struct type *fieldtype = TYPE_FIELD_TYPE (type, 0);
+ struct type *fieldtype = type->field (0).type ();
- if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT)
+ if (check_typedef (fieldtype)->code () == TYPE_CODE_FLT)
fp_return_type = 1;
}
}
/* A floating-point value belongs in the least significant part
of FP0/FP1. */
if (mips_debug)
- fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
+ gdb_printf (gdb_stderr, "Return float in $fp0\n");
regnum = mips_regnum (gdbarch)->fp0;
}
else
{
/* An integer value goes in V0/V1. */
if (mips_debug)
- fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n");
+ gdb_printf (gdb_stderr, "Return scalar in $v0\n");
regnum = MIPS_V0_REGNUM;
}
for (offset = 0;
- offset < TYPE_LENGTH (type);
+ offset < type->length ();
offset += mips_abi_regsize (gdbarch), regnum++)
{
xfer = mips_abi_regsize (gdbarch);
- if (offset + xfer > TYPE_LENGTH (type))
- xfer = TYPE_LENGTH (type) - offset;
+ if (offset + xfer > type->length ())
+ xfer = type->length () - offset;
mips_xfer_register (gdbarch, regcache,
gdbarch_num_regs (gdbarch) + regnum, xfer,
gdbarch_byte_order (gdbarch), readbuf, writebuf,
{
int i;
- if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT)
+ if (arg_type->code () != TYPE_CODE_STRUCT)
return 0;
- if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE)
+ if (mips_get_fpu_type (gdbarch) != MIPS_FPU_DOUBLE)
return 0;
- if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE)
+ if (arg_type->length () < offset + MIPS64_REGSIZE)
return 0;
- for (i = 0; i < TYPE_NFIELDS (arg_type); i++)
+ for (i = 0; i < arg_type->num_fields (); i++)
{
int pos;
struct type *field_type;
/* We're only looking at normal fields. */
- if (field_is_static (&TYPE_FIELD (arg_type, i))
- || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0)
+ if (field_is_static (&arg_type->field (i))
+ || (arg_type->field (i).loc_bitpos () % 8) != 0)
continue;
/* If we have gone past the offset, there is no double to pass. */
- pos = TYPE_FIELD_BITPOS (arg_type, i) / 8;
+ pos = arg_type->field (i).loc_bitpos () / 8;
if (pos > offset)
return 0;
- field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i));
+ field_type = check_typedef (arg_type->field (i).type ());
/* If this field is entirely before the requested offset, go
on to the next one. */
- if (pos + TYPE_LENGTH (field_type) <= offset)
+ if (pos + field_type->length () <= offset)
continue;
/* If this is our special aligned double, we can stop. */
- if (TYPE_CODE (field_type) == TYPE_CODE_FLT
- && TYPE_LENGTH (field_type) == MIPS64_REGSIZE)
+ if (field_type->code () == TYPE_CODE_FLT
+ && field_type->length () == MIPS64_REGSIZE)
return 1;
/* This field starts at or before the requested offset, and
mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
struct regcache *regcache, CORE_ADDR bp_addr,
int nargs, struct value **args, CORE_ADDR sp,
- int struct_return, CORE_ADDR struct_addr)
+ function_call_return_method return_method,
+ CORE_ADDR struct_addr)
{
int argreg;
int float_argreg;
int argnum;
- int len = 0;
+ int arg_space = 0;
int stack_offset = 0;
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
CORE_ADDR func_addr = find_function_addr (function, NULL);
/* Now make space on the stack for the args. */
for (argnum = 0; argnum < nargs; argnum++)
- len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE);
- sp -= align_up (len, 16);
+ arg_space += align_up (value_type (args[argnum])->length (),
+ MIPS64_REGSIZE);
+ sp -= align_up (arg_space, 16);
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog,
- "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
- paddress (gdbarch, sp), (long) align_up (len, 16));
+ gdb_printf (gdb_stdlog,
+ "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
+ paddress (gdbarch, sp),
+ (long) align_up (arg_space, 16));
/* Initialize the integer and float register pointers. */
argreg = MIPS_A0_REGNUM;
float_argreg = mips_fpa0_regnum (gdbarch);
/* The struct_return pointer occupies the first parameter-passing reg. */
- if (struct_return)
+ if (return_method == return_method_struct)
{
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog,
- "mips_n32n64_push_dummy_call: "
- "struct_return reg=%d %s\n",
- argreg, paddress (gdbarch, struct_addr));
+ gdb_printf (gdb_stdlog,
+ "mips_n32n64_push_dummy_call: "
+ "struct_return reg=%d %s\n",
+ argreg, paddress (gdbarch, struct_addr));
regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
}
const gdb_byte *val;
struct value *arg = args[argnum];
struct type *arg_type = check_typedef (value_type (arg));
- int len = TYPE_LENGTH (arg_type);
- enum type_code typecode = TYPE_CODE (arg_type);
+ int len = arg_type->length ();
+ enum type_code typecode = arg_type->code ();
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog,
- "mips_n32n64_push_dummy_call: %d len=%d type=%d",
- argnum + 1, len, (int) typecode);
+ gdb_printf (gdb_stdlog,
+ "mips_n32n64_push_dummy_call: %d len=%d type=%d",
+ argnum + 1, len, (int) typecode);
- val = value_contents (arg);
+ val = value_contents (arg).data ();
/* A 128-bit long double value requires an even-odd pair of
floating-point registers. */
}
if (fp_register_arg_p (gdbarch, typecode, arg_type)
- && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
+ && argreg <= mips_last_arg_regnum (gdbarch))
{
/* This is a floating point value that fits entirely
in a single register or a pair of registers. */
int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
LONGEST regval = extract_unsigned_integer (val, reglen, byte_order);
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
- float_argreg, phex (regval, reglen));
+ gdb_printf (gdb_stdlog, " - fpreg=%d val=%s",
+ float_argreg, phex (regval, reglen));
regcache_cooked_write_unsigned (regcache, float_argreg, regval);
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
- argreg, phex (regval, reglen));
+ gdb_printf (gdb_stdlog, " - reg=%d val=%s",
+ argreg, phex (regval, reglen));
regcache_cooked_write_unsigned (regcache, argreg, regval);
float_argreg++;
argreg++;
regval = extract_unsigned_integer (val + reglen,
reglen, byte_order);
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
- float_argreg, phex (regval, reglen));
+ gdb_printf (gdb_stdlog, " - fpreg=%d val=%s",
+ float_argreg, phex (regval, reglen));
regcache_cooked_write_unsigned (regcache, float_argreg, regval);
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
- argreg, phex (regval, reglen));
+ gdb_printf (gdb_stdlog, " - reg=%d val=%s",
+ argreg, phex (regval, reglen));
regcache_cooked_write_unsigned (regcache, argreg, regval);
float_argreg++;
argreg++;
int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
- partial_len);
+ gdb_printf (gdb_stdlog, " -- partial=%d",
+ partial_len);
if (fp_register_arg_p (gdbarch, typecode, arg_type))
- gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch));
+ gdb_assert (argreg > mips_last_arg_regnum (gdbarch));
/* Write this portion of the argument to the stack. */
- if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch))
+ if (argreg > mips_last_arg_regnum (gdbarch))
{
/* Should shorter than int integer values be
promoted to int before being stored? */
if (mips_debug)
{
- fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
- paddress (gdbarch, stack_offset));
- fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
- paddress (gdbarch, longword_offset));
+ gdb_printf (gdb_stdlog, " - stack_offset=%s",
+ paddress (gdbarch, stack_offset));
+ gdb_printf (gdb_stdlog, " longword_offset=%s",
+ paddress (gdbarch, longword_offset));
}
addr = sp + stack_offset + longword_offset;
if (mips_debug)
{
int i;
- fprintf_unfiltered (gdb_stdlog, " @%s ",
- paddress (gdbarch, addr));
+ gdb_printf (gdb_stdlog, " @%s ",
+ paddress (gdbarch, addr));
for (i = 0; i < partial_len; i++)
{
- fprintf_unfiltered (gdb_stdlog, "%02x",
- val[i] & 0xff);
+ gdb_printf (gdb_stdlog, "%02x",
+ val[i] & 0xff);
}
}
write_memory (addr, val, partial_len);
}
/* Note!!! This is NOT an else clause. Odd sized
- structs may go thru BOTH paths. */
+ structs may go thru BOTH paths. */
/* Write this portion of the argument to a general
- purpose register. */
- if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
+ purpose register. */
+ if (argreg <= mips_last_arg_regnum (gdbarch))
{
LONGEST regval;
|| typecode == TYPE_CODE_INT))
|| (partial_len < 4
&& typecode == TYPE_CODE_INT
- && !TYPE_UNSIGNED (arg_type)))
+ && !arg_type->is_unsigned ()))
regval = extract_signed_integer (val, partial_len,
byte_order);
else
* TARGET_CHAR_BIT);
if (mips_debug)
- fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
- argreg,
- phex (regval, MIPS64_REGSIZE));
+ gdb_printf (gdb_stdlog, " - reg=%d val=%s",
+ argreg,
+ phex (regval, MIPS64_REGSIZE));
regcache_cooked_write_unsigned (regcache, argreg, regval);
if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type,
- TYPE_LENGTH (arg_type) - len))
+ arg_type->length () - len))
{
if (mips_debug)
- fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s",
- float_argreg,
- phex (regval, MIPS64_REGSIZE));
+ gdb_printf (gdb_stdlog, " - fpreg=%d val=%s",
+ float_argreg,
+ phex (regval, MIPS64_REGSIZE));
regcache_cooked_write_unsigned (regcache, float_argreg,
regval);
}
val += partial_len;
/* Compute the offset into the stack at which we will
- copy the next parameter.
+ copy the next parameter.
- In N32 (N64?), the stack_offset only needs to be
- adjusted when it has been used. */
+ In N32 (N64?), the stack_offset only needs to be
+ adjusted when it has been used. */
if (stack_used_p)
stack_offset += align_up (partial_len, MIPS64_REGSIZE);
}
}
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog, "\n");
+ gdb_printf (gdb_stdlog, "\n");
}
regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
struct type *type, struct regcache *regcache,
gdb_byte *readbuf, const gdb_byte *writebuf)
{
- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch);
/* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
that all composite results be handled by conversion to implicit first
parameters. The MIPS/SGI Fortran implementation has always made a
specific exception to return COMPLEX results in the floating point
- registers.] */
+ registers.]
+
+ From MIPSpro Assembly Language Programmer's Guide, Document Number:
+ 007-2418-004
- if (TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE)
+ Software
+ Register Name(from
+ Name fgregdef.h) Use and Linkage
+ -----------------------------------------------------------------
+ $f0, $f2 fv0, fv1 Hold results of floating-point type function
+ ($f0) and complex type function ($f0 has the
+ real part, $f2 has the imaginary part.) */
+
+ if (type->length () > 2 * MIPS64_REGSIZE)
return RETURN_VALUE_STRUCT_CONVENTION;
- else if (TYPE_CODE (type) == TYPE_CODE_FLT
- && TYPE_LENGTH (type) == 16
+ else if ((type->code () == TYPE_CODE_COMPLEX
+ || (type->code () == TYPE_CODE_FLT && type->length () == 16))
&& tdep->mips_fpu_type != MIPS_FPU_NONE)
{
- /* A 128-bit floating-point value fills both $f0 and $f2. The
- two registers are used in the same as memory order, so the
- eight bytes with the lower memory address are in $f0. */
+ /* A complex value of up to 128 bits in width as well as a 128-bit
+ floating-point value goes in both $f0 and $f2. A single complex
+ value is held in the lower halves only of the respective registers.
+ The two registers are used in the same as memory order, so the
+ bytes with the lower memory address are in $f0. */
if (mips_debug)
- fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n");
+ gdb_printf (gdb_stderr, "Return float in $f0 and $f2\n");
mips_xfer_register (gdbarch, regcache,
(gdbarch_num_regs (gdbarch)
+ mips_regnum (gdbarch)->fp0),
- 8, gdbarch_byte_order (gdbarch),
+ type->length () / 2, gdbarch_byte_order (gdbarch),
readbuf, writebuf, 0);
mips_xfer_register (gdbarch, regcache,
(gdbarch_num_regs (gdbarch)
+ mips_regnum (gdbarch)->fp0 + 2),
- 8, gdbarch_byte_order (gdbarch),
- readbuf ? readbuf + 8 : readbuf,
- writebuf ? writebuf + 8 : writebuf, 0);
+ type->length () / 2, gdbarch_byte_order (gdbarch),
+ readbuf ? readbuf + type->length () / 2 : readbuf,
+ (writebuf
+ ? writebuf + type->length () / 2 : writebuf), 0);
return RETURN_VALUE_REGISTER_CONVENTION;
}
- else if (TYPE_CODE (type) == TYPE_CODE_FLT
+ else if (type->code () == TYPE_CODE_FLT
&& tdep->mips_fpu_type != MIPS_FPU_NONE)
{
/* A single or double floating-point value that fits in FP0. */
if (mips_debug)
- fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
+ gdb_printf (gdb_stderr, "Return float in $fp0\n");
mips_xfer_register (gdbarch, regcache,
(gdbarch_num_regs (gdbarch)
+ mips_regnum (gdbarch)->fp0),
- TYPE_LENGTH (type),
+ type->length (),
gdbarch_byte_order (gdbarch),
readbuf, writebuf, 0);
return RETURN_VALUE_REGISTER_CONVENTION;
}
- else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
- && TYPE_NFIELDS (type) <= 2
- && TYPE_NFIELDS (type) >= 1
- && ((TYPE_NFIELDS (type) == 1
- && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0)))
+ else if (type->code () == TYPE_CODE_STRUCT
+ && type->num_fields () <= 2
+ && type->num_fields () >= 1
+ && ((type->num_fields () == 1
+ && (check_typedef (type->field (0).type ())->code ()
== TYPE_CODE_FLT))
- || (TYPE_NFIELDS (type) == 2
- && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0)))
+ || (type->num_fields () == 2
+ && (check_typedef (type->field (0).type ())->code ()
== TYPE_CODE_FLT)
- && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1)))
+ && (check_typedef (type->field (1).type ())->code ()
== TYPE_CODE_FLT))))
{
/* A struct that contains one or two floats. Each value is part
- in the least significant part of their floating point
- register (or GPR, for soft float). */
+ in the least significant part of their floating point
+ register (or GPR, for soft float). */
int regnum;
int field;
for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE
? mips_regnum (gdbarch)->fp0
: MIPS_V0_REGNUM);
- field < TYPE_NFIELDS (type); field++, regnum += 2)
+ field < type->num_fields (); field++, regnum += 2)
{
- int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
- / TARGET_CHAR_BIT);
+ int offset = type->field (field).loc_bitpos () / TARGET_CHAR_BIT;
if (mips_debug)
- fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
- offset);
- if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16)
+ gdb_printf (gdb_stderr, "Return float struct+%d\n",
+ offset);
+ if (type->field (field).type ()->length () == 16)
{
/* A 16-byte long double field goes in two consecutive
registers. */
else
mips_xfer_register (gdbarch, regcache,
gdbarch_num_regs (gdbarch) + regnum,
- TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
+ type->field (field).type ()->length (),
gdbarch_byte_order (gdbarch),
readbuf, writebuf, offset);
}
return RETURN_VALUE_REGISTER_CONVENTION;
}
- else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
- || TYPE_CODE (type) == TYPE_CODE_UNION
- || TYPE_CODE (type) == TYPE_CODE_ARRAY)
+ else if (type->code () == TYPE_CODE_STRUCT
+ || type->code () == TYPE_CODE_UNION
+ || type->code () == TYPE_CODE_ARRAY)
{
/* A composite type. Extract the left justified value,
- regardless of the byte order. I.e. DO NOT USE
- mips_xfer_lower. */
+ regardless of the byte order. I.e. DO NOT USE
+ mips_xfer_lower. */
int offset;
int regnum;
for (offset = 0, regnum = MIPS_V0_REGNUM;
- offset < TYPE_LENGTH (type);
+ offset < type->length ();
offset += register_size (gdbarch, regnum), regnum++)
{
int xfer = register_size (gdbarch, regnum);
- if (offset + xfer > TYPE_LENGTH (type))
- xfer = TYPE_LENGTH (type) - offset;
+ if (offset + xfer > type->length ())
+ xfer = type->length () - offset;
if (mips_debug)
- fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
- offset, xfer, regnum);
+ gdb_printf (gdb_stderr, "Return struct+%d:%d in $%d\n",
+ offset, xfer, regnum);
mips_xfer_register (gdbarch, regcache,
gdbarch_num_regs (gdbarch) + regnum,
xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf,
else
{
/* A scalar extract each part but least-significant-byte
- justified. */
+ justified. */
int offset;
int regnum;
for (offset = 0, regnum = MIPS_V0_REGNUM;
- offset < TYPE_LENGTH (type);
+ offset < type->length ();
offset += register_size (gdbarch, regnum), regnum++)
{
int xfer = register_size (gdbarch, regnum);
- if (offset + xfer > TYPE_LENGTH (type))
- xfer = TYPE_LENGTH (type) - offset;
+ if (offset + xfer > type->length ())
+ xfer = type->length () - offset;
if (mips_debug)
- fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
- offset, xfer, regnum);
+ gdb_printf (gdb_stderr, "Return scalar+%d:%d in $%d\n",
+ offset, xfer, regnum);
mips_xfer_register (gdbarch, regcache,
gdbarch_num_regs (gdbarch) + regnum,
xfer, gdbarch_byte_order (gdbarch),
mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
struct regcache *regcache, CORE_ADDR bp_addr,
int nargs, struct value **args, CORE_ADDR sp,
- int struct_return, CORE_ADDR struct_addr)
+ function_call_return_method return_method,
+ CORE_ADDR struct_addr)
{
int argreg;
int float_argreg;
int argnum;
- int len = 0;
+ int arg_space = 0;
int stack_offset = 0;
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
CORE_ADDR func_addr = find_function_addr (function, NULL);
/* Align to double-word if necessary. */
if (mips_type_needs_double_align (arg_type))
- len = align_up (len, MIPS32_REGSIZE * 2);
+ arg_space = align_up (arg_space, MIPS32_REGSIZE * 2);
/* Allocate space on the stack. */
- len += align_up (TYPE_LENGTH (arg_type), MIPS32_REGSIZE);
+ arg_space += align_up (arg_type->length (), MIPS32_REGSIZE);
}
- sp -= align_up (len, 16);
+ sp -= align_up (arg_space, 16);
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog,
- "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
- paddress (gdbarch, sp), (long) align_up (len, 16));
+ gdb_printf (gdb_stdlog,
+ "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
+ paddress (gdbarch, sp),
+ (long) align_up (arg_space, 16));
/* Initialize the integer and float register pointers. */
argreg = MIPS_A0_REGNUM;
float_argreg = mips_fpa0_regnum (gdbarch);
/* The struct_return pointer occupies the first parameter-passing reg. */
- if (struct_return)
+ if (return_method == return_method_struct)
{
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog,
- "mips_o32_push_dummy_call: "
- "struct_return reg=%d %s\n",
- argreg, paddress (gdbarch, struct_addr));
+ gdb_printf (gdb_stdlog,
+ "mips_o32_push_dummy_call: "
+ "struct_return reg=%d %s\n",
+ argreg, paddress (gdbarch, struct_addr));
regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
stack_offset += MIPS32_REGSIZE;
}
const gdb_byte *val;
struct value *arg = args[argnum];
struct type *arg_type = check_typedef (value_type (arg));
- int len = TYPE_LENGTH (arg_type);
- enum type_code typecode = TYPE_CODE (arg_type);
+ int len = arg_type->length ();
+ enum type_code typecode = arg_type->code ();
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog,
- "mips_o32_push_dummy_call: %d len=%d type=%d",
- argnum + 1, len, (int) typecode);
+ gdb_printf (gdb_stdlog,
+ "mips_o32_push_dummy_call: %d len=%d type=%d",
+ argnum + 1, len, (int) typecode);
- val = value_contents (arg);
+ val = value_contents (arg).data ();
/* 32-bit ABIs always start floating point arguments in an
- even-numbered floating point register. Round the FP register
- up before the check to see if there are any FP registers
- left. O32 targets also pass the FP in the integer registers
- so also round up normal registers. */
+ even-numbered floating point register. Round the FP register
+ up before the check to see if there are any FP registers
+ left. O32 targets also pass the FP in the integer registers
+ so also round up normal registers. */
if (fp_register_arg_p (gdbarch, typecode, arg_type))
{
if ((float_argreg & 1))
}
/* Floating point arguments passed in registers have to be
- treated specially. On 32-bit architectures, doubles are
- passed in register pairs; the even FP register gets the
- low word, and the odd FP register gets the high word.
- On O32, the first two floating point arguments are also
- copied to general registers, following their memory order,
- because MIPS16 functions don't use float registers for
- arguments. This duplication of arguments in general
- registers can't hurt non-MIPS16 functions, because those
- registers are normally skipped. */
+ treated specially. On 32-bit architectures, doubles are
+ passed in register pairs; the even FP register gets the
+ low word, and the odd FP register gets the high word.
+ On O32, the first two floating point arguments are also
+ copied to general registers, following their memory order,
+ because MIPS16 functions don't use float registers for
+ arguments. This duplication of arguments in general
+ registers can't hurt non-MIPS16 functions, because those
+ registers are normally skipped. */
if (fp_register_arg_p (gdbarch, typecode, arg_type)
- && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch))
+ && float_argreg <= mips_last_fp_arg_regnum (gdbarch))
{
if (register_size (gdbarch, float_argreg) < 8 && len == 8)
{
/* First word. */
regval = extract_unsigned_integer (val, 4, byte_order);
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
- float_argreg + freg_offset,
- phex (regval, 4));
+ gdb_printf (gdb_stdlog, " - fpreg=%d val=%s",
+ float_argreg + freg_offset,
+ phex (regval, 4));
regcache_cooked_write_unsigned (regcache,
float_argreg++ + freg_offset,
regval);
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
- argreg, phex (regval, 4));
+ gdb_printf (gdb_stdlog, " - reg=%d val=%s",
+ argreg, phex (regval, 4));
regcache_cooked_write_unsigned (regcache, argreg++, regval);
/* Second word. */
regval = extract_unsigned_integer (val + 4, 4, byte_order);
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
- float_argreg - freg_offset,
- phex (regval, 4));
+ gdb_printf (gdb_stdlog, " - fpreg=%d val=%s",
+ float_argreg - freg_offset,
+ phex (regval, 4));
regcache_cooked_write_unsigned (regcache,
float_argreg++ - freg_offset,
regval);
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
- argreg, phex (regval, 4));
+ gdb_printf (gdb_stdlog, " - reg=%d val=%s",
+ argreg, phex (regval, 4));
regcache_cooked_write_unsigned (regcache, argreg++, regval);
}
else
{
/* This is a floating point value that fits entirely
- in a single register. */
+ in a single register. */
/* On 32 bit ABI's the float_argreg is further adjusted
- above to ensure that it is even register aligned. */
+ above to ensure that it is even register aligned. */
LONGEST regval = extract_unsigned_integer (val, len, byte_order);
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
- float_argreg, phex (regval, len));
+ gdb_printf (gdb_stdlog, " - fpreg=%d val=%s",
+ float_argreg, phex (regval, len));
regcache_cooked_write_unsigned (regcache,
float_argreg++, regval);
/* Although two FP registers are reserved for each
argument, only one corresponding integer register is
reserved. */
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
- argreg, phex (regval, len));
+ gdb_printf (gdb_stdlog, " - reg=%d val=%s",
+ argreg, phex (regval, len));
regcache_cooked_write_unsigned (regcache, argreg++, regval);
}
/* Reserve space for the FP register. */
int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE);
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
- partial_len);
+ gdb_printf (gdb_stdlog, " -- partial=%d",
+ partial_len);
/* Write this portion of the argument to the stack. */
- if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)
+ if (argreg > mips_last_arg_regnum (gdbarch)
|| odd_sized_struct)
{
/* Should shorter than int integer values be
if (mips_debug)
{
- fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
- paddress (gdbarch, stack_offset));
- fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
- paddress (gdbarch, longword_offset));
+ gdb_printf (gdb_stdlog, " - stack_offset=%s",
+ paddress (gdbarch, stack_offset));
+ gdb_printf (gdb_stdlog, " longword_offset=%s",
+ paddress (gdbarch, longword_offset));
}
addr = sp + stack_offset + longword_offset;
if (mips_debug)
{
int i;
- fprintf_unfiltered (gdb_stdlog, " @%s ",
- paddress (gdbarch, addr));
+ gdb_printf (gdb_stdlog, " @%s ",
+ paddress (gdbarch, addr));
for (i = 0; i < partial_len; i++)
{
- fprintf_unfiltered (gdb_stdlog, "%02x",
- val[i] & 0xff);
+ gdb_printf (gdb_stdlog, "%02x",
+ val[i] & 0xff);
}
}
write_memory (addr, val, partial_len);
}
/* Note!!! This is NOT an else clause. Odd sized
- structs may go thru BOTH paths. */
+ structs may go thru BOTH paths. */
/* Write this portion of the argument to a general
- purpose register. */
- if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
+ purpose register. */
+ if (argreg <= mips_last_arg_regnum (gdbarch))
{
LONGEST regval = extract_signed_integer (val, partial_len,
byte_order);
* TARGET_CHAR_BIT);
if (mips_debug)
- fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
- argreg,
- phex (regval, MIPS32_REGSIZE));
+ gdb_printf (gdb_stdlog, " - reg=%d val=%s",
+ argreg,
+ phex (regval, MIPS32_REGSIZE));
regcache_cooked_write_unsigned (regcache, argreg, regval);
argreg++;
/* Prevent subsequent floating point arguments from
being passed in floating point registers. */
- float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1;
+ float_argreg = mips_last_fp_arg_regnum (gdbarch) + 1;
}
len -= partial_len;
val += partial_len;
/* Compute the offset into the stack at which we will
- copy the next parameter.
+ copy the next parameter.
- In older ABIs, the caller reserved space for
- registers that contained arguments. This was loosely
- refered to as their "home". Consequently, space is
- always allocated. */
+ In older ABIs, the caller reserved space for
+ registers that contained arguments. This was loosely
+ refered to as their "home". Consequently, space is
+ always allocated. */
stack_offset += align_up (partial_len, MIPS32_REGSIZE);
}
}
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog, "\n");
+ gdb_printf (gdb_stdlog, "\n");
}
regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
{
CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0;
int mips16 = mips_pc_is_mips16 (gdbarch, func_addr);
- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch);
enum mips_fval_reg fval_reg;
fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both;
- if (TYPE_CODE (type) == TYPE_CODE_STRUCT
- || TYPE_CODE (type) == TYPE_CODE_UNION
- || TYPE_CODE (type) == TYPE_CODE_ARRAY)
+ if (type->code () == TYPE_CODE_STRUCT
+ || type->code () == TYPE_CODE_UNION
+ || type->code () == TYPE_CODE_ARRAY)
return RETURN_VALUE_STRUCT_CONVENTION;
- else if (TYPE_CODE (type) == TYPE_CODE_FLT
- && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE)
+ else if (type->code () == TYPE_CODE_FLT
+ && type->length () == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE)
{
/* A single-precision floating-point value. If reading in or copying,
- then we get it from/put it to FP0 for standard MIPS code or GPR2
- for MIPS16 code. If writing out only, then we put it to both FP0
- and GPR2. We do not support reading in with no function known, if
- this safety check ever triggers, then we'll have to try harder. */
+ then we get it from/put it to FP0 for standard MIPS code or GPR2
+ for MIPS16 code. If writing out only, then we put it to both FP0
+ and GPR2. We do not support reading in with no function known, if
+ this safety check ever triggers, then we'll have to try harder. */
gdb_assert (function || !readbuf);
if (mips_debug)
switch (fval_reg)
{
case mips_fval_fpr:
- fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
+ gdb_printf (gdb_stderr, "Return float in $fp0\n");
break;
case mips_fval_gpr:
- fprintf_unfiltered (gdb_stderr, "Return float in $2\n");
+ gdb_printf (gdb_stderr, "Return float in $2\n");
break;
case mips_fval_both:
- fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n");
+ gdb_printf (gdb_stderr, "Return float in $fp0 and $2\n");
break;
}
if (fval_reg != mips_fval_gpr)
mips_xfer_register (gdbarch, regcache,
(gdbarch_num_regs (gdbarch)
+ mips_regnum (gdbarch)->fp0),
- TYPE_LENGTH (type),
+ type->length (),
gdbarch_byte_order (gdbarch),
readbuf, writebuf, 0);
if (fval_reg != mips_fval_fpr)
mips_xfer_register (gdbarch, regcache,
gdbarch_num_regs (gdbarch) + 2,
- TYPE_LENGTH (type),
+ type->length (),
gdbarch_byte_order (gdbarch),
readbuf, writebuf, 0);
return RETURN_VALUE_REGISTER_CONVENTION;
}
- else if (TYPE_CODE (type) == TYPE_CODE_FLT
- && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE)
+ else if (type->code () == TYPE_CODE_FLT
+ && type->length () == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE)
{
/* A double-precision floating-point value. If reading in or copying,
- then we get it from/put it to FP1 and FP0 for standard MIPS code or
- GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
- to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
- no function known, if this safety check ever triggers, then we'll
- have to try harder. */
+ then we get it from/put it to FP1 and FP0 for standard MIPS code or
+ GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
+ to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
+ no function known, if this safety check ever triggers, then we'll
+ have to try harder. */
gdb_assert (function || !readbuf);
if (mips_debug)
switch (fval_reg)
{
case mips_fval_fpr:
- fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n");
+ gdb_printf (gdb_stderr, "Return float in $fp1/$fp0\n");
break;
case mips_fval_gpr:
- fprintf_unfiltered (gdb_stderr, "Return float in $2/$3\n");
+ gdb_printf (gdb_stderr, "Return float in $2/$3\n");
break;
case mips_fval_both:
- fprintf_unfiltered (gdb_stderr,
- "Return float in $fp1/$fp0 and $2/$3\n");
+ gdb_printf (gdb_stderr,
+ "Return float in $fp1/$fp0 and $2/$3\n");
break;
}
if (fval_reg != mips_fval_gpr)
readbuf, writebuf, 4);
break;
default:
- internal_error (__FILE__, __LINE__, _("bad switch"));
+ internal_error (_("bad switch"));
}
}
if (fval_reg != mips_fval_fpr)
return RETURN_VALUE_REGISTER_CONVENTION;
}
#if 0
- else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
- && TYPE_NFIELDS (type) <= 2
- && TYPE_NFIELDS (type) >= 1
- && ((TYPE_NFIELDS (type) == 1
- && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
+ else if (type->code () == TYPE_CODE_STRUCT
+ && type->num_fields () <= 2
+ && type->num_fields () >= 1
+ && ((type->num_fields () == 1
+ && (TYPE_CODE (type->field (0).type ())
== TYPE_CODE_FLT))
- || (TYPE_NFIELDS (type) == 2
- && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0))
+ || (type->num_fields () == 2
+ && (TYPE_CODE (type->field (0).type ())
== TYPE_CODE_FLT)
- && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1))
+ && (TYPE_CODE (type->field (1).type ())
== TYPE_CODE_FLT)))
&& tdep->mips_fpu_type != MIPS_FPU_NONE)
{
/* A struct that contains one or two floats. Each value is part
- in the least significant part of their floating point
- register.. */
+ in the least significant part of their floating point
+ register.. */
int regnum;
int field;
for (field = 0, regnum = mips_regnum (gdbarch)->fp0;
- field < TYPE_NFIELDS (type); field++, regnum += 2)
+ field < type->num_fields (); field++, regnum += 2)
{
- int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field])
- / TARGET_CHAR_BIT);
+ int offset = (type->fields ()[field].loc_bitpos () / TARGET_CHAR_BIT);
if (mips_debug)
- fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n",
- offset);
+ gdb_printf (gdb_stderr, "Return float struct+%d\n",
+ offset);
mips_xfer_register (gdbarch, regcache,
gdbarch_num_regs (gdbarch) + regnum,
- TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)),
+ TYPE_LENGTH (type->field (field).type ()),
gdbarch_byte_order (gdbarch),
readbuf, writebuf, offset);
}
}
#endif
#if 0
- else if (TYPE_CODE (type) == TYPE_CODE_STRUCT
- || TYPE_CODE (type) == TYPE_CODE_UNION)
+ else if (type->code () == TYPE_CODE_STRUCT
+ || type->code () == TYPE_CODE_UNION)
{
/* A structure or union. Extract the left justified value,
- regardless of the byte order. I.e. DO NOT USE
- mips_xfer_lower. */
+ regardless of the byte order. I.e. DO NOT USE
+ mips_xfer_lower. */
int offset;
int regnum;
for (offset = 0, regnum = MIPS_V0_REGNUM;
- offset < TYPE_LENGTH (type);
+ offset < type->length ();
offset += register_size (gdbarch, regnum), regnum++)
{
int xfer = register_size (gdbarch, regnum);
- if (offset + xfer > TYPE_LENGTH (type))
- xfer = TYPE_LENGTH (type) - offset;
+ if (offset + xfer > type->length ())
+ xfer = type->length () - offset;
if (mips_debug)
- fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n",
- offset, xfer, regnum);
+ gdb_printf (gdb_stderr, "Return struct+%d:%d in $%d\n",
+ offset, xfer, regnum);
mips_xfer_register (gdbarch, regcache,
gdbarch_num_regs (gdbarch) + regnum, xfer,
BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset);
else
{
/* A scalar extract each part but least-significant-byte
- justified. o32 thinks registers are 4 byte, regardless of
- the ISA. */
+ justified. o32 thinks registers are 4 byte, regardless of
+ the ISA. */
int offset;
int regnum;
for (offset = 0, regnum = MIPS_V0_REGNUM;
- offset < TYPE_LENGTH (type);
+ offset < type->length ();
offset += MIPS32_REGSIZE, regnum++)
{
int xfer = MIPS32_REGSIZE;
- if (offset + xfer > TYPE_LENGTH (type))
- xfer = TYPE_LENGTH (type) - offset;
+ if (offset + xfer > type->length ())
+ xfer = type->length () - offset;
if (mips_debug)
- fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
- offset, xfer, regnum);
+ gdb_printf (gdb_stderr, "Return scalar+%d:%d in $%d\n",
+ offset, xfer, regnum);
mips_xfer_register (gdbarch, regcache,
gdbarch_num_regs (gdbarch) + regnum, xfer,
gdbarch_byte_order (gdbarch),
struct regcache *regcache, CORE_ADDR bp_addr,
int nargs,
struct value **args, CORE_ADDR sp,
- int struct_return, CORE_ADDR struct_addr)
+ function_call_return_method return_method, CORE_ADDR struct_addr)
{
int argreg;
int float_argreg;
int argnum;
- int len = 0;
+ int arg_space = 0;
int stack_offset = 0;
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
CORE_ADDR func_addr = find_function_addr (function, NULL);
struct type *arg_type = check_typedef (value_type (args[argnum]));
/* Allocate space on the stack. */
- len += align_up (TYPE_LENGTH (arg_type), MIPS64_REGSIZE);
+ arg_space += align_up (arg_type->length (), MIPS64_REGSIZE);
}
- sp -= align_up (len, 16);
+ sp -= align_up (arg_space, 16);
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog,
- "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
- paddress (gdbarch, sp), (long) align_up (len, 16));
+ gdb_printf (gdb_stdlog,
+ "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
+ paddress (gdbarch, sp),
+ (long) align_up (arg_space, 16));
/* Initialize the integer and float register pointers. */
argreg = MIPS_A0_REGNUM;
float_argreg = mips_fpa0_regnum (gdbarch);
/* The struct_return pointer occupies the first parameter-passing reg. */
- if (struct_return)
+ if (return_method == return_method_struct)
{
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog,
- "mips_o64_push_dummy_call: "
- "struct_return reg=%d %s\n",
- argreg, paddress (gdbarch, struct_addr));
+ gdb_printf (gdb_stdlog,
+ "mips_o64_push_dummy_call: "
+ "struct_return reg=%d %s\n",
+ argreg, paddress (gdbarch, struct_addr));
regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
stack_offset += MIPS64_REGSIZE;
}
const gdb_byte *val;
struct value *arg = args[argnum];
struct type *arg_type = check_typedef (value_type (arg));
- int len = TYPE_LENGTH (arg_type);
- enum type_code typecode = TYPE_CODE (arg_type);
+ int len = arg_type->length ();
+ enum type_code typecode = arg_type->code ();
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog,
- "mips_o64_push_dummy_call: %d len=%d type=%d",
- argnum + 1, len, (int) typecode);
+ gdb_printf (gdb_stdlog,
+ "mips_o64_push_dummy_call: %d len=%d type=%d",
+ argnum + 1, len, (int) typecode);
- val = value_contents (arg);
+ val = value_contents (arg).data ();
/* Floating point arguments passed in registers have to be
- treated specially. On 32-bit architectures, doubles are
- passed in register pairs; the even FP register gets the
- low word, and the odd FP register gets the high word.
- On O64, the first two floating point arguments are also
- copied to general registers, because MIPS16 functions
- don't use float registers for arguments. This duplication
- of arguments in general registers can't hurt non-MIPS16
- functions because those registers are normally skipped. */
+ treated specially. On 32-bit architectures, doubles are
+ passed in register pairs; the even FP register gets the
+ low word, and the odd FP register gets the high word.
+ On O64, the first two floating point arguments are also
+ copied to general registers, because MIPS16 functions
+ don't use float registers for arguments. This duplication
+ of arguments in general registers can't hurt non-MIPS16
+ functions because those registers are normally skipped. */
if (fp_register_arg_p (gdbarch, typecode, arg_type)
- && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch))
+ && float_argreg <= mips_last_fp_arg_regnum (gdbarch))
{
LONGEST regval = extract_unsigned_integer (val, len, byte_order);
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s",
- float_argreg, phex (regval, len));
+ gdb_printf (gdb_stdlog, " - fpreg=%d val=%s",
+ float_argreg, phex (regval, len));
regcache_cooked_write_unsigned (regcache, float_argreg++, regval);
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s",
- argreg, phex (regval, len));
+ gdb_printf (gdb_stdlog, " - reg=%d val=%s",
+ argreg, phex (regval, len));
regcache_cooked_write_unsigned (regcache, argreg, regval);
argreg++;
/* Reserve space for the FP register. */
int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE);
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog, " -- partial=%d",
- partial_len);
+ gdb_printf (gdb_stdlog, " -- partial=%d",
+ partial_len);
/* Write this portion of the argument to the stack. */
- if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)
+ if (argreg > mips_last_arg_regnum (gdbarch)
|| odd_sized_struct)
{
/* Should shorter than int integer values be
if (mips_debug)
{
- fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s",
- paddress (gdbarch, stack_offset));
- fprintf_unfiltered (gdb_stdlog, " longword_offset=%s",
- paddress (gdbarch, longword_offset));
+ gdb_printf (gdb_stdlog, " - stack_offset=%s",
+ paddress (gdbarch, stack_offset));
+ gdb_printf (gdb_stdlog, " longword_offset=%s",
+ paddress (gdbarch, longword_offset));
}
addr = sp + stack_offset + longword_offset;
if (mips_debug)
{
int i;
- fprintf_unfiltered (gdb_stdlog, " @%s ",
- paddress (gdbarch, addr));
+ gdb_printf (gdb_stdlog, " @%s ",
+ paddress (gdbarch, addr));
for (i = 0; i < partial_len; i++)
{
- fprintf_unfiltered (gdb_stdlog, "%02x",
- val[i] & 0xff);
+ gdb_printf (gdb_stdlog, "%02x",
+ val[i] & 0xff);
}
}
write_memory (addr, val, partial_len);
}
/* Note!!! This is NOT an else clause. Odd sized
- structs may go thru BOTH paths. */
+ structs may go thru BOTH paths. */
/* Write this portion of the argument to a general
- purpose register. */
- if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch))
+ purpose register. */
+ if (argreg <= mips_last_arg_regnum (gdbarch))
{
LONGEST regval = extract_signed_integer (val, partial_len,
byte_order);
* TARGET_CHAR_BIT);
if (mips_debug)
- fprintf_filtered (gdb_stdlog, " - reg=%d val=%s",
- argreg,
- phex (regval, MIPS64_REGSIZE));
+ gdb_printf (gdb_stdlog, " - reg=%d val=%s",
+ argreg,
+ phex (regval, MIPS64_REGSIZE));
regcache_cooked_write_unsigned (regcache, argreg, regval);
argreg++;
/* Prevent subsequent floating point arguments from
being passed in floating point registers. */
- float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1;
+ float_argreg = mips_last_fp_arg_regnum (gdbarch) + 1;
}
len -= partial_len;
val += partial_len;
/* Compute the offset into the stack at which we will
- copy the next parameter.
+ copy the next parameter.
- In older ABIs, the caller reserved space for
- registers that contained arguments. This was loosely
- refered to as their "home". Consequently, space is
- always allocated. */
+ In older ABIs, the caller reserved space for
+ registers that contained arguments. This was loosely
+ refered to as their "home". Consequently, space is
+ always allocated. */
stack_offset += align_up (partial_len, MIPS64_REGSIZE);
}
}
if (mips_debug)
- fprintf_unfiltered (gdb_stdlog, "\n");
+ gdb_printf (gdb_stdlog, "\n");
}
regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp);
{
CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0;
int mips16 = mips_pc_is_mips16 (gdbarch, func_addr);
- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
enum mips_fval_reg fval_reg;
fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both;
- if (TYPE_CODE (type) == TYPE_CODE_STRUCT
- || TYPE_CODE (type) == TYPE_CODE_UNION
- || TYPE_CODE (type) == TYPE_CODE_ARRAY)
+ if (type->code () == TYPE_CODE_STRUCT
+ || type->code () == TYPE_CODE_UNION
+ || type->code () == TYPE_CODE_ARRAY)
return RETURN_VALUE_STRUCT_CONVENTION;
- else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type))
+ else if (fp_register_arg_p (gdbarch, type->code (), type))
{
/* A floating-point value. If reading in or copying, then we get it
- from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
- If writing out only, then we put it to both FP0 and GPR2. We do
- not support reading in with no function known, if this safety
- check ever triggers, then we'll have to try harder. */
+ from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
+ If writing out only, then we put it to both FP0 and GPR2. We do
+ not support reading in with no function known, if this safety
+ check ever triggers, then we'll have to try harder. */
gdb_assert (function || !readbuf);
if (mips_debug)
switch (fval_reg)
{
case mips_fval_fpr:
- fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n");
+ gdb_printf (gdb_stderr, "Return float in $fp0\n");
break;
case mips_fval_gpr:
- fprintf_unfiltered (gdb_stderr, "Return float in $2\n");
+ gdb_printf (gdb_stderr, "Return float in $2\n");
break;
case mips_fval_both:
- fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n");
+ gdb_printf (gdb_stderr, "Return float in $fp0 and $2\n");
break;
}
if (fval_reg != mips_fval_gpr)
mips_xfer_register (gdbarch, regcache,
(gdbarch_num_regs (gdbarch)
+ mips_regnum (gdbarch)->fp0),
- TYPE_LENGTH (type),
+ type->length (),
gdbarch_byte_order (gdbarch),
readbuf, writebuf, 0);
if (fval_reg != mips_fval_fpr)
mips_xfer_register (gdbarch, regcache,
gdbarch_num_regs (gdbarch) + 2,
- TYPE_LENGTH (type),
+ type->length (),
gdbarch_byte_order (gdbarch),
readbuf, writebuf, 0);
return RETURN_VALUE_REGISTER_CONVENTION;
else
{
/* A scalar extract each part but least-significant-byte
- justified. */
+ justified. */
int offset;
int regnum;
for (offset = 0, regnum = MIPS_V0_REGNUM;
- offset < TYPE_LENGTH (type);
+ offset < type->length ();
offset += MIPS64_REGSIZE, regnum++)
{
int xfer = MIPS64_REGSIZE;
- if (offset + xfer > TYPE_LENGTH (type))
- xfer = TYPE_LENGTH (type) - offset;
+ if (offset + xfer > type->length ())
+ xfer = type->length () - offset;
if (mips_debug)
- fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n",
- offset, xfer, regnum);
+ gdb_printf (gdb_stderr, "Return scalar+%d:%d in $%d\n",
+ offset, xfer, regnum);
mips_xfer_register (gdbarch, regcache,
gdbarch_num_regs (gdbarch) + regnum,
xfer, gdbarch_byte_order (gdbarch),
into rare_buffer. */
static void
-mips_read_fp_register_single (struct frame_info *frame, int regno,
+mips_read_fp_register_single (frame_info_ptr frame, int regno,
gdb_byte *rare_buffer)
{
struct gdbarch *gdbarch = get_frame_arch (frame);
if (raw_size == 8)
{
/* We have a 64-bit value for this register. Find the low-order
- 32 bits. */
+ 32 bits. */
int offset;
if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
register. */
static void
-mips_read_fp_register_double (struct frame_info *frame, int regno,
+mips_read_fp_register_double (frame_info_ptr frame, int regno,
gdb_byte *rare_buffer)
{
struct gdbarch *gdbarch = get_frame_arch (frame);
if (raw_size == 8 && !mips2_fp_compat (frame))
{
/* We have a 64-bit value for this register, and we should use
- all 64 bits. */
+ all 64 bits. */
if (!deprecated_frame_register_read (frame, regno, rare_buffer))
error (_("can't read register %d (%s)"),
regno, gdbarch_register_name (gdbarch, regno));
int rawnum = regno % gdbarch_num_regs (gdbarch);
if ((rawnum - mips_regnum (gdbarch)->fp0) & 1)
- internal_error (__FILE__, __LINE__,
- _("mips_read_fp_register_double: bad access to "
+ internal_error (_("mips_read_fp_register_double: bad access to "
"odd-numbered FP register"));
/* mips_read_fp_register_single will find the correct 32 bits from
- each register. */
+ each register. */
if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
{
mips_read_fp_register_single (frame, regno, rare_buffer + 4);
}
static void
-mips_print_fp_register (struct ui_file *file, struct frame_info *frame,
+mips_print_fp_register (struct ui_file *file, frame_info_ptr frame,
int regnum)
{ /* Do values for FP (float) regs. */
struct gdbarch *gdbarch = get_frame_arch (frame);
gdb_byte *raw_buffer;
std::string flt_str, dbl_str;
- const struct floatformat *flt_fmt
- = floatformat_from_type (builtin_type (gdbarch)->builtin_float);
- const struct floatformat *dbl_fmt
- = floatformat_from_type (builtin_type (gdbarch)->builtin_double);
+ const struct type *flt_type = builtin_type (gdbarch)->builtin_float;
+ const struct type *dbl_type = builtin_type (gdbarch)->builtin_double;
raw_buffer
= ((gdb_byte *)
alloca (2 * register_size (gdbarch, mips_regnum (gdbarch)->fp0)));
- fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum));
- fprintf_filtered (file, "%*s",
- 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)),
- "");
+ gdb_printf (file, "%s:", gdbarch_register_name (gdbarch, regnum));
+ gdb_printf (file, "%*s",
+ 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)),
+ "");
if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame))
{
struct value_print_options opts;
/* 4-byte registers: Print hex and floating. Also print even
- numbered registers as doubles. */
+ numbered registers as doubles. */
mips_read_fp_register_single (frame, regnum, raw_buffer);
- flt_str = floatformat_to_string (flt_fmt, raw_buffer, "%-17.9g");
+ flt_str = target_float_to_string (raw_buffer, flt_type, "%-17.9g");
get_formatted_print_options (&opts, 'x');
print_scalar_formatted (raw_buffer,
builtin_type (gdbarch)->builtin_uint32,
&opts, 'w', file);
- fprintf_filtered (file, " flt: %s", flt_str.c_str ());
+ gdb_printf (file, " flt: %s", flt_str.c_str ());
if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0)
{
mips_read_fp_register_double (frame, regnum, raw_buffer);
- dbl_str = floatformat_to_string (dbl_fmt, raw_buffer, "%-24.17g");
+ dbl_str = target_float_to_string (raw_buffer, dbl_type, "%-24.17g");
- fprintf_filtered (file, " dbl: %s", dbl_str.c_str ());
+ gdb_printf (file, " dbl: %s", dbl_str.c_str ());
}
}
else
/* Eight byte registers: print each one as hex, float and double. */
mips_read_fp_register_single (frame, regnum, raw_buffer);
- flt_str = floatformat_to_string (flt_fmt, raw_buffer, "%-17.9g");
+ flt_str = target_float_to_string (raw_buffer, flt_type, "%-17.9g");
mips_read_fp_register_double (frame, regnum, raw_buffer);
- dbl_str = floatformat_to_string (dbl_fmt, raw_buffer, "%-24.17g");
+ dbl_str = target_float_to_string (raw_buffer, dbl_type, "%-24.17g");
get_formatted_print_options (&opts, 'x');
print_scalar_formatted (raw_buffer,
builtin_type (gdbarch)->builtin_uint64,
&opts, 'g', file);
- fprintf_filtered (file, " flt: %s", flt_str.c_str ());
- fprintf_filtered (file, " dbl: %s", dbl_str.c_str ());
+ gdb_printf (file, " flt: %s", flt_str.c_str ());
+ gdb_printf (file, " dbl: %s", dbl_str.c_str ());
}
}
static void
-mips_print_register (struct ui_file *file, struct frame_info *frame,
+mips_print_register (struct ui_file *file, frame_info_ptr frame,
int regnum)
{
struct gdbarch *gdbarch = get_frame_arch (frame);
val = get_frame_register_value (frame, regnum);
- fputs_filtered (gdbarch_register_name (gdbarch, regnum), file);
+ gdb_puts (gdbarch_register_name (gdbarch, regnum), file);
/* The problem with printing numeric register names (r26, etc.) is that
the user can't use them on input. Probably the best solution is to
fix it so that either the numeric or the funky (a2, etc.) names
are accepted on input. */
if (regnum < MIPS_NUMREGS)
- fprintf_filtered (file, "(r%d): ", regnum);
+ gdb_printf (file, "(r%d): ", regnum);
else
- fprintf_filtered (file, ": ");
+ gdb_printf (file, ": ");
get_formatted_print_options (&opts, 'x');
- val_print_scalar_formatted (value_type (val),
- value_embedded_offset (val),
- val,
- &opts, 0, file);
+ value_print_scalar_formatted (val, &opts, 0, file);
}
/* Print IEEE exception condition bits in FLAGS. */
print_fpu_flags (struct ui_file *file, int flags)
{
if (flags & (1 << 0))
- fputs_filtered (" inexact", file);
+ gdb_puts (" inexact", file);
if (flags & (1 << 1))
- fputs_filtered (" uflow", file);
+ gdb_puts (" uflow", file);
if (flags & (1 << 2))
- fputs_filtered (" oflow", file);
+ gdb_puts (" oflow", file);
if (flags & (1 << 3))
- fputs_filtered (" div0", file);
+ gdb_puts (" div0", file);
if (flags & (1 << 4))
- fputs_filtered (" inval", file);
+ gdb_puts (" inval", file);
if (flags & (1 << 5))
- fputs_filtered (" unimp", file);
- fputc_filtered ('\n', file);
+ gdb_puts (" unimp", file);
+ gdb_putc ('\n', file);
}
/* Print interesting information about the floating point processor
static void
mips_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
- struct frame_info *frame, const char *args)
+ frame_info_ptr frame, const char *args)
{
int fcsr = mips_regnum (gdbarch)->fp_control_status;
- enum mips_fpu_type type = MIPS_FPU_TYPE (gdbarch);
+ enum mips_fpu_type type = mips_get_fpu_type (gdbarch);
ULONGEST fcs = 0;
int i;
if (fcsr == -1 || !read_frame_register_unsigned (frame, fcsr, &fcs))
type = MIPS_FPU_NONE;
- fprintf_filtered (file, "fpu type: %s\n",
- type == MIPS_FPU_DOUBLE ? "double-precision"
- : type == MIPS_FPU_SINGLE ? "single-precision"
- : "none / unused");
+ gdb_printf (file, "fpu type: %s\n",
+ type == MIPS_FPU_DOUBLE ? "double-precision"
+ : type == MIPS_FPU_SINGLE ? "single-precision"
+ : "none / unused");
if (type == MIPS_FPU_NONE)
return;
- fprintf_filtered (file, "reg size: %d bits\n",
- register_size (gdbarch, mips_regnum (gdbarch)->fp0) * 8);
+ gdb_printf (file, "reg size: %d bits\n",
+ register_size (gdbarch, mips_regnum (gdbarch)->fp0) * 8);
- fputs_filtered ("cond :", file);
+ gdb_puts ("cond :", file);
if (fcs & (1 << 23))
- fputs_filtered (" 0", file);
+ gdb_puts (" 0", file);
for (i = 1; i <= 7; i++)
if (fcs & (1 << (24 + i)))
- fprintf_filtered (file, " %d", i);
- fputc_filtered ('\n', file);
+ gdb_printf (file, " %d", i);
+ gdb_putc ('\n', file);
- fputs_filtered ("cause :", file);
+ gdb_puts ("cause :", file);
print_fpu_flags (file, (fcs >> 12) & 0x3f);
fputs ("mask :", stdout);
print_fpu_flags (file, (fcs >> 7) & 0x1f);
fputs ("flags :", stdout);
print_fpu_flags (file, (fcs >> 2) & 0x1f);
- fputs_filtered ("rounding: ", file);
+ gdb_puts ("rounding: ", file);
switch (fcs & 3)
{
- case 0: fputs_filtered ("nearest\n", file); break;
- case 1: fputs_filtered ("zero\n", file); break;
- case 2: fputs_filtered ("+inf\n", file); break;
- case 3: fputs_filtered ("-inf\n", file); break;
+ case 0: gdb_puts ("nearest\n", file); break;
+ case 1: gdb_puts ("zero\n", file); break;
+ case 2: gdb_puts ("+inf\n", file); break;
+ case 3: gdb_puts ("-inf\n", file); break;
}
- fputs_filtered ("flush :", file);
+ gdb_puts ("flush :", file);
if (fcs & (1 << 21))
- fputs_filtered (" nearest", file);
+ gdb_puts (" nearest", file);
if (fcs & (1 << 22))
- fputs_filtered (" override", file);
+ gdb_puts (" override", file);
if (fcs & (1 << 24))
- fputs_filtered (" zero", file);
+ gdb_puts (" zero", file);
if ((fcs & (0xb << 21)) == 0)
- fputs_filtered (" no", file);
- fputc_filtered ('\n', file);
+ gdb_puts (" no", file);
+ gdb_putc ('\n', file);
- fprintf_filtered (file, "nan2008 : %s\n", fcs & (1 << 18) ? "yes" : "no");
- fprintf_filtered (file, "abs2008 : %s\n", fcs & (1 << 19) ? "yes" : "no");
- fputc_filtered ('\n', file);
+ gdb_printf (file, "nan2008 : %s\n", fcs & (1 << 18) ? "yes" : "no");
+ gdb_printf (file, "abs2008 : %s\n", fcs & (1 << 19) ? "yes" : "no");
+ gdb_putc ('\n', file);
default_print_float_info (gdbarch, file, frame, args);
}
Print regs in pretty columns. */
static int
-print_fp_register_row (struct ui_file *file, struct frame_info *frame,
+print_fp_register_row (struct ui_file *file, frame_info_ptr frame,
int regnum)
{
- fprintf_filtered (file, " ");
+ gdb_printf (file, " ");
mips_print_fp_register (file, frame, regnum);
- fprintf_filtered (file, "\n");
+ gdb_printf (file, "\n");
return regnum + 1;
}
/* Print a row's worth of GP (int) registers, with name labels above. */
static int
-print_gp_register_row (struct ui_file *file, struct frame_info *frame,
+print_gp_register_row (struct ui_file *file, frame_info_ptr frame,
int start_regnum)
{
struct gdbarch *gdbarch = get_frame_arch (frame);
/* For GP registers, we print a separate row of names above the vals. */
for (col = 0, regnum = start_regnum;
- col < ncols && regnum < gdbarch_num_regs (gdbarch)
- + gdbarch_num_pseudo_regs (gdbarch);
+ col < ncols && regnum < gdbarch_num_cooked_regs (gdbarch);
regnum++)
{
if (*gdbarch_register_name (gdbarch, regnum) == '\0')
/* Print this register on a row by itself. */
mips_print_register (file, frame, regnum);
- fprintf_filtered (file, "\n");
+ gdb_printf (file, "\n");
return regnum + 1;
}
if (col == 0)
- fprintf_filtered (file, " ");
- fprintf_filtered (file,
- mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s",
- gdbarch_register_name (gdbarch, regnum));
+ gdb_printf (file, " ");
+ gdb_printf (file,
+ mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s",
+ gdbarch_register_name (gdbarch, regnum));
col++;
}
/* Print the R0 to R31 names. */
if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS)
- fprintf_filtered (file, "\n R%-4d",
- start_regnum % gdbarch_num_regs (gdbarch));
+ gdb_printf (file, "\n R%-4d",
+ start_regnum % gdbarch_num_regs (gdbarch));
else
- fprintf_filtered (file, "\n ");
+ gdb_printf (file, "\n ");
/* Now print the values in hex, 4 or 8 to the row. */
for (col = 0, regnum = start_regnum;
- col < ncols && regnum < gdbarch_num_regs (gdbarch)
- + gdbarch_num_pseudo_regs (gdbarch);
+ col < ncols && regnum < gdbarch_num_cooked_regs (gdbarch);
regnum++)
{
if (*gdbarch_register_name (gdbarch, regnum) == '\0')
if (value_optimized_out (value)
|| !value_entirely_available (value))
{
- fprintf_filtered (file, "%*s ",
- (int) mips_abi_regsize (gdbarch) * 2,
- (mips_abi_regsize (gdbarch) == 4 ? "<unavl>"
- : "<unavailable>"));
+ gdb_printf (file, "%*s ",
+ (int) mips_abi_regsize (gdbarch) * 2,
+ (mips_abi_regsize (gdbarch) == 4 ? "<unavl>"
+ : "<unavailable>"));
col++;
continue;
}
- raw_buffer = value_contents_all (value);
+ raw_buffer = value_contents_all (value).data ();
/* pad small registers */
for (byte = 0;
byte < (mips_abi_regsize (gdbarch)
- register_size (gdbarch, regnum)); byte++)
- fprintf_filtered (file, " ");
+ gdb_printf (file, " ");
/* Now print the register value in hex, endian order. */
if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
for (byte =
register_size (gdbarch, regnum) - register_size (gdbarch, regnum);
byte < register_size (gdbarch, regnum); byte++)
- fprintf_filtered (file, "%02x", raw_buffer[byte]);
+ gdb_printf (file, "%02x", raw_buffer[byte]);
else
for (byte = register_size (gdbarch, regnum) - 1;
byte >= 0; byte--)
- fprintf_filtered (file, "%02x", raw_buffer[byte]);
- fprintf_filtered (file, " ");
+ gdb_printf (file, "%02x", raw_buffer[byte]);
+ gdb_printf (file, " ");
col++;
}
if (col > 0) /* ie. if we actually printed anything... */
- fprintf_filtered (file, "\n");
+ gdb_printf (file, "\n");
return regnum;
}
static void
mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
- struct frame_info *frame, int regnum, int all)
+ frame_info_ptr frame, int regnum, int all)
{
if (regnum != -1) /* Do one specified register. */
{
error (_("Not a valid register for the current processor type"));
mips_print_register (file, frame, regnum);
- fprintf_filtered (file, "\n");
+ gdb_printf (file, "\n");
}
else
/* Do all (or most) registers. */
{
regnum = gdbarch_num_regs (gdbarch);
- while (regnum < gdbarch_num_regs (gdbarch)
- + gdbarch_num_pseudo_regs (gdbarch))
+ while (regnum < gdbarch_num_cooked_regs (gdbarch))
{
if (mips_float_register_p (gdbarch, regnum))
{
static int
mips_single_step_through_delay (struct gdbarch *gdbarch,
- struct frame_info *frame)
+ frame_info_ptr frame)
{
- enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
CORE_ADDR pc = get_frame_pc (frame);
- struct address_space *aspace;
enum mips_isa isa;
ULONGEST insn;
- int status;
int size;
if ((mips_pc_is_mips (pc)
/* _has_delay_slot above will have validated the read. */
insn = mips_fetch_instruction (gdbarch, isa, pc, NULL);
size = mips_insn_size (isa, insn);
- aspace = get_frame_address_space (frame);
+
+ const address_space *aspace = get_frame_address_space (frame);
+
return breakpoint_here_p (aspace, pc + size) != no_breakpoint_here;
}
CORE_ADDR addr = func_end - 12;
if (addr < func_addr + 4)
- addr = func_addr + 4;
+ addr = func_addr + 4;
if (pc < addr)
- return 0;
+ return 0;
for (; pc < func_end; pc += MIPS_INSN32_SIZE)
{
CORE_ADDR addr = func_end - 12;
if (addr < func_addr + 4)
- addr = func_addr + 4;
+ addr = func_addr + 4;
if (pc < addr)
- return 0;
+ return 0;
for (; pc < func_end; pc += MIPS_INSN16_SIZE)
{
return mips32_stack_frame_destroyed_p (gdbarch, pc);
}
-/* Root of all "set mips "/"show mips " commands. This will eventually be
- used for all MIPS-specific commands. */
-
-static void
-show_mips_command (const char *args, int from_tty)
-{
- help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout);
-}
-
-static void
-set_mips_command (const char *args, int from_tty)
-{
- printf_unfiltered
- ("\"set mips\" must be followed by an appropriate subcommand.\n");
- help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout);
-}
-
/* Commands to show/set the MIPS FPU type. */
static void
if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips)
{
- printf_unfiltered
+ gdb_printf
("The MIPS floating-point coprocessor is unknown "
"because the current architecture is not MIPS.\n");
return;
}
- switch (MIPS_FPU_TYPE (target_gdbarch ()))
+ switch (mips_get_fpu_type (target_gdbarch ()))
{
case MIPS_FPU_SINGLE:
fpu = "single-precision";
fpu = "absent (none)";
break;
default:
- internal_error (__FILE__, __LINE__, _("bad switch"));
+ internal_error (_("bad switch"));
}
if (mips_fpu_type_auto)
- printf_unfiltered ("The MIPS floating-point coprocessor "
- "is set automatically (currently %s)\n",
- fpu);
+ gdb_printf ("The MIPS floating-point coprocessor "
+ "is set automatically (currently %s)\n",
+ fpu);
else
- printf_unfiltered
+ gdb_printf
("The MIPS floating-point coprocessor is assumed to be %s\n", fpu);
}
-static void
-set_mipsfpu_command (const char *args, int from_tty)
-{
- printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
- "\"single\",\"none\" or \"auto\".\n");
- show_mipsfpu_command (args, from_tty);
-}
-
static void
set_mipsfpu_single_command (const char *args, int from_tty)
{
struct gdbarch_info info;
- gdbarch_info_init (&info);
mips_fpu_type = MIPS_FPU_SINGLE;
mips_fpu_type_auto = 0;
/* FIXME: cagney/2003-11-15: Should be setting a field in "info"
instead of relying on globals. Doing that would let generic code
handle the search for this specific architecture. */
if (!gdbarch_update_p (info))
- internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
+ internal_error (_("set mipsfpu failed"));
}
static void
set_mipsfpu_double_command (const char *args, int from_tty)
{
struct gdbarch_info info;
- gdbarch_info_init (&info);
mips_fpu_type = MIPS_FPU_DOUBLE;
mips_fpu_type_auto = 0;
/* FIXME: cagney/2003-11-15: Should be setting a field in "info"
instead of relying on globals. Doing that would let generic code
handle the search for this specific architecture. */
if (!gdbarch_update_p (info))
- internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
+ internal_error (_("set mipsfpu failed"));
}
static void
set_mipsfpu_none_command (const char *args, int from_tty)
{
struct gdbarch_info info;
- gdbarch_info_init (&info);
mips_fpu_type = MIPS_FPU_NONE;
mips_fpu_type_auto = 0;
/* FIXME: cagney/2003-11-15: Should be setting a field in "info"
instead of relying on globals. Doing that would let generic code
handle the search for this specific architecture. */
if (!gdbarch_update_p (info))
- internal_error (__FILE__, __LINE__, _("set mipsfpu failed"));
+ internal_error (_("set mipsfpu failed"));
}
static void
callable as an sfunc. */
static void
-reinit_frame_cache_sfunc (char *args, int from_tty,
+reinit_frame_cache_sfunc (const char *args, int from_tty,
struct cmd_list_element *c)
{
reinit_frame_cache ();
static int
gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info)
{
- gdb_disassembler *di
- = static_cast<gdb_disassembler *>(info->application_data);
+ gdb_disassemble_info *di
+ = static_cast<gdb_disassemble_info *> (info->application_data);
struct gdbarch *gdbarch = di->arch ();
/* FIXME: cagney/2003-06-26: Is this even necessary? The
memaddr &= (info->mach == bfd_mach_mips16
|| info->mach == bfd_mach_mips_micromips) ? ~1 : ~3;
- /* Set the disassembler options. */
- if (!info->disassembler_options)
- /* This string is not recognized explicitly by the disassembler,
- but it tells the disassembler to not try to guess the ABI from
- the bfd elf headers, such that, if the user overrides the ABI
- of a program linked as NewABI, the disassembly will follow the
- register naming conventions specified by the user. */
- info->disassembler_options = "gpr-names=32";
-
return default_print_insn (memaddr, info);
}
-static int
-gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info)
-{
- /* Set up the disassembler info, so that we get the right
- register names from libopcodes. */
- info->disassembler_options = "gpr-names=n32";
- info->flavour = bfd_target_elf_flavour;
-
- return gdb_print_insn_mips (memaddr, info);
-}
-
-static int
-gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info)
-{
- /* Set up the disassembler info, so that we get the right
- register names from libopcodes. */
- info->disassembler_options = "gpr-names=64";
- info->flavour = bfd_target_elf_flavour;
-
- return gdb_print_insn_mips (memaddr, info);
-}
-
/* Implement the breakpoint_kind_from_pc gdbarch method. */
static int
return bpaddr;
/* If the previous instruction has a branch delay slot, we have
- to move the breakpoint to the branch instruction. */
+ to move the breakpoint to the branch instruction. */
prev_addr = bpaddr - 4;
if (mips32_insn_at_pc_has_delay_slot (gdbarch, prev_addr))
bpaddr = prev_addr;
boundary = unmake_compact_addr (boundary);
/* The only MIPS16 instructions with delay slots are JAL, JALX,
- JALR and JR. An absolute JAL/JALX is always 4 bytes long,
- so try for that first, then try the 2 byte JALR/JR.
- The microMIPS ASE has a whole range of jumps and branches
- with delay slots, some of which take 4 bytes and some take
- 2 bytes, so the idea is the same.
- FIXME: We have to assume that bpaddr is not the second half
- of an extended instruction. */
+ JALR and JR. An absolute JAL/JALX is always 4 bytes long,
+ so try for that first, then try the 2 byte JALR/JR.
+ The microMIPS ASE has a whole range of jumps and branches
+ with delay slots, some of which take 4 bytes and some take
+ 2 bytes, so the idea is the same.
+ FIXME: We have to assume that bpaddr is not the second half
+ of an extended instruction. */
insn_at_pc_has_delay_slot = (mips_pc_is_micromips (gdbarch, bpaddr)
? micromips_insn_at_pc_has_delay_slot
: mips16_insn_at_pc_has_delay_slot);
else
{
/* Not a jump instruction: if we're at [target-1] this
- could be the second word of a JAL/JALX, so continue;
- otherwise we're done. */
+ could be the second word of a JAL/JALX, so continue;
+ otherwise we're done. */
if (i > 1)
break;
}
The limit on the search is arbitrarily set to 20 instructions. FIXME. */
static CORE_ADDR
-mips_get_mips16_fn_stub_pc (struct frame_info *frame, CORE_ADDR pc)
+mips_get_mips16_fn_stub_pc (frame_info_ptr frame, CORE_ADDR pc)
{
struct gdbarch *gdbarch = get_frame_arch (frame);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
gory details. */
static CORE_ADDR
-mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
+mips_skip_mips16_trampoline_code (frame_info_ptr frame, CORE_ADDR pc)
{
struct gdbarch *gdbarch = get_frame_arch (frame);
CORE_ADDR start_addr;
if (strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0)
{
/* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
- and the target PC is in $2. */
+ and the target PC is in $2. */
if (mips_is_stub_suffix (name + prefixlen, 0))
return get_frame_register_signed
(frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM);
/* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
- i.e. before the JALR instruction, this is effectively a call stub
- and the target PC is in $2. Otherwise this is effectively
- a return stub and the target PC is in $18. */
+ i.e. before the JALR instruction, this is effectively a call stub
+ and the target PC is in $2. Otherwise this is effectively
+ a return stub and the target PC is in $18. */
else if (mips_is_stub_mode (name + prefixlen)
&& name[prefixlen + 2] == '_'
&& mips_is_stub_suffix (name + prefixlen + 3, 0))
so that $t9 has the correct value at function entry. */
static CORE_ADDR
-mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
+mips_skip_pic_trampoline_code (frame_info_ptr frame, CORE_ADDR pc)
{
struct gdbarch *gdbarch = get_frame_arch (frame);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
which jumps to foo. */
msym = lookup_minimal_symbol_by_pc (pc);
if (msym.minsym == NULL
- || BMSYMBOL_VALUE_ADDRESS (msym) != pc
- || MSYMBOL_LINKAGE_NAME (msym.minsym) == NULL
- || !startswith (MSYMBOL_LINKAGE_NAME (msym.minsym), ".pic."))
+ || msym.value_address () != pc
+ || msym.minsym->linkage_name () == NULL
+ || !startswith (msym.minsym->linkage_name (), ".pic."))
return 0;
/* A two-instruction header. */
- if (MSYMBOL_SIZE (msym.minsym) == 8)
+ if (msym.minsym->size () == 8)
return pc + 8;
/* A three-instruction (plus delay slot) trampoline. */
- if (MSYMBOL_SIZE (msym.minsym) == 16)
+ if (msym.minsym->size () == 16)
{
if (target_read_memory (pc, stub_code, 16) != 0)
return 0;
}
static CORE_ADDR
-mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
+mips_skip_trampoline_code (frame_info_ptr frame, CORE_ADDR pc)
{
CORE_ADDR requested_pc = pc;
CORE_ADDR target_pc;
decide if it is valid. Should instead define a standard sim/gdb
register numbering scheme. */
if (gdbarch_register_name (gdbarch,
- gdbarch_num_regs (gdbarch) + regnum) != NULL
- && gdbarch_register_name (gdbarch,
- gdbarch_num_regs (gdbarch)
- + regnum)[0] != '\0')
+ gdbarch_num_regs (gdbarch) + regnum)[0] != '\0')
return regnum;
else
return LEGACY_SIM_REGNO_IGNORE;
struct type *type, const gdb_byte *buf)
{
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
- return extract_signed_integer (buf, TYPE_LENGTH (type), byte_order);
+ return extract_signed_integer (buf, type->length (), byte_order);
}
/* Dummy virtual frame pointer method. This is no more or less accurate
mips_find_abi_section (bfd *abfd, asection *sect, void *obj)
{
enum mips_abi *abip = (enum mips_abi *) obj;
- const char *name = bfd_get_section_name (abfd, sect);
+ const char *name = bfd_section_name (sect);
if (*abip != MIPS_ABI_UNKNOWN)
return;
mips_find_long_section (bfd *abfd, asection *sect, void *obj)
{
int *lbp = (int *) obj;
- const char *name = bfd_get_section_name (abfd, sect);
+ const char *name = bfd_section_name (sect);
if (startswith (name, ".gcc_compiled_long32"))
*lbp = 32;
if (mips_abi_strings[i] == mips_abi_string)
return (enum mips_abi) i;
- internal_error (__FILE__, __LINE__, _("unknown ABI string"));
+ internal_error (_("unknown ABI string"));
}
/* Return the default compressed instruction set, either of MIPS16
if (mips_compression_strings[i] == mips_compression_string)
return (enum mips_isa) i;
- internal_error (__FILE__, __LINE__, _("unknown compressed ISA string"));
+ internal_error (_("unknown compressed ISA string"));
}
static void
}
static struct value *
-value_of_mips_user_reg (struct frame_info *frame, const void *baton)
+value_of_mips_user_reg (frame_info_ptr frame, const void *baton)
{
const int *reg_p = (const int *) baton;
return value_of_register (*reg_p, frame);
mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
{
struct gdbarch *gdbarch;
- struct gdbarch_tdep *tdep;
int elf_flags;
enum mips_abi mips_abi, found_abi, wanted_abi;
int i, num_regs;
enum mips_fpu_type fpu_type;
- struct tdesc_arch_data *tdesc_data = NULL;
+ tdesc_arch_data_up tdesc_data;
int elf_fpu_type = Val_GNU_MIPS_ABI_FP_ANY;
- const char **reg_names;
+ const char * const *reg_names;
struct mips_regnum mips_regnum, *regnum;
enum mips_isa mips_isa;
int dspacc;
int dspctl;
- /* Fill in the OS dependent register numbers and names. */
- if (info.osabi == GDB_OSABI_LINUX)
- {
- mips_regnum.fp0 = 38;
- mips_regnum.pc = 37;
- mips_regnum.cause = 36;
- mips_regnum.badvaddr = 35;
- mips_regnum.hi = 34;
- mips_regnum.lo = 33;
- mips_regnum.fp_control_status = 70;
- mips_regnum.fp_implementation_revision = 71;
- mips_regnum.dspacc = -1;
- mips_regnum.dspctl = -1;
- dspacc = 72;
- dspctl = 78;
- num_regs = 90;
- reg_names = mips_linux_reg_names;
- }
- else
- {
- mips_regnum.lo = MIPS_EMBED_LO_REGNUM;
- mips_regnum.hi = MIPS_EMBED_HI_REGNUM;
- mips_regnum.badvaddr = MIPS_EMBED_BADVADDR_REGNUM;
- mips_regnum.cause = MIPS_EMBED_CAUSE_REGNUM;
- mips_regnum.pc = MIPS_EMBED_PC_REGNUM;
- mips_regnum.fp0 = MIPS_EMBED_FP0_REGNUM;
- mips_regnum.fp_control_status = 70;
- mips_regnum.fp_implementation_revision = 71;
- mips_regnum.dspacc = dspacc = -1;
- mips_regnum.dspctl = dspctl = -1;
- num_regs = MIPS_LAST_EMBED_REGNUM + 1;
- if (info.bfd_arch_info != NULL
- && info.bfd_arch_info->mach == bfd_mach_mips3900)
- reg_names = mips_tx39_reg_names;
- else
- reg_names = mips_generic_reg_names;
- }
-
- /* Check any target description for validity. */
- if (tdesc_has_registers (info.target_desc))
- {
- static const char *const mips_gprs[] = {
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
- "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
- "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
- "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
- };
- static const char *const mips_fprs[] = {
- "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
- "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
- "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
- "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
- };
-
- const struct tdesc_feature *feature;
- int valid_p;
-
- feature = tdesc_find_feature (info.target_desc,
- "org.gnu.gdb.mips.cpu");
- if (feature == NULL)
- return NULL;
-
- tdesc_data = tdesc_data_alloc ();
-
- valid_p = 1;
- for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++)
- valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
- mips_gprs[i]);
-
-
- valid_p &= tdesc_numbered_register (feature, tdesc_data,
- mips_regnum.lo, "lo");
- valid_p &= tdesc_numbered_register (feature, tdesc_data,
- mips_regnum.hi, "hi");
- valid_p &= tdesc_numbered_register (feature, tdesc_data,
- mips_regnum.pc, "pc");
-
- if (!valid_p)
- {
- tdesc_data_cleanup (tdesc_data);
- return NULL;
- }
-
- feature = tdesc_find_feature (info.target_desc,
- "org.gnu.gdb.mips.cp0");
- if (feature == NULL)
- {
- tdesc_data_cleanup (tdesc_data);
- return NULL;
- }
-
- valid_p = 1;
- valid_p &= tdesc_numbered_register (feature, tdesc_data,
- mips_regnum.badvaddr, "badvaddr");
- valid_p &= tdesc_numbered_register (feature, tdesc_data,
- MIPS_PS_REGNUM, "status");
- valid_p &= tdesc_numbered_register (feature, tdesc_data,
- mips_regnum.cause, "cause");
-
- if (!valid_p)
- {
- tdesc_data_cleanup (tdesc_data);
- return NULL;
- }
-
- /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
- backend is not prepared for that, though. */
- feature = tdesc_find_feature (info.target_desc,
- "org.gnu.gdb.mips.fpu");
- if (feature == NULL)
- {
- tdesc_data_cleanup (tdesc_data);
- return NULL;
- }
-
- valid_p = 1;
- for (i = 0; i < 32; i++)
- valid_p &= tdesc_numbered_register (feature, tdesc_data,
- i + mips_regnum.fp0, mips_fprs[i]);
-
- valid_p &= tdesc_numbered_register (feature, tdesc_data,
- mips_regnum.fp_control_status,
- "fcsr");
- valid_p
- &= tdesc_numbered_register (feature, tdesc_data,
- mips_regnum.fp_implementation_revision,
- "fir");
-
- if (!valid_p)
- {
- tdesc_data_cleanup (tdesc_data);
- return NULL;
- }
-
- num_regs = mips_regnum.fp_implementation_revision + 1;
-
- if (dspacc >= 0)
- {
- feature = tdesc_find_feature (info.target_desc,
- "org.gnu.gdb.mips.dsp");
- /* The DSP registers are optional; it's OK if they are absent. */
- if (feature != NULL)
- {
- i = 0;
- valid_p = 1;
- valid_p &= tdesc_numbered_register (feature, tdesc_data,
- dspacc + i++, "hi1");
- valid_p &= tdesc_numbered_register (feature, tdesc_data,
- dspacc + i++, "lo1");
- valid_p &= tdesc_numbered_register (feature, tdesc_data,
- dspacc + i++, "hi2");
- valid_p &= tdesc_numbered_register (feature, tdesc_data,
- dspacc + i++, "lo2");
- valid_p &= tdesc_numbered_register (feature, tdesc_data,
- dspacc + i++, "hi3");
- valid_p &= tdesc_numbered_register (feature, tdesc_data,
- dspacc + i++, "lo3");
-
- valid_p &= tdesc_numbered_register (feature, tdesc_data,
- dspctl, "dspctl");
-
- if (!valid_p)
- {
- tdesc_data_cleanup (tdesc_data);
- return NULL;
- }
-
- mips_regnum.dspacc = dspacc;
- mips_regnum.dspctl = dspctl;
-
- num_regs = mips_regnum.dspctl + 1;
- }
- }
-
- /* It would be nice to detect an attempt to use a 64-bit ABI
- when only 32-bit registers are provided. */
- reg_names = NULL;
- }
-
/* First of all, extract the elf_flags, if available. */
if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
elf_flags = elf_elfheader (info.abfd)->e_flags;
else if (arches != NULL)
- elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags;
+ {
+ mips_gdbarch_tdep *tdep
+ = gdbarch_tdep<mips_gdbarch_tdep> (arches->gdbarch);
+ elf_flags = tdep->elf_flags;
+ }
else
elf_flags = 0;
if (gdbarch_debug)
- fprintf_unfiltered (gdb_stdlog,
- "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags);
+ gdb_printf (gdb_stdlog,
+ "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags);
/* Check ELF_FLAGS to see if it specifies the ABI being used. */
switch ((elf_flags & EF_MIPS_ABI))
/* If we have no useful BFD information, use the ABI from the last
MIPS architecture (if there is one). */
if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL)
- found_abi = gdbarch_tdep (arches->gdbarch)->found_abi;
+ {
+ mips_gdbarch_tdep *tdep
+ = gdbarch_tdep<mips_gdbarch_tdep> (arches->gdbarch);
+ found_abi = tdep->found_abi;
+ }
/* Try the architecture for any hint of the correct ABI. */
if (found_abi == MIPS_ABI_UNKNOWN
found_abi = MIPS_ABI_N64;
if (gdbarch_debug)
- fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n",
- found_abi);
+ gdb_printf (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n",
+ found_abi);
/* What has the user specified from the command line? */
wanted_abi = global_mips_abi ();
if (gdbarch_debug)
- fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n",
- wanted_abi);
+ gdb_printf (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n",
+ wanted_abi);
/* Now that we have found what the ABI for this binary would be,
check whether the user is overriding it. */
else
mips_abi = MIPS_ABI_O32;
if (gdbarch_debug)
- fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n",
- mips_abi);
+ gdb_printf (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n",
+ mips_abi);
+
+ /* Make sure we don't use a 32-bit architecture with a 64-bit ABI. */
+ if (mips_abi != MIPS_ABI_EABI32
+ && mips_abi != MIPS_ABI_O32
+ && info.bfd_arch_info != NULL
+ && info.bfd_arch_info->arch == bfd_arch_mips
+ && info.bfd_arch_info->bits_per_word < 64)
+ info.bfd_arch_info = bfd_lookup_arch (bfd_arch_mips, bfd_mach_mips4000);
/* Determine the default compressed ISA. */
if ((elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0
/* Also used when doing an architecture lookup. */
if (gdbarch_debug)
- fprintf_unfiltered (gdb_stdlog,
- "mips_gdbarch_init: "
- "mips64_transfers_32bit_regs_p = %d\n",
- mips64_transfers_32bit_regs_p);
+ gdb_printf (gdb_stdlog,
+ "mips_gdbarch_init: "
+ "mips64_transfers_32bit_regs_p = %d\n",
+ mips64_transfers_32bit_regs_p);
/* Determine the MIPS FPU type. */
#ifdef HAVE_ELF
break;
}
else if (arches != NULL)
- fpu_type = MIPS_FPU_TYPE (arches->gdbarch);
+ fpu_type = mips_get_fpu_type (arches->gdbarch);
else
fpu_type = MIPS_FPU_DOUBLE;
if (gdbarch_debug)
- fprintf_unfiltered (gdb_stdlog,
- "mips_gdbarch_init: fpu_type = %d\n", fpu_type);
+ gdb_printf (gdb_stdlog,
+ "mips_gdbarch_init: fpu_type = %d\n", fpu_type);
/* Check for blatant incompatibilities. */
&& tdesc_property (info.target_desc, PROPERTY_GP32) != NULL
&& mips_abi != MIPS_ABI_EABI32
&& mips_abi != MIPS_ABI_O32)
+ return NULL;
+
+ /* Fill in the OS dependent register numbers and names. */
+ if (info.osabi == GDB_OSABI_LINUX)
+ {
+ mips_regnum.fp0 = 38;
+ mips_regnum.pc = 37;
+ mips_regnum.cause = 36;
+ mips_regnum.badvaddr = 35;
+ mips_regnum.hi = 34;
+ mips_regnum.lo = 33;
+ mips_regnum.fp_control_status = 70;
+ mips_regnum.fp_implementation_revision = 71;
+ mips_regnum.dspacc = -1;
+ mips_regnum.dspctl = -1;
+ dspacc = 72;
+ dspctl = 78;
+ num_regs = 90;
+ reg_names = mips_linux_reg_names;
+ }
+ else
{
- if (tdesc_data != NULL)
- tdesc_data_cleanup (tdesc_data);
- return NULL;
+ mips_regnum.lo = MIPS_EMBED_LO_REGNUM;
+ mips_regnum.hi = MIPS_EMBED_HI_REGNUM;
+ mips_regnum.badvaddr = MIPS_EMBED_BADVADDR_REGNUM;
+ mips_regnum.cause = MIPS_EMBED_CAUSE_REGNUM;
+ mips_regnum.pc = MIPS_EMBED_PC_REGNUM;
+ mips_regnum.fp0 = MIPS_EMBED_FP0_REGNUM;
+ mips_regnum.fp_control_status = 70;
+ mips_regnum.fp_implementation_revision = 71;
+ mips_regnum.dspacc = dspacc = -1;
+ mips_regnum.dspctl = dspctl = -1;
+ num_regs = MIPS_LAST_EMBED_REGNUM + 1;
+ if (info.bfd_arch_info != NULL
+ && info.bfd_arch_info->mach == bfd_mach_mips3900)
+ reg_names = mips_tx39_reg_names;
+ else
+ reg_names = mips_generic_reg_names;
+ }
+
+ /* Check any target description for validity. */
+ if (tdesc_has_registers (info.target_desc))
+ {
+ static const char *const mips_gprs[] = {
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+ "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
+ "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
+ };
+ static const char *const mips_fprs[] = {
+ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
+ "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
+ "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
+ "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
+ };
+
+ const struct tdesc_feature *feature;
+ int valid_p;
+
+ feature = tdesc_find_feature (info.target_desc,
+ "org.gnu.gdb.mips.cpu");
+ if (feature == NULL)
+ return NULL;
+
+ tdesc_data = tdesc_data_alloc ();
+
+ valid_p = 1;
+ for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++)
+ valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i,
+ mips_gprs[i]);
+
+
+ valid_p &= tdesc_numbered_register (feature, tdesc_data.get (),
+ mips_regnum.lo, "lo");
+ valid_p &= tdesc_numbered_register (feature, tdesc_data.get (),
+ mips_regnum.hi, "hi");
+ valid_p &= tdesc_numbered_register (feature, tdesc_data.get (),
+ mips_regnum.pc, "pc");
+
+ if (!valid_p)
+ return NULL;
+
+ feature = tdesc_find_feature (info.target_desc,
+ "org.gnu.gdb.mips.cp0");
+ if (feature == NULL)
+ return NULL;
+
+ valid_p = 1;
+ valid_p &= tdesc_numbered_register (feature, tdesc_data.get (),
+ mips_regnum.badvaddr, "badvaddr");
+ valid_p &= tdesc_numbered_register (feature, tdesc_data.get (),
+ MIPS_PS_REGNUM, "status");
+ valid_p &= tdesc_numbered_register (feature, tdesc_data.get (),
+ mips_regnum.cause, "cause");
+
+ if (!valid_p)
+ return NULL;
+
+ /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
+ backend is not prepared for that, though. */
+ feature = tdesc_find_feature (info.target_desc,
+ "org.gnu.gdb.mips.fpu");
+ if (feature == NULL)
+ return NULL;
+
+ valid_p = 1;
+ for (i = 0; i < 32; i++)
+ valid_p &= tdesc_numbered_register (feature, tdesc_data.get (),
+ i + mips_regnum.fp0, mips_fprs[i]);
+
+ valid_p &= tdesc_numbered_register (feature, tdesc_data.get (),
+ mips_regnum.fp_control_status,
+ "fcsr");
+ valid_p
+ &= tdesc_numbered_register (feature, tdesc_data.get (),
+ mips_regnum.fp_implementation_revision,
+ "fir");
+
+ if (!valid_p)
+ return NULL;
+
+ num_regs = mips_regnum.fp_implementation_revision + 1;
+
+ if (dspacc >= 0)
+ {
+ feature = tdesc_find_feature (info.target_desc,
+ "org.gnu.gdb.mips.dsp");
+ /* The DSP registers are optional; it's OK if they are absent. */
+ if (feature != NULL)
+ {
+ i = 0;
+ valid_p = 1;
+ valid_p &= tdesc_numbered_register (feature, tdesc_data.get (),
+ dspacc + i++, "hi1");
+ valid_p &= tdesc_numbered_register (feature, tdesc_data.get (),
+ dspacc + i++, "lo1");
+ valid_p &= tdesc_numbered_register (feature, tdesc_data.get (),
+ dspacc + i++, "hi2");
+ valid_p &= tdesc_numbered_register (feature, tdesc_data.get (),
+ dspacc + i++, "lo2");
+ valid_p &= tdesc_numbered_register (feature, tdesc_data.get (),
+ dspacc + i++, "hi3");
+ valid_p &= tdesc_numbered_register (feature, tdesc_data.get (),
+ dspacc + i++, "lo3");
+
+ valid_p &= tdesc_numbered_register (feature, tdesc_data.get (),
+ dspctl, "dspctl");
+
+ if (!valid_p)
+ return NULL;
+
+ mips_regnum.dspacc = dspacc;
+ mips_regnum.dspctl = dspctl;
+
+ num_regs = mips_regnum.dspctl + 1;
+ }
+ }
+
+ /* It would be nice to detect an attempt to use a 64-bit ABI
+ when only 32-bit registers are provided. */
+ reg_names = NULL;
}
/* Try to find a pre-existing architecture. */
arches != NULL;
arches = gdbarch_list_lookup_by_info (arches->next, &info))
{
+ mips_gdbarch_tdep *tdep
+ = gdbarch_tdep<mips_gdbarch_tdep> (arches->gdbarch);
+
/* MIPS needs to be pedantic about which ABI and the compressed
- ISA variation the object is using. */
- if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
+ ISA variation the object is using. */
+ if (tdep->elf_flags != elf_flags)
continue;
- if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi)
+ if (tdep->mips_abi != mips_abi)
continue;
- if (gdbarch_tdep (arches->gdbarch)->mips_isa != mips_isa)
+ if (tdep->mips_isa != mips_isa)
continue;
/* Need to be pedantic about which register virtual size is
- used. */
- if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p
+ used. */
+ if (tdep->mips64_transfers_32bit_regs_p
!= mips64_transfers_32bit_regs_p)
continue;
/* Be pedantic about which FPU is selected. */
- if (MIPS_FPU_TYPE (arches->gdbarch) != fpu_type)
+ if (mips_get_fpu_type (arches->gdbarch) != fpu_type)
continue;
- if (tdesc_data != NULL)
- tdesc_data_cleanup (tdesc_data);
return arches->gdbarch;
}
/* Need a new architecture. Fill in a target specific vector. */
- tdep = XCNEW (struct gdbarch_tdep);
+ mips_gdbarch_tdep *tdep = new mips_gdbarch_tdep;
gdbarch = gdbarch_alloc (&info, tdep);
tdep->elf_flags = elf_flags;
tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p;
set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double);
break;
default:
- internal_error (__FILE__, __LINE__, _("unknown ABI in switch"));
+ internal_error (_("unknown ABI in switch"));
}
/* GCC creates a pseudo-section whose name specifies the size of
set_gdbarch_ptr_bit (gdbarch, long_bit);
break;
default:
- internal_error (__FILE__, __LINE__, _("unknown ABI in switch"));
+ internal_error (_("unknown ABI in switch"));
}
}
}
set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info);
- if (mips_abi == MIPS_ABI_N32)
- set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32);
- else if (mips_abi == MIPS_ABI_N64)
- set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64);
+ set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips);
+ if (mips_abi == MIPS_ABI_N64)
+ set_gdbarch_disassembler_options_implicit
+ (gdbarch, (const char *) mips_disassembler_options_n64);
+ else if (mips_abi == MIPS_ABI_N32)
+ set_gdbarch_disassembler_options_implicit
+ (gdbarch, (const char *) mips_disassembler_options_n32);
else
- set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips);
+ set_gdbarch_disassembler_options_implicit
+ (gdbarch, (const char *) mips_disassembler_options_o32);
+ set_gdbarch_disassembler_options (gdbarch, &mips_disassembler_options);
+ set_gdbarch_valid_disassembler_options (gdbarch,
+ disassembler_options_mips ());
/* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
mips_register_g_packet_guesses (gdbarch);
/* Hook in OS ABI-specific overrides, if they have been registered. */
- info.tdesc_data = tdesc_data;
+ info.tdesc_data = tdesc_data.get ();
gdbarch_init_osabi (info, gdbarch);
/* The hook may have adjusted num_regs, fetch the final value and
frame_base_append_sniffer (gdbarch, mips_micro_frame_base_sniffer);
frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer);
- if (tdesc_data)
+ if (tdesc_data != nullptr)
{
set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type);
- tdesc_use_registers (gdbarch, info.target_desc, tdesc_data);
+ tdesc_use_registers (gdbarch, info.target_desc, std::move (tdesc_data));
/* Override the normal target description methods to handle our
dual real and pseudo registers. */
}
static void
-mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c)
+mips_abi_update (const char *ignore_args,
+ int from_tty, struct cmd_list_element *c)
{
struct gdbarch_info info;
/* Force the architecture to update, and (if it's a MIPS architecture)
mips_gdbarch_init will take care of the rest. */
- gdbarch_info_init (&info);
gdbarch_update_p (info);
}
const char *ignored_value)
{
if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips)
- fprintf_filtered
+ gdb_printf
(file,
"The MIPS ABI is unknown because the current architecture "
"is not MIPS.\n");
const char *actual_abi_str = mips_abi_strings[actual_abi];
if (global_abi == MIPS_ABI_UNKNOWN)
- fprintf_filtered
+ gdb_printf
(file,
"The MIPS ABI is set automatically (currently \"%s\").\n",
actual_abi_str);
else if (global_abi == actual_abi)
- fprintf_filtered
+ gdb_printf
(file,
"The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
actual_abi_str);
else
{
/* Probably shouldn't happen... */
- fprintf_filtered (file,
- "The (auto detected) MIPS ABI \"%s\" is in use "
- "even though the user setting was \"%s\".\n",
- actual_abi_str, mips_abi_strings[global_abi]);
+ gdb_printf (file,
+ "The (auto detected) MIPS ABI \"%s\" is in use "
+ "even though the user setting was \"%s\".\n",
+ actual_abi_str, mips_abi_strings[global_abi]);
}
}
}
show_mips_compression (struct ui_file *file, int from_tty,
struct cmd_list_element *c, const char *value)
{
- fprintf_filtered (file, _("The compressed ISA encoding used is %s.\n"),
- value);
+ gdb_printf (file, _("The compressed ISA encoding used is %s.\n"),
+ value);
}
/* Return a textual name for MIPS FPU type FPU_TYPE. */
static void
mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
{
- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch);
if (tdep != NULL)
{
int ef_mips_arch;
}
/* Determine the size of a pointer. */
ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE);
- fprintf_unfiltered (file,
- "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
- tdep->elf_flags);
- fprintf_unfiltered (file,
- "mips_dump_tdep: ef_mips_32bitmode = %d\n",
- ef_mips_32bitmode);
- fprintf_unfiltered (file,
- "mips_dump_tdep: ef_mips_arch = %d\n",
- ef_mips_arch);
- fprintf_unfiltered (file,
- "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
- tdep->mips_abi, mips_abi_strings[tdep->mips_abi]);
- fprintf_unfiltered (file,
- "mips_dump_tdep: "
- "mips_mask_address_p() %d (default %d)\n",
- mips_mask_address_p (tdep),
- tdep->default_mask_address_p);
+ gdb_printf (file,
+ "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
+ tdep->elf_flags);
+ gdb_printf (file,
+ "mips_dump_tdep: ef_mips_32bitmode = %d\n",
+ ef_mips_32bitmode);
+ gdb_printf (file,
+ "mips_dump_tdep: ef_mips_arch = %d\n",
+ ef_mips_arch);
+ gdb_printf (file,
+ "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
+ tdep->mips_abi, mips_abi_strings[tdep->mips_abi]);
+ gdb_printf (file,
+ "mips_dump_tdep: "
+ "mips_mask_address_p() %d (default %d)\n",
+ mips_mask_address_p (tdep),
+ tdep->default_mask_address_p);
}
- fprintf_unfiltered (file,
- "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
- MIPS_DEFAULT_FPU_TYPE,
- mips_fpu_type_str (MIPS_DEFAULT_FPU_TYPE));
- fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n",
- MIPS_EABI (gdbarch));
- fprintf_unfiltered (file,
- "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
- MIPS_FPU_TYPE (gdbarch),
- mips_fpu_type_str (MIPS_FPU_TYPE (gdbarch)));
-}
-
+ gdb_printf (file,
+ "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
+ MIPS_DEFAULT_FPU_TYPE,
+ mips_fpu_type_str (MIPS_DEFAULT_FPU_TYPE));
+ gdb_printf (file, "mips_dump_tdep: MIPS_EABI = %d\n",
+ mips_eabi (gdbarch));
+ gdb_printf (file,
+ "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
+ mips_get_fpu_type (gdbarch),
+ mips_fpu_type_str (mips_get_fpu_type (gdbarch)));
+}
+
+void _initialize_mips_tdep ();
void
-_initialize_mips_tdep (void)
+_initialize_mips_tdep ()
{
static struct cmd_list_element *mipsfpulist = NULL;
- struct cmd_list_element *c;
mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN];
if (MIPS_ABI_LAST + 1
!= sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0]))
- internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync"));
+ internal_error (_("mips_abi_strings out of sync"));
gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep);
- mips_pdr_data = register_objfile_data ();
-
/* Create feature sets with the appropriate properties. The values
are not important. */
- mips_tdesc_gp32 = allocate_target_description ();
+ mips_tdesc_gp32 = allocate_target_description ().release ();
set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, "");
- mips_tdesc_gp64 = allocate_target_description ();
+ mips_tdesc_gp64 = allocate_target_description ().release ();
set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, "");
/* Add root prefix command for all "set mips"/"show mips" commands. */
- add_prefix_cmd ("mips", no_class, set_mips_command,
- _("Various MIPS specific commands."),
- &setmipscmdlist, "set mips ", 0, &setlist);
-
- add_prefix_cmd ("mips", no_class, show_mips_command,
- _("Various MIPS specific commands."),
- &showmipscmdlist, "show mips ", 0, &showlist);
+ add_setshow_prefix_cmd ("mips", no_class,
+ _("Various MIPS specific commands."),
+ _("Various MIPS specific commands."),
+ &setmipscmdlist, &showmipscmdlist,
+ &setlist, &showlist);
/* Allow the user to override the ABI. */
add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings,
/* Let the user turn off floating point and set the fence post for
heuristic_proc_start. */
- add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command,
- _("Set use of MIPS floating-point coprocessor."),
- &mipsfpulist, "set mipsfpu ", 0, &setlist);
+ add_basic_prefix_cmd ("mipsfpu", class_support,
+ _("Set use of MIPS floating-point coprocessor."),
+ &mipsfpulist, 0, &setlist);
add_cmd ("single", class_support, set_mipsfpu_single_command,
_("Select single-precision MIPS floating-point coprocessor."),
&mipsfpulist);
- add_cmd ("double", class_support, set_mipsfpu_double_command,
- _("Select double-precision MIPS floating-point coprocessor."),
- &mipsfpulist);
- add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist);
- add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist);
- add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist);
- add_cmd ("none", class_support, set_mipsfpu_none_command,
- _("Select no MIPS floating-point coprocessor."), &mipsfpulist);
- add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist);
- add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist);
- add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist);
+ cmd_list_element *set_mipsfpu_double_cmd
+ = add_cmd ("double", class_support, set_mipsfpu_double_command,
+ _("Select double-precision MIPS floating-point coprocessor."),
+ &mipsfpulist);
+ add_alias_cmd ("on", set_mipsfpu_double_cmd, class_support, 1, &mipsfpulist);
+ add_alias_cmd ("yes", set_mipsfpu_double_cmd, class_support, 1, &mipsfpulist);
+ add_alias_cmd ("1", set_mipsfpu_double_cmd, class_support, 1, &mipsfpulist);
+
+ cmd_list_element *set_mipsfpu_none_cmd
+ = add_cmd ("none", class_support, set_mipsfpu_none_command,
+ _("Select no MIPS floating-point coprocessor."), &mipsfpulist);
+ add_alias_cmd ("off", set_mipsfpu_none_cmd, class_support, 1, &mipsfpulist);
+ add_alias_cmd ("no", set_mipsfpu_none_cmd, class_support, 1, &mipsfpulist);
+ add_alias_cmd ("0", set_mipsfpu_none_cmd, class_support, 1, &mipsfpulist);
add_cmd ("auto", class_support, set_mipsfpu_auto_command,
_("Select MIPS floating-point coprocessor automatically."),
&mipsfpulist);
projects / binutils-gdb.git / blobdiff