/* Target-dependent code for the RISC-V architecture, for GDB.
- Copyright (C) 2018-2022 Free Software Foundation, Inc.
+ Copyright (C) 2018-2023 Free Software Foundation, Inc.
This file is part of GDB.
#include "regcache.h"
#include "osabi.h"
#include "riscv-tdep.h"
-#include "block.h"
#include "reggroups.h"
#include "opcode/riscv.h"
#include "elf/riscv.h"
#include "prologue-value.h"
#include "arch/riscv.h"
#include "riscv-ravenscar-thread.h"
+#include "gdbsupport/gdb-safe-ctype.h"
/* The stack must be 16-byte aligned. */
#define SP_ALIGNMENT 16
#include "opcode/riscv-opc.h"
#undef DECLARE_INSN
-/* When this is set to non-zero debugging information about breakpoint
- kinds will be printed. */
+/* When this is true debugging information about breakpoint kinds will be
+ printed. */
-static unsigned int riscv_debug_breakpoints = 0;
+static bool riscv_debug_breakpoints = false;
-/* When this is set to non-zero debugging information about inferior calls
- will be printed. */
+/* Print a "riscv-breakpoints" debug statement. */
+
+#define riscv_breakpoints_debug_printf(fmt, ...) \
+ debug_prefixed_printf_cond (riscv_debug_breakpoints, \
+ "riscv-breakpoints", \
+ fmt, ##__VA_ARGS__)
+
+/* When this is true debugging information about inferior calls will be
+ printed. */
+
+static bool riscv_debug_infcall = false;
+
+/* Print a "riscv-infcall" debug statement. */
+
+#define riscv_infcall_debug_printf(fmt, ...) \
+ debug_prefixed_printf_cond (riscv_debug_infcall, "riscv-infcall", \
+ fmt, ##__VA_ARGS__)
+
+/* Print "riscv-infcall" start/end debug statements. */
+
+#define RISCV_INFCALL_SCOPED_DEBUG_START_END(fmt, ...) \
+ scoped_debug_start_end (riscv_debug_infcall, "riscv-infcall", \
+ fmt, ##__VA_ARGS__)
+
+/* When this is true debugging information about stack unwinding will be
+ printed. */
+
+static bool riscv_debug_unwinder = false;
+
+/* Print a "riscv-unwinder" debug statement. */
-static unsigned int riscv_debug_infcall = 0;
+#define riscv_unwinder_debug_printf(fmt, ...) \
+ debug_prefixed_printf_cond (riscv_debug_unwinder, "riscv-unwinder", \
+ fmt, ##__VA_ARGS__)
-/* When this is set to non-zero debugging information about stack unwinding
+/* When this is true debugging information about gdbarch initialisation
will be printed. */
-static unsigned int riscv_debug_unwinder = 0;
+static bool riscv_debug_gdbarch = false;
-/* When this is set to non-zero debugging information about gdbarch
- initialisation will be printed. */
+/* Print a "riscv-gdbarch" debug statement. */
-static unsigned int riscv_debug_gdbarch = 0;
+#define riscv_gdbarch_debug_printf(fmt, ...) \
+ debug_prefixed_printf_cond (riscv_debug_gdbarch, "riscv-gdbarch", \
+ fmt, ##__VA_ARGS__)
/* The names of the RISC-V target description features. */
const char *riscv_feature_name_csr = "org.gnu.gdb.riscv.csr";
/* Callback function for user_reg_add. */
static struct value *
-value_of_riscv_user_reg (struct frame_info *frame, const void *baton)
+value_of_riscv_user_reg (frame_info_ptr frame, const void *baton)
{
const int *reg_p = (const int *) baton;
return value_of_register (*reg_p, frame);
const char *bp = (unaligned_p || riscv_insn_length (buf[0]) == 2
? "C.EBREAK" : "EBREAK");
- gdb_printf (gdb_stdlog, "Using %s for breakpoint at %s ",
- bp, paddress (gdbarch, *pcptr));
+ std::string suffix;
if (unaligned_p)
- gdb_printf (gdb_stdlog, "(unaligned address)\n");
+ suffix = "(unaligned address)";
else
- gdb_printf (gdb_stdlog, "(instruction length %d)\n",
- riscv_insn_length (buf[0]));
+ suffix = string_printf ("(instruction length %d)",
+ riscv_insn_length (buf[0]));
+ riscv_breakpoints_debug_printf ("Using %s for breakpoint at %s %s",
+ bp, paddress (gdbarch, *pcptr),
+ suffix.c_str ());
}
if (unaligned_p || riscv_insn_length (buf[0]) == 2)
return 2;
static void
riscv_print_one_register_info (struct gdbarch *gdbarch,
struct ui_file *file,
- struct frame_info *frame,
+ frame_info_ptr frame,
int regnum)
{
const char *name = gdbarch_register_name (gdbarch, regnum);
enum tab_stops { value_column_1 = 15 };
gdb_puts (name, file);
- print_spaces (value_column_1 - strlen (name), file);
+ print_spaces (std::max<int> (1, value_column_1 - strlen (name)), file);
try
{
val = value_of_register (regnum, frame);
- regtype = value_type (val);
+ regtype = val->type ();
}
catch (const gdb_exception_error &ex)
{
return;
}
- print_raw_format = (value_entirely_available (val)
- && !value_optimized_out (val));
+ print_raw_format = (val->entirely_available ()
+ && !val->optimized_out ());
if (regtype->code () == TYPE_CODE_FLT
|| (regtype->code () == TYPE_CODE_UNION
&& regtype->field (2).type ()->code () == TYPE_CODE_FLT))
{
struct value_print_options opts;
- const gdb_byte *valaddr = value_contents_for_printing (val).data ();
+ const gdb_byte *valaddr = val->contents_for_printing ().data ();
enum bfd_endian byte_order = type_byte_order (regtype);
get_user_print_options (&opts);
- opts.deref_ref = 1;
+ opts.deref_ref = true;
common_val_print (val, file, 0, &opts, current_language);
/* Print the register in hex. */
get_formatted_print_options (&opts, 'x');
- opts.deref_ref = 1;
+ opts.deref_ref = true;
common_val_print (val, file, 0, &opts, current_language);
if (print_raw_format)
if (regtype->is_vector () == 0)
{
get_user_print_options (&opts);
- opts.deref_ref = 1;
+ opts.deref_ref = true;
gdb_printf (file, "\t");
common_val_print (val, file, 0, &opts, current_language);
}
/* Used by 'info registers' and 'info registers <groupname>'. */
- if (gdbarch_register_name (gdbarch, regnum) == NULL
- || gdbarch_register_name (gdbarch, regnum)[0] == '\0')
+ if (gdbarch_register_name (gdbarch, regnum)[0] == '\0')
return 0;
if (regnum > RISCV_LAST_REGNUM && regnum < gdbarch_num_regs (gdbarch))
static void
riscv_print_registers_info (struct gdbarch *gdbarch,
struct ui_file *file,
- struct frame_info *frame,
+ frame_info_ptr frame,
int regnum, int print_all)
{
if (regnum != -1)
{
/* Print one specified register. */
- if (gdbarch_register_name (gdbarch, regnum) == NULL
- || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
+ if (*(gdbarch_register_name (gdbarch, regnum)) == '\0')
error (_("Not a valid register for the current processor type"));
riscv_print_one_register_info (gdbarch, file, frame, regnum);
}
continue;
/* Registers with no name are not valid on this ISA. */
- if (gdbarch_register_name (gdbarch, regnum) == NULL
- || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
+ if (*(gdbarch_register_name (gdbarch, regnum)) == '\0')
continue;
/* Is the register in the group we're interested in? */
ADDW,
AUIPC,
LUI,
+ LI,
SD,
SW,
LD,
m_imm.s = EXTRACT_ITYPE_IMM (ival);
}
- /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
- void decode_ci_type_insn (enum opcode opcode, ULONGEST ival)
+ /* Helper for DECODE, decode 16-bit compressed I-type instruction. Some
+ of the CI instruction have a hard-coded rs1 register, while others
+ just use rd for both the source and destination. RS1_REGNUM, if
+ passed, is the value to place in rs1, otherwise rd is duplicated into
+ rs1. */
+ void decode_ci_type_insn (enum opcode opcode, ULONGEST ival,
+ gdb::optional<int> rs1_regnum = {})
{
m_opcode = opcode;
- m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
+ m_rd = decode_register_index (ival, OP_SH_CRS1S);
+ if (rs1_regnum.has_value ())
+ m_rs1 = *rs1_regnum;
+ else
+ m_rs1 = m_rd;
m_imm.s = EXTRACT_CITYPE_IMM (ival);
}
riscv_insn::fetch_instruction (struct gdbarch *gdbarch,
CORE_ADDR addr, int *len)
{
- enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch);
- gdb_byte buf[8];
+ gdb_byte buf[RISCV_MAX_INSN_LEN];
int instlen, status;
/* All insns are at least 16 bits. */
memory_error (TARGET_XFER_E_IO, addr + 2);
}
- return extract_unsigned_integer (buf, instlen, byte_order);
+ /* RISC-V Specification states instructions are always little endian */
+ return extract_unsigned_integer (buf, instlen, BFD_ENDIAN_LITTLE);
}
/* Fetch from target memory an instruction at PC and decode it. This can
m_rd = decode_register_index (ival, OP_SH_CRS1S);
m_imm.s = EXTRACT_CITYPE_LUI_IMM (ival);
}
+ else if (is_c_li_insn (ival))
+ decode_ci_type_insn (LI, ival);
/* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only,
and C_FSW is RV32 only. */
else if (xlen != 4 && is_c_sd_insn (ival))
decode_cl_type_insn (LD, ival);
else if (is_c_lw_insn (ival))
decode_cl_type_insn (LW, ival);
+ else if (is_c_ldsp_insn (ival))
+ decode_ci_type_insn (LD, ival, RISCV_SP_REGNUM);
+ else if (is_c_lwsp_insn (ival))
+ decode_ci_type_insn (LW, ival, RISCV_SP_REGNUM);
else
/* None of the other fields of INSN are valid in this case. */
m_opcode = OTHER;
}
else
{
- /* This must be a 6 or 8 byte instruction, we don't currently decode
- any of these, so just ignore it. */
- gdb_assert (m_length == 6 || m_length == 8);
+ /* 6 bytes or more. If the instruction is longer than 8 bytes, we don't
+ have full instruction bits in ival. At least, such long instructions
+ are not defined yet, so just ignore it. */
+ gdb_assert (m_length > 0 && m_length % 2 == 0);
m_opcode = OTHER;
}
}
+/* Return true if INSN represents an instruction something like:
+
+ ld fp,IMMEDIATE(sp)
+
+ That is, a load from stack-pointer plus some immediate offset, with the
+ result stored into the frame pointer. We also accept 'lw' as well as
+ 'ld'. */
+
+static bool
+is_insn_load_of_fp_from_sp (const struct riscv_insn &insn)
+{
+ return ((insn.opcode () == riscv_insn::LD
+ || insn.opcode () == riscv_insn::LW)
+ && insn.rd () == RISCV_FP_REGNUM
+ && insn.rs1 () == RISCV_SP_REGNUM);
+}
+
+/* Return true if INSN represents an instruction something like:
+
+ add sp,sp,IMMEDIATE
+
+ That is, an add of an immediate to the value in the stack pointer
+ register, with the result stored back to the stack pointer register. */
+
+static bool
+is_insn_addi_of_sp_to_sp (const struct riscv_insn &insn)
+{
+ return ((insn.opcode () == riscv_insn::ADDI
+ || insn.opcode () == riscv_insn::ADDIW)
+ && insn.rd () == RISCV_SP_REGNUM
+ && insn.rs1 () == RISCV_SP_REGNUM);
+}
+
+/* Is the instruction in code memory prior to address PC a load from stack
+ instruction? Return true if it is, otherwise, return false.
+
+ This is a best effort that is used as part of the function prologue
+ scanning logic. With compressed instructions and arbitrary control
+ flow in the inferior, we can never be certain what the instruction
+ prior to PC is.
+
+ This function first looks for a compressed instruction, then looks for
+ a 32-bit non-compressed instruction. */
+
+static bool
+previous_insn_is_load_fp_from_stack (struct gdbarch *gdbarch, CORE_ADDR pc)
+{
+ struct riscv_insn insn;
+ insn.decode (gdbarch, pc - 2);
+ gdb_assert (insn.length () > 0);
+
+ if (insn.length () != 2 || !is_insn_load_of_fp_from_sp (insn))
+ {
+ insn.decode (gdbarch, pc - 4);
+ gdb_assert (insn.length () > 0);
+
+ if (insn.length () != 4 || !is_insn_load_of_fp_from_sp (insn))
+ return false;
+ }
+
+ riscv_unwinder_debug_printf
+ ("previous instruction at %s (length %d) was 'ld'",
+ core_addr_to_string (pc - insn.length ()), insn.length ());
+ return true;
+}
+
+/* Is the instruction in code memory prior to address PC an add of an
+ immediate to the stack pointer, with the result being written back into
+ the stack pointer? Return true and set *PREV_PC to the address of the
+ previous instruction if we believe the previous instruction is such an
+ add, otherwise return false and *PREV_PC is undefined.
+
+ This is a best effort that is used as part of the function prologue
+ scanning logic. With compressed instructions and arbitrary control
+ flow in the inferior, we can never be certain what the instruction
+ prior to PC is.
+
+ This function first looks for a compressed instruction, then looks for
+ a 32-bit non-compressed instruction. */
+
+static bool
+previous_insn_is_add_imm_to_sp (struct gdbarch *gdbarch, CORE_ADDR pc,
+ CORE_ADDR *prev_pc)
+{
+ struct riscv_insn insn;
+ insn.decode (gdbarch, pc - 2);
+ gdb_assert (insn.length () > 0);
+
+ if (insn.length () != 2 || !is_insn_addi_of_sp_to_sp (insn))
+ {
+ insn.decode (gdbarch, pc - 4);
+ gdb_assert (insn.length () > 0);
+
+ if (insn.length () != 4 || !is_insn_addi_of_sp_to_sp (insn))
+ return false;
+ }
+
+ riscv_unwinder_debug_printf
+ ("previous instruction at %s (length %d) was 'add'",
+ core_addr_to_string (pc - insn.length ()), insn.length ());
+ *prev_pc = pc - insn.length ();
+ return true;
+}
+
+/* Try to spot when PC is located in an exit sequence for a particular
+ function. Detecting an exit sequence involves a limited amount of
+ scanning backwards through the disassembly, and so, when considering
+ compressed instructions, we can never be certain that we have
+ disassembled the preceding instructions correctly. On top of that, we
+ can't be certain that the inferior arrived at PC by passing through the
+ preceding instructions.
+
+ With all that said, we know that using prologue scanning to figure a
+ functions unwind information starts to fail when we consider returns
+ from an instruction -- we must pass through some instructions that
+ restore the previous state prior to the final return instruction, and
+ with state partially restored, our prologue derived unwind information
+ is no longer valid.
+
+ This function then, aims to spot instruction sequences like this:
+
+ ld fp, IMM_1(sp)
+ add sp, sp, IMM_2
+ ret
+
+ The first instruction restores the previous frame-pointer value, the
+ second restores the previous stack pointer value, and the final
+ instruction is the actual return.
+
+ We need to consider that some or all of these instructions might be
+ compressed.
+
+ This function makes the assumption that, when the inferior reaches the
+ 'ret' instruction the stack pointer will have been restored to its value
+ on entry to this function. This assumption will be true in most well
+ formed programs.
+
+ Return true if we detect that we are in such an instruction sequence,
+ that is PC points at one of the three instructions given above. In this
+ case, set *OFFSET to IMM_2 if PC points to either of the first
+ two instructions (the 'ld' or 'add'), otherwise set *OFFSET to 0.
+
+ Otherwise, this function returns false, and the contents of *OFFSET are
+ undefined. */
+
+static bool
+riscv_detect_end_of_function (struct gdbarch *gdbarch, CORE_ADDR pc,
+ int *offset)
+{
+ *offset = 0;
+
+ /* We only want to scan a maximum of 3 instructions. */
+ for (int i = 0; i < 3; ++i)
+ {
+ struct riscv_insn insn;
+ insn.decode (gdbarch, pc);
+ gdb_assert (insn.length () > 0);
+
+ if (is_insn_load_of_fp_from_sp (insn))
+ {
+ riscv_unwinder_debug_printf ("found 'ld' instruction at %s",
+ core_addr_to_string (pc));
+ if (i > 0)
+ return false;
+ pc += insn.length ();
+ }
+ else if (is_insn_addi_of_sp_to_sp (insn))
+ {
+ riscv_unwinder_debug_printf ("found 'add' instruction at %s",
+ core_addr_to_string (pc));
+ if (i > 1)
+ return false;
+ if (i == 0)
+ {
+ if (!previous_insn_is_load_fp_from_stack (gdbarch, pc))
+ return false;
+
+ i = 1;
+ }
+ *offset = insn.imm_signed ();
+ pc += insn.length ();
+ }
+ else if (insn.opcode () == riscv_insn::JALR
+ && insn.rs1 () == RISCV_RA_REGNUM
+ && insn.rs2 () == RISCV_ZERO_REGNUM)
+ {
+ riscv_unwinder_debug_printf ("found 'ret' instruction at %s",
+ core_addr_to_string (pc));
+ gdb_assert (i != 1);
+ if (i == 0)
+ {
+ CORE_ADDR prev_pc;
+ if (!previous_insn_is_add_imm_to_sp (gdbarch, pc, &prev_pc))
+ return false;
+ if (!previous_insn_is_load_fp_from_stack (gdbarch, prev_pc))
+ return false;
+ i = 2;
+ }
+
+ pc += insn.length ();
+ }
+ else
+ return false;
+ }
+
+ return true;
+}
+
/* The prologue scanner. This is currently only used for skipping the
prologue of a function when the DWARF information is not sufficient.
However, it is written with filling of the frame cache in mind, which
struct riscv_unwind_cache *cache)
{
CORE_ADDR cur_pc, next_pc, after_prologue_pc;
+ CORE_ADDR original_end_pc = end_pc;
CORE_ADDR end_prologue_addr = 0;
/* Find an upper limit on the function prologue using the debug
regs[regno] = pv_register (regno, 0);
pv_area stack (RISCV_SP_REGNUM, gdbarch_addr_bit (gdbarch));
- if (riscv_debug_unwinder)
- gdb_printf
- (gdb_stdlog,
- "Prologue scan for function starting at %s (limit %s)\n",
- core_addr_to_string (start_pc),
- core_addr_to_string (end_pc));
+ riscv_unwinder_debug_printf ("function starting at %s (limit %s)",
+ core_addr_to_string (start_pc),
+ core_addr_to_string (end_pc));
for (next_pc = cur_pc = start_pc; cur_pc < end_pc; cur_pc = next_pc)
{
next_pc = cur_pc + insn.length ();
/* Look for common stack adjustment insns. */
- if ((insn.opcode () == riscv_insn::ADDI
- || insn.opcode () == riscv_insn::ADDIW)
- && insn.rd () == RISCV_SP_REGNUM
- && insn.rs1 () == RISCV_SP_REGNUM)
+ if (is_insn_addi_of_sp_to_sp (insn))
{
/* Handle: addi sp, sp, -i
or: addiw sp, sp, -i */
gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
regs[insn.rd ()] = pv_constant (cur_pc + insn.imm_signed ());
}
- else if (insn.opcode () == riscv_insn::LUI)
+ else if (insn.opcode () == riscv_insn::LUI
+ || insn.opcode () == riscv_insn::LI)
{
/* Handle: lui REG, n
- Where REG is not gp register. */
+ or: li REG, n */
gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
regs[insn.rd ()] = pv_constant (insn.imm_signed ());
}
if (end_prologue_addr == 0)
end_prologue_addr = cur_pc;
- if (riscv_debug_unwinder)
- gdb_printf (gdb_stdlog, "End of prologue at %s\n",
- core_addr_to_string (end_prologue_addr));
+ riscv_unwinder_debug_printf ("end of prologue at %s",
+ core_addr_to_string (end_prologue_addr));
if (cache != NULL)
{
cache->frame_base_offset = -regs[RISCV_SP_REGNUM].k;
}
+ /* Check to see if we are located near to a return instruction in
+ this function. If we are then the one or both of the stack
+ pointer and frame pointer may have been restored to their previous
+ value. If we can spot this situation then we can adjust which
+ register and offset we use for the frame base. */
+ if (cache->frame_base_reg != RISCV_SP_REGNUM
+ || cache->frame_base_offset != 0)
+ {
+ int sp_offset;
+
+ if (riscv_detect_end_of_function (gdbarch, original_end_pc,
+ &sp_offset))
+ {
+ riscv_unwinder_debug_printf
+ ("in function epilogue at %s, stack offset is %d",
+ core_addr_to_string (original_end_pc), sp_offset);
+ cache->frame_base_reg= RISCV_SP_REGNUM;
+ cache->frame_base_offset = sp_offset;
+ }
+ }
+
/* Assign offset from old SP to all saved registers. As we don't
have the previous value for the frame base register at this
point, we store the offset as the address in the trad_frame, and
CORE_ADDR offset;
if (stack.find_reg (gdbarch, i, &offset))
{
- if (riscv_debug_unwinder)
- {
- /* Display OFFSET as a signed value, the offsets are from
- the frame base address to the registers location on
- the stack, with a descending stack this means the
- offsets are always negative. */
- gdb_printf (gdb_stdlog,
- "Register $%s at stack offset %s\n",
- gdbarch_register_name (gdbarch, i),
- plongest ((LONGEST) offset));
- }
+ /* Display OFFSET as a signed value, the offsets are from the
+ frame base address to the registers location on the stack,
+ with a descending stack this means the offsets are always
+ negative. */
+ riscv_unwinder_debug_printf ("register $%s at stack offset %s",
+ gdbarch_register_name (gdbarch, i),
+ plongest ((LONGEST) offset));
cache->regs[i].set_addr (offset);
}
}
there will be no need to write to memory later. */
int status = target_write_memory (*bp_addr, nop_insn, sizeof (nop_insn));
- if (riscv_debug_breakpoints || riscv_debug_infcall)
- gdb_printf (gdb_stdlog,
- "Writing %s-byte nop instruction to %s: %s\n",
- plongest (sizeof (nop_insn)),
- paddress (gdbarch, *bp_addr),
- (status == 0 ? "success" : "failed"));
+ riscv_infcall_debug_printf ("writing %s-byte nop instruction to %s: %s",
+ plongest (sizeof (nop_insn)),
+ paddress (gdbarch, *bp_addr),
+ (status == 0 ? "success" : "failed"));
return sp;
}
riscv_call_arg_scalar_int (struct riscv_arg_info *ainfo,
struct riscv_call_info *cinfo)
{
- if (ainfo->length > (2 * cinfo->xlen))
+ if (TYPE_HAS_DYNAMIC_LENGTH (ainfo->type)
+ || ainfo->length > (2 * cinfo->xlen))
{
/* Argument is going to be passed by reference. */
ainfo->argloc[0].loc_type
break;
case TYPE_CODE_STRUCT:
- riscv_call_arg_struct (ainfo, cinfo);
- break;
+ if (!TYPE_HAS_DYNAMIC_LENGTH (ainfo->type))
+ {
+ riscv_call_arg_struct (ainfo, cinfo);
+ break;
+ }
+ /* FALLTHROUGH */
default:
riscv_call_arg_scalar_int (ainfo, cinfo);
CORE_ADDR osp = sp;
- struct type *ftype = check_typedef (value_type (function));
+ struct type *ftype = check_typedef (function->type ());
if (ftype->code () == TYPE_CODE_PTR)
ftype = check_typedef (ftype->target_type ());
struct riscv_arg_info *info = &arg_info[i];
arg_value = args[i];
- arg_type = check_typedef (value_type (arg_value));
+ arg_type = check_typedef (arg_value->type ());
riscv_arg_location (gdbarch, info, &call_info, arg_type,
ftype->has_varargs () && i >= ftype->num_fields ());
if (info->type != arg_type)
arg_value = value_cast (info->type, arg_value);
- info->contents = value_contents (arg_value).data ();
+ info->contents = arg_value->contents ().data ();
}
/* Adjust the stack pointer and align it. */
sp = sp_refs = align_down (sp - call_info.memory.ref_offset, SP_ALIGNMENT);
sp = sp_args = align_down (sp - call_info.memory.arg_offset, SP_ALIGNMENT);
- if (riscv_debug_infcall > 0)
+ if (riscv_debug_infcall)
{
- gdb_printf (gdb_stdlog, "dummy call args:\n");
- gdb_printf (gdb_stdlog, ": floating point ABI %s in use\n",
- (riscv_has_fp_abi (gdbarch) ? "is" : "is not"));
- gdb_printf (gdb_stdlog, ": xlen: %d\n: flen: %d\n",
- call_info.xlen, call_info.flen);
+ RISCV_INFCALL_SCOPED_DEBUG_START_END ("dummy call args");
+ riscv_infcall_debug_printf ("floating point ABI %s in use",
+ (riscv_has_fp_abi (gdbarch)
+ ? "is" : "is not"));
+ riscv_infcall_debug_printf ("xlen: %d", call_info.xlen);
+ riscv_infcall_debug_printf ("flen: %d", call_info.flen);
if (return_method == return_method_struct)
- gdb_printf (gdb_stdlog,
- "[*] struct return pointer in register $A0\n");
+ riscv_infcall_debug_printf
+ ("[**] struct return pointer in register $A0");
for (i = 0; i < nargs; ++i)
{
struct riscv_arg_info *info = &arg_info [i];
+ string_file tmp;
- gdb_printf (gdb_stdlog, "[%2d] ", i);
- riscv_print_arg_location (gdb_stdlog, gdbarch, info, sp_refs, sp_args);
- gdb_printf (gdb_stdlog, "\n");
+ riscv_print_arg_location (&tmp, gdbarch, info, sp_refs, sp_args);
+ riscv_infcall_debug_printf ("[%2d] %s", i, tmp.string ().c_str ());
}
if (call_info.memory.arg_offset > 0
|| call_info.memory.ref_offset > 0)
{
- gdb_printf (gdb_stdlog, " Original sp: %s\n",
- core_addr_to_string (osp));
- gdb_printf (gdb_stdlog, "Stack required (for args): 0x%x\n",
- call_info.memory.arg_offset);
- gdb_printf (gdb_stdlog, "Stack required (for refs): 0x%x\n",
- call_info.memory.ref_offset);
- gdb_printf (gdb_stdlog, " Stack allocated: %s\n",
- core_addr_to_string_nz (osp - sp));
+ riscv_infcall_debug_printf (" Original sp: %s",
+ core_addr_to_string (osp));
+ riscv_infcall_debug_printf ("Stack required (for args): 0x%x",
+ call_info.memory.arg_offset);
+ riscv_infcall_debug_printf ("Stack required (for refs): 0x%x",
+ call_info.memory.ref_offset);
+ riscv_infcall_debug_printf (" Stack allocated: %s",
+ core_addr_to_string_nz (osp - sp));
}
}
/* Set the dummy return value to bp_addr.
A dummy breakpoint will be setup to execute the call. */
- if (riscv_debug_infcall > 0)
- gdb_printf (gdb_stdlog, ": writing $ra = %s\n",
- core_addr_to_string (bp_addr));
+ riscv_infcall_debug_printf ("writing $ra = %s",
+ core_addr_to_string (bp_addr));
regcache_cooked_write_unsigned (regcache, RISCV_RA_REGNUM, bp_addr);
/* Finally, update the stack pointer. */
- if (riscv_debug_infcall > 0)
- gdb_printf (gdb_stdlog, ": writing $sp = %s\n",
- core_addr_to_string (sp));
+ riscv_infcall_debug_printf ("writing $sp = %s", core_addr_to_string (sp));
regcache_cooked_write_unsigned (regcache, RISCV_SP_REGNUM, sp);
return sp;
struct value *function,
struct type *type,
struct regcache *regcache,
- gdb_byte *readbuf,
+ struct value **read_value,
const gdb_byte *writebuf)
{
struct riscv_call_info call_info (gdbarch);
arg_type = check_typedef (type);
riscv_arg_location (gdbarch, &info, &call_info, arg_type, false);
- if (riscv_debug_infcall > 0)
+ if (riscv_debug_infcall)
{
- gdb_printf (gdb_stdlog, "riscv return value:\n");
- gdb_printf (gdb_stdlog, "[R] ");
- riscv_print_arg_location (gdb_stdlog, gdbarch, &info, 0, 0);
- gdb_printf (gdb_stdlog, "\n");
+ string_file tmp;
+ riscv_print_arg_location (&tmp, gdbarch, &info, 0, 0);
+ riscv_infcall_debug_printf ("[R] %s", tmp.string ().c_str ());
}
- if (readbuf != nullptr || writebuf != nullptr)
+ if (read_value != nullptr || writebuf != nullptr)
{
- unsigned int arg_len;
- struct value *abi_val;
- gdb_byte *old_readbuf = nullptr;
- int regnum;
-
- /* We only do one thing at a time. */
- gdb_assert (readbuf == nullptr || writebuf == nullptr);
-
- /* In some cases the argument is not returned as the declared type,
- and we need to cast to or from the ABI type in order to
- correctly access the argument. When writing to the machine we
- do the cast here, when reading from the machine the cast occurs
- later, after extracting the value. As the ABI type can be
- larger than the declared type, then the read or write buffers
- passed in might be too small. Here we ensure that we are using
- buffers of sufficient size. */
- if (writebuf != nullptr)
+ unsigned int arg_len;
+ struct value *abi_val;
+ gdb_byte *readbuf = nullptr;
+ int regnum;
+
+ /* We only do one thing at a time. */
+ gdb_assert (read_value == nullptr || writebuf == nullptr);
+
+ /* In some cases the argument is not returned as the declared type,
+ and we need to cast to or from the ABI type in order to
+ correctly access the argument. When writing to the machine we
+ do the cast here, when reading from the machine the cast occurs
+ later, after extracting the value. As the ABI type can be
+ larger than the declared type, then the read or write buffers
+ passed in might be too small. Here we ensure that we are using
+ buffers of sufficient size. */
+ if (writebuf != nullptr)
+ {
+ struct value *arg_val;
+
+ if (is_fixed_point_type (arg_type))
+ {
+ /* Convert the argument to the type used to pass
+ the return value, but being careful to preserve
+ the fact that the value needs to be returned
+ unscaled. */
+ gdb_mpz unscaled;
+
+ unscaled.read (gdb::make_array_view (writebuf,
+ arg_type->length ()),
+ type_byte_order (arg_type),
+ arg_type->is_unsigned ());
+ abi_val = value::allocate (info.type);
+ unscaled.write (abi_val->contents_raw (),
+ type_byte_order (info.type),
+ info.type->is_unsigned ());
+ }
+ else
+ {
+ arg_val = value_from_contents (arg_type, writebuf);
+ abi_val = value_cast (info.type, arg_val);
+ }
+ writebuf = abi_val->contents_raw ().data ();
+ }
+ else
+ {
+ abi_val = value::allocate (info.type);
+ readbuf = abi_val->contents_raw ().data ();
+ }
+ arg_len = info.type->length ();
+
+ switch (info.argloc[0].loc_type)
+ {
+ /* Return value in register(s). */
+ case riscv_arg_info::location::in_reg:
{
- struct value *arg_val;
+ regnum = info.argloc[0].loc_data.regno;
+ gdb_assert (info.argloc[0].c_length <= arg_len);
+ gdb_assert (info.argloc[0].c_length
+ <= register_size (gdbarch, regnum));
- if (is_fixed_point_type (arg_type))
+ if (readbuf)
{
- /* Convert the argument to the type used to pass
- the return value, but being careful to preserve
- the fact that the value needs to be returned
- unscaled. */
- gdb_mpz unscaled;
-
- unscaled.read (gdb::make_array_view (writebuf,
- arg_type->length ()),
- type_byte_order (arg_type),
- arg_type->is_unsigned ());
- abi_val = allocate_value (info.type);
- unscaled.write (value_contents_raw (abi_val),
- type_byte_order (info.type),
- info.type->is_unsigned ());
+ gdb_byte *ptr = readbuf + info.argloc[0].c_offset;
+ regcache->cooked_read_part (regnum, 0,
+ info.argloc[0].c_length,
+ ptr);
}
- else
+
+ if (writebuf)
{
- arg_val = value_from_contents (arg_type, writebuf);
- abi_val = value_cast (info.type, arg_val);
+ const gdb_byte *ptr = writebuf + info.argloc[0].c_offset;
+ riscv_regcache_cooked_write (regnum, ptr,
+ info.argloc[0].c_length,
+ regcache, call_info.flen);
}
- writebuf = value_contents_raw (abi_val).data ();
- }
- else
- {
- abi_val = allocate_value (info.type);
- old_readbuf = readbuf;
- readbuf = value_contents_raw (abi_val).data ();
- }
- arg_len = info.type->length ();
-
- switch (info.argloc[0].loc_type)
- {
- /* Return value in register(s). */
- case riscv_arg_info::location::in_reg:
- {
- regnum = info.argloc[0].loc_data.regno;
- gdb_assert (info.argloc[0].c_length <= arg_len);
- gdb_assert (info.argloc[0].c_length
- <= register_size (gdbarch, regnum));
-
- if (readbuf)
- {
- gdb_byte *ptr = readbuf + info.argloc[0].c_offset;
- regcache->cooked_read_part (regnum, 0,
- info.argloc[0].c_length,
- ptr);
- }
- if (writebuf)
- {
- const gdb_byte *ptr = writebuf + info.argloc[0].c_offset;
- riscv_regcache_cooked_write (regnum, ptr,
- info.argloc[0].c_length,
- regcache, call_info.flen);
- }
-
- /* A return value in register can have a second part in a
- second register. */
- if (info.argloc[1].c_length > 0)
- {
- switch (info.argloc[1].loc_type)
- {
- case riscv_arg_info::location::in_reg:
- regnum = info.argloc[1].loc_data.regno;
-
- gdb_assert ((info.argloc[0].c_length
- + info.argloc[1].c_length) <= arg_len);
- gdb_assert (info.argloc[1].c_length
- <= register_size (gdbarch, regnum));
-
- if (readbuf)
- {
- readbuf += info.argloc[1].c_offset;
- regcache->cooked_read_part (regnum, 0,
- info.argloc[1].c_length,
- readbuf);
- }
-
- if (writebuf)
- {
- const gdb_byte *ptr
- = writebuf + info.argloc[1].c_offset;
- riscv_regcache_cooked_write
- (regnum, ptr, info.argloc[1].c_length,
- regcache, call_info.flen);
- }
- break;
-
- case riscv_arg_info::location::by_ref:
- case riscv_arg_info::location::on_stack:
- default:
- error (_("invalid argument location"));
- break;
- }
- }
- }
- break;
-
- /* Return value by reference will have its address in A0. */
- case riscv_arg_info::location::by_ref:
- {
- ULONGEST addr;
-
- regcache_cooked_read_unsigned (regcache, RISCV_A0_REGNUM,
- &addr);
- if (readbuf != nullptr)
- read_memory (addr, readbuf, info.length);
- if (writebuf != nullptr)
- write_memory (addr, writebuf, info.length);
- }
- break;
-
- case riscv_arg_info::location::on_stack:
- default:
- error (_("invalid argument location"));
- break;
+ /* A return value in register can have a second part in a
+ second register. */
+ if (info.argloc[1].c_length > 0)
+ {
+ switch (info.argloc[1].loc_type)
+ {
+ case riscv_arg_info::location::in_reg:
+ regnum = info.argloc[1].loc_data.regno;
+
+ gdb_assert ((info.argloc[0].c_length
+ + info.argloc[1].c_length) <= arg_len);
+ gdb_assert (info.argloc[1].c_length
+ <= register_size (gdbarch, regnum));
+
+ if (readbuf)
+ {
+ readbuf += info.argloc[1].c_offset;
+ regcache->cooked_read_part (regnum, 0,
+ info.argloc[1].c_length,
+ readbuf);
+ }
+
+ if (writebuf)
+ {
+ const gdb_byte *ptr
+ = writebuf + info.argloc[1].c_offset;
+ riscv_regcache_cooked_write
+ (regnum, ptr, info.argloc[1].c_length,
+ regcache, call_info.flen);
+ }
+ break;
+
+ case riscv_arg_info::location::by_ref:
+ case riscv_arg_info::location::on_stack:
+ default:
+ error (_("invalid argument location"));
+ break;
+ }
+ }
}
+ break;
- /* This completes the cast from abi type back to the declared type
- in the case that we are reading from the machine. See the
- comment at the head of this block for more details. */
- if (readbuf != nullptr)
+ /* Return value by reference will have its address in A0. */
+ case riscv_arg_info::location::by_ref:
{
- struct value *arg_val;
+ ULONGEST addr;
- if (is_fixed_point_type (arg_type))
+ regcache_cooked_read_unsigned (regcache, RISCV_A0_REGNUM,
+ &addr);
+ if (read_value != nullptr)
{
- /* Convert abi_val to the actual return type, but
- being careful to preserve the fact that abi_val
- is unscaled. */
- gdb_mpz unscaled;
-
- unscaled.read (value_contents (abi_val),
- type_byte_order (info.type),
- info.type->is_unsigned ());
- arg_val = allocate_value (arg_type);
- unscaled.write (value_contents_raw (arg_val),
- type_byte_order (arg_type),
- arg_type->is_unsigned ());
+ abi_val = value_at_non_lval (type, addr);
+ /* Also reset the expected type, so that the cast
+ later on is a no-op. If the cast is not a no-op,
+ and if the return type is variably-sized, then the
+ type of ABI_VAL will differ from ARG_TYPE due to
+ dynamic type resolution, and so will most likely
+ fail. */
+ arg_type = abi_val->type ();
}
- else
- arg_val = value_cast (arg_type, abi_val);
- memcpy (old_readbuf, value_contents_raw (arg_val).data (),
- arg_type->length ());
+ if (writebuf != nullptr)
+ write_memory (addr, writebuf, info.length);
}
+ break;
+
+ case riscv_arg_info::location::on_stack:
+ default:
+ error (_("invalid argument location"));
+ break;
+ }
+
+ /* This completes the cast from abi type back to the declared type
+ in the case that we are reading from the machine. See the
+ comment at the head of this block for more details. */
+ if (read_value != nullptr)
+ {
+ if (is_fixed_point_type (arg_type))
+ {
+ /* Convert abi_val to the actual return type, but
+ being careful to preserve the fact that abi_val
+ is unscaled. */
+ gdb_mpz unscaled;
+
+ unscaled.read (abi_val->contents (),
+ type_byte_order (info.type),
+ info.type->is_unsigned ());
+ *read_value = value::allocate (arg_type);
+ unscaled.write ((*read_value)->contents_raw (),
+ type_byte_order (arg_type),
+ arg_type->is_unsigned ());
+ }
+ else
+ *read_value = value_cast (arg_type, abi_val);
+ }
}
switch (info.argloc[0].loc_type)
unwinder. */
static struct riscv_unwind_cache *
-riscv_frame_cache (struct frame_info *this_frame, void **this_cache)
+riscv_frame_cache (frame_info_ptr this_frame, void **this_cache)
{
CORE_ADDR pc, start_addr;
struct riscv_unwind_cache *cache;
cache->frame_base
= (get_frame_register_unsigned (this_frame, cache->frame_base_reg)
+ cache->frame_base_offset);
- if (riscv_debug_unwinder)
- gdb_printf (gdb_stdlog, "Frame base is %s ($%s + 0x%x)\n",
- core_addr_to_string (cache->frame_base),
- gdbarch_register_name (gdbarch,
- cache->frame_base_reg),
- cache->frame_base_offset);
+ riscv_unwinder_debug_printf ("frame base is %s ($%s + 0x%x)",
+ core_addr_to_string (cache->frame_base),
+ gdbarch_register_name (gdbarch,
+ cache->frame_base_reg),
+ cache->frame_base_offset);
/* The prologue scanner sets the address of registers stored to the stack
as the offset of that register from the frame base. The prologue
/* Implement the this_id callback for RiscV frame unwinder. */
static void
-riscv_frame_this_id (struct frame_info *this_frame,
+riscv_frame_this_id (frame_info_ptr this_frame,
void **prologue_cache,
struct frame_id *this_id)
{
/* Implement the prev_register callback for RiscV frame unwinder. */
static struct value *
-riscv_frame_prev_register (struct frame_info *this_frame,
+riscv_frame_prev_register (frame_info_ptr this_frame,
void **prologue_cache,
int regnum)
{
else if (eclass == ELFCLASS64)
features.xlen = 8;
else
- internal_error (__FILE__, __LINE__,
- _("unknown ELF header class %d"), eclass);
+ internal_error (_("unknown ELF header class %d"), eclass);
if (e_flags & EF_RISCV_FLOAT_ABI_DOUBLE)
features.flen = 8;
static int
riscv_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
{
- if (reg < RISCV_DWARF_REGNUM_X31)
+ if (reg <= RISCV_DWARF_REGNUM_X31)
return RISCV_ZERO_REGNUM + (reg - RISCV_DWARF_REGNUM_X0);
- else if (reg < RISCV_DWARF_REGNUM_F31)
+ else if (reg <= RISCV_DWARF_REGNUM_F31)
return RISCV_FIRST_FP_REGNUM + (reg - RISCV_DWARF_REGNUM_F0);
else if (reg >= RISCV_DWARF_FIRST_CSR && reg <= RISCV_DWARF_LAST_CSR)
return "riscv(32|64)?";
}
+/* Implementation of `gdbarch_stap_is_single_operand', as defined in
+ gdbarch.h. */
+
+static int
+riscv_stap_is_single_operand (struct gdbarch *gdbarch, const char *s)
+{
+ return (ISDIGIT (*s) /* Literal number. */
+ || *s == '(' /* Register indirection. */
+ || ISALPHA (*s)); /* Register value. */
+}
+
+/* String that appears before a register name in a SystemTap register
+ indirect expression. */
+
+static const char *const stap_register_indirection_prefixes[] =
+{
+ "(", nullptr
+};
+
+/* String that appears after a register name in a SystemTap register
+ indirect expression. */
+
+static const char *const stap_register_indirection_suffixes[] =
+{
+ ")", nullptr
+};
+
/* Initialize the current architecture based on INFO. If possible,
re-use an architecture from ARCHES, which is a list of
architectures already created during this debugging session.
riscv_gdbarch_init (struct gdbarch_info info,
struct gdbarch_list *arches)
{
- struct gdbarch *gdbarch;
struct riscv_gdbarch_features features;
const struct target_desc *tdesc = info.target_desc;
tdesc = riscv_find_default_target_description (info);
gdb_assert (tdesc != nullptr);
- if (riscv_debug_gdbarch)
- gdb_printf (gdb_stdlog, "Have got a target description\n");
+ riscv_gdbarch_debug_printf ("have got a target description");
tdesc_arch_data_up tdesc_data = tdesc_data_alloc ();
std::vector<riscv_pending_register_alias> pending_aliases;
&pending_aliases, &features));
if (!valid_p)
{
- if (riscv_debug_gdbarch)
- gdb_printf (gdb_stdlog, "Target description is not valid\n");
+ riscv_gdbarch_debug_printf ("target description is not valid");
return NULL;
}
return arches->gdbarch;
/* None found, so create a new architecture from the information provided. */
- riscv_gdbarch_tdep *tdep = new riscv_gdbarch_tdep;
- gdbarch = gdbarch_alloc (&info, tdep);
+ gdbarch *gdbarch
+ = gdbarch_alloc (&info, gdbarch_tdep_up (new riscv_gdbarch_tdep));
+ riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
+
tdep->isa_features = features;
tdep->abi_features = abi_features;
set_gdbarch_type_align (gdbarch, riscv_type_align);
/* Information about the target architecture. */
- set_gdbarch_return_value (gdbarch, riscv_return_value);
+ set_gdbarch_return_value_as_value (gdbarch, riscv_return_value);
set_gdbarch_breakpoint_kind_from_pc (gdbarch, riscv_breakpoint_kind_from_pc);
set_gdbarch_sw_breakpoint_from_kind (gdbarch, riscv_sw_breakpoint_from_kind);
set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
disassembler_options_riscv ());
set_gdbarch_disassembler_options (gdbarch, &riscv_disassembler_options);
+ /* SystemTap Support. */
+ set_gdbarch_stap_is_single_operand (gdbarch, riscv_stap_is_single_operand);
+ set_gdbarch_stap_register_indirection_prefixes
+ (gdbarch, stap_register_indirection_prefixes);
+ set_gdbarch_stap_register_indirection_suffixes
+ (gdbarch, stap_register_indirection_suffixes);
+
/* Hook in OS ABI-specific overrides, if they have been registered. */
gdbarch_init_osabi (info, gdbarch);
&setdebugriscvcmdlist, &showdebugriscvcmdlist,
&setdebuglist, &showdebuglist);
- add_setshow_zuinteger_cmd ("breakpoints", class_maintenance,
- &riscv_debug_breakpoints, _("\
+ add_setshow_boolean_cmd ("breakpoints", class_maintenance,
+ &riscv_debug_breakpoints, _("\
Set riscv breakpoint debugging."), _("\
Show riscv breakpoint debugging."), _("\
When non-zero, print debugging information for the riscv specific parts\n\
of the breakpoint mechanism."),
- NULL,
- show_riscv_debug_variable,
- &setdebugriscvcmdlist, &showdebugriscvcmdlist);
+ nullptr,
+ show_riscv_debug_variable,
+ &setdebugriscvcmdlist, &showdebugriscvcmdlist);
- add_setshow_zuinteger_cmd ("infcall", class_maintenance,
- &riscv_debug_infcall, _("\
+ add_setshow_boolean_cmd ("infcall", class_maintenance,
+ &riscv_debug_infcall, _("\
Set riscv inferior call debugging."), _("\
Show riscv inferior call debugging."), _("\
When non-zero, print debugging information for the riscv specific parts\n\
of the inferior call mechanism."),
- NULL,
- show_riscv_debug_variable,
- &setdebugriscvcmdlist, &showdebugriscvcmdlist);
+ nullptr,
+ show_riscv_debug_variable,
+ &setdebugriscvcmdlist, &showdebugriscvcmdlist);
- add_setshow_zuinteger_cmd ("unwinder", class_maintenance,
- &riscv_debug_unwinder, _("\
+ add_setshow_boolean_cmd ("unwinder", class_maintenance,
+ &riscv_debug_unwinder, _("\
Set riscv stack unwinding debugging."), _("\
Show riscv stack unwinding debugging."), _("\
-When non-zero, print debugging information for the riscv specific parts\n\
+When on, print debugging information for the riscv specific parts\n\
of the stack unwinding mechanism."),
- NULL,
- show_riscv_debug_variable,
- &setdebugriscvcmdlist, &showdebugriscvcmdlist);
+ nullptr,
+ show_riscv_debug_variable,
+ &setdebugriscvcmdlist, &showdebugriscvcmdlist);
- add_setshow_zuinteger_cmd ("gdbarch", class_maintenance,
- &riscv_debug_gdbarch, _("\
+ add_setshow_boolean_cmd ("gdbarch", class_maintenance,
+ &riscv_debug_gdbarch, _("\
Set riscv gdbarch initialisation debugging."), _("\
Show riscv gdbarch initialisation debugging."), _("\
When non-zero, print debugging information for the riscv gdbarch\n\
initialisation process."),
- NULL,
- show_riscv_debug_variable,
- &setdebugriscvcmdlist, &showdebugriscvcmdlist);
+ nullptr,
+ show_riscv_debug_variable,
+ &setdebugriscvcmdlist, &showdebugriscvcmdlist);
/* Add root prefix command for all "set riscv" and "show riscv" commands. */
add_setshow_prefix_cmd ("riscv", no_class,
projects / binutils-gdb.git / blobdiff