/* Target-dependent code for the RISC-V architecture, for GDB.
- Copyright (C) 2018-2020 Free Software Foundation, Inc.
+ Copyright (C) 2018-2023 Free Software Foundation, Inc.
This file is part of GDB.
#include "regcache.h"
#include "osabi.h"
#include "riscv-tdep.h"
-#include "block.h"
#include "reggroups.h"
#include "opcode/riscv.h"
#include "elf/riscv.h"
#include "prologue-value.h"
#include "arch/riscv.h"
#include "riscv-ravenscar-thread.h"
+#include "gdbsupport/gdb-safe-ctype.h"
/* The stack must be 16-byte aligned. */
#define SP_ALIGNMENT 16
#include "opcode/riscv-opc.h"
#undef DECLARE_INSN
+/* When this is true debugging information about breakpoint kinds will be
+ printed. */
+
+static bool riscv_debug_breakpoints = false;
+
+/* Print a "riscv-breakpoints" debug statement. */
+
+#define riscv_breakpoints_debug_printf(fmt, ...) \
+ debug_prefixed_printf_cond (riscv_debug_breakpoints, \
+ "riscv-breakpoints", \
+ fmt, ##__VA_ARGS__)
+
+/* When this is true debugging information about inferior calls will be
+ printed. */
+
+static bool riscv_debug_infcall = false;
+
+/* Print a "riscv-infcall" debug statement. */
+
+#define riscv_infcall_debug_printf(fmt, ...) \
+ debug_prefixed_printf_cond (riscv_debug_infcall, "riscv-infcall", \
+ fmt, ##__VA_ARGS__)
+
+/* Print "riscv-infcall" start/end debug statements. */
+
+#define RISCV_INFCALL_SCOPED_DEBUG_START_END(fmt, ...) \
+ scoped_debug_start_end (riscv_debug_infcall, "riscv-infcall", \
+ fmt, ##__VA_ARGS__)
+
+/* When this is true debugging information about stack unwinding will be
+ printed. */
+
+static bool riscv_debug_unwinder = false;
+
+/* Print a "riscv-unwinder" debug statement. */
+
+#define riscv_unwinder_debug_printf(fmt, ...) \
+ debug_prefixed_printf_cond (riscv_debug_unwinder, "riscv-unwinder", \
+ fmt, ##__VA_ARGS__)
+
+/* When this is true debugging information about gdbarch initialisation
+ will be printed. */
+
+static bool riscv_debug_gdbarch = false;
+
+/* Print a "riscv-gdbarch" debug statement. */
+
+#define riscv_gdbarch_debug_printf(fmt, ...) \
+ debug_prefixed_printf_cond (riscv_debug_gdbarch, "riscv-gdbarch", \
+ fmt, ##__VA_ARGS__)
+
+/* The names of the RISC-V target description features. */
+const char *riscv_feature_name_csr = "org.gnu.gdb.riscv.csr";
+static const char *riscv_feature_name_cpu = "org.gnu.gdb.riscv.cpu";
+static const char *riscv_feature_name_fpu = "org.gnu.gdb.riscv.fpu";
+static const char *riscv_feature_name_virtual = "org.gnu.gdb.riscv.virtual";
+static const char *riscv_feature_name_vector = "org.gnu.gdb.riscv.vector";
+
+/* The current set of options to be passed to the disassembler. */
+static char *riscv_disassembler_options;
+
/* Cached information about a frame. */
struct riscv_unwind_cache
int frame_base_offset;
/* Information about previous register values. */
- struct trad_frame_saved_reg *regs;
+ trad_frame_saved_reg *regs;
/* The id for this frame. */
struct frame_id this_id;
/* RISC-V specific register group for CSRs. */
-static reggroup *csr_reggroup = NULL;
+static const reggroup *csr_reggroup = nullptr;
/* Callback function for user_reg_add. */
static struct value *
-value_of_riscv_user_reg (struct frame_info *frame, const void *baton)
+value_of_riscv_user_reg (frame_info_ptr frame, const void *baton)
{
const int *reg_p = (const int *) baton;
return value_of_register (*reg_p, frame);
const void *m_baton;
};
-/* Registers in the RISCV_REGISTER_FEATURE lists below are either optional,
- or required. For example the $pc register is always going to be a
- required register, you can't do much debugging without that. In
- contrast, most of the CSRs are optional, GDB doesn't require them in
- order to have a useful debug session. This enum models the difference
- between these register types. */
-
-enum riscv_register_required_status
-{
- /* This register is optional within this feature. */
- RISCV_REG_OPTIONAL,
-
- /* This register is required within this feature. */
- RISCV_REG_REQUIRED,
-
- /* This register is required, the register must either be in this
- feature, or it could appear within the CSR feature. */
- RISCV_REG_REQUIRED_MAYBE_CSR
-};
-
/* A set of registers that we expect to find in a tdesc_feature. These
are use in RISCV_GDBARCH_INIT when processing the target description. */
struct riscv_register_feature
{
+ explicit riscv_register_feature (const char *feature_name)
+ : m_feature_name (feature_name)
+ { /* Delete. */ }
+
+ riscv_register_feature () = delete;
+ DISABLE_COPY_AND_ASSIGN (riscv_register_feature);
+
/* Information for a single register. */
struct register_info
{
register. */
std::vector<const char *> names;
- /* Is this register required within this feature? In some cases the
- register could be required, but might also be in the CSR feature. */
- riscv_register_required_status required;
-
/* Look in FEATURE for a register with a name from this classes names
list. If the register is found then register its number with
- TDESC_DATA and add all its aliases to the ALIASES list. REG_SET is
- used to help create the aliases. */
+ TDESC_DATA and add all its aliases to the ALIASES list.
+ PREFER_FIRST_NAME_P is used when deciding which aliases to create. */
bool check (struct tdesc_arch_data *tdesc_data,
const struct tdesc_feature *feature,
- const struct riscv_register_feature *reg_set,
+ bool prefer_first_name_p,
std::vector<riscv_pending_register_alias> *aliases) const;
};
- /* The name for this feature. This is the name used to find this feature
- within the target description. */
- const char *name;
+ /* Return the name of this feature. */
+ const char *name () const
+ { return m_feature_name; }
- /* For x-regs and f-regs we always force GDB to use the first name from
- the REGISTERS.NAMES vector, it is therefore important that we create
- user-register aliases for all of the remaining names at indexes 1+ in
- the names vector.
+protected:
- For CSRs we take a different approach, we prefer whatever name the
- target description uses, in this case we want to create user-register
- aliases for any other names that aren't the target description
- provided name.
-
- When this flag is true we are dealing with the first case, and when
- this is false we are dealing with the latter. */
- bool prefer_first_name;
+ /* Return a target description feature extracted from TDESC for this
+ register feature. Will return nullptr if there is no feature in TDESC
+ with the name M_FEATURE_NAME. */
+ const struct tdesc_feature *tdesc_feature (const struct target_desc *tdesc) const
+ {
+ return tdesc_find_feature (tdesc, name ());
+ }
/* List of all the registers that we expect that we might find in this
register set. */
- std::vector<struct register_info> registers;
+ std::vector<struct register_info> m_registers;
+
+private:
+
+ /* The name for this feature. This is the name used to find this feature
+ within the target description. */
+ const char *m_feature_name;
};
/* See description in the class declaration above. */
riscv_register_feature::register_info::check
(struct tdesc_arch_data *tdesc_data,
const struct tdesc_feature *feature,
- const struct riscv_register_feature *reg_set,
+ bool prefer_first_name_p,
std::vector<riscv_pending_register_alias> *aliases) const
{
for (const char *name : this->names)
register. In RISCV_REGISTER_NAME we ensure that GDB
always uses the first name for each register, so here we
add aliases for all of the remaining names. */
- bool prefer_first_name = reg_set->prefer_first_name;
- int start_index = prefer_first_name ? 1 : 0;
+ int start_index = prefer_first_name_p ? 1 : 0;
for (int i = start_index; i < this->names.size (); ++i)
{
const char *alias = this->names[i];
- if (alias == name && !prefer_first_name)
+ if (alias == name && !prefer_first_name_p)
continue;
aliases->emplace_back (alias, (void *) &this->regnum);
}
return false;
}
-/* The general x-registers feature set. */
-
-static const struct riscv_register_feature riscv_xreg_feature =
-{
- "org.gnu.gdb.riscv.cpu", true,
- {
- { RISCV_ZERO_REGNUM + 0, { "zero", "x0" }, RISCV_REG_REQUIRED },
- { RISCV_ZERO_REGNUM + 1, { "ra", "x1" }, RISCV_REG_REQUIRED },
- { RISCV_ZERO_REGNUM + 2, { "sp", "x2" }, RISCV_REG_REQUIRED },
- { RISCV_ZERO_REGNUM + 3, { "gp", "x3" }, RISCV_REG_REQUIRED },
- { RISCV_ZERO_REGNUM + 4, { "tp", "x4" }, RISCV_REG_REQUIRED },
- { RISCV_ZERO_REGNUM + 5, { "t0", "x5" }, RISCV_REG_REQUIRED },
- { RISCV_ZERO_REGNUM + 6, { "t1", "x6" }, RISCV_REG_REQUIRED },
- { RISCV_ZERO_REGNUM + 7, { "t2", "x7" }, RISCV_REG_REQUIRED },
- { RISCV_ZERO_REGNUM + 8, { "fp", "x8", "s0" }, RISCV_REG_REQUIRED },
- { RISCV_ZERO_REGNUM + 9, { "s1", "x9" }, RISCV_REG_REQUIRED },
- { RISCV_ZERO_REGNUM + 10, { "a0", "x10" }, RISCV_REG_REQUIRED },
- { RISCV_ZERO_REGNUM + 11, { "a1", "x11" }, RISCV_REG_REQUIRED },
- { RISCV_ZERO_REGNUM + 12, { "a2", "x12" }, RISCV_REG_REQUIRED },
- { RISCV_ZERO_REGNUM + 13, { "a3", "x13" }, RISCV_REG_REQUIRED },
- { RISCV_ZERO_REGNUM + 14, { "a4", "x14" }, RISCV_REG_REQUIRED },
- { RISCV_ZERO_REGNUM + 15, { "a5", "x15" }, RISCV_REG_REQUIRED },
- { RISCV_ZERO_REGNUM + 16, { "a6", "x16" }, RISCV_REG_REQUIRED },
- { RISCV_ZERO_REGNUM + 17, { "a7", "x17" }, RISCV_REG_REQUIRED },
- { RISCV_ZERO_REGNUM + 18, { "s2", "x18" }, RISCV_REG_REQUIRED },
- { RISCV_ZERO_REGNUM + 19, { "s3", "x19" }, RISCV_REG_REQUIRED },
- { RISCV_ZERO_REGNUM + 20, { "s4", "x20" }, RISCV_REG_REQUIRED },
- { RISCV_ZERO_REGNUM + 21, { "s5", "x21" }, RISCV_REG_REQUIRED },
- { RISCV_ZERO_REGNUM + 22, { "s6", "x22" }, RISCV_REG_REQUIRED },
- { RISCV_ZERO_REGNUM + 23, { "s7", "x23" }, RISCV_REG_REQUIRED },
- { RISCV_ZERO_REGNUM + 24, { "s8", "x24" }, RISCV_REG_REQUIRED },
- { RISCV_ZERO_REGNUM + 25, { "s9", "x25" }, RISCV_REG_REQUIRED },
- { RISCV_ZERO_REGNUM + 26, { "s10", "x26" }, RISCV_REG_REQUIRED },
- { RISCV_ZERO_REGNUM + 27, { "s11", "x27" }, RISCV_REG_REQUIRED },
- { RISCV_ZERO_REGNUM + 28, { "t3", "x28" }, RISCV_REG_REQUIRED },
- { RISCV_ZERO_REGNUM + 29, { "t4", "x29" }, RISCV_REG_REQUIRED },
- { RISCV_ZERO_REGNUM + 30, { "t5", "x30" }, RISCV_REG_REQUIRED },
- { RISCV_ZERO_REGNUM + 31, { "t6", "x31" }, RISCV_REG_REQUIRED },
- { RISCV_ZERO_REGNUM + 32, { "pc" }, RISCV_REG_REQUIRED }
- }
+/* Class representing the x-registers feature set. */
+
+struct riscv_xreg_feature : public riscv_register_feature
+{
+ riscv_xreg_feature ()
+ : riscv_register_feature (riscv_feature_name_cpu)
+ {
+ m_registers = {
+ { RISCV_ZERO_REGNUM + 0, { "zero", "x0" } },
+ { RISCV_ZERO_REGNUM + 1, { "ra", "x1" } },
+ { RISCV_ZERO_REGNUM + 2, { "sp", "x2" } },
+ { RISCV_ZERO_REGNUM + 3, { "gp", "x3" } },
+ { RISCV_ZERO_REGNUM + 4, { "tp", "x4" } },
+ { RISCV_ZERO_REGNUM + 5, { "t0", "x5" } },
+ { RISCV_ZERO_REGNUM + 6, { "t1", "x6" } },
+ { RISCV_ZERO_REGNUM + 7, { "t2", "x7" } },
+ { RISCV_ZERO_REGNUM + 8, { "fp", "x8", "s0" } },
+ { RISCV_ZERO_REGNUM + 9, { "s1", "x9" } },
+ { RISCV_ZERO_REGNUM + 10, { "a0", "x10" } },
+ { RISCV_ZERO_REGNUM + 11, { "a1", "x11" } },
+ { RISCV_ZERO_REGNUM + 12, { "a2", "x12" } },
+ { RISCV_ZERO_REGNUM + 13, { "a3", "x13" } },
+ { RISCV_ZERO_REGNUM + 14, { "a4", "x14" } },
+ { RISCV_ZERO_REGNUM + 15, { "a5", "x15" } },
+ { RISCV_ZERO_REGNUM + 16, { "a6", "x16" } },
+ { RISCV_ZERO_REGNUM + 17, { "a7", "x17" } },
+ { RISCV_ZERO_REGNUM + 18, { "s2", "x18" } },
+ { RISCV_ZERO_REGNUM + 19, { "s3", "x19" } },
+ { RISCV_ZERO_REGNUM + 20, { "s4", "x20" } },
+ { RISCV_ZERO_REGNUM + 21, { "s5", "x21" } },
+ { RISCV_ZERO_REGNUM + 22, { "s6", "x22" } },
+ { RISCV_ZERO_REGNUM + 23, { "s7", "x23" } },
+ { RISCV_ZERO_REGNUM + 24, { "s8", "x24" } },
+ { RISCV_ZERO_REGNUM + 25, { "s9", "x25" } },
+ { RISCV_ZERO_REGNUM + 26, { "s10", "x26" } },
+ { RISCV_ZERO_REGNUM + 27, { "s11", "x27" } },
+ { RISCV_ZERO_REGNUM + 28, { "t3", "x28" } },
+ { RISCV_ZERO_REGNUM + 29, { "t4", "x29" } },
+ { RISCV_ZERO_REGNUM + 30, { "t5", "x30" } },
+ { RISCV_ZERO_REGNUM + 31, { "t6", "x31" } },
+ { RISCV_ZERO_REGNUM + 32, { "pc" } }
+ };
+ }
+
+ /* Return the preferred name for the register with gdb register number
+ REGNUM, which must be in the inclusive range RISCV_ZERO_REGNUM to
+ RISCV_PC_REGNUM. */
+ const char *register_name (int regnum) const
+ {
+ gdb_assert (regnum >= RISCV_ZERO_REGNUM && regnum <= m_registers.size ());
+ return m_registers[regnum].names[0];
+ }
+
+ /* Check this feature within TDESC, record the registers from this
+ feature into TDESC_DATA and update ALIASES and FEATURES. */
+ bool check (const struct target_desc *tdesc,
+ struct tdesc_arch_data *tdesc_data,
+ std::vector<riscv_pending_register_alias> *aliases,
+ struct riscv_gdbarch_features *features) const
+ {
+ const struct tdesc_feature *feature_cpu = tdesc_feature (tdesc);
+
+ if (feature_cpu == nullptr)
+ return false;
+
+ bool seen_an_optional_reg_p = false;
+ for (const auto ® : m_registers)
+ {
+ bool found = reg.check (tdesc_data, feature_cpu, true, aliases);
+
+ bool is_optional_reg_p = (reg.regnum >= RISCV_ZERO_REGNUM + 16
+ && reg.regnum < RISCV_ZERO_REGNUM + 32);
+
+ if (!found && (!is_optional_reg_p || seen_an_optional_reg_p))
+ return false;
+ else if (found && is_optional_reg_p)
+ seen_an_optional_reg_p = true;
+ }
+
+ /* Check that all of the core cpu registers have the same bitsize. */
+ int xlen_bitsize = tdesc_register_bitsize (feature_cpu, "pc");
+
+ bool valid_p = true;
+ for (auto &tdesc_reg : feature_cpu->registers)
+ valid_p &= (tdesc_reg->bitsize == xlen_bitsize);
+
+ features->xlen = (xlen_bitsize / 8);
+ features->embedded = !seen_an_optional_reg_p;
+
+ return valid_p;
+ }
};
-/* The f-registers feature set. */
-
-static const struct riscv_register_feature riscv_freg_feature =
-{
- "org.gnu.gdb.riscv.fpu", true,
- {
- { RISCV_FIRST_FP_REGNUM + 0, { "ft0", "f0" }, RISCV_REG_REQUIRED },
- { RISCV_FIRST_FP_REGNUM + 1, { "ft1", "f1" }, RISCV_REG_REQUIRED },
- { RISCV_FIRST_FP_REGNUM + 2, { "ft2", "f2" }, RISCV_REG_REQUIRED },
- { RISCV_FIRST_FP_REGNUM + 3, { "ft3", "f3" }, RISCV_REG_REQUIRED },
- { RISCV_FIRST_FP_REGNUM + 4, { "ft4", "f4" }, RISCV_REG_REQUIRED },
- { RISCV_FIRST_FP_REGNUM + 5, { "ft5", "f5" }, RISCV_REG_REQUIRED },
- { RISCV_FIRST_FP_REGNUM + 6, { "ft6", "f6" }, RISCV_REG_REQUIRED },
- { RISCV_FIRST_FP_REGNUM + 7, { "ft7", "f7" }, RISCV_REG_REQUIRED },
- { RISCV_FIRST_FP_REGNUM + 8, { "fs0", "f8" }, RISCV_REG_REQUIRED },
- { RISCV_FIRST_FP_REGNUM + 9, { "fs1", "f9" }, RISCV_REG_REQUIRED },
- { RISCV_FIRST_FP_REGNUM + 10, { "fa0", "f10" }, RISCV_REG_REQUIRED },
- { RISCV_FIRST_FP_REGNUM + 11, { "fa1", "f11" }, RISCV_REG_REQUIRED },
- { RISCV_FIRST_FP_REGNUM + 12, { "fa2", "f12" }, RISCV_REG_REQUIRED },
- { RISCV_FIRST_FP_REGNUM + 13, { "fa3", "f13" }, RISCV_REG_REQUIRED },
- { RISCV_FIRST_FP_REGNUM + 14, { "fa4", "f14" }, RISCV_REG_REQUIRED },
- { RISCV_FIRST_FP_REGNUM + 15, { "fa5", "f15" }, RISCV_REG_REQUIRED },
- { RISCV_FIRST_FP_REGNUM + 16, { "fa6", "f16" }, RISCV_REG_REQUIRED },
- { RISCV_FIRST_FP_REGNUM + 17, { "fa7", "f17" }, RISCV_REG_REQUIRED },
- { RISCV_FIRST_FP_REGNUM + 18, { "fs2", "f18" }, RISCV_REG_REQUIRED },
- { RISCV_FIRST_FP_REGNUM + 19, { "fs3", "f19" }, RISCV_REG_REQUIRED },
- { RISCV_FIRST_FP_REGNUM + 20, { "fs4", "f20" }, RISCV_REG_REQUIRED },
- { RISCV_FIRST_FP_REGNUM + 21, { "fs5", "f21" }, RISCV_REG_REQUIRED },
- { RISCV_FIRST_FP_REGNUM + 22, { "fs6", "f22" }, RISCV_REG_REQUIRED },
- { RISCV_FIRST_FP_REGNUM + 23, { "fs7", "f23" }, RISCV_REG_REQUIRED },
- { RISCV_FIRST_FP_REGNUM + 24, { "fs8", "f24" }, RISCV_REG_REQUIRED },
- { RISCV_FIRST_FP_REGNUM + 25, { "fs9", "f25" }, RISCV_REG_REQUIRED },
- { RISCV_FIRST_FP_REGNUM + 26, { "fs10", "f26" }, RISCV_REG_REQUIRED },
- { RISCV_FIRST_FP_REGNUM + 27, { "fs11", "f27" }, RISCV_REG_REQUIRED },
- { RISCV_FIRST_FP_REGNUM + 28, { "ft8", "f28" }, RISCV_REG_REQUIRED },
- { RISCV_FIRST_FP_REGNUM + 29, { "ft9", "f29" }, RISCV_REG_REQUIRED },
- { RISCV_FIRST_FP_REGNUM + 30, { "ft10", "f30" }, RISCV_REG_REQUIRED },
- { RISCV_FIRST_FP_REGNUM + 31, { "ft11", "f31" }, RISCV_REG_REQUIRED },
-
- { RISCV_CSR_FFLAGS_REGNUM, { "fflags", "csr1" }, RISCV_REG_REQUIRED_MAYBE_CSR },
- { RISCV_CSR_FRM_REGNUM, { "frm", "csr2" }, RISCV_REG_REQUIRED_MAYBE_CSR },
- { RISCV_CSR_FCSR_REGNUM, { "fcsr", "csr3" }, RISCV_REG_REQUIRED_MAYBE_CSR },
-
- }
+/* An instance of the x-register feature set. */
+
+static const struct riscv_xreg_feature riscv_xreg_feature;
+
+/* Class representing the f-registers feature set. */
+
+struct riscv_freg_feature : public riscv_register_feature
+{
+ riscv_freg_feature ()
+ : riscv_register_feature (riscv_feature_name_fpu)
+ {
+ m_registers = {
+ { RISCV_FIRST_FP_REGNUM + 0, { "ft0", "f0" } },
+ { RISCV_FIRST_FP_REGNUM + 1, { "ft1", "f1" } },
+ { RISCV_FIRST_FP_REGNUM + 2, { "ft2", "f2" } },
+ { RISCV_FIRST_FP_REGNUM + 3, { "ft3", "f3" } },
+ { RISCV_FIRST_FP_REGNUM + 4, { "ft4", "f4" } },
+ { RISCV_FIRST_FP_REGNUM + 5, { "ft5", "f5" } },
+ { RISCV_FIRST_FP_REGNUM + 6, { "ft6", "f6" } },
+ { RISCV_FIRST_FP_REGNUM + 7, { "ft7", "f7" } },
+ { RISCV_FIRST_FP_REGNUM + 8, { "fs0", "f8" } },
+ { RISCV_FIRST_FP_REGNUM + 9, { "fs1", "f9" } },
+ { RISCV_FIRST_FP_REGNUM + 10, { "fa0", "f10" } },
+ { RISCV_FIRST_FP_REGNUM + 11, { "fa1", "f11" } },
+ { RISCV_FIRST_FP_REGNUM + 12, { "fa2", "f12" } },
+ { RISCV_FIRST_FP_REGNUM + 13, { "fa3", "f13" } },
+ { RISCV_FIRST_FP_REGNUM + 14, { "fa4", "f14" } },
+ { RISCV_FIRST_FP_REGNUM + 15, { "fa5", "f15" } },
+ { RISCV_FIRST_FP_REGNUM + 16, { "fa6", "f16" } },
+ { RISCV_FIRST_FP_REGNUM + 17, { "fa7", "f17" } },
+ { RISCV_FIRST_FP_REGNUM + 18, { "fs2", "f18" } },
+ { RISCV_FIRST_FP_REGNUM + 19, { "fs3", "f19" } },
+ { RISCV_FIRST_FP_REGNUM + 20, { "fs4", "f20" } },
+ { RISCV_FIRST_FP_REGNUM + 21, { "fs5", "f21" } },
+ { RISCV_FIRST_FP_REGNUM + 22, { "fs6", "f22" } },
+ { RISCV_FIRST_FP_REGNUM + 23, { "fs7", "f23" } },
+ { RISCV_FIRST_FP_REGNUM + 24, { "fs8", "f24" } },
+ { RISCV_FIRST_FP_REGNUM + 25, { "fs9", "f25" } },
+ { RISCV_FIRST_FP_REGNUM + 26, { "fs10", "f26" } },
+ { RISCV_FIRST_FP_REGNUM + 27, { "fs11", "f27" } },
+ { RISCV_FIRST_FP_REGNUM + 28, { "ft8", "f28" } },
+ { RISCV_FIRST_FP_REGNUM + 29, { "ft9", "f29" } },
+ { RISCV_FIRST_FP_REGNUM + 30, { "ft10", "f30" } },
+ { RISCV_FIRST_FP_REGNUM + 31, { "ft11", "f31" } },
+ { RISCV_CSR_FFLAGS_REGNUM, { "fflags", "csr1" } },
+ { RISCV_CSR_FRM_REGNUM, { "frm", "csr2" } },
+ { RISCV_CSR_FCSR_REGNUM, { "fcsr", "csr3" } },
+ };
+ }
+
+ /* Return the preferred name for the register with gdb register number
+ REGNUM, which must be in the inclusive range RISCV_FIRST_FP_REGNUM to
+ RISCV_LAST_FP_REGNUM. */
+ const char *register_name (int regnum) const
+ {
+ gdb_static_assert (RISCV_LAST_FP_REGNUM == RISCV_FIRST_FP_REGNUM + 31);
+ gdb_assert (regnum >= RISCV_FIRST_FP_REGNUM
+ && regnum <= RISCV_LAST_FP_REGNUM);
+ regnum -= RISCV_FIRST_FP_REGNUM;
+ return m_registers[regnum].names[0];
+ }
+
+ /* Check this feature within TDESC, record the registers from this
+ feature into TDESC_DATA and update ALIASES and FEATURES. */
+ bool check (const struct target_desc *tdesc,
+ struct tdesc_arch_data *tdesc_data,
+ std::vector<riscv_pending_register_alias> *aliases,
+ struct riscv_gdbarch_features *features) const
+ {
+ const struct tdesc_feature *feature_fpu = tdesc_feature (tdesc);
+
+ /* It's fine if this feature is missing. Update the architecture
+ feature set and return. */
+ if (feature_fpu == nullptr)
+ {
+ features->flen = 0;
+ return true;
+ }
+
+ /* Check all of the floating pointer registers are present. We also
+ check that the floating point CSRs are present too, though if these
+ are missing this is not fatal. */
+ for (const auto ® : m_registers)
+ {
+ bool found = reg.check (tdesc_data, feature_fpu, true, aliases);
+
+ bool is_ctrl_reg_p = reg.regnum > RISCV_LAST_FP_REGNUM;
+
+ if (!found && !is_ctrl_reg_p)
+ return false;
+ }
+
+ /* Look through all of the floating point registers (not the FP CSRs
+ though), and check they all have the same bitsize. Use this bitsize
+ to update the feature set for this gdbarch. */
+ int fp_bitsize = -1;
+ for (const auto ® : m_registers)
+ {
+ /* Stop once we get to the CSRs which are at the end of the
+ M_REGISTERS list. */
+ if (reg.regnum > RISCV_LAST_FP_REGNUM)
+ break;
+
+ int reg_bitsize = -1;
+ for (const char *name : reg.names)
+ {
+ if (tdesc_unnumbered_register (feature_fpu, name))
+ {
+ reg_bitsize = tdesc_register_bitsize (feature_fpu, name);
+ break;
+ }
+ }
+ gdb_assert (reg_bitsize != -1);
+ if (fp_bitsize == -1)
+ fp_bitsize = reg_bitsize;
+ else if (fp_bitsize != reg_bitsize)
+ return false;
+ }
+
+ features->flen = (fp_bitsize / 8);
+ return true;
+ }
};
-/* Set of virtual registers. These are not physical registers on the
- hardware, but might be available from the target. These are not pseudo
- registers, reading these really does result in a register read from the
- target, it is just that there might not be a physical register backing
- the result. */
+/* An instance of the f-register feature set. */
+
+static const struct riscv_freg_feature riscv_freg_feature;
+
+/* Class representing the virtual registers. These are not physical
+ registers on the hardware, but might be available from the target.
+ These are not pseudo registers, reading these really does result in a
+ register read from the target, it is just that there might not be a
+ physical register backing the result. */
-static const struct riscv_register_feature riscv_virtual_feature =
+struct riscv_virtual_feature : public riscv_register_feature
{
- "org.gnu.gdb.riscv.virtual", false,
- {
- { RISCV_PRIV_REGNUM, { "priv" }, RISCV_REG_OPTIONAL }
- }
+ riscv_virtual_feature ()
+ : riscv_register_feature (riscv_feature_name_virtual)
+ {
+ m_registers = {
+ { RISCV_PRIV_REGNUM, { "priv" } }
+ };
+ }
+
+ bool check (const struct target_desc *tdesc,
+ struct tdesc_arch_data *tdesc_data,
+ std::vector<riscv_pending_register_alias> *aliases,
+ struct riscv_gdbarch_features *features) const
+ {
+ const struct tdesc_feature *feature_virtual = tdesc_feature (tdesc);
+
+ /* It's fine if this feature is missing. */
+ if (feature_virtual == nullptr)
+ return true;
+
+ /* We don't check the return value from the call to check here, all the
+ registers in this feature are optional. */
+ for (const auto ® : m_registers)
+ reg.check (tdesc_data, feature_virtual, true, aliases);
+
+ return true;
+ }
};
-/* Feature set for CSRs. This set is NOT constant as the register names
- list for each register is not complete. The aliases are computed
- during RISCV_CREATE_CSR_ALIASES. */
+/* An instance of the virtual register feature. */
+
+static const struct riscv_virtual_feature riscv_virtual_feature;
+
+/* Class representing the CSR feature. */
-static struct riscv_register_feature riscv_csr_feature =
+struct riscv_csr_feature : public riscv_register_feature
{
- "org.gnu.gdb.riscv.csr", false,
- {
-#define DECLARE_CSR(NAME,VALUE,CLASS,DEFINE_VER,ABORT_VER) \
- { RISCV_ ## VALUE ## _REGNUM, { # NAME }, RISCV_REG_OPTIONAL },
+ riscv_csr_feature ()
+ : riscv_register_feature (riscv_feature_name_csr)
+ {
+ m_registers = {
+#define DECLARE_CSR(NAME,VALUE,CLASS,DEFINE_VER,ABORT_VER) \
+ { RISCV_ ## VALUE ## _REGNUM, { # NAME } },
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
- }
+ };
+ riscv_create_csr_aliases ();
+ }
+
+ bool check (const struct target_desc *tdesc,
+ struct tdesc_arch_data *tdesc_data,
+ std::vector<riscv_pending_register_alias> *aliases,
+ struct riscv_gdbarch_features *features) const
+ {
+ const struct tdesc_feature *feature_csr = tdesc_feature (tdesc);
+
+ /* It's fine if this feature is missing. */
+ if (feature_csr == nullptr)
+ return true;
+
+ /* We don't check the return value from the call to check here, all the
+ registers in this feature are optional. */
+ for (const auto ® : m_registers)
+ reg.check (tdesc_data, feature_csr, true, aliases);
+
+ return true;
+ }
+
+private:
+
+ /* Complete RISCV_CSR_FEATURE, building the CSR alias names and adding them
+ to the name list for each register. */
+
+ void
+ riscv_create_csr_aliases ()
+ {
+ for (auto ® : m_registers)
+ {
+ int csr_num = reg.regnum - RISCV_FIRST_CSR_REGNUM;
+ gdb::unique_xmalloc_ptr<char> alias = xstrprintf ("csr%d", csr_num);
+ reg.names.push_back (alias.release ());
+ }
+ }
};
-/* Complete RISCV_CSR_FEATURE, building the CSR alias names and adding them
- to the name list for each register. */
+/* An instance of the csr register feature. */
-static void
-riscv_create_csr_aliases ()
+static const struct riscv_csr_feature riscv_csr_feature;
+
+/* Class representing the v-registers feature set. */
+
+struct riscv_vector_feature : public riscv_register_feature
{
- for (auto ® : riscv_csr_feature.registers)
- {
- int csr_num = reg.regnum - RISCV_FIRST_CSR_REGNUM;
- const char *alias = xstrprintf ("csr%d", csr_num);
- reg.names.push_back (alias);
+ riscv_vector_feature ()
+ : riscv_register_feature (riscv_feature_name_vector)
+ {
+ m_registers = {
+ { RISCV_V0_REGNUM + 0, { "v0" } },
+ { RISCV_V0_REGNUM + 1, { "v1" } },
+ { RISCV_V0_REGNUM + 2, { "v2" } },
+ { RISCV_V0_REGNUM + 3, { "v3" } },
+ { RISCV_V0_REGNUM + 4, { "v4" } },
+ { RISCV_V0_REGNUM + 5, { "v5" } },
+ { RISCV_V0_REGNUM + 6, { "v6" } },
+ { RISCV_V0_REGNUM + 7, { "v7" } },
+ { RISCV_V0_REGNUM + 8, { "v8" } },
+ { RISCV_V0_REGNUM + 9, { "v9" } },
+ { RISCV_V0_REGNUM + 10, { "v10" } },
+ { RISCV_V0_REGNUM + 11, { "v11" } },
+ { RISCV_V0_REGNUM + 12, { "v12" } },
+ { RISCV_V0_REGNUM + 13, { "v13" } },
+ { RISCV_V0_REGNUM + 14, { "v14" } },
+ { RISCV_V0_REGNUM + 15, { "v15" } },
+ { RISCV_V0_REGNUM + 16, { "v16" } },
+ { RISCV_V0_REGNUM + 17, { "v17" } },
+ { RISCV_V0_REGNUM + 18, { "v18" } },
+ { RISCV_V0_REGNUM + 19, { "v19" } },
+ { RISCV_V0_REGNUM + 20, { "v20" } },
+ { RISCV_V0_REGNUM + 21, { "v21" } },
+ { RISCV_V0_REGNUM + 22, { "v22" } },
+ { RISCV_V0_REGNUM + 23, { "v23" } },
+ { RISCV_V0_REGNUM + 24, { "v24" } },
+ { RISCV_V0_REGNUM + 25, { "v25" } },
+ { RISCV_V0_REGNUM + 26, { "v26" } },
+ { RISCV_V0_REGNUM + 27, { "v27" } },
+ { RISCV_V0_REGNUM + 28, { "v28" } },
+ { RISCV_V0_REGNUM + 29, { "v29" } },
+ { RISCV_V0_REGNUM + 30, { "v30" } },
+ { RISCV_V0_REGNUM + 31, { "v31" } },
+ };
+ }
- /* Setup the other csr aliases. We don't use a switch table here in
- case there are multiple aliases with the same value. Also filter
- based on ABRT_VER in order to avoid a very old alias for misa that
- duplicates the name "misa" but at a different CSR address. */
-#define DECLARE_CSR_ALIAS(NAME,VALUE,CLASS,DEF_VER,ABRT_VER) \
- if (csr_num == VALUE && ABRT_VER >= PRIV_SPEC_CLASS_1P11) \
- reg.names.push_back ( # NAME );
-#include "opcode/riscv-opc.h"
-#undef DECLARE_CSR_ALIAS
- }
-}
+ /* Return the preferred name for the register with gdb register number
+ REGNUM, which must be in the inclusive range RISCV_V0_REGNUM to
+ RISCV_V0_REGNUM + 31. */
+ const char *register_name (int regnum) const
+ {
+ gdb_assert (regnum >= RISCV_V0_REGNUM
+ && regnum <= RISCV_V0_REGNUM + 31);
+ regnum -= RISCV_V0_REGNUM;
+ return m_registers[regnum].names[0];
+ }
+
+ /* Check this feature within TDESC, record the registers from this
+ feature into TDESC_DATA and update ALIASES and FEATURES. */
+ bool check (const struct target_desc *tdesc,
+ struct tdesc_arch_data *tdesc_data,
+ std::vector<riscv_pending_register_alias> *aliases,
+ struct riscv_gdbarch_features *features) const
+ {
+ const struct tdesc_feature *feature_vector = tdesc_feature (tdesc);
+
+ /* It's fine if this feature is missing. Update the architecture
+ feature set and return. */
+ if (feature_vector == nullptr)
+ {
+ features->vlen = 0;
+ return true;
+ }
+
+ /* Check all of the vector registers are present. */
+ for (const auto ® : m_registers)
+ {
+ if (!reg.check (tdesc_data, feature_vector, true, aliases))
+ return false;
+ }
+
+ /* Look through all of the vector registers and check they all have the
+ same bitsize. Use this bitsize to update the feature set for this
+ gdbarch. */
+ int vector_bitsize = -1;
+ for (const auto ® : m_registers)
+ {
+ int reg_bitsize = -1;
+ for (const char *name : reg.names)
+ {
+ if (tdesc_unnumbered_register (feature_vector, name))
+ {
+ reg_bitsize = tdesc_register_bitsize (feature_vector, name);
+ break;
+ }
+ }
+ gdb_assert (reg_bitsize != -1);
+ if (vector_bitsize == -1)
+ vector_bitsize = reg_bitsize;
+ else if (vector_bitsize != reg_bitsize)
+ return false;
+ }
+
+ features->vlen = (vector_bitsize / 8);
+ return true;
+ }
+};
+
+/* An instance of the v-register feature set. */
+
+static const struct riscv_vector_feature riscv_vector_feature;
/* Controls whether we place compressed breakpoints or not. When in auto
mode GDB tries to determine if the target supports compressed
struct cmd_list_element *c,
const char *value)
{
- fprintf_filtered (file,
- _("Debugger's use of compressed breakpoints is set "
- "to %s.\n"), value);
+ gdb_printf (file,
+ _("Debugger's use of compressed breakpoints is set "
+ "to %s.\n"), value);
}
/* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
struct cmd_list_element *c,
const char *value)
{
- fprintf_filtered (file,
- _("RiscV debug variable `%s' is set to: %s\n"),
- c->name, value);
+ gdb_printf (file,
+ _("RiscV debug variable `%s' is set to: %s\n"),
+ c->name, value);
}
-/* When this is set to non-zero debugging information about breakpoint
- kinds will be printed. */
-
-static unsigned int riscv_debug_breakpoints = 0;
-
-/* When this is set to non-zero debugging information about inferior calls
- will be printed. */
-
-static unsigned int riscv_debug_infcall = 0;
-
-/* When this is set to non-zero debugging information about stack unwinding
- will be printed. */
-
-static unsigned int riscv_debug_unwinder = 0;
-
-/* When this is set to non-zero debugging information about gdbarch
- initialisation will be printed. */
-
-static unsigned int riscv_debug_gdbarch = 0;
-
/* See riscv-tdep.h. */
int
riscv_isa_xlen (struct gdbarch *gdbarch)
{
- return gdbarch_tdep (gdbarch)->isa_features.xlen;
+ riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
+ return tdep->isa_features.xlen;
}
/* See riscv-tdep.h. */
int
riscv_abi_xlen (struct gdbarch *gdbarch)
{
- return gdbarch_tdep (gdbarch)->abi_features.xlen;
+ riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
+ return tdep->abi_features.xlen;
}
/* See riscv-tdep.h. */
int
riscv_isa_flen (struct gdbarch *gdbarch)
{
- return gdbarch_tdep (gdbarch)->isa_features.flen;
+ riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
+ return tdep->isa_features.flen;
}
/* See riscv-tdep.h. */
int
riscv_abi_flen (struct gdbarch *gdbarch)
{
- return gdbarch_tdep (gdbarch)->abi_features.flen;
+ riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
+ return tdep->abi_features.flen;
+}
+
+/* See riscv-tdep.h. */
+
+bool
+riscv_abi_embedded (struct gdbarch *gdbarch)
+{
+ riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
+ return tdep->abi_features.embedded;
}
/* Return true if the target for GDBARCH has floating point hardware. */
static bool
riscv_has_fp_abi (struct gdbarch *gdbarch)
{
- return gdbarch_tdep (gdbarch)->abi_features.flen > 0;
+ riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
+ return tdep->abi_features.flen > 0;
}
/* Return true if REGNO is a floating pointer register. */
user. */
if (target_read_code (*pcptr, buf, 1) == -1)
buf[0] = 0;
- read_code (*pcptr, buf, 1);
}
if (riscv_debug_breakpoints)
const char *bp = (unaligned_p || riscv_insn_length (buf[0]) == 2
? "C.EBREAK" : "EBREAK");
- fprintf_unfiltered (gdb_stdlog, "Using %s for breakpoint at %s ",
- bp, paddress (gdbarch, *pcptr));
+ std::string suffix;
if (unaligned_p)
- fprintf_unfiltered (gdb_stdlog, "(unaligned address)\n");
+ suffix = "(unaligned address)";
else
- fprintf_unfiltered (gdb_stdlog, "(instruction length %d)\n",
- riscv_insn_length (buf[0]));
+ suffix = string_printf ("(instruction length %d)",
+ riscv_insn_length (buf[0]));
+ riscv_breakpoints_debug_printf ("Using %s for breakpoint at %s %s",
+ bp, paddress (gdbarch, *pcptr),
+ suffix.c_str ());
}
if (unaligned_p || riscv_insn_length (buf[0]) == 2)
return 2;
case 4:
return ebreak;
default:
- gdb_assert_not_reached (_("unhandled breakpoint kind"));
+ gdb_assert_not_reached ("unhandled breakpoint kind");
}
}
then this is an unknown register. If we do get a name back then we
look up the registers preferred name below. */
const char *name = tdesc_register_name (gdbarch, regnum);
- if (name == NULL || name[0] == '\0')
- return NULL;
+ gdb_assert (name != nullptr);
+ if (name[0] == '\0')
+ return name;
/* We want GDB to use the ABI names for registers even if the target
gives us a target description with the architectural name. For
example we want to see 'ra' instead of 'x1' whatever the target
description called it. */
if (regnum >= RISCV_ZERO_REGNUM && regnum < RISCV_FIRST_FP_REGNUM)
- {
- gdb_assert (regnum < riscv_xreg_feature.registers.size ());
- return riscv_xreg_feature.registers[regnum].names[0];
- }
+ return riscv_xreg_feature.register_name (regnum);
/* Like with the x-regs we prefer the abi names for the floating point
- registers. */
+ registers. If the target doesn't have floating point registers then
+ the tdesc_register_name call above should have returned an empty
+ string. */
if (regnum >= RISCV_FIRST_FP_REGNUM && regnum <= RISCV_LAST_FP_REGNUM)
{
- if (riscv_has_fp_regs (gdbarch))
- {
- regnum -= RISCV_FIRST_FP_REGNUM;
- gdb_assert (regnum < riscv_freg_feature.registers.size ());
- return riscv_freg_feature.registers[regnum].names[0];
- }
- else
- return NULL;
+ gdb_assert (riscv_has_fp_regs (gdbarch));
+ return riscv_freg_feature.register_name (regnum);
}
/* Some targets (QEMU) are reporting these three registers twice, once
will show up in 'info register all'. Unless, we identify the
duplicate copies of these registers (in riscv_tdesc_unknown_reg) and
then hide the registers here by giving them no name. */
- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
- if (tdep->duplicate_fflags_regnum == regnum)
- return NULL;
- if (tdep->duplicate_frm_regnum == regnum)
- return NULL;
- if (tdep->duplicate_fcsr_regnum == regnum)
- return NULL;
+ riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
+ if (tdep->duplicate_fflags_regnum == regnum
+ || tdep->duplicate_frm_regnum == regnum
+ || tdep->duplicate_fcsr_regnum == regnum)
+ return "";
/* The remaining registers are different. For all other registers on the
machine we prefer to see the names that the target description
return name;
}
+/* Implement gdbarch_pseudo_register_read. Read pseudo-register REGNUM
+ from REGCACHE and place the register value into BUF. BUF is sized
+ based on the type of register REGNUM, all of BUF should be written too,
+ the result should be sign or zero extended as appropriate. */
+
+static enum register_status
+riscv_pseudo_register_read (struct gdbarch *gdbarch,
+ readable_regcache *regcache,
+ int regnum, gdb_byte *buf)
+{
+ riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
+
+ if (regnum == tdep->fflags_regnum || regnum == tdep->frm_regnum)
+ {
+ /* Clear BUF. */
+ memset (buf, 0, register_size (gdbarch, regnum));
+
+ /* Read the first byte of the fcsr register, this contains both frm
+ and fflags. */
+ enum register_status status
+ = regcache->raw_read_part (RISCV_CSR_FCSR_REGNUM, 0, 1, buf);
+
+ if (status != REG_VALID)
+ return status;
+
+ /* Extract the appropriate parts. */
+ if (regnum == tdep->fflags_regnum)
+ buf[0] &= 0x1f;
+ else if (regnum == tdep->frm_regnum)
+ buf[0] = (buf[0] >> 5) & 0x7;
+
+ return REG_VALID;
+ }
+
+ return REG_UNKNOWN;
+}
+
+/* Implement gdbarch_pseudo_register_write. Write the contents of BUF into
+ pseudo-register REGNUM in REGCACHE. BUF is sized based on the type of
+ register REGNUM. */
+
+static void
+riscv_pseudo_register_write (struct gdbarch *gdbarch,
+ struct regcache *regcache, int regnum,
+ const gdb_byte *buf)
+{
+ riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
+
+ if (regnum == tdep->fflags_regnum || regnum == tdep->frm_regnum)
+ {
+ int fcsr_regnum = RISCV_CSR_FCSR_REGNUM;
+ gdb_byte raw_buf[register_size (gdbarch, fcsr_regnum)];
+
+ regcache->raw_read (fcsr_regnum, raw_buf);
+
+ if (regnum == tdep->fflags_regnum)
+ raw_buf[0] = (raw_buf[0] & ~0x1f) | (buf[0] & 0x1f);
+ else if (regnum == tdep->frm_regnum)
+ raw_buf[0] = (raw_buf[0] & ~(0x7 << 5)) | ((buf[0] & 0x7) << 5);
+
+ regcache->raw_write (fcsr_regnum, raw_buf);
+ }
+ else
+ gdb_assert_not_reached ("unknown pseudo register %d", regnum);
+}
+
+/* Implement the cannot_store_register gdbarch method. The zero register
+ (x0) is read-only on RISC-V. */
+
+static int
+riscv_cannot_store_register (struct gdbarch *gdbarch, int regnum)
+{
+ return regnum == RISCV_ZERO_REGNUM;
+}
+
/* Construct a type for 64-bit FP registers. */
static struct type *
riscv_fpreg_d_type (struct gdbarch *gdbarch)
{
- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
if (tdep->riscv_fpreg_d_type == nullptr)
{
"__gdb_builtin_type_fpreg_d", TYPE_CODE_UNION);
append_composite_type_field (t, "float", bt->builtin_float);
append_composite_type_field (t, "double", bt->builtin_double);
- TYPE_VECTOR (t) = 1;
+ t->set_is_vector (true);
t->set_name ("builtin_type_fpreg_d");
tdep->riscv_fpreg_d_type = t;
}
if (riscv_is_fp_regno_p (regnum))
{
/* This spots the case for RV64 where the double is defined as
- either 'ieee_double' or 'float' (which is the generic name that
- converts to 'double' on 64-bit). In these cases its better to
- present the registers using a union type. */
+ either 'ieee_double' or 'float' (which is the generic name that
+ converts to 'double' on 64-bit). In these cases its better to
+ present the registers using a union type. */
int flen = riscv_isa_flen (gdbarch);
if (flen == 8
- && type->code () == TYPE_CODE_FLT
- && TYPE_LENGTH (type) == flen
- && (strcmp (type->name (), "builtin_type_ieee_double") == 0
- || strcmp (type->name (), "double") == 0))
- type = riscv_fpreg_d_type (gdbarch);
+ && type->code () == TYPE_CODE_FLT
+ && type->length () == flen
+ && (strcmp (type->name (), "builtin_type_ieee_double") == 0
+ || strcmp (type->name (), "double") == 0))
+ type = riscv_fpreg_d_type (gdbarch);
}
if ((regnum == gdbarch_pc_regnum (gdbarch)
|| regnum == RISCV_GP_REGNUM
|| regnum == RISCV_TP_REGNUM)
&& type->code () == TYPE_CODE_INT
- && TYPE_LENGTH (type) == xlen)
+ && type->length () == xlen)
{
/* This spots the case where some interesting registers are defined
- as simple integers of the expected size, we force these registers
- to be pointers as we believe that is more useful. */
+ as simple integers of the expected size, we force these registers
+ to be pointers as we believe that is more useful. */
if (regnum == gdbarch_pc_regnum (gdbarch)
- || regnum == RISCV_RA_REGNUM)
- type = builtin_type (gdbarch)->builtin_func_ptr;
+ || regnum == RISCV_RA_REGNUM)
+ type = builtin_type (gdbarch)->builtin_func_ptr;
else if (regnum == RISCV_FP_REGNUM
- || regnum == RISCV_SP_REGNUM
- || regnum == RISCV_GP_REGNUM
- || regnum == RISCV_TP_REGNUM)
+ || regnum == RISCV_SP_REGNUM
+ || regnum == RISCV_GP_REGNUM
+ || regnum == RISCV_TP_REGNUM)
type = builtin_type (gdbarch)->builtin_data_ptr;
}
static void
riscv_print_one_register_info (struct gdbarch *gdbarch,
struct ui_file *file,
- struct frame_info *frame,
+ frame_info_ptr frame,
int regnum)
{
const char *name = gdbarch_register_name (gdbarch, regnum);
int print_raw_format;
enum tab_stops { value_column_1 = 15 };
- fputs_filtered (name, file);
- print_spaces_filtered (value_column_1 - strlen (name), file);
+ gdb_puts (name, file);
+ print_spaces (std::max<int> (1, value_column_1 - strlen (name)), file);
try
{
val = value_of_register (regnum, frame);
- regtype = value_type (val);
+ regtype = val->type ();
}
catch (const gdb_exception_error &ex)
{
/* Handle failure to read a register without interrupting the entire
- 'info registers' flow. */
- fprintf_filtered (file, "%s\n", ex.what ());
+ 'info registers' flow. */
+ gdb_printf (file, "%s\n", ex.what ());
return;
}
- print_raw_format = (value_entirely_available (val)
- && !value_optimized_out (val));
+ print_raw_format = (val->entirely_available ()
+ && !val->optimized_out ());
if (regtype->code () == TYPE_CODE_FLT
|| (regtype->code () == TYPE_CODE_UNION
&& regtype->field (2).type ()->code () == TYPE_CODE_FLT))
{
struct value_print_options opts;
- const gdb_byte *valaddr = value_contents_for_printing (val);
+ const gdb_byte *valaddr = val->contents_for_printing ().data ();
enum bfd_endian byte_order = type_byte_order (regtype);
get_user_print_options (&opts);
- opts.deref_ref = 1;
+ opts.deref_ref = true;
common_val_print (val, file, 0, &opts, current_language);
if (print_raw_format)
{
- fprintf_filtered (file, "\t(raw ");
- print_hex_chars (file, valaddr, TYPE_LENGTH (regtype), byte_order,
+ gdb_printf (file, "\t(raw ");
+ print_hex_chars (file, valaddr, regtype->length (), byte_order,
true);
- fprintf_filtered (file, ")");
+ gdb_printf (file, ")");
}
}
else
{
struct value_print_options opts;
+ riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
/* Print the register in hex. */
get_formatted_print_options (&opts, 'x');
- opts.deref_ref = 1;
+ opts.deref_ref = true;
common_val_print (val, file, 0, &opts, current_language);
if (print_raw_format)
of the number of bits in MSTATUS. */
d = value_as_long (val);
xlen = size * 8;
- fprintf_filtered (file,
- "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
- "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
- "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
- (int) ((d >> (xlen - 1)) & 0x1),
- (int) ((d >> 24) & 0x1f),
- (int) ((d >> 19) & 0x1),
- (int) ((d >> 18) & 0x1),
- (int) ((d >> 17) & 0x1),
- (int) ((d >> 15) & 0x3),
- (int) ((d >> 13) & 0x3),
- (int) ((d >> 11) & 0x3),
- (int) ((d >> 9) & 0x3),
- (int) ((d >> 8) & 0x1),
- (int) ((d >> 7) & 0x1),
- (int) ((d >> 6) & 0x1),
- (int) ((d >> 5) & 0x1),
- (int) ((d >> 4) & 0x1),
- (int) ((d >> 3) & 0x1),
- (int) ((d >> 2) & 0x1),
- (int) ((d >> 1) & 0x1),
- (int) ((d >> 0) & 0x1));
+ gdb_printf (file,
+ "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
+ "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
+ "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
+ (int) ((d >> (xlen - 1)) & 0x1),
+ (int) ((d >> 24) & 0x1f),
+ (int) ((d >> 19) & 0x1),
+ (int) ((d >> 18) & 0x1),
+ (int) ((d >> 17) & 0x1),
+ (int) ((d >> 15) & 0x3),
+ (int) ((d >> 13) & 0x3),
+ (int) ((d >> 11) & 0x3),
+ (int) ((d >> 9) & 0x3),
+ (int) ((d >> 8) & 0x1),
+ (int) ((d >> 7) & 0x1),
+ (int) ((d >> 6) & 0x1),
+ (int) ((d >> 5) & 0x1),
+ (int) ((d >> 4) & 0x1),
+ (int) ((d >> 3) & 0x1),
+ (int) ((d >> 2) & 0x1),
+ (int) ((d >> 1) & 0x1),
+ (int) ((d >> 0) & 0x1));
}
else if (regnum == RISCV_CSR_MISA_REGNUM)
{
for (; base > 0; base--)
xlen *= 2;
- fprintf_filtered (file, "\tRV%d", xlen);
+ gdb_printf (file, "\tRV%d", xlen);
for (i = 0; i < 26; i++)
{
if (d & (1 << i))
- fprintf_filtered (file, "%c", 'A' + i);
+ gdb_printf (file, "%c", 'A' + i);
}
}
else if (regnum == RISCV_CSR_FCSR_REGNUM
- || regnum == RISCV_CSR_FFLAGS_REGNUM
- || regnum == RISCV_CSR_FRM_REGNUM)
+ || regnum == tdep->fflags_regnum
+ || regnum == tdep->frm_regnum)
{
- LONGEST d;
-
- d = value_as_long (val);
-
- fprintf_filtered (file, "\t");
- if (regnum != RISCV_CSR_FRM_REGNUM)
- fprintf_filtered (file,
- "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d",
- (int) ((d >> 5) & 0x7),
- (int) ((d >> 4) & 0x1),
- (int) ((d >> 3) & 0x1),
- (int) ((d >> 2) & 0x1),
- (int) ((d >> 1) & 0x1),
- (int) ((d >> 0) & 0x1));
-
- if (regnum != RISCV_CSR_FFLAGS_REGNUM)
+ LONGEST d = value_as_long (val);
+
+ gdb_printf (file, "\t");
+ if (regnum != tdep->frm_regnum)
+ gdb_printf (file,
+ "NV:%d DZ:%d OF:%d UF:%d NX:%d",
+ (int) ((d >> 4) & 0x1),
+ (int) ((d >> 3) & 0x1),
+ (int) ((d >> 2) & 0x1),
+ (int) ((d >> 1) & 0x1),
+ (int) ((d >> 0) & 0x1));
+
+ if (regnum != tdep->fflags_regnum)
{
static const char * const sfrm[] =
{
- "RNE (round to nearest; ties to even)",
- "RTZ (Round towards zero)",
- "RDN (Round down towards -INF)",
- "RUP (Round up towards +INF)",
- "RMM (Round to nearest; ties to max magnitude)",
- "INVALID[5]",
- "INVALID[6]",
- "dynamic rounding mode",
+ _("RNE (round to nearest; ties to even)"),
+ _("RTZ (Round towards zero)"),
+ _("RDN (Round down towards -INF)"),
+ _("RUP (Round up towards +INF)"),
+ _("RMM (Round to nearest; ties to max magnitude)"),
+ _("INVALID[5]"),
+ _("INVALID[6]"),
+ /* A value of 0x7 indicates dynamic rounding mode when
+ used within an instructions rounding-mode field, but
+ is invalid within the FRM register. */
+ _("INVALID[7] (Dynamic rounding mode)"),
};
int frm = ((regnum == RISCV_CSR_FCSR_REGNUM)
- ? (d >> 5) : d) & 0x3;
+ ? (d >> 5) : d) & 0x7;
- fprintf_filtered (file, "%sFRM:%i [%s]",
- (regnum == RISCV_CSR_FCSR_REGNUM
- ? " " : ""),
- frm, sfrm[frm]);
+ gdb_printf (file, "%sFRM:%i [%s]",
+ (regnum == RISCV_CSR_FCSR_REGNUM
+ ? " " : ""),
+ frm, sfrm[frm]);
}
}
else if (regnum == RISCV_PRIV_REGNUM)
"Hypervisor",
"Machine"
};
- fprintf_filtered (file, "\tprv:%d [%s]",
- priv, sprv[priv]);
+ gdb_printf (file, "\tprv:%d [%s]",
+ priv, sprv[priv]);
}
else
- fprintf_filtered (file, "\tprv:%d [INVALID]", priv);
+ gdb_printf (file, "\tprv:%d [INVALID]", priv);
}
else
{
/* If not a vector register, print it also according to its
natural format. */
- if (TYPE_VECTOR (regtype) == 0)
+ if (regtype->is_vector () == 0)
{
get_user_print_options (&opts);
- opts.deref_ref = 1;
- fprintf_filtered (file, "\t");
+ opts.deref_ref = true;
+ gdb_printf (file, "\t");
common_val_print (val, file, 0, &opts, current_language);
}
}
}
}
- fprintf_filtered (file, "\n");
+ gdb_printf (file, "\n");
}
/* Return true if REGNUM is a valid CSR register. The CSR register space
}
}
+/* Return true if REGNUM is an unknown CSR identified in
+ riscv_tdesc_unknown_reg for GDBARCH. */
+
+static bool
+riscv_is_unknown_csr (struct gdbarch *gdbarch, int regnum)
+{
+ riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
+ return (regnum >= tdep->unknown_csrs_first_regnum
+ && regnum < (tdep->unknown_csrs_first_regnum
+ + tdep->unknown_csrs_count));
+}
+
/* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
of REGGROUP? */
static int
riscv_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
- struct reggroup *reggroup)
+ const struct reggroup *reggroup)
{
+ riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
+
/* Used by 'info registers' and 'info registers <groupname>'. */
- if (gdbarch_register_name (gdbarch, regnum) == NULL
- || gdbarch_register_name (gdbarch, regnum)[0] == '\0')
+ if (gdbarch_register_name (gdbarch, regnum)[0] == '\0')
return 0;
- if (regnum > RISCV_LAST_REGNUM)
+ if (regnum > RISCV_LAST_REGNUM && regnum < gdbarch_num_regs (gdbarch))
{
/* Any extra registers from the CSR tdesc_feature (identified in
riscv_tdesc_unknown_reg) are removed from the save/restore groups
- as some targets (QEMU) report CSRs which then can't be read. */
- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
- if ((reggroup == restore_reggroup || reggroup == save_reggroup)
- && regnum >= tdep->unknown_csrs_first_regnum
- && regnum < (tdep->unknown_csrs_first_regnum
- + tdep->unknown_csrs_count))
- return 0;
+ as some targets (QEMU) report CSRs which then can't be read and
+ having unreadable registers in the save/restore group breaks
+ things like inferior calls.
+
+ The unknown CSRs are also removed from the general group, and
+ added into both the csr and system group. This is inline with the
+ known CSRs (see below). */
+ if (riscv_is_unknown_csr (gdbarch, regnum))
+ {
+ if (reggroup == restore_reggroup || reggroup == save_reggroup
+ || reggroup == general_reggroup)
+ return 0;
+ else if (reggroup == system_reggroup || reggroup == csr_reggroup)
+ return 1;
+ }
/* This is some other unknown register from the target description.
In this case we trust whatever the target description says about
which groups this register should be in. */
int ret = tdesc_register_in_reggroup_p (gdbarch, regnum, reggroup);
if (ret != -1)
- return ret;
+ return ret;
return default_register_reggroup_p (gdbarch, regnum, reggroup);
}
if (reggroup == all_reggroup)
{
- if (regnum < RISCV_FIRST_CSR_REGNUM || regnum == RISCV_PRIV_REGNUM)
+ if (regnum < RISCV_FIRST_CSR_REGNUM || regnum >= RISCV_PRIV_REGNUM)
return 1;
if (riscv_is_regnum_a_named_csr (regnum))
- return 1;
+ return 1;
return 0;
}
else if (reggroup == float_reggroup)
return (riscv_is_fp_regno_p (regnum)
|| regnum == RISCV_CSR_FCSR_REGNUM
- || regnum == RISCV_CSR_FFLAGS_REGNUM
- || regnum == RISCV_CSR_FRM_REGNUM);
+ || regnum == tdep->fflags_regnum
+ || regnum == tdep->frm_regnum);
else if (reggroup == general_reggroup)
return regnum < RISCV_FIRST_FP_REGNUM;
else if (reggroup == restore_reggroup || reggroup == save_reggroup)
if (riscv_has_fp_regs (gdbarch))
return (regnum <= RISCV_LAST_FP_REGNUM
|| regnum == RISCV_CSR_FCSR_REGNUM
- || regnum == RISCV_CSR_FFLAGS_REGNUM
- || regnum == RISCV_CSR_FRM_REGNUM);
+ || regnum == tdep->fflags_regnum
+ || regnum == tdep->frm_regnum);
else
return regnum < RISCV_FIRST_FP_REGNUM;
}
if (regnum < RISCV_FIRST_CSR_REGNUM || regnum > RISCV_LAST_CSR_REGNUM)
return 0;
if (riscv_is_regnum_a_named_csr (regnum))
- return 1;
+ return 1;
return 0;
}
else if (reggroup == vector_reggroup)
- return 0;
+ return (regnum >= RISCV_V0_REGNUM && regnum <= RISCV_V31_REGNUM);
else
return 0;
}
+/* Return the name for pseudo-register REGNUM for GDBARCH. */
+
+static const char *
+riscv_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
+{
+ riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
+
+ if (regnum == tdep->fflags_regnum)
+ return "fflags";
+ else if (regnum == tdep->frm_regnum)
+ return "frm";
+ else
+ gdb_assert_not_reached ("unknown pseudo register number %d", regnum);
+}
+
+/* Return the type for pseudo-register REGNUM for GDBARCH. */
+
+static struct type *
+riscv_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
+{
+ riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
+
+ if (regnum == tdep->fflags_regnum || regnum == tdep->frm_regnum)
+ return builtin_type (gdbarch)->builtin_int32;
+ else
+ gdb_assert_not_reached ("unknown pseudo register number %d", regnum);
+}
+
+/* Return true (non-zero) if pseudo-register REGNUM from GDBARCH is a
+ member of REGGROUP, otherwise return false (zero). */
+
+static int
+riscv_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
+ const struct reggroup *reggroup)
+{
+ /* The standard function will also work for pseudo-registers. */
+ return riscv_register_reggroup_p (gdbarch, regnum, reggroup);
+}
+
/* Implement the print_registers_info gdbarch method. This is used by
'info registers' and 'info all-registers'. */
static void
riscv_print_registers_info (struct gdbarch *gdbarch,
struct ui_file *file,
- struct frame_info *frame,
+ frame_info_ptr frame,
int regnum, int print_all)
{
if (regnum != -1)
{
/* Print one specified register. */
- if (gdbarch_register_name (gdbarch, regnum) == NULL
- || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
- error (_("Not a valid register for the current processor type"));
+ if (*(gdbarch_register_name (gdbarch, regnum)) == '\0')
+ error (_("Not a valid register for the current processor type"));
riscv_print_one_register_info (gdbarch, file, frame, regnum);
}
else
{
- struct reggroup *reggroup;
+ const struct reggroup *reggroup;
if (print_all)
reggroup = all_reggroup;
continue;
/* Registers with no name are not valid on this ISA. */
- if (gdbarch_register_name (gdbarch, regnum) == NULL
- || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
+ if (*(gdbarch_register_name (gdbarch, regnum)) == '\0')
continue;
/* Is the register in the group we're interested in? */
ADDW,
AUIPC,
LUI,
+ LI,
SD,
SW,
+ LD,
+ LW,
+ MV,
/* These are needed for software breakpoint support. */
JAL,
JALR,
/* These are needed for stepping over atomic sequences. */
LR,
SC,
+ /* This instruction is used to do a syscall. */
+ ECALL,
/* Other instructions are not interesting during the prologue scan, and
are ignored. */
m_imm.s = EXTRACT_ITYPE_IMM (ival);
}
- /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
- void decode_ci_type_insn (enum opcode opcode, ULONGEST ival)
+ /* Helper for DECODE, decode 16-bit compressed I-type instruction. Some
+ of the CI instruction have a hard-coded rs1 register, while others
+ just use rd for both the source and destination. RS1_REGNUM, if
+ passed, is the value to place in rs1, otherwise rd is duplicated into
+ rs1. */
+ void decode_ci_type_insn (enum opcode opcode, ULONGEST ival,
+ gdb::optional<int> rs1_regnum = {})
{
m_opcode = opcode;
- m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
- m_imm.s = EXTRACT_RVC_IMM (ival);
+ m_rd = decode_register_index (ival, OP_SH_CRS1S);
+ if (rs1_regnum.has_value ())
+ m_rs1 = *rs1_regnum;
+ else
+ m_rs1 = m_rd;
+ m_imm.s = EXTRACT_CITYPE_IMM (ival);
+ }
+
+ /* Helper for DECODE, decode 16-bit compressed CL-type instruction. */
+ void decode_cl_type_insn (enum opcode opcode, ULONGEST ival)
+ {
+ m_opcode = opcode;
+ m_rd = decode_register_index_short (ival, OP_SH_CRS2S);
+ m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
+ m_imm.s = EXTRACT_CLTYPE_IMM (ival);
}
/* Helper for DECODE, decode 32-bit S-type instruction. */
{
m_opcode = opcode;
m_rd = decode_register_index (ival, OP_SH_RD);
- m_imm.s = EXTRACT_UJTYPE_IMM (ival);
+ m_imm.s = EXTRACT_JTYPE_IMM (ival);
}
/* Helper for DECODE, decode 32-bit J-type instruction. */
void decode_cj_type_insn (enum opcode opcode, ULONGEST ival)
{
m_opcode = opcode;
- m_imm.s = EXTRACT_RVC_J_IMM (ival);
+ m_imm.s = EXTRACT_CJTYPE_IMM (ival);
}
void decode_b_type_insn (enum opcode opcode, ULONGEST ival)
m_opcode = opcode;
m_rs1 = decode_register_index (ival, OP_SH_RS1);
m_rs2 = decode_register_index (ival, OP_SH_RS2);
- m_imm.s = EXTRACT_SBTYPE_IMM (ival);
+ m_imm.s = EXTRACT_BTYPE_IMM (ival);
}
void decode_cb_type_insn (enum opcode opcode, ULONGEST ival)
{
m_opcode = opcode;
m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
- m_imm.s = EXTRACT_RVC_B_IMM (ival);
+ m_imm.s = EXTRACT_CBTYPE_IMM (ival);
}
/* Fetch instruction from target memory at ADDR, return the content of
riscv_insn::fetch_instruction (struct gdbarch *gdbarch,
CORE_ADDR addr, int *len)
{
- enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch);
- gdb_byte buf[8];
+ gdb_byte buf[RISCV_MAX_INSN_LEN];
int instlen, status;
/* All insns are at least 16 bits. */
memory_error (TARGET_XFER_E_IO, addr + 2);
}
- return extract_unsigned_integer (buf, instlen, byte_order);
+ /* RISC-V Specification states instructions are always little endian */
+ return extract_unsigned_integer (buf, instlen, BFD_ENDIAN_LITTLE);
}
/* Fetch from target memory an instruction at PC and decode it. This can
decode_r_type_insn (SC, ival);
else if (is_sc_d_insn (ival))
decode_r_type_insn (SC, ival);
+ else if (is_ecall_insn (ival))
+ decode_i_type_insn (ECALL, ival);
+ else if (is_ld_insn (ival))
+ decode_i_type_insn (LD, ival);
+ else if (is_lw_insn (ival))
+ decode_i_type_insn (LW, ival);
else
/* None of the other fields are valid in this case. */
m_opcode = OTHER;
}
else if (m_length == 2)
{
- int xlen = riscv_isa_xlen (gdbarch);
+ int xlen = riscv_isa_xlen (gdbarch);
+
+ /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a
+ C_JALR. So must try to match C_JALR first as it has more bits in
+ mask. */
+ if (is_c_jalr_insn (ival))
+ decode_cr_type_insn (JALR, ival);
+ else if (is_c_add_insn (ival))
+ decode_cr_type_insn (ADD, ival);
+ /* C_ADDW is RV64 and RV128 only. */
+ else if (xlen != 4 && is_c_addw_insn (ival))
+ decode_cr_type_insn (ADDW, ival);
+ else if (is_c_addi_insn (ival))
+ decode_ci_type_insn (ADDI, ival);
+ /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128
+ only and C_JAL is RV32 only. */
+ else if (xlen != 4 && is_c_addiw_insn (ival))
+ decode_ci_type_insn (ADDIW, ival);
+ else if (xlen == 4 && is_c_jal_insn (ival))
+ decode_cj_type_insn (JAL, ival);
+ /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a
+ C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits
+ in mask. */
+ else if (is_c_addi16sp_insn (ival))
+ {
+ m_opcode = ADDI;
+ m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD);
+ m_imm.s = EXTRACT_CITYPE_ADDI16SP_IMM (ival);
+ }
+ else if (is_c_addi4spn_insn (ival))
+ {
+ m_opcode = ADDI;
+ m_rd = decode_register_index_short (ival, OP_SH_CRS2S);
+ m_rs1 = RISCV_SP_REGNUM;
+ m_imm.s = EXTRACT_CIWTYPE_ADDI4SPN_IMM (ival);
+ }
+ else if (is_c_lui_insn (ival))
+ {
+ m_opcode = LUI;
+ m_rd = decode_register_index (ival, OP_SH_CRS1S);
+ m_imm.s = EXTRACT_CITYPE_LUI_IMM (ival);
+ }
+ else if (is_c_li_insn (ival))
+ decode_ci_type_insn (LI, ival);
+ /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only,
+ and C_FSW is RV32 only. */
+ else if (xlen != 4 && is_c_sd_insn (ival))
+ decode_cs_type_insn (SD, ival, EXTRACT_CLTYPE_LD_IMM (ival));
+ else if (is_c_sw_insn (ival))
+ decode_cs_type_insn (SW, ival, EXTRACT_CLTYPE_LW_IMM (ival));
+ else if (is_c_swsp_insn (ival))
+ decode_css_type_insn (SW, ival, EXTRACT_CSSTYPE_SWSP_IMM (ival));
+ else if (xlen != 4 && is_c_sdsp_insn (ival))
+ decode_css_type_insn (SD, ival, EXTRACT_CSSTYPE_SDSP_IMM (ival));
+ /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR.
+ So must try to match C_JR first as it has more bits in mask. */
+ else if (is_c_jr_insn (ival))
+ decode_cr_type_insn (JALR, ival);
+ else if (is_c_mv_insn (ival))
+ decode_cr_type_insn (MV, ival);
+ else if (is_c_j_insn (ival))
+ decode_cj_type_insn (JAL, ival);
+ else if (is_c_beqz_insn (ival))
+ decode_cb_type_insn (BEQ, ival);
+ else if (is_c_bnez_insn (ival))
+ decode_cb_type_insn (BNE, ival);
+ else if (is_c_ld_insn (ival))
+ decode_cl_type_insn (LD, ival);
+ else if (is_c_lw_insn (ival))
+ decode_cl_type_insn (LW, ival);
+ else if (is_c_ldsp_insn (ival))
+ decode_ci_type_insn (LD, ival, RISCV_SP_REGNUM);
+ else if (is_c_lwsp_insn (ival))
+ decode_ci_type_insn (LW, ival, RISCV_SP_REGNUM);
+ else
+ /* None of the other fields of INSN are valid in this case. */
+ m_opcode = OTHER;
+ }
+ else
+ {
+ /* 6 bytes or more. If the instruction is longer than 8 bytes, we don't
+ have full instruction bits in ival. At least, such long instructions
+ are not defined yet, so just ignore it. */
+ gdb_assert (m_length > 0 && m_length % 2 == 0);
+ m_opcode = OTHER;
+ }
+}
+
+/* Return true if INSN represents an instruction something like:
+
+ ld fp,IMMEDIATE(sp)
+
+ That is, a load from stack-pointer plus some immediate offset, with the
+ result stored into the frame pointer. We also accept 'lw' as well as
+ 'ld'. */
+
+static bool
+is_insn_load_of_fp_from_sp (const struct riscv_insn &insn)
+{
+ return ((insn.opcode () == riscv_insn::LD
+ || insn.opcode () == riscv_insn::LW)
+ && insn.rd () == RISCV_FP_REGNUM
+ && insn.rs1 () == RISCV_SP_REGNUM);
+}
+
+/* Return true if INSN represents an instruction something like:
+
+ add sp,sp,IMMEDIATE
+
+ That is, an add of an immediate to the value in the stack pointer
+ register, with the result stored back to the stack pointer register. */
+
+static bool
+is_insn_addi_of_sp_to_sp (const struct riscv_insn &insn)
+{
+ return ((insn.opcode () == riscv_insn::ADDI
+ || insn.opcode () == riscv_insn::ADDIW)
+ && insn.rd () == RISCV_SP_REGNUM
+ && insn.rs1 () == RISCV_SP_REGNUM);
+}
+
+/* Is the instruction in code memory prior to address PC a load from stack
+ instruction? Return true if it is, otherwise, return false.
+
+ This is a best effort that is used as part of the function prologue
+ scanning logic. With compressed instructions and arbitrary control
+ flow in the inferior, we can never be certain what the instruction
+ prior to PC is.
+
+ This function first looks for a compressed instruction, then looks for
+ a 32-bit non-compressed instruction. */
+
+static bool
+previous_insn_is_load_fp_from_stack (struct gdbarch *gdbarch, CORE_ADDR pc)
+{
+ struct riscv_insn insn;
+ insn.decode (gdbarch, pc - 2);
+ gdb_assert (insn.length () > 0);
+
+ if (insn.length () != 2 || !is_insn_load_of_fp_from_sp (insn))
+ {
+ insn.decode (gdbarch, pc - 4);
+ gdb_assert (insn.length () > 0);
+
+ if (insn.length () != 4 || !is_insn_load_of_fp_from_sp (insn))
+ return false;
+ }
+
+ riscv_unwinder_debug_printf
+ ("previous instruction at %s (length %d) was 'ld'",
+ core_addr_to_string (pc - insn.length ()), insn.length ());
+ return true;
+}
+
+/* Is the instruction in code memory prior to address PC an add of an
+ immediate to the stack pointer, with the result being written back into
+ the stack pointer? Return true and set *PREV_PC to the address of the
+ previous instruction if we believe the previous instruction is such an
+ add, otherwise return false and *PREV_PC is undefined.
+
+ This is a best effort that is used as part of the function prologue
+ scanning logic. With compressed instructions and arbitrary control
+ flow in the inferior, we can never be certain what the instruction
+ prior to PC is.
+
+ This function first looks for a compressed instruction, then looks for
+ a 32-bit non-compressed instruction. */
+
+static bool
+previous_insn_is_add_imm_to_sp (struct gdbarch *gdbarch, CORE_ADDR pc,
+ CORE_ADDR *prev_pc)
+{
+ struct riscv_insn insn;
+ insn.decode (gdbarch, pc - 2);
+ gdb_assert (insn.length () > 0);
+
+ if (insn.length () != 2 || !is_insn_addi_of_sp_to_sp (insn))
+ {
+ insn.decode (gdbarch, pc - 4);
+ gdb_assert (insn.length () > 0);
+
+ if (insn.length () != 4 || !is_insn_addi_of_sp_to_sp (insn))
+ return false;
+ }
+
+ riscv_unwinder_debug_printf
+ ("previous instruction at %s (length %d) was 'add'",
+ core_addr_to_string (pc - insn.length ()), insn.length ());
+ *prev_pc = pc - insn.length ();
+ return true;
+}
+
+/* Try to spot when PC is located in an exit sequence for a particular
+ function. Detecting an exit sequence involves a limited amount of
+ scanning backwards through the disassembly, and so, when considering
+ compressed instructions, we can never be certain that we have
+ disassembled the preceding instructions correctly. On top of that, we
+ can't be certain that the inferior arrived at PC by passing through the
+ preceding instructions.
+
+ With all that said, we know that using prologue scanning to figure a
+ functions unwind information starts to fail when we consider returns
+ from an instruction -- we must pass through some instructions that
+ restore the previous state prior to the final return instruction, and
+ with state partially restored, our prologue derived unwind information
+ is no longer valid.
+
+ This function then, aims to spot instruction sequences like this:
+
+ ld fp, IMM_1(sp)
+ add sp, sp, IMM_2
+ ret
+
+ The first instruction restores the previous frame-pointer value, the
+ second restores the previous stack pointer value, and the final
+ instruction is the actual return.
+
+ We need to consider that some or all of these instructions might be
+ compressed.
+
+ This function makes the assumption that, when the inferior reaches the
+ 'ret' instruction the stack pointer will have been restored to its value
+ on entry to this function. This assumption will be true in most well
+ formed programs.
+
+ Return true if we detect that we are in such an instruction sequence,
+ that is PC points at one of the three instructions given above. In this
+ case, set *OFFSET to IMM_2 if PC points to either of the first
+ two instructions (the 'ld' or 'add'), otherwise set *OFFSET to 0.
+
+ Otherwise, this function returns false, and the contents of *OFFSET are
+ undefined. */
+
+static bool
+riscv_detect_end_of_function (struct gdbarch *gdbarch, CORE_ADDR pc,
+ int *offset)
+{
+ *offset = 0;
+
+ /* We only want to scan a maximum of 3 instructions. */
+ for (int i = 0; i < 3; ++i)
+ {
+ struct riscv_insn insn;
+ insn.decode (gdbarch, pc);
+ gdb_assert (insn.length () > 0);
- /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a
- C_JALR. So must try to match C_JALR first as it has more bits in
- mask. */
- if (is_c_jalr_insn (ival))
- decode_cr_type_insn (JALR, ival);
- else if (is_c_add_insn (ival))
- decode_cr_type_insn (ADD, ival);
- /* C_ADDW is RV64 and RV128 only. */
- else if (xlen != 4 && is_c_addw_insn (ival))
- decode_cr_type_insn (ADDW, ival);
- else if (is_c_addi_insn (ival))
- decode_ci_type_insn (ADDI, ival);
- /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128
- only and C_JAL is RV32 only. */
- else if (xlen != 4 && is_c_addiw_insn (ival))
- decode_ci_type_insn (ADDIW, ival);
- else if (xlen == 4 && is_c_jal_insn (ival))
- decode_cj_type_insn (JAL, ival);
- /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a
- C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits
- in mask. */
- else if (is_c_addi16sp_insn (ival))
+ if (is_insn_load_of_fp_from_sp (insn))
{
- m_opcode = ADDI;
- m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD);
- m_imm.s = EXTRACT_RVC_ADDI16SP_IMM (ival);
+ riscv_unwinder_debug_printf ("found 'ld' instruction at %s",
+ core_addr_to_string (pc));
+ if (i > 0)
+ return false;
+ pc += insn.length ();
}
- else if (is_c_addi4spn_insn (ival))
+ else if (is_insn_addi_of_sp_to_sp (insn))
{
- m_opcode = ADDI;
- m_rd = decode_register_index_short (ival, OP_SH_CRS2S);
- m_rs1 = RISCV_SP_REGNUM;
- m_imm.s = EXTRACT_RVC_ADDI4SPN_IMM (ival);
+ riscv_unwinder_debug_printf ("found 'add' instruction at %s",
+ core_addr_to_string (pc));
+ if (i > 1)
+ return false;
+ if (i == 0)
+ {
+ if (!previous_insn_is_load_fp_from_stack (gdbarch, pc))
+ return false;
+
+ i = 1;
+ }
+ *offset = insn.imm_signed ();
+ pc += insn.length ();
+ }
+ else if (insn.opcode () == riscv_insn::JALR
+ && insn.rs1 () == RISCV_RA_REGNUM
+ && insn.rs2 () == RISCV_ZERO_REGNUM)
+ {
+ riscv_unwinder_debug_printf ("found 'ret' instruction at %s",
+ core_addr_to_string (pc));
+ gdb_assert (i != 1);
+ if (i == 0)
+ {
+ CORE_ADDR prev_pc;
+ if (!previous_insn_is_add_imm_to_sp (gdbarch, pc, &prev_pc))
+ return false;
+ if (!previous_insn_is_load_fp_from_stack (gdbarch, prev_pc))
+ return false;
+ i = 2;
+ }
+
+ pc += insn.length ();
}
- else if (is_c_lui_insn (ival))
- {
- m_opcode = LUI;
- m_rd = decode_register_index (ival, OP_SH_CRS1S);
- m_imm.s = EXTRACT_RVC_LUI_IMM (ival);
- }
- /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only,
- and C_FSW is RV32 only. */
- else if (xlen != 4 && is_c_sd_insn (ival))
- decode_cs_type_insn (SD, ival, EXTRACT_RVC_LD_IMM (ival));
- else if (is_c_sw_insn (ival))
- decode_cs_type_insn (SW, ival, EXTRACT_RVC_LW_IMM (ival));
- else if (is_c_swsp_insn (ival))
- decode_css_type_insn (SW, ival, EXTRACT_RVC_SWSP_IMM (ival));
- else if (xlen != 4 && is_c_sdsp_insn (ival))
- decode_css_type_insn (SW, ival, EXTRACT_RVC_SDSP_IMM (ival));
- /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR.
- So must try to match C_JR first as it ahs more bits in mask. */
- else if (is_c_jr_insn (ival))
- decode_cr_type_insn (JALR, ival);
- else if (is_c_j_insn (ival))
- decode_cj_type_insn (JAL, ival);
- else if (is_c_beqz_insn (ival))
- decode_cb_type_insn (BEQ, ival);
- else if (is_c_bnez_insn (ival))
- decode_cb_type_insn (BNE, ival);
else
- /* None of the other fields of INSN are valid in this case. */
- m_opcode = OTHER;
- }
- else
- {
- /* This must be a 6 or 8 byte instruction, we don't currently decode
- any of these, so just ignore it. */
- gdb_assert (m_length == 6 || m_length == 8);
- m_opcode = OTHER;
+ return false;
}
+
+ return true;
}
/* The prologue scanner. This is currently only used for skipping the
struct riscv_unwind_cache *cache)
{
CORE_ADDR cur_pc, next_pc, after_prologue_pc;
+ CORE_ADDR original_end_pc = end_pc;
CORE_ADDR end_prologue_addr = 0;
/* Find an upper limit on the function prologue using the debug
regs[regno] = pv_register (regno, 0);
pv_area stack (RISCV_SP_REGNUM, gdbarch_addr_bit (gdbarch));
- if (riscv_debug_unwinder)
- fprintf_unfiltered
- (gdb_stdlog,
- "Prologue scan for function starting at %s (limit %s)\n",
- core_addr_to_string (start_pc),
- core_addr_to_string (end_pc));
+ riscv_unwinder_debug_printf ("function starting at %s (limit %s)",
+ core_addr_to_string (start_pc),
+ core_addr_to_string (end_pc));
for (next_pc = cur_pc = start_pc; cur_pc < end_pc; cur_pc = next_pc)
{
next_pc = cur_pc + insn.length ();
/* Look for common stack adjustment insns. */
- if ((insn.opcode () == riscv_insn::ADDI
- || insn.opcode () == riscv_insn::ADDIW)
- && insn.rd () == RISCV_SP_REGNUM
- && insn.rs1 () == RISCV_SP_REGNUM)
+ if (is_insn_addi_of_sp_to_sp (insn))
{
/* Handle: addi sp, sp, -i
or: addiw sp, sp, -i */
- gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
- gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
- regs[insn.rd ()]
- = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
+ gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
+ gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
+ regs[insn.rd ()]
+ = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
}
else if ((insn.opcode () == riscv_insn::SW
|| insn.opcode () == riscv_insn::SD)
or: sw reg, offset(s0)
or: sd reg, offset(s0) */
/* Instruction storing a register onto the stack. */
- gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
- gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS);
- stack.store (pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()),
- (insn.opcode () == riscv_insn::SW ? 4 : 8),
- regs[insn.rs2 ()]);
+ gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
+ gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS);
+ stack.store (pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()),
+ (insn.opcode () == riscv_insn::SW ? 4 : 8),
+ regs[insn.rs2 ()]);
}
else if (insn.opcode () == riscv_insn::ADDI
&& insn.rd () == RISCV_FP_REGNUM
{
/* Handle: addi s0, sp, size */
/* Instructions setting up the frame pointer. */
- gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
- gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
- regs[insn.rd ()]
- = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
+ gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
+ gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
+ regs[insn.rd ()]
+ = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
}
else if ((insn.opcode () == riscv_insn::ADD
|| insn.opcode () == riscv_insn::ADDW)
/* Handle: add s0, sp, 0
or: addw s0, sp, 0 */
/* Instructions setting up the frame pointer. */
- gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
- gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
- regs[insn.rd ()] = pv_add_constant (regs[insn.rs1 ()], 0);
+ gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
+ gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
+ regs[insn.rd ()] = pv_add_constant (regs[insn.rs1 ()], 0);
}
else if ((insn.opcode () == riscv_insn::ADDI
- && insn.rd () == RISCV_ZERO_REGNUM
- && insn.rs1 () == RISCV_ZERO_REGNUM
- && insn.imm_signed () == 0))
+ && insn.rd () == RISCV_ZERO_REGNUM
+ && insn.rs1 () == RISCV_ZERO_REGNUM
+ && insn.imm_signed () == 0))
{
/* Handle: add x0, x0, 0 (NOP) */
}
else if (insn.opcode () == riscv_insn::AUIPC)
- {
- gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
- regs[insn.rd ()] = pv_constant (cur_pc + insn.imm_signed ());
- }
- else if (insn.opcode () == riscv_insn::LUI)
- {
+ {
+ gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
+ regs[insn.rd ()] = pv_constant (cur_pc + insn.imm_signed ());
+ }
+ else if (insn.opcode () == riscv_insn::LUI
+ || insn.opcode () == riscv_insn::LI)
+ {
/* Handle: lui REG, n
- Where REG is not gp register. */
- gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
- regs[insn.rd ()] = pv_constant (insn.imm_signed ());
- }
+ or: li REG, n */
+ gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
+ regs[insn.rd ()] = pv_constant (insn.imm_signed ());
+ }
else if (insn.opcode () == riscv_insn::ADDI)
- {
- /* Handle: addi REG1, REG2, IMM */
- gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
- gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
- regs[insn.rd ()]
- = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
- }
+ {
+ /* Handle: addi REG1, REG2, IMM */
+ gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
+ gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
+ regs[insn.rd ()]
+ = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
+ }
else if (insn.opcode () == riscv_insn::ADD)
- {
- /* Handle: addi REG1, REG2, IMM */
- gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
- gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
- gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS);
- regs[insn.rd ()] = pv_add (regs[insn.rs1 ()], regs[insn.rs2 ()]);
- }
+ {
+ /* Handle: add REG1, REG2, REG3 */
+ gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
+ gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
+ gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS);
+ regs[insn.rd ()] = pv_add (regs[insn.rs1 ()], regs[insn.rs2 ()]);
+ }
+ else if (insn.opcode () == riscv_insn::LD
+ || insn.opcode () == riscv_insn::LW)
+ {
+ /* Handle: ld reg, offset(rs1)
+ or: c.ld reg, offset(rs1)
+ or: lw reg, offset(rs1)
+ or: c.lw reg, offset(rs1) */
+ gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
+ gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
+ regs[insn.rd ()]
+ = stack.fetch (pv_add_constant (regs[insn.rs1 ()],
+ insn.imm_signed ()),
+ (insn.opcode () == riscv_insn::LW ? 4 : 8));
+ }
+ else if (insn.opcode () == riscv_insn::MV)
+ {
+ /* Handle: c.mv RD, RS2 */
+ gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
+ gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS);
+ gdb_assert (insn.rs2 () > 0);
+ regs[insn.rd ()] = regs[insn.rs2 ()];
+ }
else
{
end_prologue_addr = cur_pc;
if (end_prologue_addr == 0)
end_prologue_addr = cur_pc;
- if (riscv_debug_unwinder)
- fprintf_unfiltered (gdb_stdlog, "End of prologue at %s\n",
- core_addr_to_string (end_prologue_addr));
+ riscv_unwinder_debug_printf ("end of prologue at %s",
+ core_addr_to_string (end_prologue_addr));
if (cache != NULL)
{
/* Figure out if it is a frame pointer or just a stack pointer. Also
- the offset held in the pv_t is from the original register value to
- the current value, which for a grows down stack means a negative
- value. The FRAME_BASE_OFFSET is the negation of this, how to get
- from the current value to the original value. */
+ the offset held in the pv_t is from the original register value to
+ the current value, which for a grows down stack means a negative
+ value. The FRAME_BASE_OFFSET is the negation of this, how to get
+ from the current value to the original value. */
if (pv_is_register (regs[RISCV_FP_REGNUM], RISCV_SP_REGNUM))
{
- cache->frame_base_reg = RISCV_FP_REGNUM;
- cache->frame_base_offset = -regs[RISCV_FP_REGNUM].k;
+ cache->frame_base_reg = RISCV_FP_REGNUM;
+ cache->frame_base_offset = -regs[RISCV_FP_REGNUM].k;
}
else
{
- cache->frame_base_reg = RISCV_SP_REGNUM;
- cache->frame_base_offset = -regs[RISCV_SP_REGNUM].k;
+ cache->frame_base_reg = RISCV_SP_REGNUM;
+ cache->frame_base_offset = -regs[RISCV_SP_REGNUM].k;
+ }
+
+ /* Check to see if we are located near to a return instruction in
+ this function. If we are then the one or both of the stack
+ pointer and frame pointer may have been restored to their previous
+ value. If we can spot this situation then we can adjust which
+ register and offset we use for the frame base. */
+ if (cache->frame_base_reg != RISCV_SP_REGNUM
+ || cache->frame_base_offset != 0)
+ {
+ int sp_offset;
+
+ if (riscv_detect_end_of_function (gdbarch, original_end_pc,
+ &sp_offset))
+ {
+ riscv_unwinder_debug_printf
+ ("in function epilogue at %s, stack offset is %d",
+ core_addr_to_string (original_end_pc), sp_offset);
+ cache->frame_base_reg= RISCV_SP_REGNUM;
+ cache->frame_base_offset = sp_offset;
+ }
}
/* Assign offset from old SP to all saved registers. As we don't
- have the previous value for the frame base register at this
- point, we store the offset as the address in the trad_frame, and
- then convert this to an actual address later. */
+ have the previous value for the frame base register at this
+ point, we store the offset as the address in the trad_frame, and
+ then convert this to an actual address later. */
for (int i = 0; i <= RISCV_NUM_INTEGER_REGS; i++)
{
CORE_ADDR offset;
if (stack.find_reg (gdbarch, i, &offset))
- {
- if (riscv_debug_unwinder)
- {
- /* Display OFFSET as a signed value, the offsets are from
- the frame base address to the registers location on
- the stack, with a descending stack this means the
- offsets are always negative. */
- fprintf_unfiltered (gdb_stdlog,
- "Register $%s at stack offset %s\n",
- gdbarch_register_name (gdbarch, i),
- plongest ((LONGEST) offset));
- }
- trad_frame_set_addr (cache->regs, i, offset);
- }
+ {
+ /* Display OFFSET as a signed value, the offsets are from the
+ frame base address to the registers location on the stack,
+ with a descending stack this means the offsets are always
+ negative. */
+ riscv_unwinder_debug_printf ("register $%s at stack offset %s",
+ gdbarch_register_name (gdbarch, i),
+ plongest ((LONGEST) offset));
+ cache->regs[i].set_addr (offset);
+ }
}
}
there will be no need to write to memory later. */
int status = target_write_memory (*bp_addr, nop_insn, sizeof (nop_insn));
- if (riscv_debug_breakpoints || riscv_debug_infcall)
- fprintf_unfiltered (gdb_stdlog,
- "Writing %s-byte nop instruction to %s: %s\n",
- plongest (sizeof (nop_insn)),
- paddress (gdbarch, *bp_addr),
- (status == 0 ? "success" : "failed"));
+ riscv_infcall_debug_printf ("writing %s-byte nop instruction to %s: %s",
+ plongest (sizeof (nop_insn)),
+ paddress (gdbarch, *bp_addr),
+ (status == 0 ? "success" : "failed"));
return sp;
}
riscv_type_align (gdbarch *gdbarch, type *type)
{
type = check_typedef (type);
- if (type->code () == TYPE_CODE_ARRAY && TYPE_VECTOR (type))
- return std::min (TYPE_LENGTH (type), (ULONGEST) BIGGEST_ALIGNMENT);
+ if (type->code () == TYPE_CODE_ARRAY && type->is_vector ())
+ return std::min (type->length (), (ULONGEST) BIGGEST_ALIGNMENT);
/* Anything else will be aligned by the generic code. */
return 0;
xlen = riscv_abi_xlen (gdbarch);
flen = riscv_abi_flen (gdbarch);
+ /* Reduce the number of integer argument registers when using the
+ embedded abi (i.e. rv32e). */
+ if (riscv_abi_embedded (gdbarch))
+ int_regs.last_regnum = RISCV_A0_REGNUM + 5;
+
/* Disable use of floating point registers if needed. */
if (!riscv_has_fp_abi (gdbarch))
float_regs.next_regnum = float_regs.last_regnum + 1;
riscv_call_arg_scalar_int (struct riscv_arg_info *ainfo,
struct riscv_call_info *cinfo)
{
- if (ainfo->length > (2 * cinfo->xlen))
+ if (TYPE_HAS_DYNAMIC_LENGTH (ainfo->type)
+ || ainfo->length > (2 * cinfo->xlen))
{
/* Argument is going to be passed by reference. */
ainfo->argloc[0].loc_type
for (i = 0; i < count; ++i)
{
- if (TYPE_FIELD_LOC_KIND (type, i) != FIELD_LOC_KIND_BITPOS)
+ if (type->field (i).loc_kind () != FIELD_LOC_KIND_BITPOS)
continue;
struct type *field_type = type->field (i).type ();
field_type = check_typedef (field_type);
int field_offset
- = offset + TYPE_FIELD_BITPOS (type, i) / TARGET_CHAR_BIT;
+ = offset + type->field (i).loc_bitpos () / TARGET_CHAR_BIT;
switch (field_type->code ())
{
except we use the type of the complex field instead of the
type from AINFO, and the first location might be at a non-zero
offset. */
- if (TYPE_LENGTH (sinfo.field_type (0)) <= (2 * cinfo->flen)
+ if (sinfo.field_type (0)->length () <= (2 * cinfo->flen)
&& riscv_arg_regs_available (&cinfo->float_regs) >= 2
&& !ainfo->is_unnamed)
{
bool result;
- int len = TYPE_LENGTH (sinfo.field_type (0)) / 2;
+ int len = sinfo.field_type (0)->length () / 2;
int offset = sinfo.field_offset (0);
result = riscv_assign_reg_location (&ainfo->argloc[0],
except we use the type of the first scalar field instead of
the type from AINFO. Also the location might be at a non-zero
offset. */
- if (TYPE_LENGTH (sinfo.field_type (0)) > cinfo->flen
+ if (sinfo.field_type (0)->length () > cinfo->flen
|| ainfo->is_unnamed)
riscv_call_arg_scalar_int (ainfo, cinfo);
else
{
int offset = sinfo.field_offset (0);
- int len = TYPE_LENGTH (sinfo.field_type (0));
+ int len = sinfo.field_type (0)->length ();
if (!riscv_assign_reg_location (&ainfo->argloc[0],
&cinfo->float_regs,
if (sinfo.number_of_fields () == 2
&& sinfo.field_type(0)->code () == TYPE_CODE_FLT
- && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen
+ && sinfo.field_type (0)->length () <= cinfo->flen
&& sinfo.field_type(1)->code () == TYPE_CODE_FLT
- && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen
+ && sinfo.field_type (1)->length () <= cinfo->flen
&& riscv_arg_regs_available (&cinfo->float_regs) >= 2)
{
- int len0 = TYPE_LENGTH (sinfo.field_type (0));
+ int len0 = sinfo.field_type (0)->length ();
int offset = sinfo.field_offset (0);
if (!riscv_assign_reg_location (&ainfo->argloc[0],
&cinfo->float_regs, len0, offset))
error (_("failed during argument setup"));
- int len1 = TYPE_LENGTH (sinfo.field_type (1));
+ int len1 = sinfo.field_type (1)->length ();
offset = sinfo.field_offset (1);
- gdb_assert (len1 <= (TYPE_LENGTH (ainfo->type)
- - TYPE_LENGTH (sinfo.field_type (0))));
+ gdb_assert (len1 <= (ainfo->type->length ()
+ - sinfo.field_type (0)->length ()));
if (!riscv_assign_reg_location (&ainfo->argloc[1],
&cinfo->float_regs,
if (sinfo.number_of_fields () == 2
&& riscv_arg_regs_available (&cinfo->int_regs) >= 1
&& (sinfo.field_type(0)->code () == TYPE_CODE_FLT
- && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen
+ && sinfo.field_type (0)->length () <= cinfo->flen
&& is_integral_type (sinfo.field_type (1))
- && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->xlen))
+ && sinfo.field_type (1)->length () <= cinfo->xlen))
{
- int len0 = TYPE_LENGTH (sinfo.field_type (0));
+ int len0 = sinfo.field_type (0)->length ();
int offset = sinfo.field_offset (0);
if (!riscv_assign_reg_location (&ainfo->argloc[0],
&cinfo->float_regs, len0, offset))
error (_("failed during argument setup"));
- int len1 = TYPE_LENGTH (sinfo.field_type (1));
+ int len1 = sinfo.field_type (1)->length ();
offset = sinfo.field_offset (1);
gdb_assert (len1 <= cinfo->xlen);
if (!riscv_assign_reg_location (&ainfo->argloc[1],
if (sinfo.number_of_fields () == 2
&& riscv_arg_regs_available (&cinfo->int_regs) >= 1
&& (is_integral_type (sinfo.field_type (0))
- && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->xlen
+ && sinfo.field_type (0)->length () <= cinfo->xlen
&& sinfo.field_type(1)->code () == TYPE_CODE_FLT
- && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen))
+ && sinfo.field_type (1)->length () <= cinfo->flen))
{
- int len0 = TYPE_LENGTH (sinfo.field_type (0));
- int len1 = TYPE_LENGTH (sinfo.field_type (1));
+ int len0 = sinfo.field_type (0)->length ();
+ int len1 = sinfo.field_type (1)->length ();
gdb_assert (len0 <= cinfo->xlen);
gdb_assert (len1 <= cinfo->flen);
struct type *type, bool is_unnamed)
{
ainfo->type = type;
- ainfo->length = TYPE_LENGTH (ainfo->type);
+ ainfo->length = ainfo->type->length ();
ainfo->align = type_align (ainfo->type);
ainfo->is_unnamed = is_unnamed;
ainfo->contents = nullptr;
case TYPE_CODE_RANGE:
case TYPE_CODE_ENUM:
case TYPE_CODE_PTR:
+ case TYPE_CODE_FIXED_POINT:
if (ainfo->length <= cinfo->xlen)
{
ainfo->type = builtin_type (gdbarch)->builtin_long;
break;
case TYPE_CODE_STRUCT:
- riscv_call_arg_struct (ainfo, cinfo);
- break;
+ if (!TYPE_HAS_DYNAMIC_LENGTH (ainfo->type))
+ {
+ riscv_call_arg_struct (ainfo, cinfo);
+ break;
+ }
+ /* FALLTHROUGH */
default:
riscv_call_arg_scalar_int (ainfo, cinfo);
struct riscv_arg_info *info,
CORE_ADDR sp_refs, CORE_ADDR sp_args)
{
- fprintf_unfiltered (stream, "type: '%s', length: 0x%x, alignment: 0x%x",
- TYPE_SAFE_NAME (info->type), info->length, info->align);
+ gdb_printf (stream, "type: '%s', length: 0x%x, alignment: 0x%x",
+ TYPE_SAFE_NAME (info->type), info->length, info->align);
switch (info->argloc[0].loc_type)
{
case riscv_arg_info::location::in_reg:
- fprintf_unfiltered
+ gdb_printf
(stream, ", register %s",
gdbarch_register_name (gdbarch, info->argloc[0].loc_data.regno));
if (info->argloc[0].c_length < info->length)
switch (info->argloc[1].loc_type)
{
case riscv_arg_info::location::in_reg:
- fprintf_unfiltered
+ gdb_printf
(stream, ", register %s",
gdbarch_register_name (gdbarch,
info->argloc[1].loc_data.regno));
break;
case riscv_arg_info::location::on_stack:
- fprintf_unfiltered (stream, ", on stack at offset 0x%x",
- info->argloc[1].loc_data.offset);
+ gdb_printf (stream, ", on stack at offset 0x%x",
+ info->argloc[1].loc_data.offset);
break;
case riscv_arg_info::location::by_ref:
}
if (info->argloc[1].c_offset > info->argloc[0].c_length)
- fprintf_unfiltered (stream, " (offset 0x%x)",
- info->argloc[1].c_offset);
+ gdb_printf (stream, " (offset 0x%x)",
+ info->argloc[1].c_offset);
}
break;
case riscv_arg_info::location::on_stack:
- fprintf_unfiltered (stream, ", on stack at offset 0x%x",
- info->argloc[0].loc_data.offset);
+ gdb_printf (stream, ", on stack at offset 0x%x",
+ info->argloc[0].loc_data.offset);
break;
case riscv_arg_info::location::by_ref:
- fprintf_unfiltered
+ gdb_printf
(stream, ", by reference, data at offset 0x%x (%s)",
info->argloc[0].loc_data.offset,
core_addr_to_string (sp_refs + info->argloc[0].loc_data.offset));
if (info->argloc[1].loc_type
== riscv_arg_info::location::in_reg)
- fprintf_unfiltered
+ gdb_printf
(stream, ", address in register %s",
gdbarch_register_name (gdbarch, info->argloc[1].loc_data.regno));
else
{
gdb_assert (info->argloc[1].loc_type
== riscv_arg_info::location::on_stack);
- fprintf_unfiltered
+ gdb_printf
(stream, ", address on stack at offset 0x%x (%s)",
info->argloc[1].loc_data.offset,
core_addr_to_string (sp_args + info->argloc[1].loc_data.offset));
break;
default:
- gdb_assert_not_reached (_("unknown argument location type"));
+ gdb_assert_not_reached ("unknown argument location type");
}
}
CORE_ADDR osp = sp;
- struct type *ftype = check_typedef (value_type (function));
+ struct type *ftype = check_typedef (function->type ());
if (ftype->code () == TYPE_CODE_PTR)
- ftype = check_typedef (TYPE_TARGET_TYPE (ftype));
+ ftype = check_typedef (ftype->target_type ());
/* We'll use register $a0 if we're returning a struct. */
if (return_method == return_method_struct)
struct riscv_arg_info *info = &arg_info[i];
arg_value = args[i];
- arg_type = check_typedef (value_type (arg_value));
+ arg_type = check_typedef (arg_value->type ());
riscv_arg_location (gdbarch, info, &call_info, arg_type,
- TYPE_VARARGS (ftype) && i >= ftype->num_fields ());
+ ftype->has_varargs () && i >= ftype->num_fields ());
if (info->type != arg_type)
arg_value = value_cast (info->type, arg_value);
- info->contents = value_contents (arg_value);
+ info->contents = arg_value->contents ().data ();
}
/* Adjust the stack pointer and align it. */
sp = sp_refs = align_down (sp - call_info.memory.ref_offset, SP_ALIGNMENT);
sp = sp_args = align_down (sp - call_info.memory.arg_offset, SP_ALIGNMENT);
- if (riscv_debug_infcall > 0)
+ if (riscv_debug_infcall)
{
- fprintf_unfiltered (gdb_stdlog, "dummy call args:\n");
- fprintf_unfiltered (gdb_stdlog, ": floating point ABI %s in use\n",
- (riscv_has_fp_abi (gdbarch) ? "is" : "is not"));
- fprintf_unfiltered (gdb_stdlog, ": xlen: %d\n: flen: %d\n",
- call_info.xlen, call_info.flen);
+ RISCV_INFCALL_SCOPED_DEBUG_START_END ("dummy call args");
+ riscv_infcall_debug_printf ("floating point ABI %s in use",
+ (riscv_has_fp_abi (gdbarch)
+ ? "is" : "is not"));
+ riscv_infcall_debug_printf ("xlen: %d", call_info.xlen);
+ riscv_infcall_debug_printf ("flen: %d", call_info.flen);
if (return_method == return_method_struct)
- fprintf_unfiltered (gdb_stdlog,
- "[*] struct return pointer in register $A0\n");
+ riscv_infcall_debug_printf
+ ("[**] struct return pointer in register $A0");
for (i = 0; i < nargs; ++i)
{
struct riscv_arg_info *info = &arg_info [i];
+ string_file tmp;
- fprintf_unfiltered (gdb_stdlog, "[%2d] ", i);
- riscv_print_arg_location (gdb_stdlog, gdbarch, info, sp_refs, sp_args);
- fprintf_unfiltered (gdb_stdlog, "\n");
+ riscv_print_arg_location (&tmp, gdbarch, info, sp_refs, sp_args);
+ riscv_infcall_debug_printf ("[%2d] %s", i, tmp.string ().c_str ());
}
if (call_info.memory.arg_offset > 0
|| call_info.memory.ref_offset > 0)
{
- fprintf_unfiltered (gdb_stdlog, " Original sp: %s\n",
- core_addr_to_string (osp));
- fprintf_unfiltered (gdb_stdlog, "Stack required (for args): 0x%x\n",
- call_info.memory.arg_offset);
- fprintf_unfiltered (gdb_stdlog, "Stack required (for refs): 0x%x\n",
- call_info.memory.ref_offset);
- fprintf_unfiltered (gdb_stdlog, " Stack allocated: %s\n",
- core_addr_to_string_nz (osp - sp));
+ riscv_infcall_debug_printf (" Original sp: %s",
+ core_addr_to_string (osp));
+ riscv_infcall_debug_printf ("Stack required (for args): 0x%x",
+ call_info.memory.arg_offset);
+ riscv_infcall_debug_printf ("Stack required (for refs): 0x%x",
+ call_info.memory.ref_offset);
+ riscv_infcall_debug_printf (" Stack allocated: %s",
+ core_addr_to_string_nz (osp - sp));
}
}
break;
default:
- gdb_assert_not_reached (_("unknown argument location type"));
+ gdb_assert_not_reached ("unknown argument location type");
}
if (second_arg_length > 0)
/* Set the dummy return value to bp_addr.
A dummy breakpoint will be setup to execute the call. */
- if (riscv_debug_infcall > 0)
- fprintf_unfiltered (gdb_stdlog, ": writing $ra = %s\n",
- core_addr_to_string (bp_addr));
+ riscv_infcall_debug_printf ("writing $ra = %s",
+ core_addr_to_string (bp_addr));
regcache_cooked_write_unsigned (regcache, RISCV_RA_REGNUM, bp_addr);
/* Finally, update the stack pointer. */
- if (riscv_debug_infcall > 0)
- fprintf_unfiltered (gdb_stdlog, ": writing $sp = %s\n",
- core_addr_to_string (sp));
+ riscv_infcall_debug_printf ("writing $sp = %s", core_addr_to_string (sp));
regcache_cooked_write_unsigned (regcache, RISCV_SP_REGNUM, sp);
return sp;
struct value *function,
struct type *type,
struct regcache *regcache,
- gdb_byte *readbuf,
+ struct value **read_value,
const gdb_byte *writebuf)
{
struct riscv_call_info call_info (gdbarch);
arg_type = check_typedef (type);
riscv_arg_location (gdbarch, &info, &call_info, arg_type, false);
- if (riscv_debug_infcall > 0)
+ if (riscv_debug_infcall)
{
- fprintf_unfiltered (gdb_stdlog, "riscv return value:\n");
- fprintf_unfiltered (gdb_stdlog, "[R] ");
- riscv_print_arg_location (gdb_stdlog, gdbarch, &info, 0, 0);
- fprintf_unfiltered (gdb_stdlog, "\n");
+ string_file tmp;
+ riscv_print_arg_location (&tmp, gdbarch, &info, 0, 0);
+ riscv_infcall_debug_printf ("[R] %s", tmp.string ().c_str ());
}
- if (readbuf != nullptr || writebuf != nullptr)
+ if (read_value != nullptr || writebuf != nullptr)
{
- unsigned int arg_len;
- struct value *abi_val;
- gdb_byte *old_readbuf = nullptr;
- int regnum;
+ unsigned int arg_len;
+ struct value *abi_val;
+ gdb_byte *readbuf = nullptr;
+ int regnum;
+
+ /* We only do one thing at a time. */
+ gdb_assert (read_value == nullptr || writebuf == nullptr);
+
+ /* In some cases the argument is not returned as the declared type,
+ and we need to cast to or from the ABI type in order to
+ correctly access the argument. When writing to the machine we
+ do the cast here, when reading from the machine the cast occurs
+ later, after extracting the value. As the ABI type can be
+ larger than the declared type, then the read or write buffers
+ passed in might be too small. Here we ensure that we are using
+ buffers of sufficient size. */
+ if (writebuf != nullptr)
+ {
+ struct value *arg_val;
- /* We only do one thing at a time. */
- gdb_assert (readbuf == nullptr || writebuf == nullptr);
+ if (is_fixed_point_type (arg_type))
+ {
+ /* Convert the argument to the type used to pass
+ the return value, but being careful to preserve
+ the fact that the value needs to be returned
+ unscaled. */
+ gdb_mpz unscaled;
+
+ unscaled.read (gdb::make_array_view (writebuf,
+ arg_type->length ()),
+ type_byte_order (arg_type),
+ arg_type->is_unsigned ());
+ abi_val = value::allocate (info.type);
+ unscaled.write (abi_val->contents_raw (),
+ type_byte_order (info.type),
+ info.type->is_unsigned ());
+ }
+ else
+ {
+ arg_val = value_from_contents (arg_type, writebuf);
+ abi_val = value_cast (info.type, arg_val);
+ }
+ writebuf = abi_val->contents_raw ().data ();
+ }
+ else
+ {
+ abi_val = value::allocate (info.type);
+ readbuf = abi_val->contents_raw ().data ();
+ }
+ arg_len = info.type->length ();
- /* In some cases the argument is not returned as the declared type,
- and we need to cast to or from the ABI type in order to
- correctly access the argument. When writing to the machine we
- do the cast here, when reading from the machine the cast occurs
- later, after extracting the value. As the ABI type can be
- larger than the declared type, then the read or write buffers
- passed in might be too small. Here we ensure that we are using
- buffers of sufficient size. */
- if (writebuf != nullptr)
- {
- struct value *arg_val = value_from_contents (arg_type, writebuf);
- abi_val = value_cast (info.type, arg_val);
- writebuf = value_contents_raw (abi_val);
- }
- else
+ switch (info.argloc[0].loc_type)
+ {
+ /* Return value in register(s). */
+ case riscv_arg_info::location::in_reg:
{
- abi_val = allocate_value (info.type);
- old_readbuf = readbuf;
- readbuf = value_contents_raw (abi_val);
+ regnum = info.argloc[0].loc_data.regno;
+ gdb_assert (info.argloc[0].c_length <= arg_len);
+ gdb_assert (info.argloc[0].c_length
+ <= register_size (gdbarch, regnum));
+
+ if (readbuf)
+ {
+ gdb_byte *ptr = readbuf + info.argloc[0].c_offset;
+ regcache->cooked_read_part (regnum, 0,
+ info.argloc[0].c_length,
+ ptr);
+ }
+
+ if (writebuf)
+ {
+ const gdb_byte *ptr = writebuf + info.argloc[0].c_offset;
+ riscv_regcache_cooked_write (regnum, ptr,
+ info.argloc[0].c_length,
+ regcache, call_info.flen);
+ }
+
+ /* A return value in register can have a second part in a
+ second register. */
+ if (info.argloc[1].c_length > 0)
+ {
+ switch (info.argloc[1].loc_type)
+ {
+ case riscv_arg_info::location::in_reg:
+ regnum = info.argloc[1].loc_data.regno;
+
+ gdb_assert ((info.argloc[0].c_length
+ + info.argloc[1].c_length) <= arg_len);
+ gdb_assert (info.argloc[1].c_length
+ <= register_size (gdbarch, regnum));
+
+ if (readbuf)
+ {
+ readbuf += info.argloc[1].c_offset;
+ regcache->cooked_read_part (regnum, 0,
+ info.argloc[1].c_length,
+ readbuf);
+ }
+
+ if (writebuf)
+ {
+ const gdb_byte *ptr
+ = writebuf + info.argloc[1].c_offset;
+ riscv_regcache_cooked_write
+ (regnum, ptr, info.argloc[1].c_length,
+ regcache, call_info.flen);
+ }
+ break;
+
+ case riscv_arg_info::location::by_ref:
+ case riscv_arg_info::location::on_stack:
+ default:
+ error (_("invalid argument location"));
+ break;
+ }
+ }
}
- arg_len = TYPE_LENGTH (info.type);
+ break;
- switch (info.argloc[0].loc_type)
+ /* Return value by reference will have its address in A0. */
+ case riscv_arg_info::location::by_ref:
{
- /* Return value in register(s). */
- case riscv_arg_info::location::in_reg:
- {
- regnum = info.argloc[0].loc_data.regno;
- gdb_assert (info.argloc[0].c_length <= arg_len);
- gdb_assert (info.argloc[0].c_length
- <= register_size (gdbarch, regnum));
+ ULONGEST addr;
- if (readbuf)
- {
- gdb_byte *ptr = readbuf + info.argloc[0].c_offset;
- regcache->cooked_read_part (regnum, 0,
- info.argloc[0].c_length,
- ptr);
- }
-
- if (writebuf)
- {
- const gdb_byte *ptr = writebuf + info.argloc[0].c_offset;
- riscv_regcache_cooked_write (regnum, ptr,
- info.argloc[0].c_length,
- regcache, call_info.flen);
- }
+ regcache_cooked_read_unsigned (regcache, RISCV_A0_REGNUM,
+ &addr);
+ if (read_value != nullptr)
+ {
+ abi_val = value_at_non_lval (type, addr);
+ /* Also reset the expected type, so that the cast
+ later on is a no-op. If the cast is not a no-op,
+ and if the return type is variably-sized, then the
+ type of ABI_VAL will differ from ARG_TYPE due to
+ dynamic type resolution, and so will most likely
+ fail. */
+ arg_type = abi_val->type ();
+ }
+ if (writebuf != nullptr)
+ write_memory (addr, writebuf, info.length);
+ }
+ break;
- /* A return value in register can have a second part in a
- second register. */
- if (info.argloc[1].c_length > 0)
- {
- switch (info.argloc[1].loc_type)
- {
- case riscv_arg_info::location::in_reg:
- regnum = info.argloc[1].loc_data.regno;
-
- gdb_assert ((info.argloc[0].c_length
- + info.argloc[1].c_length) <= arg_len);
- gdb_assert (info.argloc[1].c_length
- <= register_size (gdbarch, regnum));
-
- if (readbuf)
- {
- readbuf += info.argloc[1].c_offset;
- regcache->cooked_read_part (regnum, 0,
- info.argloc[1].c_length,
- readbuf);
- }
-
- if (writebuf)
- {
- const gdb_byte *ptr
- = writebuf + info.argloc[1].c_offset;
- riscv_regcache_cooked_write
- (regnum, ptr, info.argloc[1].c_length,
- regcache, call_info.flen);
- }
- break;
-
- case riscv_arg_info::location::by_ref:
- case riscv_arg_info::location::on_stack:
- default:
- error (_("invalid argument location"));
- break;
- }
- }
- }
- break;
+ case riscv_arg_info::location::on_stack:
+ default:
+ error (_("invalid argument location"));
+ break;
+ }
- /* Return value by reference will have its address in A0. */
- case riscv_arg_info::location::by_ref:
+ /* This completes the cast from abi type back to the declared type
+ in the case that we are reading from the machine. See the
+ comment at the head of this block for more details. */
+ if (read_value != nullptr)
+ {
+ if (is_fixed_point_type (arg_type))
{
- ULONGEST addr;
-
- regcache_cooked_read_unsigned (regcache, RISCV_A0_REGNUM,
- &addr);
- if (readbuf != nullptr)
- read_memory (addr, readbuf, info.length);
- if (writebuf != nullptr)
- write_memory (addr, writebuf, info.length);
+ /* Convert abi_val to the actual return type, but
+ being careful to preserve the fact that abi_val
+ is unscaled. */
+ gdb_mpz unscaled;
+
+ unscaled.read (abi_val->contents (),
+ type_byte_order (info.type),
+ info.type->is_unsigned ());
+ *read_value = value::allocate (arg_type);
+ unscaled.write ((*read_value)->contents_raw (),
+ type_byte_order (arg_type),
+ arg_type->is_unsigned ());
}
- break;
-
- case riscv_arg_info::location::on_stack:
- default:
- error (_("invalid argument location"));
- break;
- }
-
- /* This completes the cast from abi type back to the declared type
- in the case that we are reading from the machine. See the
- comment at the head of this block for more details. */
- if (readbuf != nullptr)
- {
- struct value *arg_val = value_cast (arg_type, abi_val);
- memcpy (old_readbuf, value_contents_raw (arg_val),
- TYPE_LENGTH (arg_type));
- }
+ else
+ *read_value = value_cast (arg_type, abi_val);
+ }
}
switch (info.argloc[0].loc_type)
case riscv_arg_info::location::in_reg:
return RETURN_VALUE_REGISTER_CONVENTION;
case riscv_arg_info::location::by_ref:
- return RETURN_VALUE_ABI_RETURNS_ADDRESS;
+ return RETURN_VALUE_ABI_PRESERVES_ADDRESS;
case riscv_arg_info::location::on_stack:
default:
error (_("invalid argument location"));
unwinder. */
static struct riscv_unwind_cache *
-riscv_frame_cache (struct frame_info *this_frame, void **this_cache)
+riscv_frame_cache (frame_info_ptr this_frame, void **this_cache)
{
CORE_ADDR pc, start_addr;
struct riscv_unwind_cache *cache;
/* We can now calculate the frame base address. */
cache->frame_base
- = (get_frame_register_signed (this_frame, cache->frame_base_reg)
+ = (get_frame_register_unsigned (this_frame, cache->frame_base_reg)
+ cache->frame_base_offset);
- if (riscv_debug_unwinder)
- fprintf_unfiltered (gdb_stdlog, "Frame base is %s ($%s + 0x%x)\n",
- core_addr_to_string (cache->frame_base),
- gdbarch_register_name (gdbarch,
- cache->frame_base_reg),
- cache->frame_base_offset);
+ riscv_unwinder_debug_printf ("frame base is %s ($%s + 0x%x)",
+ core_addr_to_string (cache->frame_base),
+ gdbarch_register_name (gdbarch,
+ cache->frame_base_reg),
+ cache->frame_base_offset);
/* The prologue scanner sets the address of registers stored to the stack
as the offset of that register from the frame base. The prologue
numregs = gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
for (regno = 0; regno < numregs; ++regno)
{
- if (trad_frame_addr_p (cache->regs, regno))
- cache->regs[regno].addr += cache->frame_base;
+ if (cache->regs[regno].is_addr ())
+ cache->regs[regno].set_addr (cache->regs[regno].addr ()
+ + cache->frame_base);
}
/* The previous $pc can be found wherever the $ra value can be found.
The previous $ra value is gone, this would have been stored be the
previous frame if required. */
cache->regs[gdbarch_pc_regnum (gdbarch)] = cache->regs[RISCV_RA_REGNUM];
- trad_frame_set_unknown (cache->regs, RISCV_RA_REGNUM);
+ cache->regs[RISCV_RA_REGNUM].set_unknown ();
/* Build the frame id. */
cache->this_id = frame_id_build (cache->frame_base, start_addr);
/* The previous $sp value is the frame base value. */
- trad_frame_set_value (cache->regs, gdbarch_sp_regnum (gdbarch),
- cache->frame_base);
+ cache->regs[gdbarch_sp_regnum (gdbarch)].set_value (cache->frame_base);
return cache;
}
/* Implement the this_id callback for RiscV frame unwinder. */
static void
-riscv_frame_this_id (struct frame_info *this_frame,
+riscv_frame_this_id (frame_info_ptr this_frame,
void **prologue_cache,
struct frame_id *this_id)
{
catch (const gdb_exception_error &ex)
{
/* Ignore errors, this leaves the frame id as the predefined outer
- frame id which terminates the backtrace at this point. */
+ frame id which terminates the backtrace at this point. */
}
}
/* Implement the prev_register callback for RiscV frame unwinder. */
static struct value *
-riscv_frame_prev_register (struct frame_info *this_frame,
+riscv_frame_prev_register (frame_info_ptr this_frame,
void **prologue_cache,
int regnum)
{
static const struct frame_unwind riscv_frame_unwind =
{
+ /*.name =*/ "riscv prologue",
/*.type =*/ NORMAL_FRAME,
/*.stop_reason =*/ default_frame_unwind_stop_reason,
/*.this_id =*/ riscv_frame_this_id,
/*.prev_arch =*/ NULL,
};
-/* Extract a set of required target features out of INFO, specifically the
- bfd being executed is examined to see what target features it requires.
- IF there is no current bfd, or the bfd doesn't indicate any useful
- features then a RISCV_GDBARCH_FEATURES is returned in its default state. */
+/* Extract a set of required target features out of ABFD. If ABFD is
+ nullptr then a RISCV_GDBARCH_FEATURES is returned in its default state. */
static struct riscv_gdbarch_features
-riscv_features_from_gdbarch_info (const struct gdbarch_info info)
+riscv_features_from_bfd (const bfd *abfd)
{
struct riscv_gdbarch_features features;
only used at all if the target hasn't given us a description, so this
is really a last ditched effort to do something sane before giving
up. */
- if (info.abfd != NULL
- && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
+ if (abfd != nullptr && bfd_get_flavour (abfd) == bfd_target_elf_flavour)
{
- unsigned char eclass = elf_elfheader (info.abfd)->e_ident[EI_CLASS];
- int e_flags = elf_elfheader (info.abfd)->e_flags;
+ unsigned char eclass = elf_elfheader (abfd)->e_ident[EI_CLASS];
+ int e_flags = elf_elfheader (abfd)->e_flags;
if (eclass == ELFCLASS32)
features.xlen = 4;
else if (eclass == ELFCLASS64)
features.xlen = 8;
else
- internal_error (__FILE__, __LINE__,
- _("unknown ELF header class %d"), eclass);
+ internal_error (_("unknown ELF header class %d"), eclass);
if (e_flags & EF_RISCV_FLOAT_ABI_DOUBLE)
features.flen = 8;
else if (e_flags & EF_RISCV_FLOAT_ABI_SINGLE)
features.flen = 4;
+
+ if (e_flags & EF_RISCV_RVE)
+ {
+ if (features.xlen == 8)
+ {
+ warning (_("64-bit ELF with RV32E flag set! Assuming 32-bit"));
+ features.xlen = 4;
+ }
+ features.embedded = true;
+ }
}
return features;
{
/* Extract desired feature set from INFO. */
struct riscv_gdbarch_features features
- = riscv_features_from_gdbarch_info (info);
+ = riscv_features_from_bfd (info.abfd);
- /* If the XLEN field is still 0 then we got nothing useful from INFO. In
- this case we fall back to a minimal useful target, 8-byte x-registers,
- with no floating point. */
+ /* If the XLEN field is still 0 then we got nothing useful from INFO.BFD,
+ maybe there was no bfd object. In this case we fall back to a minimal
+ useful target with no floating point, the x-register size is selected
+ based on the architecture from INFO. */
if (features.xlen == 0)
- features.xlen = 8;
+ features.xlen = info.bfd_arch_info->bits_per_word == 32 ? 4 : 8;
/* Now build a target description based on the feature set. */
return riscv_lookup_target_description (features);
}
-/* All of the registers in REG_SET are checked for in FEATURE, TDESC_DATA
- is updated with the register numbers for each register as listed in
- REG_SET. If any register marked as required in REG_SET is not found in
- FEATURE then this function returns false, otherwise, it returns true. */
-
-static bool
-riscv_check_tdesc_feature (struct tdesc_arch_data *tdesc_data,
- const struct tdesc_feature *main_feature,
- const struct tdesc_feature *csr_feature,
- const struct riscv_register_feature *reg_set,
- std::vector<riscv_pending_register_alias> *aliases)
-{
- for (const auto ® : reg_set->registers)
- {
- bool found = reg.check (tdesc_data, main_feature, reg_set, aliases);
-
- if (!found && reg.required != RISCV_REG_OPTIONAL)
- {
- if (reg.required == RISCV_REG_REQUIRED_MAYBE_CSR
- && csr_feature != nullptr)
- {
- gdb_assert (main_feature != csr_feature);
- found = reg.check (tdesc_data, csr_feature, reg_set, aliases);
- }
- if (!found)
- return false;
- }
- }
-
- return true;
-}
-
-/* Add all the expected register sets into GDBARCH. */
+/* Add all the RISC-V specific register groups into GDBARCH. */
static void
riscv_add_reggroups (struct gdbarch *gdbarch)
{
- /* Add predefined register groups. */
- reggroup_add (gdbarch, all_reggroup);
- reggroup_add (gdbarch, save_reggroup);
- reggroup_add (gdbarch, restore_reggroup);
- reggroup_add (gdbarch, system_reggroup);
- reggroup_add (gdbarch, vector_reggroup);
- reggroup_add (gdbarch, general_reggroup);
- reggroup_add (gdbarch, float_reggroup);
-
- /* Add RISC-V specific register groups. */
reggroup_add (gdbarch, csr_reggroup);
}
static int
riscv_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
{
- if (reg < RISCV_DWARF_REGNUM_X31)
+ if (reg <= RISCV_DWARF_REGNUM_X31)
return RISCV_ZERO_REGNUM + (reg - RISCV_DWARF_REGNUM_X0);
- else if (reg < RISCV_DWARF_REGNUM_F31)
+ else if (reg <= RISCV_DWARF_REGNUM_F31)
return RISCV_FIRST_FP_REGNUM + (reg - RISCV_DWARF_REGNUM_F0);
+ else if (reg >= RISCV_DWARF_FIRST_CSR && reg <= RISCV_DWARF_LAST_CSR)
+ return RISCV_FIRST_CSR_REGNUM + (reg - RISCV_DWARF_FIRST_CSR);
+
+ else if (reg >= RISCV_DWARF_REGNUM_V0 && reg <= RISCV_DWARF_REGNUM_V31)
+ return RISCV_V0_REGNUM + (reg - RISCV_DWARF_REGNUM_V0);
+
return -1;
}
and CSR register sets.
Some targets (QEMU) copied these target descriptions into their source
- tree, and so we're currently stuck working with some targets that
+ tree, and so we're now stuck working with some versions of QEMU that
declare the same registers twice.
- There's not much we can do about this any more. Assuming the target
- will direct a request for either register number to the correct
- underlying hardware register then it doesn't matter which one GDB
- uses, so long as we (GDB) are consistent (so that we don't end up with
- invalid cache misses).
-
- As we always scan the FPU registers first, then the CSRs, if the
- target has included the offending registers in both sets then we will
- always see the FPU copies here, as the CSR versions will replace them
- in the register list.
-
- To prevent these duplicates showing up in any of the register list,
- record their register numbers here. */
- if (strcmp (tdesc_feature_name (feature), riscv_freg_feature.name) == 0)
+ To make matters worse, if GDB tries to read or write to these
+ registers using the register number assigned in the FPU feature set,
+ then QEMU will fail to read the register, so we must use the register
+ number declared in the CSR feature set.
+
+ Luckily, GDB scans the FPU feature first, and then the CSR feature,
+ which means that the CSR feature will be the one we end up using, the
+ versions of these registers in the FPU feature will appear as unknown
+ registers and will be passed through to this code.
+
+ To prevent these duplicate registers showing up in any of the register
+ lists, and to prevent GDB every trying to access the FPU feature copies,
+ we spot the three problematic registers here, and record the register
+ number that GDB has assigned them. Then in riscv_register_name we will
+ return no name for the three duplicates, this hides the duplicates from
+ the user. */
+ if (strcmp (tdesc_feature_name (feature), riscv_freg_feature.name ()) == 0)
{
- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
int *regnum_ptr = nullptr;
if (strcmp (reg_name, "fflags") == 0)
/* Any unknown registers in the CSR feature are recorded within a single
block so we can easily identify these registers when making choices
about register groups in riscv_register_reggroup_p. */
- if (strcmp (tdesc_feature_name (feature), riscv_csr_feature.name) == 0)
+ if (strcmp (tdesc_feature_name (feature), riscv_csr_feature.name ()) == 0)
{
- struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
if (tdep->unknown_csrs_first_regnum == -1)
tdep->unknown_csrs_first_regnum = possible_regnum;
gdb_assert (tdep->unknown_csrs_first_regnum
return "riscv(32|64)?";
}
+/* Implementation of `gdbarch_stap_is_single_operand', as defined in
+ gdbarch.h. */
+
+static int
+riscv_stap_is_single_operand (struct gdbarch *gdbarch, const char *s)
+{
+ return (ISDIGIT (*s) /* Literal number. */
+ || *s == '(' /* Register indirection. */
+ || ISALPHA (*s)); /* Register value. */
+}
+
+/* String that appears before a register name in a SystemTap register
+ indirect expression. */
+
+static const char *const stap_register_indirection_prefixes[] =
+{
+ "(", nullptr
+};
+
+/* String that appears after a register name in a SystemTap register
+ indirect expression. */
+
+static const char *const stap_register_indirection_suffixes[] =
+{
+ ")", nullptr
+};
+
/* Initialize the current architecture based on INFO. If possible,
re-use an architecture from ARCHES, which is a list of
architectures already created during this debugging session.
riscv_gdbarch_init (struct gdbarch_info info,
struct gdbarch_list *arches)
{
- struct gdbarch *gdbarch;
- struct gdbarch_tdep *tdep;
struct riscv_gdbarch_features features;
const struct target_desc *tdesc = info.target_desc;
/* Ensure we always have a target description. */
if (!tdesc_has_registers (tdesc))
tdesc = riscv_find_default_target_description (info);
- gdb_assert (tdesc);
-
- if (riscv_debug_gdbarch)
- fprintf_unfiltered (gdb_stdlog, "Have got a target description\n");
+ gdb_assert (tdesc != nullptr);
- const struct tdesc_feature *feature_cpu
- = tdesc_find_feature (tdesc, riscv_xreg_feature.name);
- const struct tdesc_feature *feature_fpu
- = tdesc_find_feature (tdesc, riscv_freg_feature.name);
- const struct tdesc_feature *feature_virtual
- = tdesc_find_feature (tdesc, riscv_virtual_feature.name);
- const struct tdesc_feature *feature_csr
- = tdesc_find_feature (tdesc, riscv_csr_feature.name);
+ riscv_gdbarch_debug_printf ("have got a target description");
- if (feature_cpu == NULL)
- return NULL;
-
- struct tdesc_arch_data *tdesc_data = tdesc_data_alloc ();
+ tdesc_arch_data_up tdesc_data = tdesc_data_alloc ();
std::vector<riscv_pending_register_alias> pending_aliases;
- bool valid_p = riscv_check_tdesc_feature (tdesc_data,
- feature_cpu, feature_csr,
- &riscv_xreg_feature,
- &pending_aliases);
- if (valid_p)
- {
- /* Check that all of the core cpu registers have the same bitsize. */
- int xlen_bitsize = tdesc_register_bitsize (feature_cpu, "pc");
-
- for (auto &tdesc_reg : feature_cpu->registers)
- valid_p &= (tdesc_reg->bitsize == xlen_bitsize);
-
- if (riscv_debug_gdbarch)
- fprintf_filtered
- (gdb_stdlog,
- "From target-description, xlen = %d\n", xlen_bitsize);
-
- features.xlen = (xlen_bitsize / 8);
- }
-
- if (feature_fpu != NULL)
- {
- valid_p &= riscv_check_tdesc_feature (tdesc_data, feature_fpu,
- feature_csr,
- &riscv_freg_feature,
- &pending_aliases);
-
- /* Search for the first floating point register (by any alias), to
- determine the bitsize. */
- int bitsize = -1;
- const auto &fp0 = riscv_freg_feature.registers[0];
-
- for (const char *name : fp0.names)
- {
- if (tdesc_unnumbered_register (feature_fpu, name))
- {
- bitsize = tdesc_register_bitsize (feature_fpu, name);
- break;
- }
- }
-
- gdb_assert (bitsize != -1);
- features.flen = (bitsize / 8);
-
- if (riscv_debug_gdbarch)
- fprintf_filtered
- (gdb_stdlog,
- "From target-description, flen = %d\n", bitsize);
- }
- else
- {
- features.flen = 0;
-
- if (riscv_debug_gdbarch)
- fprintf_filtered
- (gdb_stdlog,
- "No FPU in target-description, assume soft-float ABI\n");
- }
-
- if (feature_virtual)
- riscv_check_tdesc_feature (tdesc_data, feature_virtual, feature_csr,
- &riscv_virtual_feature,
- &pending_aliases);
-
- if (feature_csr)
- riscv_check_tdesc_feature (tdesc_data, feature_csr, nullptr,
- &riscv_csr_feature,
- &pending_aliases);
-
+ bool valid_p = (riscv_xreg_feature.check (tdesc, tdesc_data.get (),
+ &pending_aliases, &features)
+ && riscv_freg_feature.check (tdesc, tdesc_data.get (),
+ &pending_aliases, &features)
+ && riscv_virtual_feature.check (tdesc, tdesc_data.get (),
+ &pending_aliases, &features)
+ && riscv_csr_feature.check (tdesc, tdesc_data.get (),
+ &pending_aliases, &features)
+ && riscv_vector_feature.check (tdesc, tdesc_data.get (),
+ &pending_aliases, &features));
if (!valid_p)
{
- if (riscv_debug_gdbarch)
- fprintf_unfiltered (gdb_stdlog, "Target description is not valid\n");
- tdesc_data_cleanup (tdesc_data);
+ riscv_gdbarch_debug_printf ("target description is not valid");
return NULL;
}
+ if (tdesc_found_register (tdesc_data.get (), RISCV_CSR_FFLAGS_REGNUM))
+ features.has_fflags_reg = true;
+ if (tdesc_found_register (tdesc_data.get (), RISCV_CSR_FRM_REGNUM))
+ features.has_frm_reg = true;
+ if (tdesc_found_register (tdesc_data.get (), RISCV_CSR_FCSR_REGNUM))
+ features.has_fcsr_reg = true;
+
/* Have a look at what the supplied (if any) bfd object requires of the
target, then check that this matches with what the target is
providing. */
struct riscv_gdbarch_features abi_features
- = riscv_features_from_gdbarch_info (info);
+ = riscv_features_from_bfd (info.abfd);
+
+ /* If the ABI_FEATURES xlen is 0 then this indicates we got no useful abi
+ features from the INFO object. In this case we just treat the
+ hardware features as defining the abi. */
+ if (abi_features.xlen == 0)
+ abi_features = features;
+
/* In theory a binary compiled for RV32 could run on an RV64 target,
however, this has not been tested in GDB yet, so for now we require
that the requested xlen match the targets xlen. */
- if (abi_features.xlen != 0 && abi_features.xlen != features.xlen)
+ if (abi_features.xlen != features.xlen)
error (_("bfd requires xlen %d, but target has xlen %d"),
- abi_features.xlen, features.xlen);
+ abi_features.xlen, features.xlen);
/* We do support running binaries compiled for 32-bit float on targets
with 64-bit float, so we only complain if the binary requires more
than the target has available. */
if (abi_features.flen > features.flen)
error (_("bfd requires flen %d, but target has flen %d"),
- abi_features.flen, features.flen);
-
- /* If the ABI_FEATURES xlen is 0 then this indicates we got no useful abi
- features from the INFO object. In this case we assume that the xlen
- abi matches the hardware. */
- if (abi_features.xlen == 0)
- abi_features.xlen = features.xlen;
+ abi_features.flen, features.flen);
/* Find a candidate among the list of pre-declared architectures. */
for (arches = gdbarch_list_lookup_by_info (arches, &info);
arches = gdbarch_list_lookup_by_info (arches->next, &info))
{
/* Check that the feature set of the ARCHES matches the feature set
- we are looking for. If it doesn't then we can't reuse this
- gdbarch. */
- struct gdbarch_tdep *other_tdep = gdbarch_tdep (arches->gdbarch);
+ we are looking for. If it doesn't then we can't reuse this
+ gdbarch. */
+ riscv_gdbarch_tdep *other_tdep
+ = gdbarch_tdep<riscv_gdbarch_tdep> (arches->gdbarch);
if (other_tdep->isa_features != features
|| other_tdep->abi_features != abi_features)
- continue;
+ continue;
break;
}
if (arches != NULL)
- {
- tdesc_data_cleanup (tdesc_data);
- return arches->gdbarch;
- }
+ return arches->gdbarch;
/* None found, so create a new architecture from the information provided. */
- tdep = new (struct gdbarch_tdep);
- gdbarch = gdbarch_alloc (&info, tdep);
+ gdbarch *gdbarch
+ = gdbarch_alloc (&info, gdbarch_tdep_up (new riscv_gdbarch_tdep));
+ riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
+
tdep->isa_features = features;
tdep->abi_features = abi_features;
set_gdbarch_float_bit (gdbarch, 32);
set_gdbarch_double_bit (gdbarch, 64);
set_gdbarch_long_double_bit (gdbarch, 128);
- set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
+ set_gdbarch_long_double_format (gdbarch, floatformats_ieee_quad);
set_gdbarch_ptr_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8);
set_gdbarch_char_signed (gdbarch, 0);
set_gdbarch_type_align (gdbarch, riscv_type_align);
/* Information about the target architecture. */
- set_gdbarch_return_value (gdbarch, riscv_return_value);
+ set_gdbarch_return_value_as_value (gdbarch, riscv_return_value);
set_gdbarch_breakpoint_kind_from_pc (gdbarch, riscv_breakpoint_kind_from_pc);
set_gdbarch_sw_breakpoint_from_kind (gdbarch, riscv_sw_breakpoint_from_kind);
set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
just a little easier. */
set_gdbarch_num_regs (gdbarch, RISCV_LAST_REGNUM + 1);
- /* We don't have to provide the count of 0 here (its the default) but
- include this line to make it explicit that, right now, we don't have
- any pseudo registers on RISC-V. */
- set_gdbarch_num_pseudo_regs (gdbarch, 0);
-
/* Some specific register numbers GDB likes to know about. */
set_gdbarch_sp_regnum (gdbarch, RISCV_SP_REGNUM);
set_gdbarch_pc_regnum (gdbarch, RISCV_PC_REGNUM);
set_gdbarch_print_registers_info (gdbarch, riscv_print_registers_info);
+ set_tdesc_pseudo_register_name (gdbarch, riscv_pseudo_register_name);
+ set_tdesc_pseudo_register_type (gdbarch, riscv_pseudo_register_type);
+ set_tdesc_pseudo_register_reggroup_p (gdbarch,
+ riscv_pseudo_register_reggroup_p);
+ set_gdbarch_pseudo_register_read (gdbarch, riscv_pseudo_register_read);
+ set_gdbarch_pseudo_register_write (gdbarch, riscv_pseudo_register_write);
+
/* Finalise the target description registers. */
- tdesc_use_registers (gdbarch, tdesc, tdesc_data, riscv_tdesc_unknown_reg);
+ tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data),
+ riscv_tdesc_unknown_reg);
+
+ /* Calculate the number of pseudo registers we need. The fflags and frm
+ registers are sub-fields of the fcsr CSR register (csr3). However,
+ these registers can also be accessed directly as separate CSR
+ registers (fflags is csr1, and frm is csr2). And so, some targets
+ might choose to offer direct access to all three registers in the
+ target description, while other targets might choose to only offer
+ access to fcsr.
+
+ As we scan the target description we spot which of fcsr, fflags, and
+ frm are available. If fcsr is available but either of fflags and/or
+ frm are not available, then we add pseudo-registers to provide the
+ missing functionality.
+
+ This has to be done after the call to tdesc_use_registers as we don't
+ know the final register number until after that call, and the pseudo
+ register numbers need to be after the physical registers. */
+ int num_pseudo_regs = 0;
+ int next_pseudo_regnum = gdbarch_num_regs (gdbarch);
+
+ if (features.has_fflags_reg)
+ tdep->fflags_regnum = RISCV_CSR_FFLAGS_REGNUM;
+ else if (features.has_fcsr_reg)
+ {
+ tdep->fflags_regnum = next_pseudo_regnum;
+ pending_aliases.emplace_back ("csr1", (void *) &tdep->fflags_regnum);
+ next_pseudo_regnum++;
+ num_pseudo_regs++;
+ }
+
+ if (features.has_frm_reg)
+ tdep->frm_regnum = RISCV_CSR_FRM_REGNUM;
+ else if (features.has_fcsr_reg)
+ {
+ tdep->frm_regnum = next_pseudo_regnum;
+ pending_aliases.emplace_back ("csr2", (void *) &tdep->frm_regnum);
+ next_pseudo_regnum++;
+ num_pseudo_regs++;
+ }
+
+ set_gdbarch_num_pseudo_regs (gdbarch, num_pseudo_regs);
/* Override the register type callback setup by the target description
mechanism. This allows us to provide special type for floating point
registers, no matter what the target description called them. */
set_gdbarch_register_name (gdbarch, riscv_register_name);
+ /* Tell GDB which RISC-V registers are read-only. */
+ set_gdbarch_cannot_store_register (gdbarch, riscv_cannot_store_register);
+
/* Override the register group callback setup by the target description
mechanism. This allows us to force registers into the groups we
want, ignoring what the target tells us. */
set_gdbarch_gcc_target_options (gdbarch, riscv_gcc_target_options);
set_gdbarch_gnu_triplet_regexp (gdbarch, riscv_gnu_triplet_regexp);
+ /* Disassembler options support. */
+ set_gdbarch_valid_disassembler_options (gdbarch,
+ disassembler_options_riscv ());
+ set_gdbarch_disassembler_options (gdbarch, &riscv_disassembler_options);
+
+ /* SystemTap Support. */
+ set_gdbarch_stap_is_single_operand (gdbarch, riscv_stap_is_single_operand);
+ set_gdbarch_stap_register_indirection_prefixes
+ (gdbarch, stap_register_indirection_prefixes);
+ set_gdbarch_stap_register_indirection_suffixes
+ (gdbarch, stap_register_indirection_suffixes);
+
/* Hook in OS ABI-specific overrides, if they have been registered. */
gdbarch_init_osabi (info, gdbarch);
riscv_next_pc (struct regcache *regcache, CORE_ADDR pc)
{
struct gdbarch *gdbarch = regcache->arch ();
+ const riscv_gdbarch_tdep *tdep
+ = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
struct riscv_insn insn;
CORE_ADDR next_pc;
if (src1 >= src2)
next_pc = pc + insn.imm_signed ();
}
+ else if (insn.opcode () == riscv_insn::ECALL)
+ {
+ if (tdep->syscall_next_pc != nullptr)
+ next_pc = tdep->syscall_next_pc (get_current_frame ());
+ }
return next_pc;
}
csr_reggroup = reggroup_new ("csr", USER_REGGROUP);
}
+/* See riscv-tdep.h. */
+
+void
+riscv_supply_regset (const struct regset *regset,
+ struct regcache *regcache, int regnum,
+ const void *regs, size_t len)
+{
+ regcache->supply_regset (regset, regnum, regs, len);
+
+ if (regnum == -1 || regnum == RISCV_ZERO_REGNUM)
+ regcache->raw_supply_zeroed (RISCV_ZERO_REGNUM);
+
+ struct gdbarch *gdbarch = regcache->arch ();
+ riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch);
+
+ if (regnum == -1
+ || regnum == tdep->fflags_regnum
+ || regnum == tdep->frm_regnum)
+ {
+ int fcsr_regnum = RISCV_CSR_FCSR_REGNUM;
+
+ /* Ensure that FCSR has been read into REGCACHE. */
+ if (regnum != -1)
+ regcache->supply_regset (regset, fcsr_regnum, regs, len);
+
+ /* Grab the FCSR value if it is now in the regcache. We must check
+ the status first as, if the register was not supplied by REGSET,
+ this call will trigger a recursive attempt to fetch the
+ registers. */
+ if (regcache->get_register_status (fcsr_regnum) == REG_VALID)
+ {
+ /* If we have an fcsr register then we should have fflags and frm
+ too, either provided by the target, or provided as a pseudo
+ register by GDB. */
+ gdb_assert (tdep->fflags_regnum >= 0);
+ gdb_assert (tdep->frm_regnum >= 0);
+
+ ULONGEST fcsr_val;
+ regcache->raw_read (fcsr_regnum, &fcsr_val);
+
+ /* Extract the fflags and frm values. */
+ ULONGEST fflags_val = fcsr_val & 0x1f;
+ ULONGEST frm_val = (fcsr_val >> 5) & 0x7;
+
+ /* And supply these if needed. We can only supply real
+ registers, so don't try to supply fflags or frm if they are
+ implemented as pseudo-registers. */
+ if ((regnum == -1 || regnum == tdep->fflags_regnum)
+ && tdep->fflags_regnum < gdbarch_num_regs (gdbarch))
+ regcache->raw_supply_integer (tdep->fflags_regnum,
+ (gdb_byte *) &fflags_val,
+ sizeof (fflags_val),
+ /* is_signed */ false);
+
+ if ((regnum == -1 || regnum == tdep->frm_regnum)
+ && tdep->frm_regnum < gdbarch_num_regs (gdbarch))
+ regcache->raw_supply_integer (tdep->frm_regnum,
+ (gdb_byte *)&frm_val,
+ sizeof (fflags_val),
+ /* is_signed */ false);
+ }
+ }
+}
+
void _initialize_riscv_tdep ();
void
_initialize_riscv_tdep ()
{
- riscv_create_csr_aliases ();
riscv_init_reggroups ();
gdbarch_register (bfd_arch_riscv, riscv_gdbarch_init, NULL);
/* Add root prefix command for all "set debug riscv" and "show debug
riscv" commands. */
- add_basic_prefix_cmd ("riscv", no_class,
- _("RISC-V specific debug commands."),
- &setdebugriscvcmdlist, "set debug riscv ", 0,
- &setdebuglist);
-
- add_show_prefix_cmd ("riscv", no_class,
- _("RISC-V specific debug commands."),
- &showdebugriscvcmdlist, "show debug riscv ", 0,
- &showdebuglist);
-
- add_setshow_zuinteger_cmd ("breakpoints", class_maintenance,
- &riscv_debug_breakpoints, _("\
+ add_setshow_prefix_cmd ("riscv", no_class,
+ _("RISC-V specific debug commands."),
+ _("RISC-V specific debug commands."),
+ &setdebugriscvcmdlist, &showdebugriscvcmdlist,
+ &setdebuglist, &showdebuglist);
+
+ add_setshow_boolean_cmd ("breakpoints", class_maintenance,
+ &riscv_debug_breakpoints, _("\
Set riscv breakpoint debugging."), _("\
Show riscv breakpoint debugging."), _("\
When non-zero, print debugging information for the riscv specific parts\n\
of the breakpoint mechanism."),
- NULL,
- show_riscv_debug_variable,
- &setdebugriscvcmdlist, &showdebugriscvcmdlist);
+ nullptr,
+ show_riscv_debug_variable,
+ &setdebugriscvcmdlist, &showdebugriscvcmdlist);
- add_setshow_zuinteger_cmd ("infcall", class_maintenance,
- &riscv_debug_infcall, _("\
+ add_setshow_boolean_cmd ("infcall", class_maintenance,
+ &riscv_debug_infcall, _("\
Set riscv inferior call debugging."), _("\
Show riscv inferior call debugging."), _("\
When non-zero, print debugging information for the riscv specific parts\n\
of the inferior call mechanism."),
- NULL,
- show_riscv_debug_variable,
- &setdebugriscvcmdlist, &showdebugriscvcmdlist);
+ nullptr,
+ show_riscv_debug_variable,
+ &setdebugriscvcmdlist, &showdebugriscvcmdlist);
- add_setshow_zuinteger_cmd ("unwinder", class_maintenance,
- &riscv_debug_unwinder, _("\
+ add_setshow_boolean_cmd ("unwinder", class_maintenance,
+ &riscv_debug_unwinder, _("\
Set riscv stack unwinding debugging."), _("\
Show riscv stack unwinding debugging."), _("\
-When non-zero, print debugging information for the riscv specific parts\n\
+When on, print debugging information for the riscv specific parts\n\
of the stack unwinding mechanism."),
- NULL,
- show_riscv_debug_variable,
- &setdebugriscvcmdlist, &showdebugriscvcmdlist);
+ nullptr,
+ show_riscv_debug_variable,
+ &setdebugriscvcmdlist, &showdebugriscvcmdlist);
- add_setshow_zuinteger_cmd ("gdbarch", class_maintenance,
- &riscv_debug_gdbarch, _("\
+ add_setshow_boolean_cmd ("gdbarch", class_maintenance,
+ &riscv_debug_gdbarch, _("\
Set riscv gdbarch initialisation debugging."), _("\
Show riscv gdbarch initialisation debugging."), _("\
When non-zero, print debugging information for the riscv gdbarch\n\
initialisation process."),
- NULL,
- show_riscv_debug_variable,
- &setdebugriscvcmdlist, &showdebugriscvcmdlist);
+ nullptr,
+ show_riscv_debug_variable,
+ &setdebugriscvcmdlist, &showdebugriscvcmdlist);
/* Add root prefix command for all "set riscv" and "show riscv" commands. */
- add_basic_prefix_cmd ("riscv", no_class,
- _("RISC-V specific commands."),
- &setriscvcmdlist, "set riscv ", 0, &setlist);
-
- add_show_prefix_cmd ("riscv", no_class,
- _("RISC-V specific commands."),
- &showriscvcmdlist, "show riscv ", 0, &showlist);
+ add_setshow_prefix_cmd ("riscv", no_class,
+ _("RISC-V specific commands."),
+ _("RISC-V specific commands."),
+ &setriscvcmdlist, &showriscvcmdlist,
+ &setlist, &showlist);
use_compressed_breakpoints = AUTO_BOOLEAN_AUTO;
projects / binutils-gdb.git / blobdiff