Tidy dwarf1 cached section contents

[binutils-gdb.git] / gdb / riscv-tdep.h

diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h
index 03870cf9e5b721a75c719afa077832fe68c81b69..4c3afb08e0710af8fbcdf94f833c2c4128aab1b0 100644 (file)
--- a/gdb/riscv-tdep.h
+++ b/gdb/riscv-tdep.h
@@ -1,7 +1,7 @@
 /* Target-dependent header for the RISC-V architecture, for GDB, the
    GNU Debugger.
 
-   Copyright (C) 2018-2021 Free Software Foundation, Inc.
+   Copyright (C) 2018-2023 Free Software Foundation, Inc.
 
    This file is part of GDB.
 
@@ -22,6 +22,7 @@
 #define RISCV_TDEP_H
 
 #include "arch/riscv.h"
+#include "gdbarch.h"
 
 /* RiscV register numbers.  */
 enum
@@ -75,7 +76,7 @@ enum
 };
 
 /* RISC-V specific per-architecture information.  */
-struct gdbarch_tdep
+struct riscv_gdbarch_tdep : gdbarch_tdep_base
 {
   /* Features about the target hardware that impact how the gdbarch is
      configured.  Two gdbarch instances are compatible only if this field
@@ -89,6 +90,12 @@ struct gdbarch_tdep
   /* ISA-specific data types.  */
   struct type *riscv_fpreg_d_type = nullptr;
 
+  /* The location of these registers, set to -2 by default so we don't
+     match against -1 which is frequently used to mean "all registers",
+     e.g. in the regcache supply/collect code.  */
+  int fflags_regnum = -2;
+  int frm_regnum = -2;
+
   /* Use for tracking unknown CSRs in the target description.
      UNKNOWN_CSRS_FIRST_REGNUM is the number assigned to the first unknown
      CSR.  All other unknown CSRs will be assigned sequential numbers after
@@ -105,7 +112,7 @@ struct gdbarch_tdep
 
   /* Return the expected next PC assuming FRAME is stopped at a syscall
      instruction.  */
-  CORE_ADDR (*syscall_next_pc) (struct frame_info *frame);
+  CORE_ADDR (*syscall_next_pc) (frame_info_ptr frame) = nullptr;
 };