#include "objfiles.h"
#include "arch-utils.h"
#include "regcache.h"
+#include "regset.h"
#include "doublest.h"
#include "value.h"
#include "parser-defs.h"
return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
}
-/* Use the architectures FP registers? */
+
+/* Return non-zero if the architecture described by GDBARCH has
+ floating-point registers (f0 --- f31 and fpscr). */
int
ppc_floating_point_unit_p (struct gdbarch *gdbarch)
{
- const struct bfd_arch_info *info = gdbarch_bfd_arch_info (gdbarch);
- if (info->arch == bfd_arch_powerpc)
- return (info->mach != bfd_mach_ppc_e500);
- if (info->arch == bfd_arch_rs6000)
- return 1;
- return 0;
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+ return (tdep->ppc_fp0_regnum >= 0
+ && tdep->ppc_fpscr_regnum >= 0);
+}
+\f
+
+/* Register set support functions. */
+
+static void
+ppc_supply_reg (struct regcache *regcache, int regnum,
+ const char *regs, size_t offset)
+{
+ if (regnum != -1 && offset != -1)
+ regcache_raw_supply (regcache, regnum, regs + offset);
+}
+
+static void
+ppc_collect_reg (const struct regcache *regcache, int regnum,
+ char *regs, size_t offset)
+{
+ if (regnum != -1 && offset != -1)
+ regcache_raw_collect (regcache, regnum, regs + offset);
+}
+
+/* Supply register REGNUM in the general-purpose register set REGSET
+ from the buffer specified by GREGS and LEN to register cache
+ REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
+
+void
+ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
+ int regnum, const void *gregs, size_t len)
+{
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ const struct ppc_reg_offsets *offsets = regset->descr;
+ size_t offset;
+ int i;
+
+ for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
+ i < tdep->ppc_gp0_regnum + 32;
+ i++, offset += 4)
+ {
+ if (regnum == -1 || regnum == i)
+ ppc_supply_reg (regcache, i, gregs, offset);
+ }
+
+ if (regnum == -1 || regnum == PC_REGNUM)
+ ppc_supply_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
+ if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
+ ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
+ gregs, offsets->ps_offset);
+ if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
+ ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
+ gregs, offsets->cr_offset);
+ if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
+ ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
+ gregs, offsets->lr_offset);
+ if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
+ ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
+ gregs, offsets->ctr_offset);
+ if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
+ ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
+ gregs, offsets->cr_offset);
+ if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
+ ppc_supply_reg (regcache, tdep->ppc_mq_regnum, gregs, offsets->mq_offset);
+}
+
+/* Supply register REGNUM in the floating-point register set REGSET
+ from the buffer specified by FPREGS and LEN to register cache
+ REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
+
+void
+ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
+ int regnum, const void *fpregs, size_t len)
+{
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ const struct ppc_reg_offsets *offsets = regset->descr;
+ size_t offset;
+ int i;
+
+ gdb_assert (ppc_floating_point_unit_p (gdbarch));
+
+ offset = offsets->f0_offset;
+ for (i = tdep->ppc_fp0_regnum;
+ i < tdep->ppc_fp0_regnum + ppc_num_fprs;
+ i++, offset += 4)
+ {
+ if (regnum == -1 || regnum == i)
+ ppc_supply_reg (regcache, i, fpregs, offset);
+ }
+
+ if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
+ ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
+ fpregs, offsets->fpscr_offset);
+}
+
+/* Collect register REGNUM in the general-purpose register set
+ REGSET. from register cache REGCACHE into the buffer specified by
+ GREGS and LEN. If REGNUM is -1, do this for all registers in
+ REGSET. */
+
+void
+ppc_collect_gregset (const struct regset *regset,
+ const struct regcache *regcache,
+ int regnum, void *gregs, size_t len)
+{
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ const struct ppc_reg_offsets *offsets = regset->descr;
+ size_t offset;
+ int i;
+
+ offset = offsets->r0_offset;
+ for (i = tdep->ppc_gp0_regnum;
+ i < tdep->ppc_gp0_regnum + 32;
+ i++, offset += 4)
+ {
+ if (regnum == -1 || regnum == i)
+ ppc_collect_reg (regcache, i, gregs, offset);
+ }
+
+ if (regnum == -1 || regnum == PC_REGNUM)
+ ppc_collect_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
+ if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
+ ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
+ gregs, offsets->ps_offset);
+ if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
+ ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
+ gregs, offsets->cr_offset);
+ if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
+ ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
+ gregs, offsets->lr_offset);
+ if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
+ ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
+ gregs, offsets->ctr_offset);
+ if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
+ ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
+ gregs, offsets->xer_offset);
+ if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
+ ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
+ gregs, offsets->mq_offset);
}
+/* Collect register REGNUM in the floating-point register set
+ REGSET. from register cache REGCACHE into the buffer specified by
+ FPREGS and LEN. If REGNUM is -1, do this for all registers in
+ REGSET. */
+
+void
+ppc_collect_fpregset (const struct regset *regset,
+ const struct regcache *regcache,
+ int regnum, void *fpregs, size_t len)
+{
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ const struct ppc_reg_offsets *offsets = regset->descr;
+ size_t offset;
+ int i;
+
+ gdb_assert (ppc_floating_point_unit_p (gdbarch));
+
+ offset = offsets->f0_offset;
+ for (i = tdep->ppc_fp0_regnum;
+ i <= tdep->ppc_fp0_regnum + ppc_num_fprs;
+ i++, offset += 4)
+ {
+ if (regnum == -1 || regnum == i)
+ ppc_collect_reg (regcache, regnum, fpregs, offset);
+ }
+
+ if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
+ ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
+ fpregs, offsets->fpscr_offset);
+}
+\f
+
/* Read a LEN-byte address from debugged memory address MEMADDR. */
static CORE_ADDR
/* store parameters in stack */
}
+ /* Move parameters from argument registers to temporary register. */
+ else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
+ (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
+ (((op >> 21) & 31) <= 10) &&
+ (((op >> 16) & 31) == 0)) /* Rx: scratch register r0 */
+ {
+ continue;
+ }
else if ((op & 0xfc1f0003) == 0xf8010000 || /* std rx,NUM(r1) */
(op & 0xfc1f0000) == 0xd8010000 || /* stfd Rx,NUM(r1) */
(op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
/* store parameters in stack via frame pointer */
}
else if (framep &&
- ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r1) */
- (op & 0xfc1f0000) == 0xd81f0000 || /* stfd Rx,NUM(r1) */
- (op & 0xfc1f0000) == 0xfc1f0000))
- { /* frsp, fp?,NUM(r1) */
+ ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
+ (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
+ (op & 0xfc1f0000) == 0xd81f0000 || /* stfd Rx,NUM(r31) */
+ (op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
+ {
continue;
/* Set up frame pointer */
CORE_ADDR saved_sp;
+ /* The calling convention this function implements assumes the
+ processor has floating-point registers. We shouldn't be using it
+ on PPC variants that lack them. */
+ gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
+
/* The first eight words of ther arguments are passed in registers.
Copy them appropriately. */
ii = 0;
printf_unfiltered (
"Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno);
- memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE (FP0_REGNUM + 1 + f_argno)],
+ memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE
+ (tdep->ppc_fp0_regnum + 1 + f_argno)],
VALUE_CONTENTS (arg),
len);
++f_argno;
printf_unfiltered (
"Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno);
- memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE (FP0_REGNUM + 1 + f_argno)],
+ memcpy (&(deprecated_registers
+ [DEPRECATED_REGISTER_BYTE
+ (tdep->ppc_fp0_regnum + 1 + f_argno)]),
VALUE_CONTENTS (arg),
len);
++f_argno;
int offset = 0;
struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+ /* The calling convention this function implements assumes the
+ processor has floating-point registers. We shouldn't be using it
+ on PPC variants that lack them. */
+ gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
+
if (TYPE_CODE (valtype) == TYPE_CODE_FLT)
{
- double dd;
- float ff;
/* floats and doubles are returned in fpr1. fpr's have a size of 8 bytes.
We need to truncate the return value into float size (4 byte) if
necessary. */
- if (TYPE_LENGTH (valtype) > 4) /* this is a double */
- memcpy (valbuf,
- ®buf[DEPRECATED_REGISTER_BYTE (FP0_REGNUM + 1)],
- TYPE_LENGTH (valtype));
- else
- { /* float */
- memcpy (&dd, ®buf[DEPRECATED_REGISTER_BYTE (FP0_REGNUM + 1)], 8);
- ff = (float) dd;
- memcpy (valbuf, &ff, sizeof (float));
- }
+ convert_typed_floating (®buf[DEPRECATED_REGISTER_BYTE
+ (tdep->ppc_fp0_regnum + 1)],
+ builtin_type_double,
+ valbuf,
+ valtype);
}
else if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY
&& TYPE_LENGTH (valtype) == 16
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
if (reg_nr >= tdep->ppc_gp0_regnum
- && reg_nr <= tdep->ppc_gplast_regnum)
+ && reg_nr < tdep->ppc_gp0_regnum + ppc_num_gprs)
{
base_regnum = reg_nr - tdep->ppc_gp0_regnum + tdep->ppc_ev0_regnum;
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
if (reg_nr >= tdep->ppc_gp0_regnum
- && reg_nr <= tdep->ppc_gplast_regnum)
+ && reg_nr < tdep->ppc_gp0_regnum + ppc_num_gprs)
{
base_regnum = reg_nr - tdep->ppc_gp0_regnum + tdep->ppc_ev0_regnum;
/* reg_nr is 32 bit here, and base_regnum is 64 bits. */
}
}
-/* Convert a dwarf2 register number to a gdb REGNUM. */
+/* Convert a dbx stab or Dwarf 2 register number (from `r'
+ declaration) to a gdb REGNUM. */
static int
-e500_dwarf2_reg_to_regnum (int num)
+rs6000_dwarf2_stab_reg_to_regnum (int num)
{
- int regnum;
- if (0 <= num && num <= 31)
- return num + gdbarch_tdep (current_gdbarch)->ppc_gp0_regnum;
- else
- return num;
-}
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
-/* Convert a dbx stab register number (from `r' declaration) to a gdb
- REGNUM. */
-static int
-rs6000_stab_reg_to_regnum (int num)
-{
- int regnum;
- switch (num)
- {
- case 64:
- regnum = gdbarch_tdep (current_gdbarch)->ppc_mq_regnum;
- break;
- case 65:
- regnum = gdbarch_tdep (current_gdbarch)->ppc_lr_regnum;
- break;
- case 66:
- regnum = gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum;
- break;
- case 76:
- regnum = gdbarch_tdep (current_gdbarch)->ppc_xer_regnum;
- break;
- default:
- regnum = num;
- break;
- }
- return regnum;
+ if (0 <= num && num <= 31)
+ return tdep->ppc_gp0_regnum + num;
+ else if (32 <= num && num <= 63)
+ /* FIXME: jimb/2004-05-05: What should we do when the debug info
+ specifies registers the architecture doesn't have? Our
+ callers don't check the value we return. */
+ return tdep->ppc_fp0_regnum + (num - 32);
+ else if (1200 <= num && num < 1200 + 32)
+ return tdep->ppc_ev0_regnum + (num - 1200);
+ else
+ switch (num)
+ {
+ case 64:
+ return tdep->ppc_mq_regnum;
+ case 65:
+ return tdep->ppc_lr_regnum;
+ case 66:
+ return tdep->ppc_ctr_regnum;
+ case 76:
+ return tdep->ppc_xer_regnum;
+ case 109:
+ return tdep->ppc_vrsave_regnum;
+ default:
+ return num;
+ }
+
+ /* FIXME: jimb/2004-03-28: Doesn't something need to be done here
+ for the Altivec registers, too?
+
+ Looking at GCC, the headers in config/rs6000 never define a
+ DBX_REGISTER_NUMBER macro, so the debug info uses the same
+ numbers GCC does internally. Then, looking at the REGISTER_NAMES
+ macro defined in config/rs6000/rs6000.h, it seems that GCC gives
+ v0 -- v31 the numbers 77 -- 108. But we number them 119 -- 150.
+
+ I don't have a way to test this ready to hand, but I noticed it
+ and thought I should include a note. */
}
static void
{
struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+ /* The calling convention this function implements assumes the
+ processor has floating-point registers. We shouldn't be using it
+ on PPC variants that lack them. */
+ gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
+
if (TYPE_CODE (type) == TYPE_CODE_FLT)
/* Floating point values are returned starting from FPR1 and up.
Say a double_double_double type could be returned in
FPR1/FPR2/FPR3 triple. */
- deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (FP0_REGNUM + 1), valbuf,
- TYPE_LENGTH (type));
+ deprecated_write_register_bytes
+ (DEPRECATED_REGISTER_BYTE (tdep->ppc_fp0_regnum + 1),
+ valbuf,
+ TYPE_LENGTH (type));
else if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
{
if (TYPE_LENGTH (type) == 16
{
/* gpr0-gpr31, fpr0-fpr31 */
COMMON_UISA_REGS,
- /* ctr, xre, lr, cr */
+ /* cr, lr, ctr, xer, fpscr */
PPC_UISA_SPRS,
/* sr0-sr15 */
PPC_SEGMENT_REGS,
R8(acc), R(spefscr),
/* NOTE: Add new registers here the end of the raw register
list and just before the first pseudo register. */
- /* 39...70 */
+ /* 41...72 */
PPC_GPRS_PSEUDO_REGS
};
{
int i;
CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
- for (i = fdata.saved_fpr; i < 32; i++)
- {
- cache->saved_regs[FP0_REGNUM + i].addr = fpr_addr;
- fpr_addr += 8;
- }
+
+ /* If skip_prologue says floating-point registers were saved,
+ but the current architecture has no floating-point registers,
+ then that's strange. But we have no indices to even record
+ the addresses under, so we just ignore it. */
+ if (ppc_floating_point_unit_p (gdbarch))
+ for (i = fdata.saved_fpr; i < 32; i++)
+ {
+ cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
+ fpr_addr += 8;
+ }
}
/* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
tdep->regs = v->regs;
tdep->ppc_gp0_regnum = 0;
- tdep->ppc_gplast_regnum = 31;
tdep->ppc_toc_regnum = 2;
tdep->ppc_ps_regnum = 65;
tdep->ppc_cr_regnum = 66;
tdep->ppc_mq_regnum = 70;
else
tdep->ppc_mq_regnum = -1;
+ tdep->ppc_fp0_regnum = 32;
tdep->ppc_fpscr_regnum = power ? 71 : 70;
set_gdbarch_pc_regnum (gdbarch, 64);
break;
case bfd_mach_ppc_e500:
tdep->ppc_gp0_regnum = 41;
- tdep->ppc_gplast_regnum = tdep->ppc_gp0_regnum + 32 - 1;
tdep->ppc_toc_regnum = -1;
tdep->ppc_ps_regnum = 1;
tdep->ppc_cr_regnum = 2;
tdep->ppc_xer_regnum = 5;
tdep->ppc_ev0_regnum = 7;
tdep->ppc_ev31_regnum = 38;
+ tdep->ppc_fp0_regnum = -1;
+ tdep->ppc_fpscr_regnum = -1;
set_gdbarch_pc_regnum (gdbarch, 0);
set_gdbarch_sp_regnum (gdbarch, tdep->ppc_gp0_regnum + 1);
set_gdbarch_deprecated_fp_regnum (gdbarch, tdep->ppc_gp0_regnum + 1);
- set_gdbarch_dwarf2_reg_to_regnum (gdbarch, e500_dwarf2_reg_to_regnum);
set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read);
set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write);
break;
set_gdbarch_deprecated_register_convertible (gdbarch, rs6000_register_convertible);
set_gdbarch_deprecated_register_convert_to_virtual (gdbarch, rs6000_register_convert_to_virtual);
set_gdbarch_deprecated_register_convert_to_raw (gdbarch, rs6000_register_convert_to_raw);
- set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
+ set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_dwarf2_stab_reg_to_regnum);
+ set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_stab_reg_to_regnum);
/* Note: kevinb/2002-04-12: I'm not convinced that rs6000_push_arguments()
is correct for the SysV ABI when the wordsize is 8, but I'm also
fairly certain that ppc_sysv_abi_push_arguments() will give even
frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
break;
default:
- set_gdbarch_deprecated_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos);
set_gdbarch_believe_pcc_promotion (gdbarch, 1);
set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
projects / binutils-gdb.git / blobdiff