s390_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
int regnum, gdb_byte *buf)
{
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
ULONGEST val;
switch (regnum)
{
case S390_PC_REGNUM:
regcache_raw_read_unsigned (regcache, S390_PSWA_REGNUM, &val);
- store_unsigned_integer (buf, 4, val & 0x7fffffff);
+ store_unsigned_integer (buf, 4, byte_order, val & 0x7fffffff);
break;
case S390_CC_REGNUM:
regcache_raw_read_unsigned (regcache, S390_PSWM_REGNUM, &val);
- store_unsigned_integer (buf, 4, (val >> 12) & 3);
+ store_unsigned_integer (buf, 4, byte_order, (val >> 12) & 3);
break;
default:
s390_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
int regnum, const gdb_byte *buf)
{
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
ULONGEST val, psw;
switch (regnum)
{
case S390_PC_REGNUM:
- val = extract_unsigned_integer (buf, 4);
+ val = extract_unsigned_integer (buf, 4, byte_order);
regcache_raw_read_unsigned (regcache, S390_PSWA_REGNUM, &psw);
psw = (psw & 0x80000000) | (val & 0x7fffffff);
regcache_raw_write_unsigned (regcache, S390_PSWA_REGNUM, psw);
break;
case S390_CC_REGNUM:
- val = extract_unsigned_integer (buf, 4);
+ val = extract_unsigned_integer (buf, 4, byte_order);
regcache_raw_read_unsigned (regcache, S390_PSWM_REGNUM, &psw);
psw = (psw & ~((ULONGEST)3 << 12)) | ((val & 3) << 12);
regcache_raw_write_unsigned (regcache, S390_PSWM_REGNUM, psw);
s390x_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
int regnum, gdb_byte *buf)
{
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
ULONGEST val;
switch (regnum)
case S390_CC_REGNUM:
regcache_raw_read_unsigned (regcache, S390_PSWM_REGNUM, &val);
- store_unsigned_integer (buf, 4, (val >> 44) & 3);
+ store_unsigned_integer (buf, 4, byte_order, (val >> 44) & 3);
break;
default:
s390x_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
int regnum, const gdb_byte *buf)
{
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
ULONGEST val, psw;
switch (regnum)
break;
case S390_CC_REGNUM:
- val = extract_unsigned_integer (buf, 4);
+ val = extract_unsigned_integer (buf, 4, byte_order);
regcache_raw_read_unsigned (regcache, S390_PSWM_REGNUM, &psw);
psw = (psw & ~((ULONGEST)3 << 44)) | ((val & 3) << 44);
regcache_raw_write_unsigned (regcache, S390_PSWM_REGNUM, psw);
op_bas = 0x4d,
op_bcr = 0x07,
op_bc = 0x0d,
+ op_bctr = 0x06,
+ op_bctgr = 0xb946,
+ op_bct = 0x46,
+ op1_bctg = 0xe3, op2_bctg = 0x46,
+ op_bxh = 0x86,
+ op1_bxhg = 0xeb, op2_bxhg = 0x44,
+ op_bxle = 0x87,
+ op1_bxleg= 0xeb, op2_bxleg= 0x45,
op1_bras = 0xa7, op2_bras = 0x05,
op1_brasl= 0xc0, op2_brasl= 0x05,
op1_brc = 0xa7, op2_brc = 0x04,
op1_brcl = 0xc0, op2_brcl = 0x04,
+ op1_brct = 0xa7, op2_brct = 0x06,
+ op1_brctg= 0xa7, op2_brctg= 0x07,
+ op_brxh = 0x84,
+ op1_brxhg= 0xec, op2_brxhg= 0x44,
+ op_brxle = 0x85,
+ op1_brxlg= 0xec, op2_brxlg= 0x45,
};
}
+static int
+is_rsi (bfd_byte *insn, int op,
+ unsigned int *r1, unsigned int *r3, int *i2)
+{
+ if (insn[0] == op)
+ {
+ *r1 = (insn[1] >> 4) & 0xf;
+ *r3 = insn[1] & 0xf;
+ /* i2 is a 16-bit signed quantity. */
+ *i2 = (((insn[2] << 8) | insn[3]) ^ 0x8000) - 0x8000;
+ return 1;
+ }
+ else
+ return 0;
+}
+
+
+static int
+is_rie (bfd_byte *insn, int op1, int op2,
+ unsigned int *r1, unsigned int *r3, int *i2)
+{
+ if (insn[0] == op1
+ && insn[5] == op2)
+ {
+ *r1 = (insn[1] >> 4) & 0xf;
+ *r3 = insn[1] & 0xf;
+ /* i2 is a 16-bit signed quantity. */
+ *i2 = (((insn[2] << 8) | insn[3]) ^ 0x8000) - 0x8000;
+ return 1;
+ }
+ else
+ return 0;
+}
+
+
static int
is_rx (bfd_byte *insn, int op,
unsigned int *r1, unsigned int *d2, unsigned int *x2, unsigned int *b2)
/* The stack. */
struct pv_area *stack;
- /* The size of a GPR or FPR. */
+ /* The size and byte-order of a GPR or FPR. */
int gpr_size;
int fpr_size;
+ enum bfd_endian byte_order;
/* The general-purpose registers. */
pv_t gpr[S390_NUM_GPRS];
if (secp != NULL
&& (bfd_get_section_flags (secp->bfd, secp->the_bfd_section)
& SEC_READONLY))
- return pv_constant (read_memory_integer (addr.k, size));
+ return pv_constant (read_memory_integer (addr.k, size,
+ data->byte_order));
}
/* Check whether we are accessing one of our save slots. */
{
int i;
- data->stack = make_pv_area (S390_SP_REGNUM);
+ data->stack = make_pv_area (S390_SP_REGNUM, gdbarch_addr_bit (gdbarch));
/* For the purpose of prologue tracking, we consider the GPR size to
be equal to the ABI word size, even if it is actually larger
(i.e. when running a 32-bit binary under a 64-bit kernel). */
data->gpr_size = word_size;
data->fpr_size = 8;
+ data->byte_order = gdbarch_byte_order (gdbarch);
for (i = 0; i < S390_NUM_GPRS; i++)
data->gpr[i] = pv_register (S390_R0_REGNUM + i, 0);
return 0;
}
+/* Displaced stepping. */
+
+/* Fix up the state of registers and memory after having single-stepped
+ a displaced instruction. */
+static void
+s390_displaced_step_fixup (struct gdbarch *gdbarch,
+ struct displaced_step_closure *closure,
+ CORE_ADDR from, CORE_ADDR to,
+ struct regcache *regs)
+{
+ /* Since we use simple_displaced_step_copy_insn, our closure is a
+ copy of the instruction. */
+ gdb_byte *insn = (gdb_byte *) closure;
+ static int s390_instrlen[] = { 2, 4, 4, 6 };
+ int insnlen = s390_instrlen[insn[0] >> 6];
+
+ /* Fields for various kinds of instructions. */
+ unsigned int b2, r1, r2, x2, r3;
+ int i2, d2;
+
+ /* Get current PC and addressing mode bit. */
+ CORE_ADDR pc = regcache_read_pc (regs);
+ ULONGEST amode = 0;
+
+ if (register_size (gdbarch, S390_PSWA_REGNUM) == 4)
+ {
+ regcache_cooked_read_unsigned (regs, S390_PSWA_REGNUM, &amode);
+ amode &= 0x80000000;
+ }
+
+ if (debug_displaced)
+ fprintf_unfiltered (gdb_stdlog,
+ "displaced: (s390) fixup (%s, %s) pc %s amode 0x%x\n",
+ paddress (gdbarch, from), paddress (gdbarch, to),
+ paddress (gdbarch, pc), (int) amode);
+
+ /* Handle absolute branch and save instructions. */
+ if (is_rr (insn, op_basr, &r1, &r2)
+ || is_rx (insn, op_bas, &r1, &d2, &x2, &b2))
+ {
+ /* Recompute saved return address in R1. */
+ regcache_cooked_write_unsigned (regs, S390_R0_REGNUM + r1,
+ amode | (from + insnlen));
+ }
+
+ /* Handle absolute branch instructions. */
+ else if (is_rr (insn, op_bcr, &r1, &r2)
+ || is_rx (insn, op_bc, &r1, &d2, &x2, &b2)
+ || is_rr (insn, op_bctr, &r1, &r2)
+ || is_rre (insn, op_bctgr, &r1, &r2)
+ || is_rx (insn, op_bct, &r1, &d2, &x2, &b2)
+ || is_rxy (insn, op1_bctg, op2_brctg, &r1, &d2, &x2, &b2)
+ || is_rs (insn, op_bxh, &r1, &r3, &d2, &b2)
+ || is_rsy (insn, op1_bxhg, op2_bxhg, &r1, &r3, &d2, &b2)
+ || is_rs (insn, op_bxle, &r1, &r3, &d2, &b2)
+ || is_rsy (insn, op1_bxleg, op2_bxleg, &r1, &r3, &d2, &b2))
+ {
+ /* Update PC iff branch was *not* taken. */
+ if (pc == to + insnlen)
+ regcache_write_pc (regs, from + insnlen);
+ }
+
+ /* Handle PC-relative branch and save instructions. */
+ else if (is_ri (insn, op1_bras, op2_bras, &r1, &i2)
+ || is_ril (insn, op1_brasl, op2_brasl, &r1, &i2))
+ {
+ /* Update PC. */
+ regcache_write_pc (regs, pc - to + from);
+ /* Recompute saved return address in R1. */
+ regcache_cooked_write_unsigned (regs, S390_R0_REGNUM + r1,
+ amode | (from + insnlen));
+ }
+
+ /* Handle PC-relative branch instructions. */
+ else if (is_ri (insn, op1_brc, op2_brc, &r1, &i2)
+ || is_ril (insn, op1_brcl, op2_brcl, &r1, &i2)
+ || is_ri (insn, op1_brct, op2_brct, &r1, &i2)
+ || is_ri (insn, op1_brctg, op2_brctg, &r1, &i2)
+ || is_rsi (insn, op_brxh, &r1, &r3, &i2)
+ || is_rie (insn, op1_brxhg, op2_brxhg, &r1, &r3, &i2)
+ || is_rsi (insn, op_brxle, &r1, &r3, &i2)
+ || is_rie (insn, op1_brxlg, op2_brxlg, &r1, &r3, &i2))
+ {
+ /* Update PC. */
+ regcache_write_pc (regs, pc - to + from);
+ }
+
+ /* Handle LOAD ADDRESS RELATIVE LONG. */
+ else if (is_ril (insn, op1_larl, op2_larl, &r1, &i2))
+ {
+ /* Recompute output address in R1. */
+ regcache_cooked_write_unsigned (regs, S390_R0_REGNUM + r1,
+ amode | (from + insnlen + i2*2));
+ }
+
+ /* If we executed a breakpoint instruction, point PC right back at it. */
+ else if (insn[0] == 0x0 && insn[1] == 0x1)
+ regcache_write_pc (regs, from);
+
+ /* For any other insn, PC points right after the original instruction. */
+ else
+ regcache_write_pc (regs, from + insnlen);
+}
/* Normal stack frames. */
CORE_ADDR prev_sp;
int frame_pointer;
int size;
+ struct frame_info *next_frame;
/* Try to find the function start address. If we can't find it, we don't
bother searching for it -- with modern compilers this would be mostly
/* FIXME: cagney/2004-05-01: This sanity check shouldn't be
needed, instead the code should simpliy rely on its
analysis. */
- if (get_next_frame (this_frame)
+ next_frame = get_next_frame (this_frame);
+ while (next_frame && get_frame_type (next_frame) == INLINE_FRAME)
+ next_frame = get_next_frame (next_frame);
+ if (next_frame
&& get_frame_type (get_next_frame (this_frame)) == NORMAL_FRAME)
return 0;
This can only happen in an innermost frame. */
/* FIXME: cagney/2004-05-01: This sanity check shouldn't be needed,
instead the code should simpliy rely on its analysis. */
+ next_frame = get_next_frame (this_frame);
+ while (next_frame && get_frame_type (next_frame) == INLINE_FRAME)
+ next_frame = get_next_frame (next_frame);
if (size > 0
- && (!get_next_frame (this_frame)
+ && (next_frame == NULL
|| get_frame_type (get_next_frame (this_frame)) != NORMAL_FRAME))
{
/* See the comment in s390_in_function_epilogue_p on why this is
{
struct gdbarch *gdbarch = get_frame_arch (this_frame);
int word_size = gdbarch_ptr_bit (gdbarch) / 8;
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
CORE_ADDR backchain;
ULONGEST reg;
LONGEST sp;
/* Get the backchain. */
reg = get_frame_register_unsigned (this_frame, S390_SP_REGNUM);
- backchain = read_memory_unsigned_integer (reg, word_size);
+ backchain = read_memory_unsigned_integer (reg, word_size, byte_order);
/* A zero backchain terminates the frame chain. As additional
sanity check, let's verify that the spill slot for SP in the
save area pointed to by the backchain in fact links back to
the save area. */
if (backchain != 0
- && safe_read_memory_integer (backchain + 15*word_size, word_size, &sp)
+ && safe_read_memory_integer (backchain + 15*word_size,
+ word_size, byte_order, &sp)
&& (CORE_ADDR)sp == backchain)
{
/* We don't know which registers were saved, but it will have
{
struct gdbarch *gdbarch = get_frame_arch (this_frame);
int word_size = gdbarch_ptr_bit (gdbarch) / 8;
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
struct s390_sigtramp_unwind_cache *info;
ULONGEST this_sp, prev_sp;
CORE_ADDR next_ra, next_cfa, sigreg_ptr;
pointer to sigregs */
else
{
- sigreg_ptr = read_memory_unsigned_integer (next_cfa + 8, word_size);
+ sigreg_ptr = read_memory_unsigned_integer (next_cfa + 8,
+ word_size, byte_order);
}
/* The sigregs structure looks like this:
/* Restore the previous frame's SP. */
prev_sp = read_memory_unsigned_integer (
info->saved_regs[S390_SP_REGNUM].addr,
- word_size);
+ word_size, byte_order);
/* Determine our frame base. */
info->frame_base = prev_sp + 16*word_size + 32;
/* Return ARG, a `SIMPLE_ARG', sign-extended or zero-extended to a full
word as required for the ABI. */
static LONGEST
-extend_simple_arg (struct value *arg)
+extend_simple_arg (struct gdbarch *gdbarch, struct value *arg)
{
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
struct type *type = value_type (arg);
/* Even structs get passed in the least significant bits of the
an integer, but it does take care of the extension. */
if (TYPE_UNSIGNED (type))
return extract_unsigned_integer (value_contents (arg),
- TYPE_LENGTH (type));
+ TYPE_LENGTH (type), byte_order);
else
return extract_signed_integer (value_contents (arg),
- TYPE_LENGTH (type));
+ TYPE_LENGTH (type), byte_order);
}
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
int word_size = gdbarch_ptr_bit (gdbarch) / 8;
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
ULONGEST orig_sp;
int i;
}
else
{
- write_memory_unsigned_integer (starg, word_size, copy_addr[i]);
+ write_memory_unsigned_integer (starg, word_size, byte_order,
+ copy_addr[i]);
starg += word_size;
}
}
{
/* Integer arguments are always extended to word size. */
regcache_cooked_write_signed (regcache, S390_R0_REGNUM + gr,
- extend_simple_arg (arg));
+ extend_simple_arg (gdbarch, arg));
gr++;
}
else
{
/* Integer arguments are always extended to word size. */
- write_memory_signed_integer (starg, word_size,
- extend_simple_arg (arg));
+ write_memory_signed_integer (starg, word_size, byte_order,
+ extend_simple_arg (gdbarch, arg));
starg += word_size;
}
}
struct type *type, struct regcache *regcache,
gdb_byte *out, const gdb_byte *in)
{
+ enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
int word_size = gdbarch_ptr_bit (gdbarch) / 8;
int length = TYPE_LENGTH (type);
enum return_value_convention rvc =
/* Integer arguments are always extended to word size. */
if (TYPE_UNSIGNED (type))
regcache_cooked_write_unsigned (regcache, S390_R2_REGNUM,
- extract_unsigned_integer (in, length));
+ extract_unsigned_integer (in, length, byte_order));
else
regcache_cooked_write_signed (regcache, S390_R2_REGNUM,
- extract_signed_integer (in, length));
+ extract_signed_integer (in, length, byte_order));
}
else if (length == 2*word_size)
{
set_gdbarch_unwind_pc (gdbarch, s390_unwind_pc);
set_gdbarch_unwind_sp (gdbarch, s390_unwind_sp);
+ /* Displaced stepping. */
+ set_gdbarch_displaced_step_copy_insn (gdbarch,
+ simple_displaced_step_copy_insn);
+ set_gdbarch_displaced_step_fixup (gdbarch, s390_displaced_step_fixup);
+ set_gdbarch_displaced_step_free_closure (gdbarch,
+ simple_displaced_step_free_closure);
+ set_gdbarch_displaced_step_location (gdbarch,
+ displaced_step_at_entry_point);
+ set_gdbarch_max_insn_length (gdbarch, S390_MAX_INSTR_SIZE);
+
switch (info.bfd_arch_info->mach)
{
case bfd_mach_s390_31:
projects / binutils-gdb.git / blobdiff