/* GNU/Linux/AArch64 specific low level interface, for the remote server for
GDB.
- Copyright (C) 2009-2020 Free Software Foundation, Inc.
+ Copyright (C) 2009-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GDB.
#include "gdb_proc_service.h"
#include "arch/aarch64.h"
+#include "arch/aarch64-mte-linux.h"
#include "linux-aarch32-tdesc.h"
#include "linux-aarch64-tdesc.h"
+#include "nat/aarch64-mte-linux-ptrace.h"
#include "nat/aarch64-sve-linux-ptrace.h"
#include "tdesc.h"
#include <sys/reg.h>
#endif
+#ifdef HAVE_GETAUXVAL
+#include <sys/auxv.h>
+#endif
+
/* Linux target op definitions for the AArch64 architecture. */
class aarch64_target : public linux_process_target
const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override;
+ bool supports_z_point_type (char z_type) override;
+
+ bool supports_tracepoints () override;
+
+ bool supports_fast_tracepoints () override;
+
+ int install_fast_tracepoint_jump_pad
+ (CORE_ADDR tpoint, CORE_ADDR tpaddr, CORE_ADDR collector,
+ CORE_ADDR lockaddr, ULONGEST orig_size, CORE_ADDR *jump_entry,
+ CORE_ADDR *trampoline, ULONGEST *trampoline_size,
+ unsigned char *jjump_pad_insn, ULONGEST *jjump_pad_insn_size,
+ CORE_ADDR *adjusted_insn_addr, CORE_ADDR *adjusted_insn_addr_end,
+ char *err) override;
+
+ int get_min_fast_tracepoint_insn_len () override;
+
+ struct emit_ops *emit_ops () override;
+
+ bool supports_memory_tagging () override;
+
+ bool fetch_memtags (CORE_ADDR address, size_t len,
+ gdb::byte_vector &tags, int type) override;
+
+ bool store_memtags (CORE_ADDR address, size_t len,
+ const gdb::byte_vector &tags, int type) override;
+
protected:
void low_arch_setup () override;
void low_set_pc (regcache *regcache, CORE_ADDR newpc) override;
bool low_breakpoint_at (CORE_ADDR pc) override;
+
+ int low_insert_point (raw_bkpt_type type, CORE_ADDR addr,
+ int size, raw_breakpoint *bp) override;
+
+ int low_remove_point (raw_bkpt_type type, CORE_ADDR addr,
+ int size, raw_breakpoint *bp) override;
+
+ bool low_stopped_by_watchpoint () override;
+
+ CORE_ADDR low_stopped_data_address () override;
+
+ bool low_siginfo_fixup (siginfo_t *native, gdb_byte *inf,
+ int direction) override;
+
+ arch_process_info *low_new_process () override;
+
+ void low_delete_process (arch_process_info *info) override;
+
+ void low_new_thread (lwp_info *) override;
+
+ void low_delete_thread (arch_lwp_info *) override;
+
+ void low_new_fork (process_info *parent, process_info *child) override;
+
+ void low_prepare_to_resume (lwp_info *lwp) override;
+
+ int low_get_thread_area (int lwpid, CORE_ADDR *addrp) override;
+
+ bool low_supports_range_stepping () override;
+
+ bool low_supports_catch_syscall () override;
+
+ void low_get_syscall_trapinfo (regcache *regcache, int *sysno) override;
};
/* The singleton target ops object. */
"is not implemented by the target");
}
+void
+aarch64_target::low_prepare_to_resume (lwp_info *lwp)
+{
+ aarch64_linux_prepare_to_resume (lwp);
+}
+
/* Per-process arch-specific data we want to keep. */
struct arch_process_info
return register_size (regcache->tdesc, 0) == 8;
}
-/* Return true if the regcache contains the number of SVE registers. */
-
-static bool
-is_sve_tdesc (void)
-{
- struct regcache *regcache = get_thread_regcache (current_thread, 0);
-
- return tdesc_contains_feature (regcache->tdesc, "org.gnu.gdb.aarch64.sve");
-}
-
static void
aarch64_fill_gregset (struct regcache *regcache, void *buf)
{
&pauth_regset[1]);
}
+/* Fill BUF with the MTE registers from the regcache. */
+
+static void
+aarch64_fill_mteregset (struct regcache *regcache, void *buf)
+{
+ uint64_t *mte_regset = (uint64_t *) buf;
+ int mte_base = find_regno (regcache->tdesc, "tag_ctl");
+
+ collect_register (regcache, mte_base, mte_regset);
+}
+
+/* Store the MTE registers to regcache. */
+
+static void
+aarch64_store_mteregset (struct regcache *regcache, const void *buf)
+{
+ uint64_t *mte_regset = (uint64_t *) buf;
+ int mte_base = find_regno (regcache->tdesc, "tag_ctl");
+
+ /* Tag Control register */
+ supply_register (regcache, mte_base, mte_regset);
+}
+
+/* Fill BUF with TLS register from the regcache. */
+
+static void
+aarch64_fill_tlsregset (struct regcache *regcache, void *buf)
+{
+ int tls_regnum = find_regno (regcache->tdesc, "tpidr");
+
+ collect_register (regcache, tls_regnum, buf);
+}
+
+/* Store TLS register to regcache. */
+
+static void
+aarch64_store_tlsregset (struct regcache *regcache, const void *buf)
+{
+ int tls_regnum = find_regno (regcache->tdesc, "tpidr");
+
+ supply_register (regcache, tls_regnum, buf);
+}
+
bool
aarch64_target::low_supports_breakpoints ()
{
return &proc->priv->arch_private->debug_reg_state;
}
-/* Implementation of linux_target_ops method "supports_z_point_type". */
+/* Implementation of target ops method "supports_z_point_type". */
-static int
-aarch64_supports_z_point_type (char z_type)
+bool
+aarch64_target::supports_z_point_type (char z_type)
{
switch (z_type)
{
case Z_PACKET_WRITE_WP:
case Z_PACKET_READ_WP:
case Z_PACKET_ACCESS_WP:
- return 1;
+ return true;
default:
- return 0;
+ return false;
}
}
-/* Implementation of linux_target_ops method "insert_point".
+/* Implementation of linux target ops method "low_insert_point".
It actually only records the info of the to-be-inserted bp/wp;
the actual insertion will happen when threads are resumed. */
-static int
-aarch64_insert_point (enum raw_bkpt_type type, CORE_ADDR addr,
- int len, struct raw_breakpoint *bp)
+int
+aarch64_target::low_insert_point (raw_bkpt_type type, CORE_ADDR addr,
+ int len, raw_breakpoint *bp)
{
int ret;
enum target_hw_bp_type targ_type;
if (targ_type != hw_execute)
{
- if (aarch64_linux_region_ok_for_watchpoint (addr, len))
+ if (aarch64_region_ok_for_watchpoint (addr, len))
ret = aarch64_handle_watchpoint (targ_type, addr, len,
- 1 /* is_insert */, state);
+ 1 /* is_insert */,
+ current_lwp_ptid (), state);
else
ret = -1;
}
len = 2;
}
ret = aarch64_handle_breakpoint (targ_type, addr, len,
- 1 /* is_insert */, state);
+ 1 /* is_insert */, current_lwp_ptid (),
+ state);
}
if (show_debug_regs)
return ret;
}
-/* Implementation of linux_target_ops method "remove_point".
+/* Implementation of linux target ops method "low_remove_point".
It actually only records the info of the to-be-removed bp/wp,
the actual removal will be done when threads are resumed. */
-static int
-aarch64_remove_point (enum raw_bkpt_type type, CORE_ADDR addr,
- int len, struct raw_breakpoint *bp)
+int
+aarch64_target::low_remove_point (raw_bkpt_type type, CORE_ADDR addr,
+ int len, raw_breakpoint *bp)
{
int ret;
enum target_hw_bp_type targ_type;
if (targ_type != hw_execute)
ret =
aarch64_handle_watchpoint (targ_type, addr, len, 0 /* is_insert */,
- state);
+ current_lwp_ptid (), state);
else
{
if (len == 3)
len = 2;
}
ret = aarch64_handle_breakpoint (targ_type, addr, len,
- 0 /* is_insert */, state);
+ 0 /* is_insert */, current_lwp_ptid (),
+ state);
}
if (show_debug_regs)
return ret;
}
-/* Implementation of linux_target_ops method "stopped_data_address". */
+/* Return the address only having significant bits. This is used to ignore
+ the top byte (TBI). */
static CORE_ADDR
-aarch64_stopped_data_address (void)
+address_significant (CORE_ADDR addr)
+{
+ /* Clear insignificant bits of a target address and sign extend resulting
+ address. */
+ int addr_bit = 56;
+
+ CORE_ADDR sign = (CORE_ADDR) 1 << (addr_bit - 1);
+ addr &= ((CORE_ADDR) 1 << addr_bit) - 1;
+ addr = (addr ^ sign) - sign;
+
+ return addr;
+}
+
+/* Implementation of linux target ops method "low_stopped_data_address". */
+
+CORE_ADDR
+aarch64_target::low_stopped_data_address ()
{
siginfo_t siginfo;
int pid, i;
|| (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
return (CORE_ADDR) 0;
+ /* Make sure to ignore the top byte, otherwise we may not recognize a
+ hardware watchpoint hit. The stopped data addresses coming from the
+ kernel can potentially be tagged addresses. */
+ const CORE_ADDR addr_trap
+ = address_significant ((CORE_ADDR) siginfo.si_addr);
+
/* Check if the address matches any watched address. */
state = aarch64_get_debug_reg_state (pid_of (current_thread));
for (i = aarch64_num_wp_regs - 1; i >= 0; --i)
const unsigned int offset
= aarch64_watchpoint_offset (state->dr_ctrl_wp[i]);
const unsigned int len = aarch64_watchpoint_length (state->dr_ctrl_wp[i]);
- const CORE_ADDR addr_trap = (CORE_ADDR) siginfo.si_addr;
const CORE_ADDR addr_watch = state->dr_addr_wp[i] + offset;
const CORE_ADDR addr_watch_aligned = align_down (state->dr_addr_wp[i], 8);
const CORE_ADDR addr_orig = state->dr_addr_orig_wp[i];
return (CORE_ADDR) 0;
}
-/* Implementation of linux_target_ops method "stopped_by_watchpoint". */
+/* Implementation of linux target ops method "low_stopped_by_watchpoint". */
-static int
-aarch64_stopped_by_watchpoint (void)
+bool
+aarch64_target::low_stopped_by_watchpoint ()
{
- if (aarch64_stopped_data_address () != 0)
- return 1;
- else
- return 0;
+ return (low_stopped_data_address () != 0);
}
/* Fetch the thread-local storage pointer for libthread_db. */
is_64bit_tdesc ());
}
-/* Implementation of linux_target_ops method "siginfo_fixup". */
+/* Implementation of linux target ops method "low_siginfo_fixup". */
-static int
-aarch64_linux_siginfo_fixup (siginfo_t *native, gdb_byte *inf, int direction)
+bool
+aarch64_target::low_siginfo_fixup (siginfo_t *native, gdb_byte *inf,
+ int direction)
{
/* Is the inferior 32-bit? If so, then fixup the siginfo object. */
if (!is_64bit_tdesc ())
aarch64_siginfo_from_compat_siginfo (native,
(struct compat_siginfo *) inf);
- return 1;
+ return true;
}
- return 0;
+ return false;
}
-/* Implementation of linux_target_ops method "new_process". */
+/* Implementation of linux target ops method "low_new_process". */
-static struct arch_process_info *
-aarch64_linux_new_process (void)
+arch_process_info *
+aarch64_target::low_new_process ()
{
struct arch_process_info *info = XCNEW (struct arch_process_info);
return info;
}
-/* Implementation of linux_target_ops method "delete_process". */
+/* Implementation of linux target ops method "low_delete_process". */
-static void
-aarch64_linux_delete_process (struct arch_process_info *info)
+void
+aarch64_target::low_delete_process (arch_process_info *info)
{
xfree (info);
}
-/* Implementation of linux_target_ops method "linux_new_fork". */
+void
+aarch64_target::low_new_thread (lwp_info *lwp)
+{
+ aarch64_linux_new_thread (lwp);
+}
+
+void
+aarch64_target::low_delete_thread (arch_lwp_info *arch_lwp)
+{
+ aarch64_linux_delete_thread (arch_lwp);
+}
-static void
-aarch64_linux_new_fork (struct process_info *parent,
- struct process_info *child)
+/* Implementation of linux target ops method "low_new_fork". */
+
+void
+aarch64_target::low_new_fork (process_info *parent,
+ process_info *child)
{
/* These are allocated by linux_add_process. */
gdb_assert (parent->priv != NULL
*child->priv->arch_private = *parent->priv->arch_private;
}
-/* Matches HWCAP_PACA in kernel header arch/arm64/include/uapi/asm/hwcap.h. */
-#define AARCH64_HWCAP_PACA (1 << 30)
-
-/* Implementation of linux target ops method "low_arch_setup". */
-
-void
-aarch64_target::low_arch_setup ()
-{
- unsigned int machine;
- int is_elf64;
- int tid;
-
- tid = lwpid_of (current_thread);
-
- is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine);
-
- if (is_elf64)
- {
- uint64_t vq = aarch64_sve_get_vq (tid);
- unsigned long hwcap = linux_get_hwcap (8);
- bool pauth_p = hwcap & AARCH64_HWCAP_PACA;
-
- current_process ()->tdesc = aarch64_linux_read_description (vq, pauth_p);
- }
- else
- current_process ()->tdesc = aarch32_linux_read_description ();
-
- aarch64_linux_get_debug_reg_capacity (lwpid_of (current_thread));
-}
-
/* Wrapper for aarch64_sve_regs_copy_to_reg_buf. */
static void
return aarch64_sve_regs_copy_from_reg_buf (regcache, buf);
}
+/* Array containing all the possible register sets for AArch64/Linux. During
+ architecture setup, these will be checked against the HWCAP/HWCAP2 bits for
+ validity and enabled/disabled accordingly.
+
+ Their sizes are set to 0 here, but they will be adjusted later depending
+ on whether each register set is available or not. */
static struct regset_info aarch64_regsets[] =
{
+ /* GPR registers. */
{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS,
- sizeof (struct user_pt_regs), GENERAL_REGS,
+ 0, GENERAL_REGS,
aarch64_fill_gregset, aarch64_store_gregset },
+ /* Floating Point (FPU) registers. */
{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET,
- sizeof (struct user_fpsimd_state), FP_REGS,
+ 0, FP_REGS,
aarch64_fill_fpregset, aarch64_store_fpregset
},
+ /* Scalable Vector Extension (SVE) registers. */
+ { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_SVE,
+ 0, EXTENDED_REGS,
+ aarch64_sve_regs_copy_from_regcache, aarch64_sve_regs_copy_to_regcache
+ },
+ /* PAC registers. */
{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_PAC_MASK,
- AARCH64_PAUTH_REGS_SIZE, OPTIONAL_REGS,
- NULL, aarch64_store_pauthregset },
+ 0, OPTIONAL_REGS,
+ nullptr, aarch64_store_pauthregset },
+ /* Tagged address control / MTE registers. */
+ { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_TAGGED_ADDR_CTRL,
+ 0, OPTIONAL_REGS,
+ aarch64_fill_mteregset, aarch64_store_mteregset },
+ /* TLS register. */
+ { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_TLS,
+ 0, OPTIONAL_REGS,
+ aarch64_fill_tlsregset, aarch64_store_tlsregset },
NULL_REGSET
};
{
aarch64_regsets, /* regsets */
0, /* num_regsets */
- NULL, /* disabled_regsets */
+ nullptr, /* disabled_regsets */
};
static struct regs_info regs_info_aarch64 =
{
- NULL, /* regset_bitmap */
- NULL, /* usrregs */
+ nullptr, /* regset_bitmap */
+ nullptr, /* usrregs */
&aarch64_regsets_info,
};
-static struct regset_info aarch64_sve_regsets[] =
+/* Given FEATURES, adjust the available register sets by setting their
+ sizes. A size of 0 means the register set is disabled and won't be
+ used. */
+
+static void
+aarch64_adjust_register_sets (const struct aarch64_features &features)
{
- { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS,
- sizeof (struct user_pt_regs), GENERAL_REGS,
- aarch64_fill_gregset, aarch64_store_gregset },
- { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_SVE,
- SVE_PT_SIZE (AARCH64_MAX_SVE_VQ, SVE_PT_REGS_SVE), EXTENDED_REGS,
- aarch64_sve_regs_copy_from_regcache, aarch64_sve_regs_copy_to_regcache
- },
- { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_PAC_MASK,
- AARCH64_PAUTH_REGS_SIZE, OPTIONAL_REGS,
- NULL, aarch64_store_pauthregset },
- NULL_REGSET
-};
+ struct regset_info *regset;
-static struct regsets_info aarch64_sve_regsets_info =
- {
- aarch64_sve_regsets, /* regsets. */
- 0, /* num_regsets. */
- NULL, /* disabled_regsets. */
- };
+ for (regset = aarch64_regsets; regset->size >= 0; regset++)
+ {
+ switch (regset->nt_type)
+ {
+ case NT_PRSTATUS:
+ /* General purpose registers are always present. */
+ regset->size = sizeof (struct user_pt_regs);
+ break;
+ case NT_FPREGSET:
+ /* This is unavailable when SVE is present. */
+ if (!features.sve)
+ regset->size = sizeof (struct user_fpsimd_state);
+ break;
+ case NT_ARM_SVE:
+ if (features.sve)
+ regset->size = SVE_PT_SIZE (AARCH64_MAX_SVE_VQ, SVE_PT_REGS_SVE);
+ break;
+ case NT_ARM_PAC_MASK:
+ if (features.pauth)
+ regset->size = AARCH64_PAUTH_REGS_SIZE;
+ break;
+ case NT_ARM_TAGGED_ADDR_CTRL:
+ if (features.mte)
+ regset->size = AARCH64_LINUX_SIZEOF_MTE;
+ break;
+ case NT_ARM_TLS:
+ if (features.tls)
+ regset->size = AARCH64_TLS_REGS_SIZE;
+ break;
+ default:
+ gdb_assert_not_reached ("Unknown register set found.");
+ }
+ }
+}
-static struct regs_info regs_info_aarch64_sve =
- {
- NULL, /* regset_bitmap. */
- NULL, /* usrregs. */
- &aarch64_sve_regsets_info,
- };
+/* Matches HWCAP_PACA in kernel header arch/arm64/include/uapi/asm/hwcap.h. */
+#define AARCH64_HWCAP_PACA (1 << 30)
+
+/* Implementation of linux target ops method "low_arch_setup". */
+
+void
+aarch64_target::low_arch_setup ()
+{
+ unsigned int machine;
+ int is_elf64;
+ int tid;
+
+ tid = lwpid_of (current_thread);
+
+ is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine);
+
+ if (is_elf64)
+ {
+ struct aarch64_features features;
+
+ uint64_t vq = aarch64_sve_get_vq (tid);
+ features.sve = (vq > 0);
+ /* A-profile PAC is 64-bit only. */
+ features.pauth = linux_get_hwcap (8) & AARCH64_HWCAP_PACA;
+ /* A-profile MTE is 64-bit only. */
+ features.mte = linux_get_hwcap2 (8) & HWCAP2_MTE;
+ features.tls = true;
+
+ current_process ()->tdesc
+ = aarch64_linux_read_description (vq, features.pauth, features.mte,
+ features.tls);
+
+ /* Adjust the register sets we should use for this particular set of
+ features. */
+ aarch64_adjust_register_sets (features);
+ }
+ else
+ current_process ()->tdesc = aarch32_linux_read_description ();
+
+ aarch64_linux_get_debug_reg_capacity (lwpid_of (current_thread));
+}
/* Implementation of linux target ops method "get_regs_info". */
if (!is_64bit_tdesc ())
return ®s_info_aarch32;
- if (is_sve_tdesc ())
- return ®s_info_aarch64_sve;
-
+ /* AArch64 64-bit registers. */
return ®s_info_aarch64;
}
-/* Implementation of linux_target_ops method "supports_tracepoints". */
+/* Implementation of target ops method "supports_tracepoints". */
-static int
-aarch64_supports_tracepoints (void)
+bool
+aarch64_target::supports_tracepoints ()
{
if (current_thread == NULL)
- return 1;
+ return true;
else
{
/* We don't support tracepoints on aarch32 now. */
}
}
-/* Implementation of linux_target_ops method "get_thread_area". */
+/* Implementation of linux target ops method "low_get_thread_area". */
-static int
-aarch64_get_thread_area (int lwpid, CORE_ADDR *addrp)
+int
+aarch64_target::low_get_thread_area (int lwpid, CORE_ADDR *addrp)
{
struct iovec iovec;
uint64_t reg;
return 0;
}
-/* Implementation of linux_target_ops method "get_syscall_trapinfo". */
+bool
+aarch64_target::low_supports_catch_syscall ()
+{
+ return true;
+}
-static void
-aarch64_get_syscall_trapinfo (struct regcache *regcache, int *sysno)
+/* Implementation of linux target ops method "low_get_syscall_trapinfo". */
+
+void
+aarch64_target::low_get_syscall_trapinfo (regcache *regcache, int *sysno)
{
int use_64bit = register_size (regcache->tdesc, 0) == 8;
aarch64_ftrace_insn_reloc_others,
};
-/* Implementation of linux_target_ops method
+bool
+aarch64_target::supports_fast_tracepoints ()
+{
+ return true;
+}
+
+/* Implementation of target ops method
"install_fast_tracepoint_jump_pad". */
-static int
-aarch64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint,
- CORE_ADDR tpaddr,
- CORE_ADDR collector,
- CORE_ADDR lockaddr,
- ULONGEST orig_size,
- CORE_ADDR *jump_entry,
- CORE_ADDR *trampoline,
- ULONGEST *trampoline_size,
- unsigned char *jjump_pad_insn,
- ULONGEST *jjump_pad_insn_size,
- CORE_ADDR *adjusted_insn_addr,
- CORE_ADDR *adjusted_insn_addr_end,
- char *err)
+int
+aarch64_target::install_fast_tracepoint_jump_pad
+ (CORE_ADDR tpoint, CORE_ADDR tpaddr, CORE_ADDR collector,
+ CORE_ADDR lockaddr, ULONGEST orig_size, CORE_ADDR *jump_entry,
+ CORE_ADDR *trampoline, ULONGEST *trampoline_size,
+ unsigned char *jjump_pad_insn, ULONGEST *jjump_pad_insn_size,
+ CORE_ADDR *adjusted_insn_addr, CORE_ADDR *adjusted_insn_addr_end,
+ char *err)
{
uint32_t buf[256];
uint32_t *p = buf;
{
CORE_ADDR buildaddr = current_insn_ptr;
- if (debug_threads)
- debug_printf ("Adding %d instrucions at %s\n",
- len, paddress (buildaddr));
+ threads_debug_printf ("Adding %d instrucions at %s",
+ len, paddress (buildaddr));
append_insns (&buildaddr, len, start);
current_insn_ptr = buildaddr;
aarch64_emit_ge_got,
};
-/* Implementation of linux_target_ops method "emit_ops". */
+/* Implementation of target ops method "emit_ops". */
-static struct emit_ops *
-aarch64_emit_ops (void)
+emit_ops *
+aarch64_target::emit_ops ()
{
return &aarch64_emit_ops_impl;
}
-/* Implementation of linux_target_ops method
+/* Implementation of target ops method
"get_min_fast_tracepoint_insn_len". */
-static int
-aarch64_get_min_fast_tracepoint_insn_len (void)
+int
+aarch64_target::get_min_fast_tracepoint_insn_len ()
{
return 4;
}
-/* Implementation of linux_target_ops method "supports_range_stepping". */
+/* Implementation of linux target ops method "low_supports_range_stepping". */
-static int
-aarch64_supports_range_stepping (void)
+bool
+aarch64_target::low_supports_range_stepping ()
{
- return 1;
+ return true;
}
/* Implementation of target ops method "sw_breakpoint_from_kind". */
return arm_breakpoint_kind_from_current_state (pcptr);
}
-/* Support for hardware single step. */
+/* Returns true if memory tagging is supported. */
+bool
+aarch64_target::supports_memory_tagging ()
+{
+ if (current_thread == NULL)
+ {
+ /* We don't have any processes running, so don't attempt to
+ use linux_get_hwcap2 as it will try to fetch the current
+ thread id. Instead, just fetch the auxv from the self
+ PID. */
+#ifdef HAVE_GETAUXVAL
+ return (getauxval (AT_HWCAP2) & HWCAP2_MTE) != 0;
+#else
+ return true;
+#endif
+ }
-static int
-aarch64_supports_hardware_single_step (void)
-{
- return 1;
-}
-
-struct linux_target_ops the_low_target =
-{
- aarch64_supports_z_point_type,
- aarch64_insert_point,
- aarch64_remove_point,
- aarch64_stopped_by_watchpoint,
- aarch64_stopped_data_address,
- NULL, /* collect_ptrace_register */
- NULL, /* supply_ptrace_register */
- aarch64_linux_siginfo_fixup,
- aarch64_linux_new_process,
- aarch64_linux_delete_process,
- aarch64_linux_new_thread,
- aarch64_linux_delete_thread,
- aarch64_linux_new_fork,
- aarch64_linux_prepare_to_resume,
- NULL, /* process_qsupported */
- aarch64_supports_tracepoints,
- aarch64_get_thread_area,
- aarch64_install_fast_tracepoint_jump_pad,
- aarch64_emit_ops,
- aarch64_get_min_fast_tracepoint_insn_len,
- aarch64_supports_range_stepping,
- aarch64_supports_hardware_single_step,
- aarch64_get_syscall_trapinfo,
-};
+ return (linux_get_hwcap2 (8) & HWCAP2_MTE) != 0;
+}
+
+bool
+aarch64_target::fetch_memtags (CORE_ADDR address, size_t len,
+ gdb::byte_vector &tags, int type)
+{
+ /* Allocation tags are per-process, so any tid is fine. */
+ int tid = lwpid_of (current_thread);
+
+ /* Allocation tag? */
+ if (type == static_cast <int> (aarch64_memtag_type::mte_allocation))
+ return aarch64_mte_fetch_memtags (tid, address, len, tags);
+
+ return false;
+}
+
+bool
+aarch64_target::store_memtags (CORE_ADDR address, size_t len,
+ const gdb::byte_vector &tags, int type)
+{
+ /* Allocation tags are per-process, so any tid is fine. */
+ int tid = lwpid_of (current_thread);
+
+ /* Allocation tag? */
+ if (type == static_cast <int> (aarch64_memtag_type::mte_allocation))
+ return aarch64_mte_store_memtags (tid, address, len, tags);
+
+ return false;
+}
/* The linux target ops object. */
initialize_low_arch_aarch32 ();
initialize_regsets_info (&aarch64_regsets_info);
- initialize_regsets_info (&aarch64_sve_regsets_info);
}
projects / binutils-gdb.git / blobdiff