/* GNU/Linux/AArch64 specific low level interface, for the remote server for
GDB.
- Copyright (C) 2009-2021 Free Software Foundation, Inc.
+ Copyright (C) 2009-2022 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of GDB.
#include "arch/aarch64-mte-linux.h"
#include "linux-aarch32-tdesc.h"
#include "linux-aarch64-tdesc.h"
+#include "nat/aarch64-mte-linux-ptrace.h"
#include "nat/aarch64-sve-linux-ptrace.h"
#include "tdesc.h"
#include <sys/reg.h>
#endif
+#ifdef HAVE_GETAUXVAL
+#include <sys/auxv.h>
+#endif
+
/* Linux target op definitions for the AArch64 architecture. */
class aarch64_target : public linux_process_target
struct emit_ops *emit_ops () override;
+ bool supports_memory_tagging () override;
+
+ bool fetch_memtags (CORE_ADDR address, size_t len,
+ gdb::byte_vector &tags, int type) override;
+
+ bool store_memtags (CORE_ADDR address, size_t len,
+ const gdb::byte_vector &tags, int type) override;
+
protected:
void low_arch_setup () override;
return register_size (regcache->tdesc, 0) == 8;
}
-/* Return true if the regcache contains the number of SVE registers. */
-
-static bool
-is_sve_tdesc (void)
-{
- struct regcache *regcache = get_thread_regcache (current_thread, 0);
-
- return tdesc_contains_feature (regcache->tdesc, "org.gnu.gdb.aarch64.sve");
-}
-
static void
aarch64_fill_gregset (struct regcache *regcache, void *buf)
{
supply_register (regcache, mte_base, mte_regset);
}
+/* Fill BUF with TLS register from the regcache. */
+
+static void
+aarch64_fill_tlsregset (struct regcache *regcache, void *buf)
+{
+ int tls_regnum = find_regno (regcache->tdesc, "tpidr");
+
+ collect_register (regcache, tls_regnum, buf);
+}
+
+/* Store TLS register to regcache. */
+
+static void
+aarch64_store_tlsregset (struct regcache *regcache, const void *buf)
+{
+ int tls_regnum = find_regno (regcache->tdesc, "tpidr");
+
+ supply_register (regcache, tls_regnum, buf);
+}
+
bool
aarch64_target::low_supports_breakpoints ()
{
if (targ_type != hw_execute)
{
- if (aarch64_linux_region_ok_for_watchpoint (addr, len))
+ if (aarch64_region_ok_for_watchpoint (addr, len))
ret = aarch64_handle_watchpoint (targ_type, addr, len,
- 1 /* is_insert */, state);
+ 1 /* is_insert */,
+ current_lwp_ptid (), state);
else
ret = -1;
}
len = 2;
}
ret = aarch64_handle_breakpoint (targ_type, addr, len,
- 1 /* is_insert */, state);
+ 1 /* is_insert */, current_lwp_ptid (),
+ state);
}
if (show_debug_regs)
if (targ_type != hw_execute)
ret =
aarch64_handle_watchpoint (targ_type, addr, len, 0 /* is_insert */,
- state);
+ current_lwp_ptid (), state);
else
{
if (len == 3)
len = 2;
}
ret = aarch64_handle_breakpoint (targ_type, addr, len,
- 0 /* is_insert */, state);
+ 0 /* is_insert */, current_lwp_ptid (),
+ state);
}
if (show_debug_regs)
*child->priv->arch_private = *parent->priv->arch_private;
}
-/* Matches HWCAP_PACA in kernel header arch/arm64/include/uapi/asm/hwcap.h. */
-#define AARCH64_HWCAP_PACA (1 << 30)
-
-/* Implementation of linux target ops method "low_arch_setup". */
-
-void
-aarch64_target::low_arch_setup ()
-{
- unsigned int machine;
- int is_elf64;
- int tid;
-
- tid = lwpid_of (current_thread);
-
- is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine);
-
- if (is_elf64)
- {
- uint64_t vq = aarch64_sve_get_vq (tid);
- unsigned long hwcap = linux_get_hwcap (8);
- unsigned long hwcap2 = linux_get_hwcap2 (8);
- bool pauth_p = hwcap & AARCH64_HWCAP_PACA;
- /* MTE is AArch64-only. */
- bool mte_p = hwcap2 & HWCAP2_MTE;
-
- current_process ()->tdesc
- = aarch64_linux_read_description (vq, pauth_p, mte_p);
- }
- else
- current_process ()->tdesc = aarch32_linux_read_description ();
-
- aarch64_linux_get_debug_reg_capacity (lwpid_of (current_thread));
-}
-
/* Wrapper for aarch64_sve_regs_copy_to_reg_buf. */
static void
return aarch64_sve_regs_copy_from_reg_buf (regcache, buf);
}
+/* Array containing all the possible register sets for AArch64/Linux. During
+ architecture setup, these will be checked against the HWCAP/HWCAP2 bits for
+ validity and enabled/disabled accordingly.
+
+ Their sizes are set to 0 here, but they will be adjusted later depending
+ on whether each register set is available or not. */
static struct regset_info aarch64_regsets[] =
{
+ /* GPR registers. */
{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS,
- sizeof (struct user_pt_regs), GENERAL_REGS,
+ 0, GENERAL_REGS,
aarch64_fill_gregset, aarch64_store_gregset },
+ /* Floating Point (FPU) registers. */
{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_FPREGSET,
- sizeof (struct user_fpsimd_state), FP_REGS,
+ 0, FP_REGS,
aarch64_fill_fpregset, aarch64_store_fpregset
},
+ /* Scalable Vector Extension (SVE) registers. */
+ { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_SVE,
+ 0, EXTENDED_REGS,
+ aarch64_sve_regs_copy_from_regcache, aarch64_sve_regs_copy_to_regcache
+ },
+ /* PAC registers. */
{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_PAC_MASK,
- AARCH64_PAUTH_REGS_SIZE, OPTIONAL_REGS,
- NULL, aarch64_store_pauthregset },
+ 0, OPTIONAL_REGS,
+ nullptr, aarch64_store_pauthregset },
+ /* Tagged address control / MTE registers. */
{ PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_TAGGED_ADDR_CTRL,
- AARCH64_LINUX_SIZEOF_MTE, OPTIONAL_REGS, aarch64_fill_mteregset,
- aarch64_store_mteregset },
+ 0, OPTIONAL_REGS,
+ aarch64_fill_mteregset, aarch64_store_mteregset },
+ /* TLS register. */
+ { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_TLS,
+ 0, OPTIONAL_REGS,
+ aarch64_fill_tlsregset, aarch64_store_tlsregset },
NULL_REGSET
};
{
aarch64_regsets, /* regsets */
0, /* num_regsets */
- NULL, /* disabled_regsets */
+ nullptr, /* disabled_regsets */
};
static struct regs_info regs_info_aarch64 =
{
- NULL, /* regset_bitmap */
- NULL, /* usrregs */
+ nullptr, /* regset_bitmap */
+ nullptr, /* usrregs */
&aarch64_regsets_info,
};
-static struct regset_info aarch64_sve_regsets[] =
+/* Given FEATURES, adjust the available register sets by setting their
+ sizes. A size of 0 means the register set is disabled and won't be
+ used. */
+
+static void
+aarch64_adjust_register_sets (const struct aarch64_features &features)
{
- { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS,
- sizeof (struct user_pt_regs), GENERAL_REGS,
- aarch64_fill_gregset, aarch64_store_gregset },
- { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_SVE,
- SVE_PT_SIZE (AARCH64_MAX_SVE_VQ, SVE_PT_REGS_SVE), EXTENDED_REGS,
- aarch64_sve_regs_copy_from_regcache, aarch64_sve_regs_copy_to_regcache
- },
- { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_PAC_MASK,
- AARCH64_PAUTH_REGS_SIZE, OPTIONAL_REGS,
- NULL, aarch64_store_pauthregset },
- { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_TAGGED_ADDR_CTRL,
- AARCH64_LINUX_SIZEOF_MTE, OPTIONAL_REGS, aarch64_fill_mteregset,
- aarch64_store_mteregset },
- NULL_REGSET
-};
+ struct regset_info *regset;
-static struct regsets_info aarch64_sve_regsets_info =
- {
- aarch64_sve_regsets, /* regsets. */
- 0, /* num_regsets. */
- NULL, /* disabled_regsets. */
- };
+ for (regset = aarch64_regsets; regset->size >= 0; regset++)
+ {
+ switch (regset->nt_type)
+ {
+ case NT_PRSTATUS:
+ /* General purpose registers are always present. */
+ regset->size = sizeof (struct user_pt_regs);
+ break;
+ case NT_FPREGSET:
+ /* This is unavailable when SVE is present. */
+ if (!features.sve)
+ regset->size = sizeof (struct user_fpsimd_state);
+ break;
+ case NT_ARM_SVE:
+ if (features.sve)
+ regset->size = SVE_PT_SIZE (AARCH64_MAX_SVE_VQ, SVE_PT_REGS_SVE);
+ break;
+ case NT_ARM_PAC_MASK:
+ if (features.pauth)
+ regset->size = AARCH64_PAUTH_REGS_SIZE;
+ break;
+ case NT_ARM_TAGGED_ADDR_CTRL:
+ if (features.mte)
+ regset->size = AARCH64_LINUX_SIZEOF_MTE;
+ break;
+ case NT_ARM_TLS:
+ if (features.tls)
+ regset->size = AARCH64_TLS_REGS_SIZE;
+ break;
+ default:
+ gdb_assert_not_reached ("Unknown register set found.");
+ }
+ }
+}
-static struct regs_info regs_info_aarch64_sve =
- {
- NULL, /* regset_bitmap. */
- NULL, /* usrregs. */
- &aarch64_sve_regsets_info,
- };
+/* Matches HWCAP_PACA in kernel header arch/arm64/include/uapi/asm/hwcap.h. */
+#define AARCH64_HWCAP_PACA (1 << 30)
+
+/* Implementation of linux target ops method "low_arch_setup". */
+
+void
+aarch64_target::low_arch_setup ()
+{
+ unsigned int machine;
+ int is_elf64;
+ int tid;
+
+ tid = lwpid_of (current_thread);
+
+ is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine);
+
+ if (is_elf64)
+ {
+ struct aarch64_features features;
+
+ uint64_t vq = aarch64_sve_get_vq (tid);
+ features.sve = (vq > 0);
+ /* A-profile PAC is 64-bit only. */
+ features.pauth = linux_get_hwcap (8) & AARCH64_HWCAP_PACA;
+ /* A-profile MTE is 64-bit only. */
+ features.mte = linux_get_hwcap2 (8) & HWCAP2_MTE;
+ features.tls = true;
+
+ current_process ()->tdesc
+ = aarch64_linux_read_description (vq, features.pauth, features.mte,
+ features.tls);
+
+ /* Adjust the register sets we should use for this particular set of
+ features. */
+ aarch64_adjust_register_sets (features);
+ }
+ else
+ current_process ()->tdesc = aarch32_linux_read_description ();
+
+ aarch64_linux_get_debug_reg_capacity (lwpid_of (current_thread));
+}
/* Implementation of linux target ops method "get_regs_info". */
if (!is_64bit_tdesc ())
return ®s_info_aarch32;
- if (is_sve_tdesc ())
- return ®s_info_aarch64_sve;
-
+ /* AArch64 64-bit registers. */
return ®s_info_aarch64;
}
{
CORE_ADDR buildaddr = current_insn_ptr;
- if (debug_threads)
- debug_printf ("Adding %d instrucions at %s\n",
- len, paddress (buildaddr));
+ threads_debug_printf ("Adding %d instrucions at %s",
+ len, paddress (buildaddr));
append_insns (&buildaddr, len, start);
current_insn_ptr = buildaddr;
return arm_breakpoint_kind_from_current_state (pcptr);
}
+/* Returns true if memory tagging is supported. */
+bool
+aarch64_target::supports_memory_tagging ()
+{
+ if (current_thread == NULL)
+ {
+ /* We don't have any processes running, so don't attempt to
+ use linux_get_hwcap2 as it will try to fetch the current
+ thread id. Instead, just fetch the auxv from the self
+ PID. */
+#ifdef HAVE_GETAUXVAL
+ return (getauxval (AT_HWCAP2) & HWCAP2_MTE) != 0;
+#else
+ return true;
+#endif
+ }
+
+ return (linux_get_hwcap2 (8) & HWCAP2_MTE) != 0;
+}
+
+bool
+aarch64_target::fetch_memtags (CORE_ADDR address, size_t len,
+ gdb::byte_vector &tags, int type)
+{
+ /* Allocation tags are per-process, so any tid is fine. */
+ int tid = lwpid_of (current_thread);
+
+ /* Allocation tag? */
+ if (type == static_cast <int> (aarch64_memtag_type::mte_allocation))
+ return aarch64_mte_fetch_memtags (tid, address, len, tags);
+
+ return false;
+}
+
+bool
+aarch64_target::store_memtags (CORE_ADDR address, size_t len,
+ const gdb::byte_vector &tags, int type)
+{
+ /* Allocation tags are per-process, so any tid is fine. */
+ int tid = lwpid_of (current_thread);
+
+ /* Allocation tag? */
+ if (type == static_cast <int> (aarch64_memtag_type::mte_allocation))
+ return aarch64_mte_store_memtags (tid, address, len, tags);
+
+ return false;
+}
+
/* The linux target ops object. */
linux_process_target *the_linux_target = &the_aarch64_target;
initialize_low_arch_aarch32 ();
initialize_regsets_info (&aarch64_regsets_info);
- initialize_regsets_info (&aarch64_sve_regsets_info);
}
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