else:
return getattr(self.groups[self.sel], name)
-# BitSlip ------------------------------------------------------------------------------------------
-
-
-class BitSlip(Elaboratable):
- def __init__(self, dw, rst=None, slp=None, cycles=1):
- self.i = Signal(dw)
- self.o = Signal(dw)
- self.rst = Signal() if rst is None else rst
- self.slp = Signal() if slp is None else slp
- self._cycles = cycles
-
- def elaborate(self, platform):
- m = Module()
-
- value = Signal(range(self._cycles*dw))
- with m.If(self.slp):
- m.d.sync += value.eq(value+1)
- with m.Elif(self.rst):
- m.d.sync += value.eq(0)
-
- r = Signal((self._cycles+1)*dw, reset_less=True)
- m.d.sync += r.eq(Cat(r[dw:], self.i))
- cases = {}
- for i in range(self._cycles*dw):
- cases[i] = self.o.eq(r[i:dw+i])
- m.d.comb += Case(value, cases)
-
- return m
-
# DQS Pattern --------------------------------------------------------------------------------------
class gramNativePort(Settings):
- def __init__(self, mode, address_width, data_width, clock_domain="sys", id=0):
+ def __init__(self, mode, address_width, data_width, clock_domain="sync", id=0):
self.set_attributes(locals())
self.lock = Signal()
self.flush = Signal()
- # retro-compatibility # FIXME: remove
- self.aw = self.address_width
- self.dw = self.data_width
- self.cd = self.clock_domain
-
def get_bank_address(self, bank_bits, cba_shift):
cba_upper = cba_shift + bank_bits
return self.cmd.addr[cba_shift:cba_upper]
class tXXDController(Elaboratable):
def __init__(self, txxd):
self.valid = Signal()
- self.ready = ready = Signal(reset=txxd is None)
- # ready.attr.add("no_retiming") TODO
+ self.ready = ready = Signal(reset=txxd is None, attrs={"no_retiming": True})
self._txxd = txxd
def elaborate(self, platform):
class tFAWController(Elaboratable):
def __init__(self, tfaw):
self.valid = Signal()
- self.ready = Signal(reset=1)
- # ready.attr.add("no_retiming") TODO
+ self.ready = Signal(reset=1, attrs={"no_retiming": True})
self._tfaw = tfaw
def elaborate(self, platform):